Build Report

Generated: Fri Dec 23 22:55:39 2022 by LibreSilicon Standard Cell Library Generator

Input files: PDK, DRC, layer definitions, process parameters:

These input files are necessary to define the rules and parameters for the standard cell library. All those files are collected in the Tech directory.

Filename	Description
Xdrc.lydrc	DRC rules for KLayout GDS Viewer
√librecell_tech.py	Cell layouting rules, DRC
√libresilicon.m	Transistor BSIM model SPICE parameters (*.lib files in other tools)
√libresilicon.tech	Magic Layers and Parasitic extraction parameters
√nmos.sp	Transistor size template for SPICE models
√pmos.sp	Transistor size template for SPICE models
√template.lef	Template for the header of Library Exchange Format LEF Files

Standard Cells:

These are the generated standard cells. You can click on the green ticks and the error messages to get more details or download the files. By moving the mouse over the header line you will get explanations for each column.

Cell	cell	Magic	Layout	Schematic	Log	Err	DRC	Liberty	LEF	GDS	SPICE	Parasitic	LayoutTime	Iterat.	Errors
AAAAOI3322.cell	√	√	√	X	√	√	√ 279	X	√	√	√	√	0:03:10 3	1	UNSAT: Constraints not satisfiable. Minimum area fixing failed!
AAAOAI3221.cell	√	√	√	X	√	√	√ 331	X	√	√	√	√	0:01:49 1	0	UNSAT: Constraints not satisfiable. Minimum area fixing failed!
AAAOAOI33311.cell	√	√	√	X	√	√	√ 348	X	√	√	√	√	0:05:36 5	5	UNSAT: Constraints not satisfiable. Minimum area fixing failed!
AAAOI222.cell	√	√	√	X	√	√	√ 162	X	√	√	√	√	0:01:25 1	2	UNSAT: Constraints not satisfiable. Minimum area fixing failed!
AAAOI333.cell	√	√	√	X	√	√	√ 250	X	√	√	√	√	0:02:10 2	1	UNSAT: Constraints not satisfiable. Minimum area fixing failed!
AAOAOI33111.cell	√	√	√	X	√	√	√ 326	X	√	√	√	√	0:02:36 2	2	UNSAT: Constraints not satisfiable. Minimum area fixing failed!
AAOI22.cell	√	√	√	X	√	√	√ 132	X	√	√	√	√	0:00:34 0	1	UNSAT: Constraints not satisfiable. Minimum area fixing failed!
AOAAOI2124.cell	√	√	√	X	√	√	√ 296	X	√	√	√	√	0:03:11 3	3	UNSAT: Constraints not satisfiable. Minimum area fixing failed!
ASYNC3.cell	√	√	√	X	√	√	√ 210	X	√	√	√	√	0:01:31 1	2	UNSAT: Constraints not satisfiable. Minimum area fixing failed!
INV.cell	√	√	√	X	√	√	√ 82	X	√	√	√	√	0:00:12 0	0	UNSAT: Constraints not satisfiable. Minimum area fixing failed!
MUX8.cell	√	√	√	X	√	√	√ 530	X	√	√	√	√	0:04:37 4	0	UNSAT: Constraints not satisfiable. Minimum area fixing failed! Short circuit detected: INT1->vdd->vdd Y->gnd->gnd!
NAND4.cell	√	√	√	X	√	√	√ 130	X	√	√	√	√	0:00:30 0	1	UNSAT: Constraints not satisfiable. Minimum area fixing failed!

Output files (needed by RTL2GDS tools like qflow, OpenROAD, Cadence, Synopsys, ...):

These are the resulting output files, you can download and use them with other EDA tools to build your chips:

Filename	Description
√ ../Documents/StdCellLib.pdf	PDF Documentation of the Standard cell library
Xdemoboard.mag	Demoboard: with all cells
√ library.gds	GDS-II file with masks for all cells, can be viewed with KLayout
Xlibresilicon.lef	Library Exchange Format (LEF) File with all cells
Xlibresilicon.lib	LIBERTY File with Characterization of all cells, can be viewed with libertyviz
√ libresilicon.sp	SPICE netlist with all cells

Stats: Max memory per cell: 2703MB , Max time per cell: 0:05:42 Cells: 12 SVGs: 12

If you want to build your own standard cell library, you can try our Online Standard Cell Library Generator or download the generator software and run it yourself.