Build Report

Generated: Wed Jun 24 20:50:27 2020 by LibreSilicon Standard Cell Library Generator

Input files: PDK, DRC, layer definitions, process parameters:

These input files are necessary to define the rules and parameters for the standard cell library. All those files are collected in the Tech directory.

Filename	Description
√drc.lydrc	DRC rules for KLayout GDS Viewer
√librecell_tech.py	Cell layouting rules, DRC
√libresilicon.m	Transistor BSIM model SPICE parameters (*.lib files in other tools)
√libresilicon.tech	Magic Layers and Parasitic extraction parameters
√template.lef	Template for the header of Library Exchange Format LEF Files
√transistor.sp	Transistor size template for SPICE models

Standard Cells:

These are the generated standard cells. You can click on the green ticks and the error messages to get more details or download the files. By moving the mouse over the header line you will get explanations for each column.

Cell	cell	Magic	Layout	Schematic	Log	Err	Liberty	LEF	GDS	SPICE	Parasitic	Area	LVS	Euler	LayoutTime	Nets	Ports	Iterat.	Errors
AND2X1.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	4	0:00:14.731552	10	5	0
AND2X2.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	4	0:00:14.909894	10	5	0
AND4.cell	√	√	√	√	√	√	X	√	√	√	√		SUCCESS	144	0:00:50.111917	14	7	6	Supplied boolean function and simulation are inconsistent.
AOI21.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:11.596070	8	5	9
AOI21X1.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	8	0:00:30.146931	11	6	19
AOI22X1.cell	√	√	√	X	√	√	√	√	√	√	√	5600	SUCCESS	8	0:00:45.212283	13	7	16
AOI31.cell	√	√	√	√	√	√	√	√	√	√	√	5600	SUCCESS	24	0:00:53.702862	13	7	23
BUFX2.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:08.197469	8	4	1
BUFX4.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	4	0:00:31.866280	9	4	21
CLKBUF1.cell	√	√	√	√	√	√	√	√	√	√	√	10080	SUCCESS	2	0:03:00.512455	16	4	24
CLKBUF2.cell	√	√	√	√	√	√	X	√	√	√	√		SUCCESS	2	0:07:20.714430	22	4	22	Output signal not yet stable at end.
CLKBUF3.cell	√	X	X	√	√	√	X	X	X	X	X						0
DFFNEGX1.cell	√	√	√	√	√	√	X	√	√	√	√		SUCCESS	2	0:08:28.941311	28	5	31
DFFPOSX1.cell	√	√	√	√	√	√	X	√	√	√	√		SUCCESS	2	0:13:41.917725	29	5	58
DFFSR.cell	√	√	X	√	√	√	X	X	X	√	√			2			0	999	Failed to route Supplied boolean function and simulation are inconsistent.
FAX1.cell	√	√	X	√	√	√	√	X	X	√	√	1		2			0	999	Failed to route
HAX1.cell	√	√	√	X	√	√	√	√	√	√	√	12320	SUCCESS	2	0:03:16.597274	20	6	11
INV.cell	√	√	√	√	√	√	√	√	√	√	√	2240	SUCCESS	2	0:00:02.925834	6	4	0
INVX1.cell	√	√	√	√	√	√	√	√	√	√	√	2240	SUCCESS	2	0:00:02.659331	6	4	0
INVX2.cell	√	√	√	√	√	√	√	√	√	√	√	2240	SUCCESS	2	0:00:03.097912	6	4	0
INVX4.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:15.946654	7	4	18
INVX8.cell	√	√	√	√	√	√	√	√	√	√	√	5600	SUCCESS	24	0:01:06.724443	9	4	18
LATCH.cell	√	√	√	√	√	√	X	√	√	√	√		SUCCESS	4	0:01:07.243444	16	5	9	Supplied boolean function and simulation are inconsistent.
MUX2X1.cell	√	√	√	√	√	√	√	√	√	√	√	6720	SUCCESS	4	0:00:43.320746	15	6	7
NAND2.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:14.455753	8	5	17
NAND2X1.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:12.470874	8	5	17
NAND3.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	24	0:00:25.973828	10	6	17
NAND3X1.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	24	0:00:26.350086	10	6	17
NOR2.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:14.652290	9	5	17
NOR2X1.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:14.044520	9	5	17
NOR3.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	2	0:00:22.209295	12	6	10
NOR3X1.cell	√	√	X	X	√	√	√	X	X	√	√	1		16			0	999	Failed to route
OAI21.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:11.256432	9	5	9
OAI21X1.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	2	0:00:29.568477	11	6	19
OAI22X1.cell	√	√	√	X	√	√	√	√	√	√	√	5600	SUCCESS	2	0:00:48.855188	14	7	18
OAI31.cell	√	√	√	√	√	√	√	√	√	√	√	5600	SUCCESS	2	0:00:39.361366	14	7	11
OR2X1.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	2	0:00:15.913896	11	5	2
OR2X2.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	2	0:00:15.949221	11	5	2
OR4.cell	√	√	√	√	√	√	√	√	√	√	√	6720	SUCCESS	2	0:00:47.114723	17	7	6
PADINC.cell	√	√	X	X	√	√	X	X	X	√	√			0			0		Cell has no input pins.
PADINOUT.cell	√	√	X	X	√	√	X	X	X	√	√			0			0		Cell has no input pins.
PADOUT.cell	√	√	X	X	√	√	X	X	X	√	√			0			0		Cell has no input pins.
TBUFX1.cell	√	√	√	√	√	√	X	√	√	√	√		SUCCESS	2	0:00:13.415902	11	5	1	Supplied boolean function and simulation are inconsistent.
TBUFX2.cell	√	√	√	X	√	√	X	√	√	√	√		SUCCESS	8	0:02:23.625725	13	5	67	Supplied boolean function and simulation are inconsistent.
XNOR2X1.cell	√	√	√	√	√	√	√	√	√	√	√	7840	SUCCESS	4	0:02:38.845140	16	5	57
XOR2X1.cell	√	√	√	√	√	√	√	√	√	√	√	7840	SUCCESS	4	0:01:30.107128	16	5	22

Output files (needed by RTL2GDS tools like qflow, OpenROAD, Cadence, Synopsys, ...):

These are the resulting output files, you can download and use them with other EDA tools to build your chips:

Filename	Description
√ ../Documents/StdCellLib.pdf	PDF Documentation of the Standard cell library
√ demoboard.mag	Demoboard: with all cells
√ library.gds	GDS-II file with masks for all cells, can be viewed with KLayout
√ libresilicon.lef	Library Exchange Format (LEF) File with all cells
√ libresilicon.lib	LIBERTY File with Characterization of all cells, can be viewed with libertyviz
√ libresilicon.sp	SPICE netlist with all cells

If you want to build your own standard cell library, you can try our Online Standard Cell Library Generator or download the generator software and run it yourself.