Index of /dist/StdCellLib_20230504_GF180/Catalog/gf180_stdcelllib_1/caravel/verilog/rtl

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[   ]__uprj_netlists.v2022-12-24 05:10 1.4K 
[   ]__user_project_wrapper.v2022-12-24 05:10 2.1K 
[   ]caravel.v2022-12-24 05:10 5.0K 
[   ]caravel_clocking.v2022-12-24 05:10 3.3K 
[   ]caravel_core.v2022-12-24 05:10 39K 
[   ]caravel_gf180_pdn.v2022-12-24 05:10 1.6K 
[   ]caravel_logo.v2022-12-24 05:10 34  
[   ]caravel_motto.v2022-12-24 05:10 35  
[   ]caravel_netlists.v2022-12-24 05:10 2.5K 
[   ]chip_io.v2022-12-24 05:10 7.8K 
[   ]clock_div.v2022-12-24 05:10 6.3K 
[   ]copyright_block.v2022-12-24 05:10 37  
[   ]defines.v2022-12-24 05:10 2.0K 
[   ]digital_pll.v2022-12-24 05:10 2.1K 
[   ]digital_pll_controller.v2022-12-24 05:10 4.9K 
[   ]gpio_control_block.v2022-12-24 05:10 7.5K 
[   ]gpio_defaults_block.v2022-12-24 05:10 2.3K 
[   ]housekeeping.v2022-12-24 05:10 49K 
[   ]housekeeping_spi.v2022-12-24 05:10 8.4K 
[   ]mgmt_protect.v2022-12-24 05:10 5.3K 
[   ]mprj_io_buffer.v2022-12-24 05:10 533  
[   ]open_source.v2022-12-24 05:10 33  
[   ]ring_osc2x13.v2022-12-24 05:10 5.6K 
[   ]simple_por.v2022-12-24 05:10 1.8K 
[   ]spare_logic_block.v2022-12-24 05:10 3.7K 
[   ]user_defines.v2022-12-24 05:10 4.2K 
[   ]user_id_programming.v2022-12-24 05:10 1.8K 
[   ]user_id_textblock.v2022-12-24 05:10 39