%%  ************    LibreSilicon's StdCellLibrary   *******************
%%
%%  Organisation:   Chipforge
%%                  Germany / European Union
%%
%%  Profile:        Chipforge focus on fine System-on-Chip Cores in
%%                  Verilog HDL Code which are easy understandable and
%%                  adjustable. For further information see
%%                          www.chipforge.org
%%                  there are projects from small cores up to PCBs, too.
%%
%%  File:           StdCellLib/Documents/LaTeX/stdcelllib.tex
%%
%%  Purpose:        Top Level File for Standard Cell Library Documentation
%%
%%  ************    LaTeX with circdia.sty package      ***************
%%
%%  ///////////////////////////////////////////////////////////////////
%%
%%  Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
%%  All rights reserved.
%%
%%      This Standard Cell Library is licensed under the Libre Silicon
%%      public license; you can redistribute it and/or modify it under
%%      the terms of the Libre Silicon public license as published by
%%      the Libre Silicon alliance, either version 1 of the License, or
%%      (at your option) any later version.
%%
%%      This design is distributed in the hope that it will be useful,
%%      but WITHOUT ANY WARRANTY; without even the implied warranty of
%%      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
%%      See the Libre Silicon Public License for more details.
%%
%%  ///////////////////////////////////////////////////////////////////
\documentclass[10pt,a4paper,twoside]{article}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
%\usepackage{amsmath}
%\usepackage{amsfonts}
\usepackage{amssymb}
%\usepackage{gensymb}
%\usepackage{graphicx}
\usepackage[digital,srcmeas,semicon]{circdia}
% \usepackage[dvipsnames]{xcolor}
\usepackage[left=2cm,right=2cm,top=2cm,bottom=2cm]{geometry}

\title{LibreSilicon Standard Cell Library}
\author{Hagen Sankowski}
\date{\today}

\makeindex  % usefull for ToC
\setlength{\parindent}{0pt} % get rid of annoying indents

\begin{document}
\maketitle
\begin{abstract}
\begin{quote}
Copyright \textcopyright  2018 CHIPFORGE.ORG. All rights reserved.

This process is licensed under the Libre Silicon public license; you can redistribute it and/or modify it under the terms of the Libre Silicon public license as published by the Libre Silicon alliance either version 2 of the License, or (at your option) any later version.

This design is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the Libre Silicon Public License for more details.

For further clarification consult the complete documentation of the process.
\end{quote}
\end{abstract}

\clearpage
\tableofcontents
\clearpage

\pagestyle{headings}

\section{Considerations}
\newcommand{\stacktfour}{YES}
%\newcommand{\stacktfour}{NO}
\clearpage

\section{Logical Cells}
\twocolumn

\input{cells.tex}
\clearpage


%\onecolumn
%\section{Physical Cells}

%\twocolumn
%\input{TIE0_manpage.tex}
%\input{TIE1_manpage.tex}
%\input{FILL_manpage.tex}

VDDIO \\
GND \\
ANA

\onecolumn
\
\end{document}
