Build Report

Generated: Sat Dec 19 01:37:57 2020 by LibreSilicon Standard Cell Library Generator

Input files: PDK, DRC, layer definitions, process parameters:

These input files are necessary to define the rules and parameters for the standard cell library. All those files are collected in the Tech directory.
FilenameDescription
XDRC rules for KLayout GDS Viewer
librecell_tech.pyCell layouting rules, DRC
libresilicon.mTransistor BSIM model SPICE parameters (*.lib files in other tools)
libresilicon.techMagic Layers and Parasitic extraction parameters
template.lefTemplate for the header of Library Exchange Format LEF Files
transistor.spTransistor size template for SPICE models

Standard Cells:

These are the generated standard cells. You can click on the green ticks and the error messages to get more details or download the files. By moving the mouse over the header line you will get explanations for each column.
CellcellMagicLayoutSchematicLogErrDRCLibertyLEFGDSSPICEParasiticAreaLVSEulerLayoutTimeNetsPortsIterat.Errors
AND2X1.cellX176640FAILED40:00:01.681252551LVS check failed! LVS check failed!
AND2X2.cellX176640FAILED40:00:01.760059551LVS check failed! LVS check failed!
AOI21X1.cellX176640FAILED80:00:01.671616561LVS check failed! LVS check failed!
AOI22X1.cellX220800FAILED80:00:02.274057572LVS check failed! LVS check failed!
BUFX2.cellX132480FAILED20:00:01.327597441LVS check failed! LVS check failed!
BUFX4.cellX176640FAILED40:00:01.727431441LVS check failed! LVS check failed!
CLKBUF1.cellX397440FAILED20:00:04.569325641LVS check failed! LVS check failed!
CLKBUF2.cellXXXXXXXXX0 This cell has been excluded from building
CLKBUF3.cellXXXXXXXXX0 This cell has been excluded from building
DFFNEGX1.cellXXXXXXXXX0 This cell has been excluded from building
DFFPOSX1.cellXXXXXXXXX0 This cell has been excluded from building
DFFSR.cellXXXXXXXXX0 This cell has been excluded from building
FAX1.cellXXXXXXXXX0 This cell has been excluded from building
HAX1.cellX485760FAILED20:00:05.217752862LVS check failed! LVS check failed!
INV.cellX88320FAILED20:00:00.812461340LVS check failed! LVS check failed!
INVX1.cellX88320FAILED20:00:00.804592340LVS check failed! LVS check failed!
INVX2.cellX88320FAILED20:00:00.826335340LVS check failed! LVS check failed!
INVX4.cellX132480FAILED20:00:01.264242341LVS check failed! LVS check failed!
INVX8.cellX220800FAILED240:00:02.763201341LVS check failed! LVS check failed!
LATCH.cellXXFAILED40:00:03.370149952LVS check failed! LVS check failed! Supplied boolean function and simulation are inconsistent.
MUX2X1.cellX264960FAILED40:00:02.818230861LVS check failed! LVS check failed!
NAND2X1.cellX132480FAILED20:00:01.243192451LVS check failed! LVS check failed!
NAND3X1.cellX176640FAILED240:00:01.782221561LVS check failed! LVS check failed!
NOR2X1.cellX132480FAILED20:00:01.259370451LVS check failed! LVS check failed!
NOR3X1.cellX309120FAILED160:00:03.5677644613LVS check failed! LVS check failed!
OAI21X1.cellX176640FAILED20:00:01.755583561LVS check failed! LVS check failed!
OAI22X1.cellX220800FAILED20:00:02.221688672LVS check failed! LVS check failed!
OR2X1.cellX176640FAILED20:00:01.680054551LVS check failed! LVS check failed!
OR2X2.cellX176640FAILED20:00:01.717304551LVS check failed! LVS check failed!
PADINC.cellXXXXXXXXX0 This cell has been excluded from building
PADINOUT.cellXXXXXXXXX0 This cell has been excluded from building
PADOUT.cellXXXXXXXXX0 This cell has been excluded from building
TBUFX1.cellXXXXXXXXX0 This cell has been excluded from building
TBUFX2.cellXXXXXXXXX0 This cell has been excluded from building
XNOR2X1.cellX309120FAILED40:00:03.296989951LVS check failed! LVS check failed!
XOR2X1.cellX309120FAILED40:00:03.341224752LVS check failed! LVS check failed!

Output files (needed by RTL2GDS tools like qflow, OpenROAD, Cadence, Synopsys, ...):

These are the resulting output files, you can download and use them with other EDA tools to build your chips:
FilenameDescription
../Documents/StdCellLib.pdfPDF Documentation of the Standard cell library
demoboard.magDemoboard: with all cells
library.gdsGDS-II file with masks for all cells, can be viewed with KLayout
libresilicon.lefLibrary Exchange Format (LEF) File with all cells
libresilicon.libLIBERTY File with Characterization of all cells, can be viewed with libertyviz
libresilicon.spSPICE netlist with all cells
If you want to build your own standard cell library, you can try our Online Standard Cell Library Generator or download the generator software and run it yourself.