NEXT CELL: INVX2 NEXT STEP: Running cell2spice NEXT STEP: Running lclayout 2020-07-20 16:18:14 tech_util INFO: Loading tech file: ../Tech/librecell_tech.py 2020-07-20 16:18:14 standalone INFO: Placement algorithm: EulerPlacer 2020-07-20 16:18:14 standalone INFO: Signal routing algorithm: DijkstraRouter 2020-07-20 16:18:14 standalone INFO: Load netlist: libresilicon.sp 2020-07-20 16:18:14 standalone INFO: Supply net: VDD 2020-07-20 16:18:14 standalone INFO: Ground net: GND 2020-07-20 16:18:14 standalone DEBUG: Rescale transistors. 2020-07-20 16:18:14 standalone DEBUG: Setup layout. 2020-07-20 16:18:14 standalone INFO: Find transistor placement 2020-07-20 16:18:14 euler_placer DEBUG: Find eulerian tours. 2020-07-20 16:18:14 euler_placer DEBUG: Number of even-degree graphs: 1 2020-07-20 16:18:14 euler_placer DEBUG: Number of eulertours: 2 2020-07-20 16:18:14 euler_placer DEBUG: Number of deduplicated eulertours: 2 2020-07-20 16:18:14 euler_placer DEBUG: Number of even-degree graphs: 1 2020-07-20 16:18:14 euler_placer DEBUG: Number of eulertours: 2 2020-07-20 16:18:14 euler_placer DEBUG: Number of deduplicated eulertours: 2 2020-07-20 16:18:14 euler_placer DEBUG: Number of NMOS placements with cyclic shifts: 2 2020-07-20 16:18:14 euler_placer DEBUG: Number of PMOS placements with cyclic shifts: 2 2020-07-20 16:18:14 euler_placer INFO: Found multiple optimal placements: 2. Take the first. 2020-07-20 16:18:14 standalone INFO: Cell placement: (Y, A, VDD) (Y, A, GND) 2020-07-20 16:18:14 standalone DEBUG: Draw transistors. 2020-07-20 16:18:14 standalone DEBUG: Draw cell template. 2020-07-20 16:18:14 routing_graph DEBUG: Create routing graph. 2020-07-20 16:18:14 routing_graph INFO: Terminal node A poly ('poly', (1040, 1230)) 2020-07-20 16:18:14 routing_graph INFO: Terminal node A poly ('poly', (1040, 480)) 2020-07-20 16:18:14 routing_graph INFO: Terminal node A poly ('poly', (1040, 3680)) 2020-07-20 16:18:14 routing_graph INFO: Terminal node A poly ('poly', (1040, 2930)) 2020-07-20 16:18:14 standalone INFO: Start routing 2020-07-20 16:18:14 standalone DEBUG: Find conflicting nodes. 2020-07-20 16:18:15 hv_router DEBUG: Start global routing with corner avoidance. 2020-07-20 16:18:15 pathfinder INFO: Start global routing. 2020-07-20 16:18:15 pathfinder DEBUG: Mean edge cost (without virtual edges): 611877.61 2020-07-20 16:18:15 pathfinder DEBUG: Pre-scaling factor for edge costs: 1/611877.61 2020-07-20 16:18:15 pathfinder INFO: Routing iteration 0 2020-07-20 16:18:15 pathfinder DEBUG: Routing order: ['Y', 'VDD', 'GND', 'A'] 2020-07-20 16:18:16 pathfinder DEBUG: weight of Y: 642752.00 2020-07-20 16:18:16 pathfinder DEBUG: weight of GND: 248252.00 2020-07-20 16:18:16 pathfinder DEBUG: weight of VDD: 248252.00 2020-07-20 16:18:16 pathfinder DEBUG: weight of A: 547252.00 2020-07-20 16:18:16 pathfinder INFO: Global routing done in 0 iterations 2020-07-20 16:18:16 pathfinder INFO: Run single-net optimizations. 2020-07-20 16:18:16 pathfinder DEBUG: Single-net optimization: Y 2020-07-20 16:18:16 pathfinder DEBUG: Old weight for Y: 1.0504584388235432 2020-07-20 16:18:16 pathfinder DEBUG: New weight for Y: 1.0504584388235432 2020-07-20 16:18:16 pathfinder DEBUG: Single-net optimization: GND 2020-07-20 16:18:16 pathfinder DEBUG: Old weight for GND: 0.40572165991676784 2020-07-20 16:18:16 pathfinder DEBUG: New weight for GND: 0.40572165991676784 2020-07-20 16:18:16 pathfinder DEBUG: Single-net optimization: VDD 2020-07-20 16:18:16 pathfinder DEBUG: Old weight for VDD: 0.40572165991676784 2020-07-20 16:18:16 pathfinder DEBUG: New weight for VDD: 0.40572165991676784 2020-07-20 16:18:16 pathfinder DEBUG: Single-net optimization: A 2020-07-20 16:18:16 pathfinder DEBUG: Old weight for A: 0.8943814746014976 2020-07-20 16:18:16 pathfinder DEBUG: New weight for A: 0.8943814746014976 2020-07-20 16:18:16 standalone DEBUG: Drawing wires 2020-07-20 16:18:16 standalone DEBUG: Draw via: diff_contact (520, 845) 2020-07-20 16:18:16 standalone DEBUG: Draw via: via1 (520, 845) 2020-07-20 16:18:16 standalone DEBUG: Draw via: via1 (520, 3315) 2020-07-20 16:18:16 standalone DEBUG: Draw via: diff_contact (520, 3315) 2020-07-20 16:18:16 standalone DEBUG: Drawing wires 2020-07-20 16:18:16 standalone DEBUG: Draw via: diff_contact (1560, 845) 2020-07-20 16:18:16 standalone DEBUG: Draw via: via1 (1560, 845) 2020-07-20 16:18:16 standalone DEBUG: Drawing wires 2020-07-20 16:18:16 standalone DEBUG: Draw via: diff_contact (1560, 3315) 2020-07-20 16:18:16 standalone DEBUG: Draw via: via1 (1560, 3315) 2020-07-20 16:18:16 standalone DEBUG: Drawing wires 2020-07-20 16:18:16 standalone DEBUG: Draw via: poly_contact (1040, 1235) 2020-07-20 16:18:16 standalone DEBUG: Draw via: via1 (1040, 1235) 2020-07-20 16:18:16 standalone DEBUG: Draw via: via1 (1040, 2925) 2020-07-20 16:18:16 standalone DEBUG: Draw via: poly_contact (1040, 2925) 2020-07-20 16:18:16 standalone INFO: No minimum area violations. 2020-07-20 16:18:16 standalone DEBUG: Add pin label: Y, (520, 845) 2020-07-20 16:18:16 standalone DEBUG: Add pin label: A, (1040, 1235) 2020-07-20 16:18:16 standalone INFO: Running LVS check 2020-07-20 16:18:16 lvs DEBUG: Loading netlist (convert MOS4 to MOS3): libresilicon.sp 2020-07-20 16:18:16 lvs DEBUG: Extracting netlist from layout 2020-07-20 16:18:16 lvs DEBUG: Netlist comparision result: True 2020-07-20 16:18:16 standalone INFO: LVS result: SUCCESS 2020-07-20 16:18:16 standalone DEBUG: Call output writer: MagWriter 2020-07-20 16:18:16 magic_writer INFO: Number of layers: 15 2020-07-20 16:18:16 magic_writer INFO: Processing cell: INVX2 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 1 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 6 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 4 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 1 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 6 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 12 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 0 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 0 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 0 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 8 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 5 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 5 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 2 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 4 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 1 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 1 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 3 2020-07-20 16:18:16 magic_writer DEBUG: Number of trapezoids: 3 2020-07-20 16:18:16 magic_writer INFO: Writing MAG file: outputlib/INVX2.mag 2020-07-20 16:18:16 standalone DEBUG: Call output writer: LefWriter 2020-07-20 16:18:16 writer DEBUG: Remap layers. 2020-07-20 16:18:16 writer WARNING: Layer 'pwell' will not be written to the output. This might be alright though. 2020-07-20 16:18:16 lef_writer DEBUG: dbu = 0.001 µm 2020-07-20 16:18:16 lef_writer DEBUG: Generate LEF MACRO structure for INVX2. 2020-07-20 16:18:16 lef_writer INFO: Write LEF: outputlib/INVX2.lef 2020-07-20 16:18:16 standalone DEBUG: Call output writer: GdsWriter 2020-07-20 16:18:16 writer DEBUG: Remap layers. 2020-07-20 16:18:16 writer WARNING: Layer 'pwell' will not be written to the output. This might be alright though. 2020-07-20 16:18:16 gds_writer DEBUG: dbu = 0.001 µm 2020-07-20 16:18:16 gds_writer INFO: Write GDS: outputlib/INVX2.gds 2020-07-20 16:18:16 standalone INFO: Done (Total duration: 0:00:02.198249) NEXT STEP: magic2 ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "mcon" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "bound" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "licon1" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "licon1" Total of 6 warnings. Warning- FET resistance not included or set to zero in technology file- All driven nodes will be extracted Port: name = VDD exists, forcing drivepoint Location is (0, 397); drivepoint (208, 397) Port: name = GND exists, forcing drivepoint Location is (0, -19); drivepoint (208, -20) Port: name = Y exists, forcing drivepoint Location is (41, 320); drivepoint (64, 73) Port: name = Y exists, forcing drivepoint Location is (41, 320); drivepoint (59, 96) Port: name = Y exists, forcing drivepoint Location is (41, 320); drivepoint (64, 320) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (116, 112) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (111, 135) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (116, 281) Couldn't find wire at 208 397 Error in extracting node VDD Couldn't find wire at 208 -20 Error in extracting node GND Couldn't find wire at 64 320 Error in extracting node Y Couldn't find wire at 116 281 Error in extracting node A Total Nets: 22 Nets extracted: 8 (0.363636) Nets output: 4 (0.181818) Port: name = VDD exists, forcing drivepoint Location is (0, 397); drivepoint (208, 397) Port: name = GND exists, forcing drivepoint Location is (0, -19); drivepoint (208, -20) Port: name = Y exists, forcing drivepoint Location is (41, 320); drivepoint (64, 73) Port: name = Y exists, forcing drivepoint Location is (41, 320); drivepoint (59, 96) Port: name = Y exists, forcing drivepoint Location is (41, 320); drivepoint (64, 320) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (116, 112) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (111, 135) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (116, 281) Couldn't find wire at 208 397 Error in extracting node VDD Couldn't find wire at 208 -20 Error in extracting node GND Couldn't find wire at 64 320 Error in extracting node Y Couldn't find wire at 116 281 Error in extracting node A Total Nets: 22 Nets extracted: 8 (0.363636) Nets output: 4 (0.181818) NEXT STEP: magic3 ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "mcon" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "bound" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "licon1" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "licon1" NEXT STEP: Generating Liberty Template ERROR: A cell without an input! NEXT STEP: Characterization Traceback (most recent call last): File "/usr/local/bin/lctime", line 11, in load_entry_point('librecell-lib==0.0.3.post0', 'console_scripts', 'lctime')() File "/usr/lib/python3/dist-packages/pkg_resources/__init__.py", line 490, in load_entry_point return get_distribution(dist).load_entry_point(group, name) File "/usr/lib/python3/dist-packages/pkg_resources/__init__.py", line 2854, in load_entry_point return ep.load() File "/usr/lib/python3/dist-packages/pkg_resources/__init__.py", line 2445, in load return self.resolve() File "/usr/lib/python3/dist-packages/pkg_resources/__init__.py", line 2451, in resolve module = __import__(self.module_name, fromlist=['__name__'], level=0) ModuleNotFoundError: No module named 'lclib.characterization.standalone' NEXT STEP: Visualisation NEXT STEP: gds2mag NEXT STEP: mag2svg