NEXT CELL: AND2X1 NEXT STEP: Running cell2spice NEXT STEP: Running lclayout 2020-07-20 16:11:47 tech_util INFO: Loading tech file: ../Tech/librecell_tech.py 2020-07-20 16:11:47 standalone INFO: Placement algorithm: EulerPlacer 2020-07-20 16:11:47 standalone INFO: Signal routing algorithm: DijkstraRouter 2020-07-20 16:11:47 standalone INFO: Load netlist: libresilicon.sp 2020-07-20 16:11:47 standalone INFO: Supply net: VDD 2020-07-20 16:11:47 standalone INFO: Ground net: GND 2020-07-20 16:11:47 standalone DEBUG: Rescale transistors. 2020-07-20 16:11:47 standalone DEBUG: Setup layout. 2020-07-20 16:11:47 standalone INFO: Find transistor placement 2020-07-20 16:11:47 euler_placer DEBUG: Find eulerian tours. 2020-07-20 16:11:47 euler_placer DEBUG: Number of even-degree graphs: 1 2020-07-20 16:11:47 euler_placer DEBUG: Number of eulertours: 2 2020-07-20 16:11:47 euler_placer DEBUG: Number of deduplicated eulertours: 2 2020-07-20 16:11:47 euler_placer DEBUG: Number of even-degree graphs: 1 2020-07-20 16:11:47 euler_placer DEBUG: Number of eulertours: 4 2020-07-20 16:11:47 euler_placer DEBUG: Number of deduplicated eulertours: 4 2020-07-20 16:11:47 euler_placer DEBUG: Number of NMOS placements with cyclic shifts: 2 2020-07-20 16:11:47 euler_placer DEBUG: Number of PMOS placements with cyclic shifts: 4 2020-07-20 16:11:47 standalone INFO: Cell placement: (VDD, A, 1) | (1, B, VDD) | (VDD, 1, Y) (1, A, 2) | (2, B, GND) | (GND, 1, Y) 2020-07-20 16:11:47 standalone DEBUG: Draw transistors. 2020-07-20 16:11:47 standalone DEBUG: Draw cell template. 2020-07-20 16:11:47 routing_graph DEBUG: Create routing graph. 2020-07-20 16:11:48 routing_graph INFO: Terminal node 1 poly ('poly', (3120, 3680)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node 1 poly ('poly', (3120, 2930)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node A poly ('poly', (1040, 1230)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node A poly ('poly', (1040, 480)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node B poly ('poly', (2080, 1230)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node B poly ('poly', (2080, 480)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node 1 poly ('poly', (3120, 1230)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node 1 poly ('poly', (3120, 480)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node A poly ('poly', (1040, 3680)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node A poly ('poly', (1040, 2930)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node B poly ('poly', (2080, 3680)) 2020-07-20 16:11:48 routing_graph INFO: Terminal node B poly ('poly', (2080, 2930)) 2020-07-20 16:11:48 standalone INFO: Start routing 2020-07-20 16:11:48 standalone DEBUG: Find conflicting nodes. 2020-07-20 16:11:52 hv_router DEBUG: Start global routing with corner avoidance. 2020-07-20 16:11:52 pathfinder INFO: Start global routing. 2020-07-20 16:11:52 pathfinder DEBUG: Mean edge cost (without virtual edges): 710104.11 2020-07-20 16:11:52 pathfinder DEBUG: Pre-scaling factor for edge costs: 1/710104.11 2020-07-20 16:11:57 pathfinder INFO: Routing iteration 0 2020-07-20 16:11:57 pathfinder DEBUG: Routing order: ['Y', 'VDD', 'GND', 'B', 'A', '2', '1'] 2020-07-20 16:11:58 pathfinder DEBUG: weight of 1: 1498757.00 2020-07-20 16:11:58 pathfinder DEBUG: weight of 2: 0.00 2020-07-20 16:11:58 pathfinder DEBUG: weight of GND: 248252.00 2020-07-20 16:11:58 pathfinder DEBUG: weight of Y: 642752.00 2020-07-20 16:11:58 pathfinder DEBUG: weight of VDD: 496504.00 2020-07-20 16:11:58 pathfinder DEBUG: weight of A: 547252.00 2020-07-20 16:11:58 pathfinder DEBUG: weight of B: 547252.00 2020-07-20 16:11:58 pathfinder INFO: Routing iteration 1 2020-07-20 16:11:58 pathfinder DEBUG: Routing order: ['1', 'Y', 'B', 'A', 'VDD', 'GND', '2'] 2020-07-20 16:11:59 pathfinder DEBUG: weight of 1: 1498756.00 2020-07-20 16:11:59 pathfinder DEBUG: weight of 2: 0.00 2020-07-20 16:11:59 pathfinder DEBUG: weight of GND: 5191504.00 2020-07-20 16:11:59 pathfinder DEBUG: weight of Y: 334000.00 2020-07-20 16:11:59 pathfinder DEBUG: weight of VDD: 5439756.00 2020-07-20 16:11:59 pathfinder DEBUG: weight of A: 336000.00 2020-07-20 16:11:59 pathfinder DEBUG: weight of B: 336000.00 2020-07-20 16:11:59 pathfinder INFO: Global routing done in 1 iterations 2020-07-20 16:11:59 pathfinder INFO: Run single-net optimizations. 2020-07-20 16:11:59 pathfinder DEBUG: Single-net optimization: 1 2020-07-20 16:11:59 pathfinder DEBUG: Old weight for 1: 2.110614465712209 2020-07-20 16:11:59 pathfinder DEBUG: New weight for 1: 2.110614465712209 2020-07-20 16:11:59 pathfinder DEBUG: Single-net optimization: 2 2020-07-20 16:11:59 pathfinder DEBUG: Old weight for 2: 0 2020-07-20 16:11:59 pathfinder DEBUG: New weight for 2: 0 2020-07-20 16:11:59 pathfinder DEBUG: Single-net optimization: GND 2020-07-20 16:11:59 pathfinder DEBUG: Old weight for GND: 7.3109054717397655 2020-07-20 16:11:59 pathfinder DEBUG: New weight for GND: 7.3109054717397655 2020-07-20 16:11:59 pathfinder DEBUG: Single-net optimization: Y 2020-07-20 16:11:59 pathfinder DEBUG: Old weight for Y: 0.4703535675906406 2020-07-20 16:11:59 pathfinder DEBUG: New weight for Y: 0.9051517852575434 2020-07-20 16:11:59 pathfinder DEBUG: Single-net optimization: VDD 2020-07-20 16:11:59 pathfinder DEBUG: Old weight for VDD: 7.660504914438905 2020-07-20 16:11:59 pathfinder DEBUG: New weight for VDD: 7.660504914438905 2020-07-20 16:11:59 pathfinder DEBUG: Single-net optimization: A 2020-07-20 16:11:59 pathfinder DEBUG: Old weight for A: 0.47317005601932705 2020-07-20 16:11:59 pathfinder DEBUG: New weight for A: 0.7706644627877642 2020-07-20 16:11:59 pathfinder DEBUG: Single-net optimization: B 2020-07-20 16:11:59 pathfinder DEBUG: Old weight for B: 0.47317005601932705 2020-07-20 16:11:59 pathfinder DEBUG: New weight for B: 0.7706644627877642 2020-07-20 16:11:59 standalone DEBUG: Drawing wires 2020-07-20 16:11:59 standalone DEBUG: Draw via: diff_contact (520, 845) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (520, 845) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (3120, 1235) 2020-07-20 16:11:59 standalone DEBUG: Draw via: poly_contact (3120, 1235) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (3120, 2925) 2020-07-20 16:11:59 standalone DEBUG: Draw via: poly_contact (3120, 2925) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (1560, 3315) 2020-07-20 16:11:59 standalone DEBUG: Draw via: diff_contact (1560, 3315) 2020-07-20 16:11:59 standalone DEBUG: Drawing wires 2020-07-20 16:11:59 standalone DEBUG: Drawing wires 2020-07-20 16:11:59 standalone DEBUG: Draw via: diff_contact (2600, 845) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (2600, 455) 2020-07-20 16:11:59 standalone DEBUG: Drawing wires 2020-07-20 16:11:59 standalone DEBUG: Draw via: diff_contact (3640, 845) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (3640, 845) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (3640, 3315) 2020-07-20 16:11:59 standalone DEBUG: Draw via: diff_contact (3640, 3315) 2020-07-20 16:11:59 standalone DEBUG: Drawing wires 2020-07-20 16:11:59 standalone DEBUG: Draw via: diff_contact (2600, 3315) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (2600, 3705) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (520, 3315) 2020-07-20 16:11:59 standalone DEBUG: Draw via: diff_contact (520, 3315) 2020-07-20 16:11:59 standalone DEBUG: Drawing wires 2020-07-20 16:11:59 standalone DEBUG: Draw via: poly_contact (1040, 1235) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (1040, 1235) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (1040, 2925) 2020-07-20 16:11:59 standalone DEBUG: Draw via: poly_contact (1040, 2925) 2020-07-20 16:11:59 standalone DEBUG: Drawing wires 2020-07-20 16:11:59 standalone DEBUG: Draw via: poly_contact (2080, 1235) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (2080, 1235) 2020-07-20 16:11:59 standalone DEBUG: Draw via: via1 (2080, 2925) 2020-07-20 16:11:59 standalone DEBUG: Draw via: poly_contact (2080, 2925) 2020-07-20 16:11:59 standalone INFO: No minimum area violations. 2020-07-20 16:11:59 standalone DEBUG: Add pin label: Y, (3640, 845) 2020-07-20 16:11:59 standalone DEBUG: Add pin label: A, (1040, 1235) 2020-07-20 16:11:59 standalone DEBUG: Add pin label: B, (2080, 1235) 2020-07-20 16:11:59 standalone INFO: Running LVS check 2020-07-20 16:11:59 lvs DEBUG: Loading netlist (convert MOS4 to MOS3): libresilicon.sp 2020-07-20 16:11:59 lvs DEBUG: Extracting netlist from layout 2020-07-20 16:11:59 lvs DEBUG: Netlist comparision result: True 2020-07-20 16:11:59 standalone INFO: LVS result: SUCCESS 2020-07-20 16:11:59 standalone DEBUG: Call output writer: MagWriter 2020-07-20 16:11:59 magic_writer INFO: Number of layers: 15 2020-07-20 16:11:59 magic_writer INFO: Processing cell: AND2X1 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 1 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 13 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 12 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 1 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 15 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 28 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 0 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 0 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 0 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 11 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 7 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 9 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 6 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 7 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 1 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 1 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 3 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 3 2020-07-20 16:11:59 magic_writer DEBUG: Number of trapezoids: 3 2020-07-20 16:11:59 magic_writer INFO: Writing MAG file: outputlib/AND2X1.mag 2020-07-20 16:11:59 standalone DEBUG: Call output writer: LefWriter 2020-07-20 16:11:59 writer DEBUG: Remap layers. 2020-07-20 16:11:59 writer WARNING: Layer 'pwell' will not be written to the output. This might be alright though. 2020-07-20 16:11:59 lef_writer DEBUG: dbu = 0.001 µm 2020-07-20 16:11:59 lef_writer DEBUG: Generate LEF MACRO structure for AND2X1. 2020-07-20 16:11:59 lef_writer INFO: Write LEF: outputlib/AND2X1.lef 2020-07-20 16:11:59 standalone DEBUG: Call output writer: GdsWriter 2020-07-20 16:11:59 writer DEBUG: Remap layers. 2020-07-20 16:11:59 writer WARNING: Layer 'pwell' will not be written to the output. This might be alright though. 2020-07-20 16:11:59 gds_writer DEBUG: dbu = 0.001 µm 2020-07-20 16:11:59 gds_writer INFO: Write GDS: outputlib/AND2X1.gds 2020-07-20 16:11:59 standalone INFO: Done (Total duration: 0:00:11.194777) NEXT STEP: magic2 ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "mcon" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "bound" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "licon1" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "licon1" Total of 9 warnings. Warning- FET resistance not included or set to zero in technology file- All driven nodes will be extracted Port: name = VDD exists, forcing drivepoint Location is (0, 397); drivepoint (416, 397) Port: name = GND exists, forcing drivepoint Location is (0, -19); drivepoint (416, -20) Port: name = Y exists, forcing drivepoint Location is (353, 320); drivepoint (376, 73) Port: name = Y exists, forcing drivepoint Location is (353, 320); drivepoint (371, 96) Port: name = Y exists, forcing drivepoint Location is (353, 320); drivepoint (376, 320) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (116, 112) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (111, 135) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (116, 281) Port: name = B exists, forcing drivepoint Location is (197, 281); drivepoint (220, 112) Port: name = B exists, forcing drivepoint Location is (197, 281); drivepoint (215, 135) Port: name = B exists, forcing drivepoint Location is (197, 281); drivepoint (220, 281) Couldn't find wire at 416 397 Error in extracting node VDD Couldn't find wire at 416 -20 Error in extracting node GND Couldn't find wire at 376 320 Error in extracting node Y Couldn't find wire at 116 281 Error in extracting node A Couldn't find wire at 220 281 Error in extracting node B Total Nets: 40 Nets extracted: 13 (0.325000) Nets output: 8 (0.200000) Port: name = VDD exists, forcing drivepoint Location is (0, 397); drivepoint (416, 397) Port: name = GND exists, forcing drivepoint Location is (0, -19); drivepoint (416, -20) Port: name = Y exists, forcing drivepoint Location is (353, 320); drivepoint (376, 73) Port: name = Y exists, forcing drivepoint Location is (353, 320); drivepoint (371, 96) Port: name = Y exists, forcing drivepoint Location is (353, 320); drivepoint (376, 320) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (116, 112) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (111, 135) Port: name = A exists, forcing drivepoint Location is (93, 281); drivepoint (116, 281) Port: name = B exists, forcing drivepoint Location is (197, 281); drivepoint (220, 112) Port: name = B exists, forcing drivepoint Location is (197, 281); drivepoint (215, 135) Port: name = B exists, forcing drivepoint Location is (197, 281); drivepoint (220, 281) Couldn't find wire at 416 397 Error in extracting node VDD Couldn't find wire at 416 -20 Error in extracting node GND Couldn't find wire at 376 320 Error in extracting node Y Couldn't find wire at 116 281 Error in extracting node A Couldn't find wire at 220 281 Error in extracting node B Total Nets: 40 Nets extracted: 13 (0.325000) Nets output: 8 (0.200000) NEXT STEP: magic3 ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "mcon" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "bound" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "licon1" ../Tech/libresilicon.tech: line 3781: section (none): Unrecognized layer (type) name "licon1" NEXT STEP: Generating Liberty Template NEXT STEP: Characterization Traceback (most recent call last): File "/usr/local/bin/lctime", line 11, in load_entry_point('librecell-lib==0.0.3.post0', 'console_scripts', 'lctime')() File "/usr/lib/python3/dist-packages/pkg_resources/__init__.py", line 490, in load_entry_point return get_distribution(dist).load_entry_point(group, name) File "/usr/lib/python3/dist-packages/pkg_resources/__init__.py", line 2854, in load_entry_point return ep.load() File "/usr/lib/python3/dist-packages/pkg_resources/__init__.py", line 2445, in load return self.resolve() File "/usr/lib/python3/dist-packages/pkg_resources/__init__.py", line 2451, in resolve module = __import__(self.module_name, fromlist=['__name__'], level=0) ModuleNotFoundError: No module named 'lclib.characterization.standalone' NEXT STEP: Visualisation NEXT STEP: gds2mag NEXT STEP: mag2svg