Build Report

Generated: Thu Jul 16 21:00:47 2020 by LibreSilicon Standard Cell Library Generator

Input files: PDK, DRC, layer definitions, process parameters:

These input files are necessary to define the rules and parameters for the standard cell library. All those files are collected in the Tech directory.
FilenameDescription
XDRC rules for KLayout GDS Viewer
√librecell_tech.pyCell layouting rules, DRC
√libresilicon.mTransistor BSIM model SPICE parameters (*.lib files in other tools)
√libresilicon.techMagic Layers and Parasitic extraction parameters
√template.lefTemplate for the header of Library Exchange Format LEF Files
√transistor.spTransistor size template for SPICE models

Standard Cells:

These are the generated standard cells. You can click on the green ticks and the error messages to get more details or download the files. By moving the mouse over the header line you will get explanations for each column.
CellcellMagicLayoutSchematicLogErrLibertyLEFGDSSPICEParasiticAreaLVSEulerLayoutTimeNetsPortsIterat.Errors
AND2X1.cell√√√X√√X√√√√SUCCESS40:00:31.35047210531
AND2X2.cell√√√X√√X√√√√SUCCESS40:00:32.27625710531
AOI21X1.cell√√√X√√X√√√√SUCCESS80:00:33.84107411635
AOI22X1.cell√√√X√√X√√√√SUCCESS80:01:19.44964413754
BUFX2.cell√√√X√√X√√√√SUCCESS20:00:15.8932118434
BUFX4.cell√√√X√√X√√√√SUCCESS40:00:31.8200859433
CLKBUF1.cell√√√X√√X√√√√SUCCESS20:03:25.90607116439
CLKBUF2.cell√√√X√√X√√√√SUCCESS20:07:55.91091722437
CLKBUF3.cell√XXX√√XXXXX0
DFFNEGX1.cell√√√X√√X√√√√SUCCESS20:09:16.25243629536
DFFPOSX1.cell√√√X√√X√√√√SUCCESS20:11:47.60263929555
DFFSR.cell√√XX√√XXX√√20122
FAX1.cell√√XX√√XXX√√0
FILL.cell√√XX√√XXX√√0A cell without an input!
HAX1.cell√√XX√√XXX√√0A cell without an input!
INV.cell√√XX√√XXX√√0A cell without an input!
INVX1.cell√√XX√√XXX√√0A cell without an input!
INVX2.cell√√XX√√XXX√√0A cell without an input!
INVX4.cell√√XX√√XXX√√0A cell without an input!
INVX8.cell√√XX√√XXX√√0A cell without an input!
LATCH.cell√√XX√√XXX√√0A cell without an input!
MUX2X1.cell√√XX√√XXX√√0A cell without an input!
NAND2X1.cell√√XX√√XXX√√0A cell without an input!
NAND3X1.cell√√XX√√XXX√√0A cell without an input!
NOR2X1.cell√√XX√√XXX√√0A cell without an input!
NOR3X1.cell√√XX√√XXX√√0A cell without an input!
OAI21X1.cell√√XX√√XXX√√0A cell without an input!
OAI22X1.cell√√XX√√XXX√√0A cell without an input!
OR2X1.cell√√XX√√XXX√√0A cell without an input!
OR2X2.cell√√XX√√XXX√√0A cell without an input!
PADINC.cell√√XX√√XXX√√0A cell without an input!
PADINOUT.cell√√XX√√XXX√√0A cell without an input!
PADOUT.cell√√XX√√XXX√√0A cell without an input!
TBUFX1.cell√√XX√√XXX√√0A cell without an input!
TBUFX2.cell√√XX√√XXX√√0A cell without an input!
XNOR2X1.cell√√XX√√XXX√√0A cell without an input!
XOR2X1.cell√√XX√√XXX√√0A cell without an input!

Output files (needed by RTL2GDS tools like qflow, OpenROAD, Cadence, Synopsys, ...):

These are the resulting output files, you can download and use them with other EDA tools to build your chips:
FilenameDescription
√ ../Documents/StdCellLib.pdfPDF Documentation of the Standard cell library
Xdemoboard.magDemoboard: with all cells
√ library.gdsGDS-II file with masks for all cells, can be viewed with KLayout
√ libresilicon.lefLibrary Exchange Format (LEF) File with all cells
Xlibresilicon.libLIBERTY File with Characterization of all cells, can be viewed with libertyviz
Xlibresilicon.spSPICE netlist with all cells
If you want to build your own standard cell library, you can try our Online Standard Cell Library Generator or download the generator software and run it yourself.