%%  ************    LibreSilicon's StdCellLibrary   *******************
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%%  Organisation:   Chipforge
%%                  Germany / European Union
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%%  Profile:        Chipforge focus on fine System-on-Chip Cores in
%%                  Verilog HDL Code which are easy understandable and
%%                  adjustable. For further information see
%%                          www.chipforge.org
%%                  there are projects from small cores up to PCBs, too.
%%
%%  File:           StdCellLib/Documents/LaTeX/OAI31_schematic.tex
%%
%%  Purpose:        Auto-generated Schematic File for OAI31
%%
%%  ************    LaTeX with circdia.sty package      ***************
%%
%%  ///////////////////////////////////////////////////////////////////
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%%  Copyright (c) 2020 by chipforge <hsank@nospam.chipforge.org>
%%  All rights reserved.
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%%      This Standard Cell Library is licensed under the Libre Silicon
%%      public license; you can redistribute it and/or modify it under
%%      the terms of the Libre Silicon public license as published by
%%      the Libre Silicon alliance, either version 1 of the License, or
%%      (at your option) any later version.
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%%      This design is distributed in the hope that it will be useful,
%%      but WITHOUT ANY WARRANTY; without even the implied warranty of
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%%      See the Libre Silicon Public License for more details.
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%%  ///////////////////////////////////////////////////////////////////
\begin{center}
    Schematic (one stage, 3$T_{p}$/2$T_{n}$ stacked, 8$T$ total)
    \begin{figure}[h]
        \begin{center}
            \begin{circuitdiagram}{36}{32}
                % ---- '*PA' pmos pattern ----
                \trans[\wireUD{0.5}]{penh*}{7}{16}{R}{}{$*_{PA}$}
                \pin{4}{17.5}{L}{A}
                % ---- '*PB' pmos pattern ----
                \trans[\wireUD{0.5}]{penh*}{16}{16}{R}{}{$*_{PB}$}
                \pin{13}{17.5}{L}{B}
                \wire{9}{13}{18}{13}
                \power{9}{19}{U}{}
                % ---- '*PB1' pmos pattern ----
                \trans[\wireUD{0.5}]{penh*}{16}{22}{R}{}{$*_{PB1}$}
                \pin{13}{23.5}{L}{B1}
                % ---- '*PB2' pmos pattern ----
                \trans[\wireUD{0.5}]{penh*}{16}{28}{R}{}{$*_{PB2}$}
                \pin{13}{29.5}{L}{B2}
                \power{18}{31}{U}{}
                % ---- '*NA' nmos pattern ----
                \trans[\wireUD{0.5}]{nenh*}{7}{10}{R}{$*_{NA}$}{}
                \pin{4}{8.5}{L}{A}
                % ---- '*NB' nmos pattern ----
                \trans[\wireUD{0.5}]{nenh*}{7}{4}{R}{$*_{NB}$}{}
                \pin{4}{2.5}{L}{B}
                % ---- '*NB1' nmos pattern ----
                \trans[\wireUD{0.5}]{nenh*}{16}{4}{R}{$*_{NB1}$}{}
                \pin{13}{2.5}{L}{B1}
                \wire{9}{7}{18}{7}
                % ---- '*NB2' nmos pattern ----
                \trans[\wireUD{0.5}]{nenh*}{25}{4}{R}{$*_{NB2}$}{}
                \pin{22}{2.5}{L}{B2}
                \wire{18}{7}{27}{7}
                \ground{9}{1}{D}
                \ground{18}{1}{D}
                \ground{27}{1}{D}
                % ---- output pattern ----
                \pin{31}{13}{R}{Y}
                \wire{27}{13}{30}{13}
                \wire{9}{13}{27}{13}
            \end{circuitdiagram}
        \end{center}
    \end{figure}
\end{center}
