Build Report

Generated: Mon Jun 22 23:49:32 2020 by LibreSilicon Standard Cell Library Generator

Input files: PDK, DRC, layer definitions, process parameters:

These input files are necessary to define the rules and parameters for the standard cell library. All those files are collected in the Tech directory.

Filename	Description
√drc.lydrc	DRC rules for KLayout GDS Viewer
√librecell_tech.py	Cell layouting rules, DRC
√libresilicon.m	Transistor BSIM model SPICE parameters (*.lib files in other tools)
√libresilicon.tech	Magic Layers and Parasitic extraction parameters
√template.lef	Template for the header of Library Exchange Format LEF Files
√transistor.sp	Transistor size template for SPICE models

Standard Cells:

These are the generated standard cells. You can click on the green ticks and the error messages to get more details or download the files. By moving the mouse over the header line you will get explanations for each column.

Cell	cell	Magic	Layout	Schematic	Log	Err	Liberty	LEF	GDS	SPICE	Parasitic	Area	LVS	Euler	LayoutTime	Nets	Ports	Iterat.	Errors
AND2X1.cell	√	√	√	X	√	√	√	√	√	√	√	4480	SUCCESS	4	0:00:14.308488	10	5	1
AND2X2.cell	√	√	√	X	√	√	√	√	√	√	√	4480	SUCCESS	4	0:00:14.873796	10	5	0
AND4.cell	√	√	√	√	√	√	X	√	√	√	√			2		13	7
AOI21.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:13.985061	8	5	17
AOI21X1.cell	√	√	√	X	√	√	√	√	√	√	√	4480	SUCCESS	8	0:00:28.264019	11	6	19
AOI22X1.cell	√	√	√	X	√	√	√	√	√	√	√	5600	SUCCESS	8	0:00:50.100954	13	7	19
AOI31.cell	√	√	√	√	√	√	√	√	√	√	√	5600	SUCCESS	24	0:00:53.808709	13	7	23
BUFX2.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:08.541148	8	4	1
BUFX4.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	4	0:00:33.556017	9	4	23
CLKBUF1.cell	√	√	√	X	√	√	√	√	√	√	√	10080	SUCCESS	2	0:02:42.508960	16	4	16
CLKBUF2.cell	√	√	√	X	√	√	X	√	√	√	√					17	4
CLKBUF3.cell	√	X	X	X	√	√	X	X	X	√	X						0
DFFNEGX1.cell	√	√	√	X	√	√	X	√	√	√	√					20	5
DFFPOSX1.cell	√	√	√	X	√	√	X	√	√	√	√					20	5
DFFSR.cell	√	√	√	X	√	√	X	X	X	√	√						0
FAX1.cell	√	√	√	X	√	√	√	X	X	√	√	1		2			0	999	Failed to route
HAX1.cell	√	√	√	X	√	√	√	√	√	√	√	11200	SUCCESS	2	0:03:13.436315	19	6	18
INV.cell	√	√	√	X	√	√	√	√	√	√	√	2240	SUCCESS	2	0:00:02.712364	6	4	0
INVX1.cell	√	√	√	√	√	√	√	√	√	√	√	2240	SUCCESS	2	0:00:03.098411	6	4	0
INVX2.cell	√	√	√	√	√	√	√	√	√	√	√	2240	SUCCESS	2	0:00:03.039959	6	4	0
INVX4.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:16.610362	7	4	17
INVX8.cell	√	√	√	√	√	√	√	√	√	√	√	5600	SUCCESS	24	0:01:11.768080	9	4	22
LATCH.cell	√	√	√	X	√	√	X	√	√	√	√					12	5
MUX2X1.cell	√	√	√	√	√	√	√	√	√	√	√	6720	SUCCESS	4	0:00:41.299097	15	6	5
NAND2.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:14.132035	8	5	17
NAND2X1.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:10.397427	8	5	9
NAND3.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	24	0:00:25.982292	10	6	17
NAND3X1.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	24	0:00:21.739842	10	6	10
NOR2.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:14.585332	9	5	17
NOR2X1.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:14.625036	9	5	17
NOR3.cell	√	√	√	√	√	√	√	√	√	√	√	4480	SUCCESS	2	0:00:27.015403	12	6	17
NOR3X1.cell	√	√	√	X	√	√	√	√	√	√	√	7840	SUCCESS	16	0:38:00.252674	12	6	876
OAI21.cell	√	√	√	√	√	√	√	√	√	√	√	3360	SUCCESS	2	0:00:14.986484	9	5	17
OAI21X1.cell	√	√	√	X	√	√	√	√	√	√	√	4480	SUCCESS	2	0:00:29.980252	11	6	19
OAI22X1.cell	√	√	√	X	√	√	√	√	√	√	√	5600	SUCCESS	2	0:00:46.769392	14	7	17
OAI31.cell	√	√	√	√	√	√	√	√	√	√	√	5600	SUCCESS	2	0:00:47.412870	14	7	18
OR2X1.cell	√	√	√	X	√	√	√	√	√	√	√	4480	SUCCESS	2	0:00:16.340687	11	5	2
OR2X2.cell	√	√	√	X	√	√	√	√	√	√	√	4480	SUCCESS	2	0:00:15.391811	11	5	2
OR4.cell	√	√	√	√	√	√	√	√	√	√	√	6720	SUCCESS	2	0:00:48.432393	17	7	6
PADINC.cell	√	√	√	X	√	√	X	X	X	√	√						0
PADINOUT.cell	√	√	√	X	√	√	X	X	X	√	√						0
PADOUT.cell	√	√	√	X	√	√	X	X	X	√	√						0
TBUFX1.cell	√	√	√	√	√	√	X	√	√	√	√					9	5
TBUFX2.cell	√	√	√	X	√	√	X	X	X	√	√						0
XNOR2X1.cell	√	√	√	√	√	√	√	√	√	√	√	7840	SUCCESS	4	0:01:19.674010	16	5	17
XOR2X1.cell	√	√	√	√	√	√	√	√	√	√	√	7840	SUCCESS	4	0:02:23.975312	16	5	57

Output files (needed by RTL2GDS tools like qflow, OpenROAD, Cadence, Synopsys, ...):

These are the resulting output files, you can download and use them with other EDA tools to build your chips:

Filename	Description
√ ../Documents/StdCellLib.pdf	PDF Documentation of the Standard cell library
√ demoboard.mag	Demoboard: with all cells
√ library.gds	GDS-II file with masks for all cells, can be viewed with KLayout
√ libresilicon.lef	Library Exchange Format (LEF) File with all cells
√ libresilicon.lib	LIBERTY File with Characterization of all cells, can be viewed with libertyviz
√ libresilicon.sp	SPICE netlist with all cells

If you want to build your own standard cell library, you can try our Online Standard Cell Library Generator or download the generator software and run it yourself.