Build Report

Generated: Fri Apr 17 17:30:45 2020

Input files: PDK, DRC, layer definitions, parameters:

FilenameDescription
drc.lydrcDRC for KLayout
librecell_tech.pyCell layouting rules, DRC
libresilicon.mTransitor BSIM parameters
libresilicon.techMagic Layers and Parasitic extraction parameters
template.lefTemplate for LEF Files
transistor.spTransistor size template for SPICE models

Standard Cells:

CellcellMagSVGLogErrLibertyLEFGDSParasiticAreaLVSEulerLayoutTimeNetsPortsIterat.Errors
AND2X1.cell4480SUCCESS40:00:13.9093931351
AND2X2.cell4480SUCCESS40:00:13.9673961351
AOI21X1.cell4480SUCCESS80:00:26.99563514619
AOI22X1.cell5600SUCCESS80:00:42.52853917716
BUFX2.cell3360SUCCESS20:00:07.4099041041
BUFX4.cell4480FAILED49423LVS check failed!
CLKBUF1.cell10080FAILED21649LVS check failed!
CLKBUF2.cell14560FAILED222411LVS check failed!
CLKBUF3.cellXXXXXX0
DFFNEGX1.cellX295A cell without an input!
DFFPOSX1.cellXX285
DFFSR.cellX276999Failed to route Supplied boolean function and simulation are inconsistent.
FAX1.cell17664000236999Failed to route
FILL.cellXXX0Cell has no input pins.
HAX1.cell11200SUCCESS20:03:02.18349326622
INV.cell2240SUCCESS20:00:03.058350840
INVX1.cell2240SUCCESS20:00:03.103704840
INVX2.cell2240SUCCESS20:00:03.049226840
INVX4.cell1104FAILED28318LVS check failed!
INVX8.cell1840FAILED2412317LVS check failed!
LATCH.cellXSUCCESS40:00:59.9936611959Supplied boolean function and simulation are inconsistent.
MUX2X1.cell6720SUCCESS40:00:39.0151051866
NAND2X1.cell3360SUCCESS20:00:10.5325331159
NAND3X1.cell4480SUCCESS240:00:19.74764114610
NOR2X1.cell3360SUCCESS20:00:13.31316211517
NOR3X1.cell7728000FAILED1633188LVS check failed!
OAI21.cell3360SUCCESS20:00:13.16516711517
OAI21X1.cell4480SUCCESS20:00:26.71194914619
OAI22X1.cell5600SUCCESS20:00:41.49935317716
OR2X1.cell4480SUCCESS20:00:14.4165381352
OR2X2.cell4480SUCCESS20:00:14.3549291352
PADINC.cellXXX00A cell without an input! Cell has no input pins.
PADINOUT.cellXXX00A cell without an input! Cell has no input pins.
PADOUT.cellXXX00A cell without an input! Cell has no input pins.
TBUFX1.cellXSUCCESS20:00:12.6349201351Supplied boolean function and simulation are inconsistent.
TBUFX2.cellX832999Failed to route Supplied boolean function and simulation are inconsistent.
XNOR2X1.cell7840SUCCESS40:01:15.27838819515
XOR2X1.cell7840SUCCESS40:01:54.02673119538

Output files:

FilenameDescription
../Documents/StdCellLib.pdfPDF Documentation of the Standard cell library
library.gdsGDS-II file with masks for all cells
libresilicon.lefLEF File with all cells
libresilicon.libLIBERTY File with Characterization of all cells
libresilicon.spSPICE netlist with all cells