OK area : 0;
OK area : 176;
    capacitance : 0;
    capacitance : 0.00453706;
 capacitance model : typ
  capacitive_load_unit (1,pf);
      cell_fall(delay_template_5x1) {
      cell_fall(delay_template_5x5) {
      cell_fall(delay_template_5x6) {
      cell_fall(delay_template_6x6) {
  cell_footprint : buf;
  cell_leakage_power : 0.0221741;
  cell_leakage_power : 0.745304;

      cell_rise(delay_template_5x1) {
      cell_rise(delay_template_5x5) {
      cell_rise(delay_template_5x6) {
      cell_rise(delay_template_6x6) {

 check model :       typ
    clear_preset_var1 : L;
    clear : "(!R)";
    clocked_on : "(!CLK)";
    clocked_on : "CLK";
    clock : true;
  current_unit : "1uA";
    data_in : "D";
  default_operating_conditions : typical;
  delay_model : table_lookup;
 delay model :       typ
    direction : input;
    direction : output;
    enable : "CLK";
    fall_capacitance : 0;
    fall_capacitance : 0.00453706;
    fall_capacitance : 0.0746269;
      fall_constraint(hold_template_3x5) {
      fall_constraint(hold_template_3x6) {
      fall_constraint(setup_template_3x5) {
      fall_constraint(setup_template_3x6) {
      fall_power(energy_template_5x5) {
      fall_power(energy_template_5x6) {
      fall_power(energy_template_6x6) {
      fall_power(passive_energy_template_5x1) {
      fall_power(passive_energy_template_6x1) {
      fall_transition(delay_template_5x1) {
      fall_transition(delay_template_5x5) {
      fall_transition(delay_template_5x6) {
      fall_transition(delay_template_6x6) {
  ff (DS0000,P0002) {
  ff (P0002,P0003) {
    function : "DS0000";
    function : "P0002";
  in_place_swap_mode : match_footprint;
  input_threshold_pct_fall : 50;
  input_threshold_pct_rise : 50;
    internal_power() {
  latch (DS0000,P0000) {
  leakage_power_unit : "1nW";
library(osu018_stdcells) {
    max_capacitance : 0.481203;
    max_capacitance : 3.93763;
    min_pulse_width_high : 0.0939412;
    min_pulse_width_high : 0.283301;
    min_pulse_width_low : 0.09927;
    min_pulse_width_low : 0.205581;
    next_state : "D";
  nom_process : 1;
  nom_temperature : 25;
  nom_voltage : 1.8;
  operating_conditions ( typical ) {
 other model :       typ
  output_threshold_pct_fall : 50;
  output_threshold_pct_rise : 50;
    power(energy_template_6x6) {
  power_lut_template(energy_template_5x5) {
  power_lut_template(energy_template_5x6) {
  power_lut_template(energy_template_6x6) {
  power_lut_template(passive_energy_template_5x1) {
  power_lut_template(passive_energy_template_6x1) {
 power model :       typ
    preset : "(!S)";
     process : 1;
  pulling_resistance_unit : "1kohm";
      related_pin : "A";
      related_pin : "B";
      related_pin : "C";
      related_pin : "CLK";
      related_pin : "D";
      related_pin : "EN";
      related_pin : "R";
      related_pin : "S";
    rise_capacitance : 0;
    rise_capacitance : 0.0139855;
    rise_capacitance : 0.0745842;
      rise_constraint(hold_template_3x5) {
      rise_constraint(hold_template_3x6) {
      rise_constraint(recovery_template_3x6) {
      rise_constraint(recovery_template_6x6) {
      rise_constraint(removal_template_3x6) {
      rise_constraint(setup_template_3x5) {
      rise_constraint(setup_template_3x6) {
      rise_power(energy_template_5x5) {
      rise_power(energy_template_5x6) {
      rise_power(energy_template_6x6) {
      rise_power(passive_energy_template_5x1) {
      rise_power(passive_energy_template_6x1) {
      rise_transition(delay_template_5x1) {
      rise_transition(delay_template_5x5) {
      rise_transition(delay_template_5x6) {
      rise_transition(delay_template_6x6) {
      sdf_cond : "\~D\&R";
      sdf_cond : "D\&S";
      sdf_cond : "S\&R";
  slew_lower_threshold_pct_fall : 20;
  slew_lower_threshold_pct_rise : 20;
  slew_upper_threshold_pct_fall : 80;
  slew_upper_threshold_pct_rise : 80;
     temperature : 25;
    three_state : "(!EN)";
  time_unit : "1ns";
    timing() {
      timing_sense : negative_unate;
      timing_sense : non_unate;
      timing_sense : positive_unate;
      timing_type : clear;
      timing_type : falling_edge;
      timing_type : hold_falling;
      timing_type : hold_rising;
      timing_type : preset;
      timing_type : recovery_rising;
      timing_type : removal_rising;
      timing_type : rising_edge;
      timing_type : setup_falling;
      timing_type : setup_rising;
      timing_type : three_state_disable;
      timing_type : three_state_enable;
    variable_1 : input_net_transition;
    variable_1 : input_transition_time;
    variable_1 : related_pin_transition;
    variable_1 : total_output_net_capacitance;
    variable_2 : constrained_pin_transition;
    variable_2 : input_net_transition;
    variable_2 : input_transition_time;
     voltage : 1.8;
  voltage_unit : "1V";
      when : "!D&R";
      when : "D&S";
      when : "S&R";