Reports:

Submodule: user_proj_example

###############################################
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: openram_tc_1kb-alpha-1-457-gc86ca2f
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example
[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
mergeLef.py : Merging LEFs
NAND3X1.lef: SITEs matched found: 0
NAND3X1.lef: MACROs matched found: 1
INVX8.lef: SITEs matched found: 0
INVX8.lef: MACROs matched found: 1
OAI21X1.lef: SITEs matched found: 0
OAI21X1.lef: MACROs matched found: 1
INVX4.lef: SITEs matched found: 0
INVX4.lef: MACROs matched found: 1
OAI22X1.lef: SITEs matched found: 0
OAI22X1.lef: MACROs matched found: 1
XOR2X1.lef: SITEs matched found: 0
XOR2X1.lef: MACROs matched found: 1
BUFX4.lef: SITEs matched found: 0
BUFX4.lef: MACROs matched found: 1
NOR2X1.lef: SITEs matched found: 0
NOR2X1.lef: MACROs matched found: 1
HAX1.lef: SITEs matched found: 0
HAX1.lef: MACROs matched found: 1
LATCH.lef: SITEs matched found: 0
LATCH.lef: MACROs matched found: 1
AOI21X1.lef: SITEs matched found: 0
AOI21X1.lef: MACROs matched found: 1
BUFX2.lef: SITEs matched found: 0
BUFX2.lef: MACROs matched found: 1
OR2X1.lef: SITEs matched found: 0
OR2X1.lef: MACROs matched found: 1
NAND2X1.lef: SITEs matched found: 0
NAND2X1.lef: MACROs matched found: 1
INVX2.lef: SITEs matched found: 0
INVX2.lef: MACROs matched found: 1
NOR3X1.lef: SITEs matched found: 0
NOR3X1.lef: MACROs matched found: 1
AND2X2.lef: SITEs matched found: 0
AND2X2.lef: MACROs matched found: 1
OR2X2.lef: SITEs matched found: 0
OR2X2.lef: MACROs matched found: 1
TBUFX2.lef: SITEs matched found: 0
TBUFX2.lef: MACROs matched found: 1
AOI22X1.lef: SITEs matched found: 0
AOI22X1.lef: MACROs matched found: 1
CLKBUF1.lef: SITEs matched found: 0
CLKBUF1.lef: MACROs matched found: 1
XNOR2X1.lef: SITEs matched found: 0
XNOR2X1.lef: MACROs matched found: 1
AND2X1.lef: SITEs matched found: 0
AND2X1.lef: MACROs matched found: 1
TBUFX1.lef: SITEs matched found: 0
TBUFX1.lef: MACROs matched found: 1
INVX1.lef: SITEs matched found: 0
INVX1.lef: MACROs matched found: 1
INV.lef: SITEs matched found: 0
INV.lef: MACROs matched found: 1
mergeLef.py : Merging LEFs complete
[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX8.lef /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef /project/openlane/user_proj_example/../../cells/lef/XOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX4.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/HAX1.lef /project/openlane/user_proj_example/../../cells/lef/LATCH.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/NOR3X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X2.lef /project/openlane/user_proj_example/../../cells/lef/TBUFX2.lef /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef /project/openlane/user_proj_example/../../cells/lef/CLKBUF1.lef /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/TBUFX1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...
Reading /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib as a blackbox

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Liberty frontend.
Imported 24 cell types from liberty file.

3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation.
Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:9.1-16.10.
Generating RTLIL representation for module `\AND2X1'.
Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:18.1-25.10.
Generating RTLIL representation for module `\AND2X2'.
Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:27.1-35.10.
Generating RTLIL representation for module `\OR2X1'.
Replacing existing blackbox module `\OR2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:37.1-45.10.
Generating RTLIL representation for module `\OR2X2'.
Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:47.1-55.10.
Generating RTLIL representation for module `\NOR2X1'.
Generating RTLIL representation for module `\NOR2X2'.
Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:67.1-73.10.
Generating RTLIL representation for module `\INV'.
Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:75.1-81.10.
Generating RTLIL representation for module `\INVX1'.
Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:82.1-88.10.
Generating RTLIL representation for module `\INVX2'.
Generating RTLIL representation for module `\INVX3'.
Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:96.1-102.10.
Generating RTLIL representation for module `\INVX4'.
Generating RTLIL representation for module `\BUFX1'.
Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:111.1-117.10.
Generating RTLIL representation for module `\BUFX2'.
Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:119.1-128.10.
Generating RTLIL representation for module `\AOI21X1'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:47: Warning: Identifier `\vccd1' is implicitly declared.
/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:48: Warning: Identifier `\vssd1' is implicitly declared.
Successfully finished Verilog frontend.

6. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/hierarchy.dot'.
Dumping module user_proj_example to page 1.

7. Executing HIERARCHY pass (managing design hierarchy).

7.1. Analyzing design hierarchy..
Top module:  \user_proj_example

7.2. Analyzing design hierarchy..
Top module:  \user_proj_example
Removed 0 unused modules.

8. Executing SYNTH pass.

8.1. Executing HIERARCHY pass (managing design hierarchy).

8.1.1. Analyzing design hierarchy..
Top module:  \user_proj_example

8.1.2. Analyzing design hierarchy..
Top module:  \user_proj_example
Removed 0 unused modules.

8.2. Executing PROC pass (convert processes to netlists).

8.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

8.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

8.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

8.2.4. Executing PROC_INIT pass (extract init attributes).

8.2.5. Executing PROC_ARST pass (detect async resets in processes).

8.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).

8.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

8.2.8. Executing PROC_DFF pass (convert process syncs to FFs).

8.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

8.3. Executing FLATTEN pass (flatten design).

8.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.6. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.
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Warning: Wire user_proj_example.\la_data_out [21] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [18] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [17] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [15] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [13] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [10] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [6] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [3] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.
Warning: Wire user_proj_example.\io_out [37] is used but has no driver.
Warning: Wire user_proj_example.\io_out [36] is used but has no driver.
Warning: Wire user_proj_example.\io_out [35] is used but has no driver.
Warning: Wire user_proj_example.\io_out [34] is used but has no driver.
Warning: Wire user_proj_example.\io_out [33] is used but has no driver.
Warning: Wire user_proj_example.\io_out [32] is used but has no driver.
Warning: Wire user_proj_example.\io_out [31] is used but has no driver.
Warning: Wire user_proj_example.\io_out [30] is used but has no driver.
Warning: Wire user_proj_example.\io_out [29] is used but has no driver.
Warning: Wire user_proj_example.\io_out [27] is used but has no driver.
Warning: Wire user_proj_example.\io_out [26] is used but has no driver.
Warning: Wire user_proj_example.\io_out [24] is used but has no driver.
Warning: Wire user_proj_example.\io_out [23] is used but has no driver.
Warning: Wire user_proj_example.\io_out [21] is used but has no driver.
Warning: Wire user_proj_example.\io_out [20] is used but has no driver.
Warning: Wire user_proj_example.\io_out [18] is used but has no driver.
Warning: Wire user_proj_example.\io_out [16] is used but has no driver.
Warning: Wire user_proj_example.\io_out [14] is used but has no driver.
Warning: Wire user_proj_example.\io_out [12] is used but has no driver.
Warning: Wire user_proj_example.\io_out [10] is used but has no driver.
Warning: Wire user_proj_example.\io_out [8] is used but has no driver.
Warning: Wire user_proj_example.\io_out [7] is used but has no driver.
Warning: Wire user_proj_example.\io_out [6] is used but has no driver.
Warning: Wire user_proj_example.\io_out [4] is used but has no driver.
Warning: Wire user_proj_example.\io_out [3] is used but has no driver.
Warning: Wire user_proj_example.\io_out [1] is used but has no driver.
Warning: Wire user_proj_example.\io_out [0] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [37] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [36] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [35] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [34] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [33] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [32] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [31] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [30] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [29] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [28] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [27] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [26] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [25] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [24] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [23] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [22] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [21] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [20] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [19] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [18] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [17] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [16] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [15] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [14] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [13] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [12] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [11] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [10] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [9] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [8] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [7] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [6] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [5] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [4] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [3] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [2] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [1] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [0] is used but has no driver.
found and reported 226 problems.

8.7. Executing OPT pass (performing simple optimizations).

8.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

8.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

8.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.7.6. Executing OPT_DFF pass (perform DFF optimizations).

8.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.7.9. Finished OPT passes. (There is nothing left to do.)

8.8. Executing FSM pass (extract and optimize FSM).

8.8.1. Executing FSM_DETECT pass (finding FSMs in design).

8.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

8.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

8.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

8.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

8.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

8.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

8.9. Executing OPT pass (performing simple optimizations).

8.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

8.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

8.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.9.6. Executing OPT_DFF pass (perform DFF optimizations).

8.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.9.9. Finished OPT passes. (There is nothing left to do.)

8.10. Executing WREDUCE pass (reducing word size of cells).

8.11. Executing PEEPOPT pass (run peephole optimizers).

8.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module user_proj_example:
  created 0 $alu and 0 $macc cells.

8.14. Executing SHARE pass (SAT-based resource sharing).

8.15. Executing OPT pass (performing simple optimizations).

8.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

8.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

8.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.15.6. Executing OPT_DFF pass (perform DFF optimizations).

8.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.15.9. Finished OPT passes. (There is nothing left to do.)

8.16. Executing MEMORY pass.

8.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

8.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

8.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

8.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

8.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.18. Executing OPT pass (performing simple optimizations).

8.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.


8.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.18.3. Executing OPT_DFF pass (perform DFF optimizations).

8.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.18.5. Finished fast OPT passes.

8.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

8.20. Executing OPT pass (performing simple optimizations).

8.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

8.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

8.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.20.6. Executing OPT_SHARE pass.

8.20.7. Executing OPT_DFF pass (perform DFF optimizations).

8.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.20.10. Finished OPT passes. (There is nothing left to do.)

8.21. Executing TECHMAP pass (map to technology primitives).

8.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

8.21.2. Continuing TECHMAP pass.
No more expansions possible.


8.22. Executing OPT pass (performing simple optimizations).

8.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.22.3. Executing OPT_DFF pass (perform DFF optimizations).

8.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.22.5. Finished fast OPT passes.

8.23. Executing ABC pass (technology mapping using ABC).

8.23.1. Extracting gate netlist of module `\user_proj_example' to `/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

8.24. Executing OPT pass (performing simple optimizations).

8.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

8.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

8.24.3. Executing OPT_DFF pass (perform DFF optimizations).

8.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

8.24.5. Finished fast OPT passes.

8.25. Executing HIERARCHY pass (managing design hierarchy).

8.25.1. Analyzing design hierarchy..
Top module:  \user_proj_example

8.25.2. Analyzing design hierarchy..
Top module:  \user_proj_example
Removed 0 unused modules.

8.26. Printing statistics.

=== user_proj_example ===

   Number of wires:                 18
   Number of wire bits:            606
   Number of public wires:          18
   Number of public wire bits:     606
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     BUFX2                           1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     NOR2X1                          1
     OR2X1                           1
     OR2X2                           1

8.27. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.

9. Executing SHARE pass (SAT-based resource sharing).

10. Executing OPT pass (performing simple optimizations).

10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

10.6. Executing OPT_DFF pass (perform DFF optimizations).

10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

10.9. Finished OPT passes. (There is nothing left to do.)

11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

12. Printing statistics.

=== user_proj_example ===

   Number of wires:                 18
   Number of wire bits:            606
   Number of public wires:          18
   Number of public wire bits:     606
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     BUFX2                           1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     NOR2X1                          1
     OR2X1                           1
     OR2X2                           1

13. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

13.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\user_proj_example':

14. Printing statistics.
[INFO]: ABC: WireLoad : S_2

=== user_proj_example ===

   Number of wires:                 18
   Number of wire bits:            606
   Number of public wires:          18
   Number of public wire bits:     606
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     BUFX2                           1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     NOR2X1                          1
     OR2X1                           1
     OR2X2                           1

15. Executing ABC pass (technology mapping using ABC).

15.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-C9hqmu/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

16. Executing SETUNDEF pass (replace undef values with defined constants).

17. Executing HILOMAP pass (mapping to constant drivers).

18. Executing SPLITNETS pass (splitting up multi-bit signals).

19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 0 unused cells and 226 unused wires.


20. Executing INSBUF pass (insert buffer cells for connected wires).

21. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.

22. Printing statistics.

=== user_proj_example ===

   Number of wires:                 18
   Number of wire bits:            606
   Number of public wires:          18
   Number of public wire bits:     606
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                237
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     BUFX2                           1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     NOR2X1                          1
     OR2X1                           1
     OR2X2                           1
     sky130_fd_sc_hd__conb_1       226

   Area for cell type \AND2X1 is unknown!
   Area for cell type \AND2X2 is unknown!
   Area for cell type \AOI21X1 is unknown!
   Area for cell type \BUFX2 is unknown!
   Area for cell type \INV is unknown!
   Area for cell type \INVX1 is unknown!
   Area for cell type \INVX2 is unknown!
   Area for cell type \INVX4 is unknown!
   Area for cell type \NOR2X1 is unknown!
   Area for cell type \OR2X1 is unknown!
   Area for cell type \OR2X2 is unknown!

   Chip area for module '\user_proj_example': 848.313600

23. Executing Verilog backend.
Dumping module `\user_proj_example'.

Warnings: 228 unique messages, 228 total
End of script. Logfile hash: 566c41ab32, CPU: user 1.96s system 0.06s, MEM: 44.19 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 32% 4x read_liberty (0 sec), 31% 4x stat (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 700 module AND2X1 not found.  Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 707 module AND2X2 not found.  Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 714 module AOI21X1 not found.  Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 722 module BUFX2 not found.  Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 728 module INV not found.  Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 734 module INVX1 not found.  Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 740 module INVX2 not found.  Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 746 module INVX4 not found.  Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 752 module NOR2X1 not found.  Creating black box for NOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 759 module OR2X1 not found.  Creating black box for OR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 766 module OR2X2 not found.  Creating black box for OR2X2.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 0.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 0.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF master AND2X1 has no liberty cell.
Warning: LEF master AND2X2 has no liberty cell.
Warning: LEF master AOI21X1 has no liberty cell.
Warning: LEF master BUFX2 has no liberty cell.
Warning: LEF master INV has no liberty cell.
Warning: LEF master INVX1 has no liberty cell.
Warning: LEF master INVX2 has no liberty cell.
Warning: LEF master INVX4 has no liberty cell.
Warning: LEF master NOR2X1 has no liberty cell.
Warning: LEF master OR2X1 has no liberty cell.
Warning: LEF master OR2X2 has no liberty cell.
Info: Added 212 rows of 1280 sites.
[INFO]: Core area width: 588.96
[INFO]: Core area height: 578.24
[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 237 components and 955 component-terminals.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
Top-level design name: user_proj_example
Block boundaries: 0 0 600000 600000
Writing /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
[INFO]:  Manual Macro Placement...
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 237 components and 955 component-terminals.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
Placing the following macros:
{'AND2X1': ['50000', '10000', 'N'], 'AND2X2': ['50000', '20000', 'N'], 'AOI21X1': ['50000', '30000', 'N'], 'BUFX2': ['50000', '40000', 'N'], 'INV': ['50000', '50000', 'N'], 'INVX1': ['50000', '60000', 'N'], 'INVX2': ['50000', '70000', 'N'], 'INVX4': ['50000', '80000', 'N'], 'NOR2X1': ['50000', '90000', 'N'], 'OR2X1': ['50000', '100000', 'N'], 'OR2X2': ['50000', '110000', 'N']}
Design name: user_proj_example
Placing AND2X1
Placing AND2X2
Placing AOI21X1
Placing BUFX2
Placing INV
Placing INVX1
Placing INVX2
Placing INVX4
Placing NOR2X1
Placing OR2X1
Placing OR2X2
Successfully placed 11 instances
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 237 components and 955 component-terminals.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 0
[INFO] #Original rows: 212
[INFO] #Cut rows: 0
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 424
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 4387
Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def to /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO]: Running Placement...
[WARNING]: Performing Random Global Placement...
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 5048 components and 10577 component-terminals.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
Design name: user_proj_example
Core Area Boundaries: 5520 10880 594320 587520
Number of instances 5048
Placed 226 instances
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
[INFO]: Running OpenPhySyn Timing Optimization...
[INFO]: Trimming Liberty...
[OpenPhySyn] [2020-11-30 16:36:24.086] [info] Loaded 6 transforms.
[OpenPhySyn] [2020-11-30 16:36:26.424] [info] OpenPhySyn: 1.8.1
Warning: /project/openlane/user_proj_example/runs/user_proj_example/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 5048 components and 10577 component-terminals.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
[INFO]: Setting output delay to: 0.0
[INFO]: Setting input delay to: 0.0
[INFO]: Setting load to: 0.01765
=============== Initial Reports =============
No paths found.
Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Initial area: 80160 um2
OpenPhySyn timing repair:
[OpenPhySyn] [2020-11-30 16:37:30.833] [info] Invoking repair_timing transform
[OpenPhySyn] [2020-11-30 16:37:30.859] [info] Buffer library: sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_1
[OpenPhySyn] [2020-11-30 16:37:30.860] [info] Inverter library: None
[OpenPhySyn] [2020-11-30 16:37:30.860] [info] Buffering: enabled
[OpenPhySyn] [2020-11-30 16:37:30.860] [info] Driver sizing: enabled
[OpenPhySyn] [2020-11-30 16:37:30.860] [info] Pin-swapping: enabled
[OpenPhySyn] [2020-11-30 16:37:30.860] [info] Mode: Timing-Driven
[OpenPhySyn] [2020-11-30 16:37:30.860] [info] Iteration 1
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] No more violations or cannot find more optimal buffer
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Runtime: 0s
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Buffers: 0
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Resize up: 0
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Resize down: 0
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Pin Swap: 0
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Buffered nets: 0
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Fanout violations: 0
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Transition violations: 0
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Capacitance violations: 0
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Slack gain: 0.0
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Initial area: 8016
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] New area: 8016
[OpenPhySyn] [2020-11-30 16:37:30.976] [info] Finished repair_timing transform (0)
Added/updated 0 cells
=============== Final Reports =============
No paths found.
Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Final area: 80160 um2
Export optimized design
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 5048 components and 10577 component-terminals.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 34 module AND2X1 not found.  Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 39 module AND2X2 not found.  Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 44 module AOI21X1 not found.  Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 50 module BUFX2 not found.  Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 54 module INV not found.  Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 58 module INVX1 not found.  Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 62 module INVX2 not found.  Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 66 module INVX4 not found.  Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 70 module NOR2X1 not found.  Creating black box for NOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 75 module OR2X1 not found.  Creating black box for OR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 80 module OR2X2 not found.  Creating black box for OR2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 735 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found.  Creating black box for PHY_424.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 0.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 0.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Running Detailed Placement...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 5048 components and 10577 component-terminals.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
detailed_placement...
Warning: could not find power special net
Design Stats
--------------------------------
total instances          5048
multi row instances         0
fixed instances          4822
nets                      606
design area          339525.6 u^2
fixed area             7168.1 u^2
movable area            848.3 u^2
utilization                 0 %
utilization padded          0 %
rows                      212
row height                2.7 u

Placement Analysis
--------------------------------
total displacement      363.2 u
average displacement      0.1 u
max displacement          6.0 u
original HPWL        135402.0 u
legalized HPWL       135240.5 u
delta HPWL                 -0 %

check_placement...
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def to /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def to /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
[INFO]: Generating PDN...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 5048 components and 10577 component-terminals.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_proj_example
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
    Stdcell Rails
      Layer: met1 -  width: 0.480  pitch: 2.720  offset: 0.000 
    Straps
      Layer: met4 -  width: 1.600  pitch: 153.600  offset: 16.320 
      Layer: met5 -  width: 1.600  pitch: 153.180  offset: 16.650 
    Connect: {met1 met4} {met4 met5}
Type: macro, macro_1
    Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
    Straps
    Connect:  
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/pdn.def
[INFO]: Routing...
[INFO]: Running Global Routing...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/pdn.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 5048 components and 10577 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/pdn.def
[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 6
[PARAMS] Global adjustment: 0
[PARAMS] Unidirectional routing: 1
[PARAMS] Grid origin: (-1, -1)
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 33670
[INFO] #DB Macros: 0
[INFO] Found 0 clock nets
[INFO] Minimum degree: 2
[INFO] Maximum degree: 11
[INFO] Processing 21448 obstacles on layer 1
[INFO] Processing 10287 obstacles on layer 2
[INFO] Processing 119 obstacles on layer 3
[INFO] Processing 8 obstacles on layer 5
[INFO] Processing 8 obstacles on layer 6
[INFO] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 18959, WIRELEN1 : 0
[INFO] NumSeg  : 275
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 18959, WIRELEN1 : 18959
[INFO] NumSeg  : 275
[INFO] NumShift: 0
[Overflow Report] Total hCap    : 217116
[Overflow Report] Total vCap    : 161757
[Overflow Report] Total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Second L Route
[Overflow Report] Total hCap    : 217116
[Overflow Report] Total vCap    : 161757
[Overflow Report] Total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

First Z Route
[Overflow Report] Total hCap    : 217116
[Overflow Report] Total vCap    : 161757
[Overflow Report] Total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 0, enlarge 10 
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 1, enlarge 15 
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 2, enlarge 20 
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Usage checked
Maze routing finished
[INFO] P3 runtime: 0.000000 sec
[INFO] Final 2D results: 
[Overflow Report] total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 60.040001 sec
Post Processing Begins 
Post Processsing finished
 Starting via filling
[INFO] Via related to pin nodes 735
[INFO] Via related stiner nodes 0
Via filling finished

Final usage/overflow report: 
[INFO] Usage per layer: 
    Layer 1 usage: 0
    Layer 2 usage: 6965
    Layer 3 usage: 11937
    Layer 4 usage: 57
    Layer 5 usage: 0
    Layer 6 usage: 0

[INFO] Capacity per layer: 
    Layer 1 capacity: 0
    Layer 2 capacity: 128716
    Layer 3 capacity: 110664
    Layer 4 capacity: 73780
    Layer 5 capacity: 51093
    Layer 6 capacity: 14620

[INFO] Use percentage per layer: 
    Layer 1 use percentage: 0.0%
    Layer 2 use percentage: 5.41%
    Layer 3 use percentage: 10.79%
    Layer 4 use percentage: 0.08%
    Layer 5 use percentage: 0.00%
    Layer 6 use percentage: 0.00%

[INFO] Overflow per layer: 
    Layer 1 overflow: 0
    Layer 2 overflow: 0
    Layer 3 overflow: 0
    Layer 4 overflow: 0
    Layer 5 overflow: 0
    Layer 6 overflow: 0

[Overflow Report] Total Usage   : 18959
[Overflow Report] Total Capacity: 378873
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] Final usage          : 18959
[INFO] Final number of vias : 1068
[INFO] Final usage 3D       : 22163
[INFO] Total wirelength: 140125 um
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 11 T shapes.
Notice 0: Split top of 8 T shapes.
Repairing antennas...
[WARNING]No OR_DEFAULT vias defined
[INFO] #Antenna violations: 0
Warning: Site check failed (11).
[INFO] Num routed nets: 257
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 5048 components and 10577 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 6
[PARAMS] Global adjustment: 0
[PARAMS] Unidirectional routing: 1
[PARAMS] Grid origin: (-1, -1)
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 33670
[INFO] #DB Macros: 0
[INFO] Found 0 clock nets
[INFO] Minimum degree: 2
[INFO] Maximum degree: 11
[INFO] Processing 21448 obstacles on layer 1
[INFO] Processing 10287 obstacles on layer 2
[INFO] Processing 119 obstacles on layer 3
[INFO] Processing 8 obstacles on layer 5
[INFO] Processing 8 obstacles on layer 6
[INFO] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 18959, WIRELEN1 : 0
[INFO] NumSeg  : 275
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 18959, WIRELEN1 : 18959
[INFO] NumSeg  : 275
[INFO] NumShift: 0
[Overflow Report] Total hCap    : 217116
[Overflow Report] Total vCap    : 161757
[Overflow Report] Total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Second L Route
[Overflow Report] Total hCap    : 217116
[Overflow Report] Total vCap    : 161757
[Overflow Report] Total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

First Z Route
[Overflow Report] Total hCap    : 217116
[Overflow Report] Total vCap    : 161757
[Overflow Report] Total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 0, enlarge 10 
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 1, enlarge 15 
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 2, enlarge 20 
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Usage checked
Maze routing finished
[INFO] P3 runtime: 0.000000 sec
[INFO] Final 2D results: 
[Overflow Report] total Usage   : 18959
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 60.490002 sec
Post Processing Begins 
Post Processsing finished
 Starting via filling
[INFO] Via related to pin nodes 735
[INFO] Via related stiner nodes 0
Via filling finished

Final usage/overflow report: 
[INFO] Usage per layer: 
    Layer 1 usage: 0
    Layer 2 usage: 6965
    Layer 3 usage: 11937
    Layer 4 usage: 57
    Layer 5 usage: 0
    Layer 6 usage: 0

[INFO] Capacity per layer: 
    Layer 1 capacity: 0
    Layer 2 capacity: 128716
    Layer 3 capacity: 110664
    Layer 4 capacity: 73780
    Layer 5 capacity: 51093
    Layer 6 capacity: 14620

[INFO] Use percentage per layer: 
    Layer 1 use percentage: 0.0%
    Layer 2 use percentage: 5.41%
    Layer 3 use percentage: 10.79%
    Layer 4 use percentage: 0.08%
    Layer 5 use percentage: 0.00%
    Layer 6 use percentage: 0.00%

[INFO] Overflow per layer: 
    Layer 1 overflow: 0
    Layer 2 overflow: 0
    Layer 3 overflow: 0
    Layer 4 overflow: 0
    Layer 5 overflow: 0
    Layer 6 overflow: 0

[Overflow Report] Total Usage   : 18959
[Overflow Report] Total Capacity: 378873
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] Final usage          : 18959
[INFO] Final number of vias : 1068
[INFO] Final usage 3D       : 22163
[INFO] Total wirelength: 140125 um
[INFO] Num routed nets: 257
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 0.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 0.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
Warning: missing route to pin NOR2X1/vdd
Warning: missing route to pin INVX4/vdd
Warning: missing route to pin INVX2/vdd
Warning: missing route to pin INVX1/vdd
Warning: missing route to pin BUFX2/vdd
Warning: missing route to pin NOR2X1/gnd
Warning: missing route to pin INVX4/gnd
Warning: missing route to pin INVX2/gnd
Warning: missing route to pin INV/gnd
Warning: missing route to pin AOI21X1/gnd
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
[INFO]: Current Def is /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
[INFO]: Running Fill Insertion...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 5048 components and 10577 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
Placed 22845 filler instances.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/addspacers.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/addspacers.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 27893 components and 56267 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/addspacers.def
[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_preroute.v
[INFO]: Running Detailed Routing...

reading lef ...
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!
Error: unsupported lefiGeometries in getLefPins!

units:       1000
#layers:     13
#macros:     463
#vias:       25
#viarulegen: 25

reading def ...
defIn read 10000 components
defIn read 20000 components

design:      user_proj_example
die area:    ( 0 0 ) ( 600000 600000 )
trackPts:    12
defvias:     4
#components: 27893
#terminals:  606
#snets:      2
#nets:       606

reading guide ...

#guides:     1269
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig
Error: instAnalysis unsupported pinFig

instance analysis ...
  complete 10000 instances
  complete 20000 instances
#unique instances = 31

init region query ...
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
Error: unsupported region query add
  complete 10000 insts
  complete 20000 insts
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 156762
mcon shape region query size = 542414
met1 shape region query size = 56829
via shape region query size = 3408
met2 shape region query size = 2335
via2 shape region query size = 3408
met3 shape region query size = 1704
via3 shape region query size = 3408
met4 shape region query size = 892
via4 shape region query size = 32
met5 shape region query size = 42


start pin access
  complete 55 pins
Error: no valid pattern for unique instance INVX4, refBlock is INVX4
Error: no valid pattern for unique instance NOR2X1, refBlock is NOR2X1
  pin ordering (with ap): 
    A (50.92, 91.46) (50.83, 91.12) (50.92, 91.12)
    Y (50.37, 90.78) (52.21, 90.78) (50.83, 90.78) (51.29, 90.78) (51.75, 90.78)
    vdd (50.37, 92.82) (50.83, 92.82) (51.29, 92.82) (51.75, 92.82) (52.21, 92.82) (52.67, 92.82)
    gnd (50.37, 90.1) (50.83, 90.1) (51.29, 90.1) (51.75, 90.1) (52.21, 90.1) (52.67, 90.1)
    B (51.84, 91.46) (51.75, 91.12) (51.84, 91.12)
Error: no valid pattern for unique instance BUFX2, refBlock is BUFX2
  pin ordering (with ap): 
    A (50.83, 41.625) (50.92, 41.625)
    vdd (50.37, 42.84) (50.83, 42.84) (51.29, 42.84) (51.75, 42.84) (52.21, 42.84) (52.67, 42.84)
    gnd (50.37, 40.12) (50.83, 40.12) (51.29, 40.12) (51.75, 40.12) (52.21, 40.12) (52.67, 40.12)
    Y (52.3, 41.14) (52.3, 41.82) (52.21, 40.8)
Error: no valid pattern for unique instance OR2X1, refBlock is OR2X1
  pin ordering (with ap): 
    A (50.83, 101.66) (50.92, 101.66) (50.92, 101.32)
    B (51.75, 101.66) (51.84, 101.66) (51.75, 101.625)
    vdd (50.37, 102.68) (50.83, 102.68) (51.29, 102.68) (51.75, 102.68) (52.21, 102.68) (52.67, 102.68) (53.13, 102.68) (53.59, 102.68)
    gnd (50.37, 99.96) (50.83, 99.96) (51.29, 99.96) (51.75, 99.96) (52.21, 99.96) (52.67, 99.96) (53.13, 99.96) (53.59, 99.96)
    Y (53.22, 100.98) (53.22, 101.66) (53.13, 100.64) (53.13, 102)
Error: no valid pattern for unique instance INVX2, refBlock is INVX2
  pin ordering (with ap): 
    Y (50.46, 71.06) (50.46, 71.74) (50.37, 70.72) (50.37, 72.08)
    A (50.83, 71.06) (50.83, 71.74) (50.92, 71.06) (50.92, 71.74)
    vdd (50.37, 72.76) (50.83, 72.76) (51.29, 72.76) (51.75, 72.76)
    gnd (50.37, 70.04) (50.83, 70.04) (51.29, 70.04) (51.75, 70.04)
Error: no valid pattern for unique instance AND2X2, refBlock is AND2X2
  pin ordering (with ap): 
    A (50.92, 21.42) (50.83, 21.08) (50.92, 21.08)
    B (51.75, 21.625) (51.84, 21.625)
    vdd (50.37, 22.78) (50.83, 22.78) (51.29, 22.78) (51.75, 22.78) (52.21, 22.78) (52.67, 22.78) (53.13, 22.78) (53.59, 22.78)
    gnd (50.37, 20.06) (50.83, 20.06) (51.29, 20.06) (51.75, 20.06) (52.21, 20.06) (52.67, 20.06) (53.13, 20.06) (53.59, 20.06)
    Y (53.13, 20.74) (53.13, 22.1) (53.22, 20.74) (53.22, 21.42) (53.22, 22.1)
Error: no valid pattern for unique instance OR2X2, refBlock is OR2X2
  pin ordering (with ap): 
    A (50.83, 111.18) (50.92, 111.18) (50.83, 111.52)
    B (51.75, 111.52) (51.84, 111.52) (51.75, 111.625)
    vdd (50.37, 112.54) (50.83, 112.54) (51.29, 112.54) (51.75, 112.54) (52.21, 112.54) (52.67, 112.54) (53.13, 112.54) (53.59, 112.54)
    gnd (50.37, 109.82) (50.83, 109.82) (51.29, 109.82) (51.75, 109.82) (52.21, 109.82) (52.67, 109.82) (53.13, 109.82) (53.59, 109.82)
    Y (53.22, 111.18) (53.22, 111.86) (53.22, 110.84) (53.22, 111.52)
Error: no valid pattern for unique instance AND2X1, refBlock is AND2X1
  pin ordering (with ap): 
    A (50.83, 11.22) (50.92, 11.22) (50.83, 11.56)
    B (51.75, 11.56) (51.84, 11.56) (51.75, 11.625)
    vdd (50.37, 12.58) (50.83, 12.58) (51.29, 12.58) (51.75, 12.58) (52.21, 12.58) (52.67, 12.58) (53.13, 12.58) (53.59, 12.58)
    gnd (50.37, 9.86) (50.83, 9.86) (51.29, 9.86) (51.75, 9.86) (52.21, 9.86) (52.67, 9.86) (53.13, 9.86) (53.59, 9.86)
    Y (53.13, 11.9) (53.22, 11.22) (53.22, 11.9)
Error: no valid pattern for unique instance INVX1, refBlock is INVX1
  pin ordering (with ap): 
    A (50.83, 61.54) (50.92, 61.54) (50.83, 61.2)
    vdd (50.37, 62.9) (50.83, 62.9) (51.29, 62.9) (51.75, 62.9)
    gnd (50.37, 60.18) (50.83, 60.18) (51.29, 60.18) (51.75, 60.18)
    Y (51.38, 60.86) (51.38, 61.54) (51.38, 61.2) (51.38, 61.88)
Error: no valid pattern for unique instance INV, refBlock is INV
  pin ordering (with ap): 
    Y (50.37, 50.66) (50.37, 52.02) (50.46, 50.66) (50.46, 51.34) (50.46, 52.02)
    A (50.92, 51.34) (50.83, 51) (50.83, 51.68)
    vdd (50.37, 52.7) (50.83, 52.7) (51.29, 52.7) (51.75, 52.7)
    gnd (50.37, 49.98) (50.83, 49.98) (51.29, 49.98) (51.75, 49.98)
Error: no valid pattern for unique instance AOI21X1, refBlock is AOI21X1
  pin ordering (with ap): 
    B (50.83, 31.62) (50.92, 31.62) (50.92, 31.28)
    A (51.75, 31.62) (51.84, 31.62) (51.84, 31.28)
    vdd (50.37, 32.64) (50.83, 32.64) (51.29, 32.64) (51.75, 32.64) (52.21, 32.64) (52.67, 32.64) (53.13, 32.64) (53.59, 32.64)
    gnd (50.37, 29.92) (50.83, 29.92) (51.29, 29.92) (51.75, 29.92) (52.21, 29.92) (52.67, 29.92) (53.13, 29.92) (53.59, 29.92)
    Y (53.22, 30.94) (53.22, 31.62) (50.37, 30.6) (53.13, 30.6) (53.13, 31.96)
    C (52.67, 31.62) (52.76, 31.62) (52.76, 31.28)
  pin ordering (with ap): 
    A (50.92, 81.26) (51.84, 81.26) (50.83, 81.6) (51.75, 81.6) (51.29, 81.6)
    Y (50.37, 81.94) (52.21, 81.94) (50.46, 81.26) (50.46, 81.94) (52.3, 81.26) (52.3, 81.94)
    vdd (50.37, 82.62) (50.83, 82.62) (51.29, 82.62) (51.75, 82.62) (52.21, 82.62) (52.67, 82.62)
    gnd (50.37, 79.9) (50.83, 79.9) (51.29, 79.9) (51.75, 79.9) (52.21, 79.9) (52.67, 79.9)
  complete 25 unique inst patterns
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
@@@ dead end inst
@@@ dead end inst
Error: valid access pattern combination not found
  complete 237 groups
Expt1 runtime (pin-level access point gen): 1.21134
Expt2 runtime (design-level access pattern gen): 0.0151738
#scanned instances     = 27893
#unique  instances     = 31
#stdCellGenAp          = 259
#stdCellValidPlanarAp  = 243
#stdCellValidViaAp     = 16
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 277
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0

complete pin access
cpu time = 00:00:01, elapsed time = 00:00:01, memory = 59.37 (MB), peak = 71.34 (MB)

post process guides ...
GCELLGRID X -1 DO 86 STEP 6900 ;
GCELLGRID Y -1 DO 86 STEP 6900 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5
Error: genGuides_gCell2TermMap unsupoprted pinfig
[ERROR]: during executing: "TritonRoute /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/tritonRoute.param |& tee >&@stdout /project/openlane/user_proj_example/runs/user_proj_example/logs/routing/tritonRoute.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check TritonRoute  log file
[ERROR]: Dumping to /project/openlane/user_proj_example/runs/user_proj_example/error.log

    while executing
"try_catch TritonRoute  $::env(tritonRoute_tmp_file_tag).param  |& tee $::env(TERMINAL_OUTPUT) $::env(tritonRoute_log_file_tag).log"
    (procedure "detailed_routing" line 7)
    invoked from within
"detailed_routing"
    (procedure "run_routing" line 30)
    invoked from within
"run_routing"
    (procedure "run_non_interactive_mode" line 16)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 169)
make: *** [Makefile:29: user_proj_example] Fehler 1