Reports:

Submodule: caravel

###############################################
/bin/sh: 1: [[: not found
[INFO]: 

	___   ____   ___  ____   _       ____  ____     ___

	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]

	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_

	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]

	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_

	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|





[INFO]: Version: rc4

[INFO]: Running non-interactively

[INFO]: Using design configuration at /project/openlane/caravel/config.tcl

[INFO]: Sourcing Configurations from /project/openlane/caravel/config.tcl

[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A

[INFO]: PDK: sky130A

[INFO]: Standard Cell Library: sky130_fd_sc_hvl

no files matched glob pattern "/media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hvl/lef/*.lef"

    while executing

"glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef""

    invoked from within

"set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"]"

    (file "/media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/openlane/config.tcl" line 13)

    invoked from within

"source $pdk_config"

    (procedure "prep" line 124)

    invoked from within

"prep {*}$args"

    (procedure "run_non_interactive_mode" line 9)

    invoked from within

"run_non_interactive_mode {*}$argv"

    invoked from within

"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {

	puts_info "Running interactively"

	if { [info exists arg_values(-file)..."

    (file "/openLANE_flow/flow.tcl" line 164)

make: *** [Makefile:26: caravel] Fehler 1

Submodule: chip_io

###############################################
/bin/sh: 1: [[: not found
[INFO]: 

	___   ____   ___  ____   _       ____  ____     ___

	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]

	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_

	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]

	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_

	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|





[INFO]: Version: rc4

[INFO]: Running non-interactively

[INFO]: Using design configuration at /project/openlane/chip_io/config.tcl

[INFO]: Sourcing Configurations from /project/openlane/chip_io/config.tcl

[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A

[INFO]: PDK: sky130A

[INFO]: Standard Cell Library: sky130_fd_sc_hd

[INFO]: Sourcing Configurations from /project/openlane/chip_io/config.tcl

[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.


[INFO]: Current run directory is /project/openlane/chip_io/runs/chip_io

[WARNING]: Removing exisiting run /project/openlane/chip_io/runs/chip_io


[INFO]: Preparing LEF Files

mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 3.68
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished

[INFO]: Merging the following GPIO LEF views: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef

[INFO]: Trimming Liberty...

[WARNING]: GPIO_PADS_VERILOG is not set; cannot read as a blackbox


[INFO]: Preparation complete

[INFO]: Running Synthesis...


 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/stubs/sky130_fd_io__top_xres4v2.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/stubs/sky130_fd_io__top_xres4v2.v' to AST representation.
Generating RTLIL representation for module `\sky130_fd_io__top_xres4v2'.
Successfully finished Verilog frontend.


2. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.


3. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/pads.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/pads.v' to AST representation.
Successfully finished Verilog frontend.


4. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/mprj_io.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/mprj_io.v' to AST representation.
Generating RTLIL representation for module `\mprj_io'.
Successfully finished Verilog frontend.


5. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/chip_io.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/chip_io.v' to AST representation.
Generating RTLIL representation for module `\chip_io'.
/project/openlane/chip_io/../../verilog/rtl/chip_io.v:173: Warning: Identifier `\loop_gpio' is implicitly declared.

/project/openlane/chip_io/../../verilog/rtl/chip_io.v:178: Warning: Identifier `\loop_flash_io0' is implicitly declared.

/project/openlane/chip_io/../../verilog/rtl/chip_io.v:181: Warning: Identifier `\loop_flash_io1' is implicitly declared.

/project/openlane/chip_io/../../verilog/rtl/chip_io.v:196: Warning: Identifier `\xresloop' is implicitly declared.

Successfully finished Verilog frontend.


6. Executing HIERARCHY pass (managing design hierarchy).

6.1. Analyzing design hierarchy..
ERROR: Module `\sky130_ef_io__gpiov2_pad' referenced in module `\mprj_io' in cell `\area2_io_pad[19]' is not part of the design.

[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/chip_io/runs/chip_io/logs/synthesis/yosys.log |& tee >&@stdout"


[ERROR]: Exit code: 1


[ERROR]: Last 10 lines:


child process exited abnormally



[ERROR]: Please check yosys  log file


[ERROR]: Dumping to /project/openlane/chip_io/runs/chip_io/error.log




    while executing

"try_catch [get_yosys_bin]  -c $::env(SYNTH_SCRIPT)  -l $::env(yosys_log_file_tag).log  |& tee $::env(TERMINAL_OUTPUT)"

    (procedure "run_yosys" line 18)

    invoked from within

"run_yosys"

    (procedure "run_synthesis" line 4)

    invoked from within

"run_synthesis"

    (procedure "run_non_interactive_mode" line 11)

    invoked from within

"run_non_interactive_mode {*}$argv"

    invoked from within

"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {

	puts_info "Running interactively"

	if { [info exists arg_values(-file)..."

    (file "/openLANE_flow/flow.tcl" line 164)

make: *** [Makefile:26: chip_io] Fehler 1

Submodule: DFFRAM

###############################################
/bin/sh: 1: [[: not found
[INFO]: 

	___   ____   ___  ____   _       ____  ____     ___

	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]

	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_

	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]

	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_

	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|





[INFO]: Version: rc4

[INFO]: Running non-interactively

[INFO]: Using design configuration at /project/openlane/DFFRAM/config.tcl

[INFO]: Sourcing Configurations from /project/openlane/DFFRAM/config.tcl

[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A

[INFO]: PDK: sky130A

[INFO]: Standard Cell Library: sky130_fd_sc_hd

[INFO]: Sourcing Configurations from /project/openlane/DFFRAM/config.tcl

[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.


[INFO]: Current run directory is /project/openlane/DFFRAM/runs/DFFRAM

[WARNING]: Removing exisiting run /project/openlane/DFFRAM/runs/DFFRAM


[INFO]: Preparing LEF Files

mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 0.0
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished

[INFO]: Trimming Liberty...

[INFO]: Preparation complete

[INFO]: Running Synthesis...


 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/DFFRAM/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/DFFRAM/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.


3. Executing Verilog-2005 frontend: /project/openlane/DFFRAM/../../verilog/rtl/DFFRAM.v
Parsing Verilog input from `/project/openlane/DFFRAM/../../verilog/rtl/DFFRAM.v' to AST representation.
Generating RTLIL representation for module `\DFFRAM'.
Successfully finished Verilog frontend.


4. Executing Verilog-2005 frontend: /project/openlane/DFFRAM/../../verilog/rtl/DFFRAMBB.v
Parsing Verilog input from `/project/openlane/DFFRAM/../../verilog/rtl/DFFRAMBB.v' to AST representation.
Generating RTLIL representation for module `\BYTE'.
Generating RTLIL representation for module `\WORD32'.
Generating RTLIL representation for module `\DEC1x2'.
Generating RTLIL representation for module `\DEC2x4'.
Generating RTLIL representation for module `\DEC3x8'.
Generating RTLIL representation for module `\DEC6x64'.
Generating RTLIL representation for module `\MUX2x1_32'.
Generating RTLIL representation for module `\MUX4x1_32'.
Generating RTLIL representation for module `\PASS'.
Generating RTLIL representation for module `\SRAM64x32'.
Generating RTLIL representation for module `\DFFRAM_COL4'.
Successfully finished Verilog frontend.


5. Executing HIERARCHY pass (managing design hierarchy).

5.1. Analyzing design hierarchy..
Top module:  \DFFRAM
Used module:     \PASS
Used module:     \DFFRAM_COL4
Used module:         \MUX4x1_32
Used module:         \SRAM64x32
Used module:             \WORD32
Used module:                 \BYTE
Used module:             \DEC6x64
Used module:                 \DEC3x8
Used module:         \DEC2x4

5.2. Analyzing design hierarchy..
Top module:  \DFFRAM
Used module:     \PASS
Used module:     \DFFRAM_COL4
Used module:         \MUX4x1_32
Used module:         \SRAM64x32
Used module:             \WORD32
Used module:                 \BYTE
Used module:             \DEC6x64
Used module:                 \DEC3x8
Used module:         \DEC2x4
Removing unused module `\MUX2x1_32'.
Removing unused module `\DEC1x2'.
Removed 2 unused modules.

6. Printing statistics.

=== PASS ===

   Number of wires:                  2
   Number of wire bits:             64
   Number of public wires:           2
   Number of public wire bits:      64
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== MUX4x1_32 ===

   Number of wires:                  6
   Number of wire bits:            162
   Number of public wires:           6
   Number of public wire bits:     162
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     sky130_fd_sc_hd__mux4_1        32

=== DFFRAM_COL4 ===

   Number of wires:                 16
   Number of wire bits:            282
   Number of public wires:          16
   Number of public wire bits:     282
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 46
     DEC2x4                          1
     MUX4x1_32                       1
     SRAM64x32                       4
     sky130_fd_sc_hd__clkbuf_16      3
     sky130_fd_sc_hd__clkbuf_8      37

=== DEC6x64 ===

   Number of wires:                  5
   Number of wire bits:             82
   Number of public wires:           5
   Number of public wire bits:      82
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 12
     DEC3x8                          9
     sky130_fd_sc_hd__clkbuf_16      3

=== DEC3x8 ===

   Number of wires:                  3
   Number of wire bits:             12
   Number of public wires:           3
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  8
     sky130_fd_sc_hd__and4_2         1
     sky130_fd_sc_hd__and4b_2        3
     sky130_fd_sc_hd__and4bb_2       3
     sky130_fd_sc_hd__nor4b_2        1

=== DEC2x4 ===

   Number of wires:                  3
   Number of wire bits:              7
   Number of public wires:           3
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     sky130_fd_sc_hd__and3_4         1
     sky130_fd_sc_hd__and3b_4        2
     sky130_fd_sc_hd__nor3b_4        1

=== SRAM64x32 ===

   Number of wires:                 13
   Number of wire bits:            211
   Number of public wires:          13
   Number of public wire bits:     211
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                168
     DEC6x64                         1
     WORD32                         64
     sky130_fd_sc_hd__clkbuf_16     37
     sky130_fd_sc_hd__clkbuf_4       1
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfxtp_1       32
     sky130_fd_sc_hd__ebufn_4       32

=== WORD32 ===

   Number of wires:                  5
   Number of wire bits:             70
   Number of public wires:           5
   Number of public wire bits:      70
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     BYTE                            4

=== BYTE ===

   Number of wires:                  9
   Number of wire bits:             30
   Number of public wires:           9
   Number of public wire bits:      30
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     sky130_fd_sc_hd__and2_1         1
     sky130_fd_sc_hd__dfxtp_1        8
     sky130_fd_sc_hd__dlclkp_1       1
     sky130_fd_sc_hd__ebufn_2        8
     sky130_fd_sc_hd__inv_1          1

=== DFFRAM ===

   Number of wires:                  9
   Number of wire bits:            143
   Number of public wires:           9
   Number of public wire bits:     143
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 35
     DFFRAM_COL4                     1
     PASS                            1
     sky130_fd_sc_hd__clkbuf_4      33

=== design hierarchy ===

   DFFRAM                            1
     DFFRAM_COL4                     1
       DEC2x4                        1
       MUX4x1_32                     1
       SRAM64x32                     4
         DEC6x64                     1
           DEC3x8                    9
         WORD32                     64
           BYTE                      4
     PASS                            1

   Number of wires:              10712
   Number of wire bits:          50902
   Number of public wires:       10712
   Number of public wire bits:   50902
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              20277
     sky130_fd_sc_hd__and2_1      1024
     sky130_fd_sc_hd__and3_4         1
     sky130_fd_sc_hd__and3b_4        2
     sky130_fd_sc_hd__and4_2        36
     sky130_fd_sc_hd__and4b_2      108
     sky130_fd_sc_hd__and4bb_2     108
     sky130_fd_sc_hd__clkbuf_16    163
     sky130_fd_sc_hd__clkbuf_4      37
     sky130_fd_sc_hd__clkbuf_8      37
     sky130_fd_sc_hd__conb_1         4
     sky130_fd_sc_hd__dfxtp_1     8320
     sky130_fd_sc_hd__dlclkp_1    1024
     sky130_fd_sc_hd__ebufn_2     8192
     sky130_fd_sc_hd__ebufn_4      128
     sky130_fd_sc_hd__inv_1       1024
     sky130_fd_sc_hd__mux4_1        32
     sky130_fd_sc_hd__nor3b_4        1
     sky130_fd_sc_hd__nor4b_2       36

7. Executing SPLITNETS pass (splitting up multi-bit signals).

8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \PASS..
Finding unused cells or wires in module \MUX4x1_32..
Finding unused cells or wires in module \DFFRAM_COL4..
Finding unused cells or wires in module \DEC6x64..
Finding unused cells or wires in module \DEC3x8..
Finding unused cells or wires in module \DEC2x4..
Finding unused cells or wires in module \SRAM64x32..
Finding unused cells or wires in module \WORD32..
Finding unused cells or wires in module \BYTE..
Finding unused cells or wires in module \DFFRAM..

9. Executing CHECK pass (checking for obvious problems).
checking module BYTE..
checking module DEC2x4..
checking module DEC3x8..
checking module DEC6x64..
checking module DFFRAM..
checking module DFFRAM_COL4..
checking module MUX4x1_32..
checking module PASS..
checking module SRAM64x32..
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[9]:

    port Z[0] of cell FLOATBUF[9] (sky130_fd_sc_hd__ebufn_4)
    port Do[9] of cell WORD[0].W (WORD32)
    port Do[9] of cell WORD[10].W (WORD32)
    port Do[9] of cell WORD[11].W (WORD32)
    port Do[9] of cell WORD[12].W (WORD32)
    port Do[9] of cell WORD[13].W (WORD32)
    port Do[9] of cell WORD[14].W (WORD32)
    port Do[9] of cell WORD[15].W (WORD32)
    port Do[9] of cell WORD[16].W (WORD32)
    port Do[9] of cell WORD[17].W (WORD32)
    port Do[9] of cell WORD[18].W (WORD32)
    port Do[9] of cell WORD[19].W (WORD32)
    port Do[9] of cell WORD[1].W (WORD32)
    port Do[9] of cell WORD[20].W (WORD32)
    port Do[9] of cell WORD[21].W (WORD32)
    port Do[9] of cell WORD[22].W (WORD32)
    port Do[9] of cell WORD[23].W (WORD32)
    port Do[9] of cell WORD[24].W (WORD32)
    port Do[9] of cell WORD[25].W (WORD32)
    port Do[9] of cell WORD[26].W (WORD32)
    port Do[9] of cell WORD[27].W (WORD32)
    port Do[9] of cell WORD[28].W (WORD32)
    port Do[9] of cell WORD[29].W (WORD32)
    port Do[9] of cell WORD[2].W (WORD32)
    port Do[9] of cell WORD[30].W (WORD32)
    port Do[9] of cell WORD[31].W (WORD32)
    port Do[9] of cell WORD[32].W (WORD32)
    port Do[9] of cell WORD[33].W (WORD32)
    port Do[9] of cell WORD[34].W (WORD32)
    port Do[9] of cell WORD[35].W (WORD32)
    port Do[9] of cell WORD[36].W (WORD32)
    port Do[9] of cell WORD[37].W (WORD32)
    port Do[9] of cell WORD[38].W (WORD32)
    port Do[9] of cell WORD[39].W (WORD32)
    port Do[9] of cell WORD[3].W (WORD32)
    port Do[9] of cell WORD[40].W (WORD32)
    port Do[9] of cell WORD[41].W (WORD32)
    port Do[9] of cell WORD[42].W (WORD32)
    port Do[9] of cell WORD[43].W (WORD32)
    port Do[9] of cell WORD[44].W (WORD32)
    port Do[9] of cell WORD[45].W (WORD32)
    port Do[9] of cell WORD[46].W (WORD32)
    port Do[9] of cell WORD[47].W (WORD32)
    port Do[9] of cell WORD[48].W (WORD32)
    port Do[9] of cell WORD[49].W (WORD32)
    port Do[9] of cell WORD[4].W (WORD32)
    port Do[9] of cell WORD[50].W (WORD32)
    port Do[9] of cell WORD[51].W (WORD32)
    port Do[9] of cell WORD[52].W (WORD32)
    port Do[9] of cell WORD[53].W (WORD32)
    port Do[9] of cell WORD[54].W (WORD32)
    port Do[9] of cell WORD[55].W (WORD32)
    port Do[9] of cell WORD[56].W (WORD32)
    port Do[9] of cell WORD[57].W (WORD32)
    port Do[9] of cell WORD[58].W (WORD32)
    port Do[9] of cell WORD[59].W (WORD32)
    port Do[9] of cell WORD[5].W (WORD32)
    port Do[9] of cell WORD[60].W (WORD32)
    port Do[9] of cell WORD[61].W (WORD32)
    port Do[9] of cell WORD[62].W (WORD32)
    port Do[9] of cell WORD[63].W (WORD32)
    port Do[9] of cell WORD[6].W (WORD32)
    port Do[9] of cell WORD[7].W (WORD32)
    port Do[9] of cell WORD[8].W (WORD32)
    port Do[9] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[8]:

    port Z[0] of cell FLOATBUF[8] (sky130_fd_sc_hd__ebufn_4)
    port Do[8] of cell WORD[0].W (WORD32)
    port Do[8] of cell WORD[10].W (WORD32)
    port Do[8] of cell WORD[11].W (WORD32)
    port Do[8] of cell WORD[12].W (WORD32)
    port Do[8] of cell WORD[13].W (WORD32)
    port Do[8] of cell WORD[14].W (WORD32)
    port Do[8] of cell WORD[15].W (WORD32)
    port Do[8] of cell WORD[16].W (WORD32)
    port Do[8] of cell WORD[17].W (WORD32)
    port Do[8] of cell WORD[18].W (WORD32)
    port Do[8] of cell WORD[19].W (WORD32)
    port Do[8] of cell WORD[1].W (WORD32)
    port Do[8] of cell WORD[20].W (WORD32)
    port Do[8] of cell WORD[21].W (WORD32)
    port Do[8] of cell WORD[22].W (WORD32)
    port Do[8] of cell WORD[23].W (WORD32)
    port Do[8] of cell WORD[24].W (WORD32)
    port Do[8] of cell WORD[25].W (WORD32)
    port Do[8] of cell WORD[26].W (WORD32)
    port Do[8] of cell WORD[27].W (WORD32)
    port Do[8] of cell WORD[28].W (WORD32)
    port Do[8] of cell WORD[29].W (WORD32)
    port Do[8] of cell WORD[2].W (WORD32)
    port Do[8] of cell WORD[30].W (WORD32)
    port Do[8] of cell WORD[31].W (WORD32)
    port Do[8] of cell WORD[32].W (WORD32)
    port Do[8] of cell WORD[33].W (WORD32)
    port Do[8] of cell WORD[34].W (WORD32)
    port Do[8] of cell WORD[35].W (WORD32)
    port Do[8] of cell WORD[36].W (WORD32)
    port Do[8] of cell WORD[37].W (WORD32)
    port Do[8] of cell WORD[38].W (WORD32)
    port Do[8] of cell WORD[39].W (WORD32)
    port Do[8] of cell WORD[3].W (WORD32)
    port Do[8] of cell WORD[40].W (WORD32)
    port Do[8] of cell WORD[41].W (WORD32)
    port Do[8] of cell WORD[42].W (WORD32)
    port Do[8] of cell WORD[43].W (WORD32)
    port Do[8] of cell WORD[44].W (WORD32)
    port Do[8] of cell WORD[45].W (WORD32)
    port Do[8] of cell WORD[46].W (WORD32)
    port Do[8] of cell WORD[47].W (WORD32)
    port Do[8] of cell WORD[48].W (WORD32)
    port Do[8] of cell WORD[49].W (WORD32)
    port Do[8] of cell WORD[4].W (WORD32)
    port Do[8] of cell WORD[50].W (WORD32)
    port Do[8] of cell WORD[51].W (WORD32)
    port Do[8] of cell WORD[52].W (WORD32)
    port Do[8] of cell WORD[53].W (WORD32)
    port Do[8] of cell WORD[54].W (WORD32)
    port Do[8] of cell WORD[55].W (WORD32)
    port Do[8] of cell WORD[56].W (WORD32)
    port Do[8] of cell WORD[57].W (WORD32)
    port Do[8] of cell WORD[58].W (WORD32)
    port Do[8] of cell WORD[59].W (WORD32)
    port Do[8] of cell WORD[5].W (WORD32)
    port Do[8] of cell WORD[60].W (WORD32)
    port Do[8] of cell WORD[61].W (WORD32)
    port Do[8] of cell WORD[62].W (WORD32)
    port Do[8] of cell WORD[63].W (WORD32)
    port Do[8] of cell WORD[6].W (WORD32)
    port Do[8] of cell WORD[7].W (WORD32)
    port Do[8] of cell WORD[8].W (WORD32)
    port Do[8] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[7]:

    port Z[0] of cell FLOATBUF[7] (sky130_fd_sc_hd__ebufn_4)
    port Do[7] of cell WORD[0].W (WORD32)
    port Do[7] of cell WORD[10].W (WORD32)
    port Do[7] of cell WORD[11].W (WORD32)
    port Do[7] of cell WORD[12].W (WORD32)
    port Do[7] of cell WORD[13].W (WORD32)
    port Do[7] of cell WORD[14].W (WORD32)
    port Do[7] of cell WORD[15].W (WORD32)
    port Do[7] of cell WORD[16].W (WORD32)
    port Do[7] of cell WORD[17].W (WORD32)
    port Do[7] of cell WORD[18].W (WORD32)
    port Do[7] of cell WORD[19].W (WORD32)
    port Do[7] of cell WORD[1].W (WORD32)
    port Do[7] of cell WORD[20].W (WORD32)
    port Do[7] of cell WORD[21].W (WORD32)
    port Do[7] of cell WORD[22].W (WORD32)
    port Do[7] of cell WORD[23].W (WORD32)
    port Do[7] of cell WORD[24].W (WORD32)
    port Do[7] of cell WORD[25].W (WORD32)
    port Do[7] of cell WORD[26].W (WORD32)
    port Do[7] of cell WORD[27].W (WORD32)
    port Do[7] of cell WORD[28].W (WORD32)
    port Do[7] of cell WORD[29].W (WORD32)
    port Do[7] of cell WORD[2].W (WORD32)
    port Do[7] of cell WORD[30].W (WORD32)
    port Do[7] of cell WORD[31].W (WORD32)
    port Do[7] of cell WORD[32].W (WORD32)
    port Do[7] of cell WORD[33].W (WORD32)
    port Do[7] of cell WORD[34].W (WORD32)
    port Do[7] of cell WORD[35].W (WORD32)
    port Do[7] of cell WORD[36].W (WORD32)
    port Do[7] of cell WORD[37].W (WORD32)
    port Do[7] of cell WORD[38].W (WORD32)
    port Do[7] of cell WORD[39].W (WORD32)
    port Do[7] of cell WORD[3].W (WORD32)
    port Do[7] of cell WORD[40].W (WORD32)
    port Do[7] of cell WORD[41].W (WORD32)
    port Do[7] of cell WORD[42].W (WORD32)
    port Do[7] of cell WORD[43].W (WORD32)
    port Do[7] of cell WORD[44].W (WORD32)
    port Do[7] of cell WORD[45].W (WORD32)
    port Do[7] of cell WORD[46].W (WORD32)
    port Do[7] of cell WORD[47].W (WORD32)
    port Do[7] of cell WORD[48].W (WORD32)
    port Do[7] of cell WORD[49].W (WORD32)
    port Do[7] of cell WORD[4].W (WORD32)
    port Do[7] of cell WORD[50].W (WORD32)
    port Do[7] of cell WORD[51].W (WORD32)
    port Do[7] of cell WORD[52].W (WORD32)
    port Do[7] of cell WORD[53].W (WORD32)
    port Do[7] of cell WORD[54].W (WORD32)
    port Do[7] of cell WORD[55].W (WORD32)
    port Do[7] of cell WORD[56].W (WORD32)
    port Do[7] of cell WORD[57].W (WORD32)
    port Do[7] of cell WORD[58].W (WORD32)
    port Do[7] of cell WORD[59].W (WORD32)
    port Do[7] of cell WORD[5].W (WORD32)
    port Do[7] of cell WORD[60].W (WORD32)
    port Do[7] of cell WORD[61].W (WORD32)
    port Do[7] of cell WORD[62].W (WORD32)
    port Do[7] of cell WORD[63].W (WORD32)
    port Do[7] of cell WORD[6].W (WORD32)
    port Do[7] of cell WORD[7].W (WORD32)
    port Do[7] of cell WORD[8].W (WORD32)
    port Do[7] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[6]:

    port Z[0] of cell FLOATBUF[6] (sky130_fd_sc_hd__ebufn_4)
    port Do[6] of cell WORD[0].W (WORD32)
    port Do[6] of cell WORD[10].W (WORD32)
    port Do[6] of cell WORD[11].W (WORD32)
    port Do[6] of cell WORD[12].W (WORD32)
    port Do[6] of cell WORD[13].W (WORD32)
    port Do[6] of cell WORD[14].W (WORD32)
    port Do[6] of cell WORD[15].W (WORD32)
    port Do[6] of cell WORD[16].W (WORD32)
    port Do[6] of cell WORD[17].W (WORD32)
    port Do[6] of cell WORD[18].W (WORD32)
    port Do[6] of cell WORD[19].W (WORD32)
    port Do[6] of cell WORD[1].W (WORD32)
    port Do[6] of cell WORD[20].W (WORD32)
    port Do[6] of cell WORD[21].W (WORD32)
    port Do[6] of cell WORD[22].W (WORD32)
    port Do[6] of cell WORD[23].W (WORD32)
    port Do[6] of cell WORD[24].W (WORD32)
    port Do[6] of cell WORD[25].W (WORD32)
    port Do[6] of cell WORD[26].W (WORD32)
    port Do[6] of cell WORD[27].W (WORD32)
    port Do[6] of cell WORD[28].W (WORD32)
    port Do[6] of cell WORD[29].W (WORD32)
    port Do[6] of cell WORD[2].W (WORD32)
    port Do[6] of cell WORD[30].W (WORD32)
    port Do[6] of cell WORD[31].W (WORD32)
    port Do[6] of cell WORD[32].W (WORD32)
    port Do[6] of cell WORD[33].W (WORD32)
    port Do[6] of cell WORD[34].W (WORD32)
    port Do[6] of cell WORD[35].W (WORD32)
    port Do[6] of cell WORD[36].W (WORD32)
    port Do[6] of cell WORD[37].W (WORD32)
    port Do[6] of cell WORD[38].W (WORD32)
    port Do[6] of cell WORD[39].W (WORD32)
    port Do[6] of cell WORD[3].W (WORD32)
    port Do[6] of cell WORD[40].W (WORD32)
    port Do[6] of cell WORD[41].W (WORD32)
    port Do[6] of cell WORD[42].W (WORD32)
    port Do[6] of cell WORD[43].W (WORD32)
    port Do[6] of cell WORD[44].W (WORD32)
    port Do[6] of cell WORD[45].W (WORD32)
    port Do[6] of cell WORD[46].W (WORD32)
    port Do[6] of cell WORD[47].W (WORD32)
    port Do[6] of cell WORD[48].W (WORD32)
    port Do[6] of cell WORD[49].W (WORD32)
    port Do[6] of cell WORD[4].W (WORD32)
    port Do[6] of cell WORD[50].W (WORD32)
    port Do[6] of cell WORD[51].W (WORD32)
    port Do[6] of cell WORD[52].W (WORD32)
    port Do[6] of cell WORD[53].W (WORD32)
    port Do[6] of cell WORD[54].W (WORD32)
    port Do[6] of cell WORD[55].W (WORD32)
    port Do[6] of cell WORD[56].W (WORD32)
    port Do[6] of cell WORD[57].W (WORD32)
    port Do[6] of cell WORD[58].W (WORD32)
    port Do[6] of cell WORD[59].W (WORD32)
    port Do[6] of cell WORD[5].W (WORD32)
    port Do[6] of cell WORD[60].W (WORD32)
    port Do[6] of cell WORD[61].W (WORD32)
    port Do[6] of cell WORD[62].W (WORD32)
    port Do[6] of cell WORD[63].W (WORD32)
    port Do[6] of cell WORD[6].W (WORD32)
    port Do[6] of cell WORD[7].W (WORD32)
    port Do[6] of cell WORD[8].W (WORD32)
    port Do[6] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[5]:

    port Z[0] of cell FLOATBUF[5] (sky130_fd_sc_hd__ebufn_4)
    port Do[5] of cell WORD[0].W (WORD32)
    port Do[5] of cell WORD[10].W (WORD32)
    port Do[5] of cell WORD[11].W (WORD32)
    port Do[5] of cell WORD[12].W (WORD32)
    port Do[5] of cell WORD[13].W (WORD32)
    port Do[5] of cell WORD[14].W (WORD32)
    port Do[5] of cell WORD[15].W (WORD32)
    port Do[5] of cell WORD[16].W (WORD32)
    port Do[5] of cell WORD[17].W (WORD32)
    port Do[5] of cell WORD[18].W (WORD32)
    port Do[5] of cell WORD[19].W (WORD32)
    port Do[5] of cell WORD[1].W (WORD32)
    port Do[5] of cell WORD[20].W (WORD32)
    port Do[5] of cell WORD[21].W (WORD32)
    port Do[5] of cell WORD[22].W (WORD32)
    port Do[5] of cell WORD[23].W (WORD32)
    port Do[5] of cell WORD[24].W (WORD32)
    port Do[5] of cell WORD[25].W (WORD32)
    port Do[5] of cell WORD[26].W (WORD32)
    port Do[5] of cell WORD[27].W (WORD32)
    port Do[5] of cell WORD[28].W (WORD32)
    port Do[5] of cell WORD[29].W (WORD32)
    port Do[5] of cell WORD[2].W (WORD32)
    port Do[5] of cell WORD[30].W (WORD32)
    port Do[5] of cell WORD[31].W (WORD32)
    port Do[5] of cell WORD[32].W (WORD32)
    port Do[5] of cell WORD[33].W (WORD32)
    port Do[5] of cell WORD[34].W (WORD32)
    port Do[5] of cell WORD[35].W (WORD32)
    port Do[5] of cell WORD[36].W (WORD32)
    port Do[5] of cell WORD[37].W (WORD32)
    port Do[5] of cell WORD[38].W (WORD32)
    port Do[5] of cell WORD[39].W (WORD32)
    port Do[5] of cell WORD[3].W (WORD32)
    port Do[5] of cell WORD[40].W (WORD32)
    port Do[5] of cell WORD[41].W (WORD32)
    port Do[5] of cell WORD[42].W (WORD32)
    port Do[5] of cell WORD[43].W (WORD32)
    port Do[5] of cell WORD[44].W (WORD32)
    port Do[5] of cell WORD[45].W (WORD32)
    port Do[5] of cell WORD[46].W (WORD32)
    port Do[5] of cell WORD[47].W (WORD32)
    port Do[5] of cell WORD[48].W (WORD32)
    port Do[5] of cell WORD[49].W (WORD32)
    port Do[5] of cell WORD[4].W (WORD32)
    port Do[5] of cell WORD[50].W (WORD32)
    port Do[5] of cell WORD[51].W (WORD32)
    port Do[5] of cell WORD[52].W (WORD32)
    port Do[5] of cell WORD[53].W (WORD32)
    port Do[5] of cell WORD[54].W (WORD32)
    port Do[5] of cell WORD[55].W (WORD32)
    port Do[5] of cell WORD[56].W (WORD32)
    port Do[5] of cell WORD[57].W (WORD32)
    port Do[5] of cell WORD[58].W (WORD32)
    port Do[5] of cell WORD[59].W (WORD32)
    port Do[5] of cell WORD[5].W (WORD32)
    port Do[5] of cell WORD[60].W (WORD32)
    port Do[5] of cell WORD[61].W (WORD32)
    port Do[5] of cell WORD[62].W (WORD32)
    port Do[5] of cell WORD[63].W (WORD32)
    port Do[5] of cell WORD[6].W (WORD32)
    port Do[5] of cell WORD[7].W (WORD32)
    port Do[5] of cell WORD[8].W (WORD32)
    port Do[5] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[4]:

    port Z[0] of cell FLOATBUF[4] (sky130_fd_sc_hd__ebufn_4)
    port Do[4] of cell WORD[0].W (WORD32)
    port Do[4] of cell WORD[10].W (WORD32)
    port Do[4] of cell WORD[11].W (WORD32)
    port Do[4] of cell WORD[12].W (WORD32)
    port Do[4] of cell WORD[13].W (WORD32)
    port Do[4] of cell WORD[14].W (WORD32)
    port Do[4] of cell WORD[15].W (WORD32)
    port Do[4] of cell WORD[16].W (WORD32)
    port Do[4] of cell WORD[17].W (WORD32)
    port Do[4] of cell WORD[18].W (WORD32)
    port Do[4] of cell WORD[19].W (WORD32)
    port Do[4] of cell WORD[1].W (WORD32)
    port Do[4] of cell WORD[20].W (WORD32)
    port Do[4] of cell WORD[21].W (WORD32)
    port Do[4] of cell WORD[22].W (WORD32)
    port Do[4] of cell WORD[23].W (WORD32)
    port Do[4] of cell WORD[24].W (WORD32)
    port Do[4] of cell WORD[25].W (WORD32)
    port Do[4] of cell WORD[26].W (WORD32)
    port Do[4] of cell WORD[27].W (WORD32)
    port Do[4] of cell WORD[28].W (WORD32)
    port Do[4] of cell WORD[29].W (WORD32)
    port Do[4] of cell WORD[2].W (WORD32)
    port Do[4] of cell WORD[30].W (WORD32)
    port Do[4] of cell WORD[31].W (WORD32)
    port Do[4] of cell WORD[32].W (WORD32)
    port Do[4] of cell WORD[33].W (WORD32)
    port Do[4] of cell WORD[34].W (WORD32)
    port Do[4] of cell WORD[35].W (WORD32)
    port Do[4] of cell WORD[36].W (WORD32)
    port Do[4] of cell WORD[37].W (WORD32)
    port Do[4] of cell WORD[38].W (WORD32)
    port Do[4] of cell WORD[39].W (WORD32)
    port Do[4] of cell WORD[3].W (WORD32)
    port Do[4] of cell WORD[40].W (WORD32)
    port Do[4] of cell WORD[41].W (WORD32)
    port Do[4] of cell WORD[42].W (WORD32)
    port Do[4] of cell WORD[43].W (WORD32)
    port Do[4] of cell WORD[44].W (WORD32)
    port Do[4] of cell WORD[45].W (WORD32)
    port Do[4] of cell WORD[46].W (WORD32)
    port Do[4] of cell WORD[47].W (WORD32)
    port Do[4] of cell WORD[48].W (WORD32)
    port Do[4] of cell WORD[49].W (WORD32)
    port Do[4] of cell WORD[4].W (WORD32)
    port Do[4] of cell WORD[50].W (WORD32)
    port Do[4] of cell WORD[51].W (WORD32)
    port Do[4] of cell WORD[52].W (WORD32)
    port Do[4] of cell WORD[53].W (WORD32)
    port Do[4] of cell WORD[54].W (WORD32)
    port Do[4] of cell WORD[55].W (WORD32)
    port Do[4] of cell WORD[56].W (WORD32)
    port Do[4] of cell WORD[57].W (WORD32)
    port Do[4] of cell WORD[58].W (WORD32)
    port Do[4] of cell WORD[59].W (WORD32)
    port Do[4] of cell WORD[5].W (WORD32)
    port Do[4] of cell WORD[60].W (WORD32)
    port Do[4] of cell WORD[61].W (WORD32)
    port Do[4] of cell WORD[62].W (WORD32)
    port Do[4] of cell WORD[63].W (WORD32)
    port Do[4] of cell WORD[6].W (WORD32)
    port Do[4] of cell WORD[7].W (WORD32)
    port Do[4] of cell WORD[8].W (WORD32)
    port Do[4] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[3]:

    port Z[0] of cell FLOATBUF[3] (sky130_fd_sc_hd__ebufn_4)
    port Do[3] of cell WORD[0].W (WORD32)
    port Do[3] of cell WORD[10].W (WORD32)
    port Do[3] of cell WORD[11].W (WORD32)
    port Do[3] of cell WORD[12].W (WORD32)
    port Do[3] of cell WORD[13].W (WORD32)
    port Do[3] of cell WORD[14].W (WORD32)
    port Do[3] of cell WORD[15].W (WORD32)
    port Do[3] of cell WORD[16].W (WORD32)
    port Do[3] of cell WORD[17].W (WORD32)
    port Do[3] of cell WORD[18].W (WORD32)
    port Do[3] of cell WORD[19].W (WORD32)
    port Do[3] of cell WORD[1].W (WORD32)
    port Do[3] of cell WORD[20].W (WORD32)
    port Do[3] of cell WORD[21].W (WORD32)
    port Do[3] of cell WORD[22].W (WORD32)
    port Do[3] of cell WORD[23].W (WORD32)
    port Do[3] of cell WORD[24].W (WORD32)
    port Do[3] of cell WORD[25].W (WORD32)
    port Do[3] of cell WORD[26].W (WORD32)
    port Do[3] of cell WORD[27].W (WORD32)
    port Do[3] of cell WORD[28].W (WORD32)
    port Do[3] of cell WORD[29].W (WORD32)
    port Do[3] of cell WORD[2].W (WORD32)
    port Do[3] of cell WORD[30].W (WORD32)
    port Do[3] of cell WORD[31].W (WORD32)
    port Do[3] of cell WORD[32].W (WORD32)
    port Do[3] of cell WORD[33].W (WORD32)
    port Do[3] of cell WORD[34].W (WORD32)
    port Do[3] of cell WORD[35].W (WORD32)
    port Do[3] of cell WORD[36].W (WORD32)
    port Do[3] of cell WORD[37].W (WORD32)
    port Do[3] of cell WORD[38].W (WORD32)
    port Do[3] of cell WORD[39].W (WORD32)
    port Do[3] of cell WORD[3].W (WORD32)
    port Do[3] of cell WORD[40].W (WORD32)
    port Do[3] of cell WORD[41].W (WORD32)
    port Do[3] of cell WORD[42].W (WORD32)
    port Do[3] of cell WORD[43].W (WORD32)
    port Do[3] of cell WORD[44].W (WORD32)
    port Do[3] of cell WORD[45].W (WORD32)
    port Do[3] of cell WORD[46].W (WORD32)
    port Do[3] of cell WORD[47].W (WORD32)
    port Do[3] of cell WORD[48].W (WORD32)
    port Do[3] of cell WORD[49].W (WORD32)
    port Do[3] of cell WORD[4].W (WORD32)
    port Do[3] of cell WORD[50].W (WORD32)
    port Do[3] of cell WORD[51].W (WORD32)
    port Do[3] of cell WORD[52].W (WORD32)
    port Do[3] of cell WORD[53].W (WORD32)
    port Do[3] of cell WORD[54].W (WORD32)
    port Do[3] of cell WORD[55].W (WORD32)
    port Do[3] of cell WORD[56].W (WORD32)
    port Do[3] of cell WORD[57].W (WORD32)
    port Do[3] of cell WORD[58].W (WORD32)
    port Do[3] of cell WORD[59].W (WORD32)
    port Do[3] of cell WORD[5].W (WORD32)
    port Do[3] of cell WORD[60].W (WORD32)
    port Do[3] of cell WORD[61].W (WORD32)
    port Do[3] of cell WORD[62].W (WORD32)
    port Do[3] of cell WORD[63].W (WORD32)
    port Do[3] of cell WORD[6].W (WORD32)
    port Do[3] of cell WORD[7].W (WORD32)
    port Do[3] of cell WORD[8].W (WORD32)
    port Do[3] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[31]:

    port Z[0] of cell FLOATBUF[31] (sky130_fd_sc_hd__ebufn_4)
    port Do[31] of cell WORD[0].W (WORD32)
    port Do[31] of cell WORD[10].W (WORD32)
    port Do[31] of cell WORD[11].W (WORD32)
    port Do[31] of cell WORD[12].W (WORD32)
    port Do[31] of cell WORD[13].W (WORD32)
    port Do[31] of cell WORD[14].W (WORD32)
    port Do[31] of cell WORD[15].W (WORD32)
    port Do[31] of cell WORD[16].W (WORD32)
    port Do[31] of cell WORD[17].W (WORD32)
    port Do[31] of cell WORD[18].W (WORD32)
    port Do[31] of cell WORD[19].W (WORD32)
    port Do[31] of cell WORD[1].W (WORD32)
    port Do[31] of cell WORD[20].W (WORD32)
    port Do[31] of cell WORD[21].W (WORD32)
    port Do[31] of cell WORD[22].W (WORD32)
    port Do[31] of cell WORD[23].W (WORD32)
    port Do[31] of cell WORD[24].W (WORD32)
    port Do[31] of cell WORD[25].W (WORD32)
    port Do[31] of cell WORD[26].W (WORD32)
    port Do[31] of cell WORD[27].W (WORD32)
    port Do[31] of cell WORD[28].W (WORD32)
    port Do[31] of cell WORD[29].W (WORD32)
    port Do[31] of cell WORD[2].W (WORD32)
    port Do[31] of cell WORD[30].W (WORD32)
    port Do[31] of cell WORD[31].W (WORD32)
    port Do[31] of cell WORD[32].W (WORD32)
    port Do[31] of cell WORD[33].W (WORD32)
    port Do[31] of cell WORD[34].W (WORD32)
    port Do[31] of cell WORD[35].W (WORD32)
    port Do[31] of cell WORD[36].W (WORD32)
    port Do[31] of cell WORD[37].W (WORD32)
    port Do[31] of cell WORD[38].W (WORD32)
    port Do[31] of cell WORD[39].W (WORD32)
    port Do[31] of cell WORD[3].W (WORD32)
    port Do[31] of cell WORD[40].W (WORD32)
    port Do[31] of cell WORD[41].W (WORD32)
    port Do[31] of cell WORD[42].W (WORD32)
    port Do[31] of cell WORD[43].W (WORD32)
    port Do[31] of cell WORD[44].W (WORD32)
    port Do[31] of cell WORD[45].W (WORD32)
    port Do[31] of cell WORD[46].W (WORD32)
    port Do[31] of cell WORD[47].W (WORD32)
    port Do[31] of cell WORD[48].W (WORD32)
    port Do[31] of cell WORD[49].W (WORD32)
    port Do[31] of cell WORD[4].W (WORD32)
    port Do[31] of cell WORD[50].W (WORD32)
    port Do[31] of cell WORD[51].W (WORD32)
    port Do[31] of cell WORD[52].W (WORD32)
    port Do[31] of cell WORD[53].W (WORD32)
    port Do[31] of cell WORD[54].W (WORD32)
    port Do[31] of cell WORD[55].W (WORD32)
    port Do[31] of cell WORD[56].W (WORD32)
    port Do[31] of cell WORD[57].W (WORD32)
    port Do[31] of cell WORD[58].W (WORD32)
    port Do[31] of cell WORD[59].W (WORD32)
    port Do[31] of cell WORD[5].W (WORD32)
    port Do[31] of cell WORD[60].W (WORD32)
    port Do[31] of cell WORD[61].W (WORD32)
    port Do[31] of cell WORD[62].W (WORD32)
    port Do[31] of cell WORD[63].W (WORD32)
    port Do[31] of cell WORD[6].W (WORD32)
    port Do[31] of cell WORD[7].W (WORD32)
    port Do[31] of cell WORD[8].W (WORD32)
    port Do[31] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[30]:

    port Z[0] of cell FLOATBUF[30] (sky130_fd_sc_hd__ebufn_4)
    port Do[30] of cell WORD[0].W (WORD32)
    port Do[30] of cell WORD[10].W (WORD32)
    port Do[30] of cell WORD[11].W (WORD32)
    port Do[30] of cell WORD[12].W (WORD32)
    port Do[30] of cell WORD[13].W (WORD32)
    port Do[30] of cell WORD[14].W (WORD32)
    port Do[30] of cell WORD[15].W (WORD32)
    port Do[30] of cell WORD[16].W (WORD32)
    port Do[30] of cell WORD[17].W (WORD32)
    port Do[30] of cell WORD[18].W (WORD32)
    port Do[30] of cell WORD[19].W (WORD32)
    port Do[30] of cell WORD[1].W (WORD32)
    port Do[30] of cell WORD[20].W (WORD32)
    port Do[30] of cell WORD[21].W (WORD32)
    port Do[30] of cell WORD[22].W (WORD32)
    port Do[30] of cell WORD[23].W (WORD32)
    port Do[30] of cell WORD[24].W (WORD32)
    port Do[30] of cell WORD[25].W (WORD32)
    port Do[30] of cell WORD[26].W (WORD32)
    port Do[30] of cell WORD[27].W (WORD32)
    port Do[30] of cell WORD[28].W (WORD32)
    port Do[30] of cell WORD[29].W (WORD32)
    port Do[30] of cell WORD[2].W (WORD32)
    port Do[30] of cell WORD[30].W (WORD32)
    port Do[30] of cell WORD[31].W (WORD32)
    port Do[30] of cell WORD[32].W (WORD32)
    port Do[30] of cell WORD[33].W (WORD32)
    port Do[30] of cell WORD[34].W (WORD32)
    port Do[30] of cell WORD[35].W (WORD32)
    port Do[30] of cell WORD[36].W (WORD32)
    port Do[30] of cell WORD[37].W (WORD32)
    port Do[30] of cell WORD[38].W (WORD32)
    port Do[30] of cell WORD[39].W (WORD32)
    port Do[30] of cell WORD[3].W (WORD32)
    port Do[30] of cell WORD[40].W (WORD32)
    port Do[30] of cell WORD[41].W (WORD32)
    port Do[30] of cell WORD[42].W (WORD32)
    port Do[30] of cell WORD[43].W (WORD32)
    port Do[30] of cell WORD[44].W (WORD32)
    port Do[30] of cell WORD[45].W (WORD32)
    port Do[30] of cell WORD[46].W (WORD32)
    port Do[30] of cell WORD[47].W (WORD32)
    port Do[30] of cell WORD[48].W (WORD32)
    port Do[30] of cell WORD[49].W (WORD32)
    port Do[30] of cell WORD[4].W (WORD32)
    port Do[30] of cell WORD[50].W (WORD32)
    port Do[30] of cell WORD[51].W (WORD32)
    port Do[30] of cell WORD[52].W (WORD32)
    port Do[30] of cell WORD[53].W (WORD32)
    port Do[30] of cell WORD[54].W (WORD32)
    port Do[30] of cell WORD[55].W (WORD32)
    port Do[30] of cell WORD[56].W (WORD32)
    port Do[30] of cell WORD[57].W (WORD32)
    port Do[30] of cell WORD[58].W (WORD32)
    port Do[30] of cell WORD[59].W (WORD32)
    port Do[30] of cell WORD[5].W (WORD32)
    port Do[30] of cell WORD[60].W (WORD32)
    port Do[30] of cell WORD[61].W (WORD32)
    port Do[30] of cell WORD[62].W (WORD32)
    port Do[30] of cell WORD[63].W (WORD32)
    port Do[30] of cell WORD[6].W (WORD32)
    port Do[30] of cell WORD[7].W (WORD32)
    port Do[30] of cell WORD[8].W (WORD32)
    port Do[30] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[2]:

    port Z[0] of cell FLOATBUF[2] (sky130_fd_sc_hd__ebufn_4)
    port Do[2] of cell WORD[0].W (WORD32)
    port Do[2] of cell WORD[10].W (WORD32)
    port Do[2] of cell WORD[11].W (WORD32)
    port Do[2] of cell WORD[12].W (WORD32)
    port Do[2] of cell WORD[13].W (WORD32)
    port Do[2] of cell WORD[14].W (WORD32)
    port Do[2] of cell WORD[15].W (WORD32)
    port Do[2] of cell WORD[16].W (WORD32)
    port Do[2] of cell WORD[17].W (WORD32)
    port Do[2] of cell WORD[18].W (WORD32)
    port Do[2] of cell WORD[19].W (WORD32)
    port Do[2] of cell WORD[1].W (WORD32)
    port Do[2] of cell WORD[20].W (WORD32)
    port Do[2] of cell WORD[21].W (WORD32)
    port Do[2] of cell WORD[22].W (WORD32)
    port Do[2] of cell WORD[23].W (WORD32)
    port Do[2] of cell WORD[24].W (WORD32)
    port Do[2] of cell WORD[25].W (WORD32)
    port Do[2] of cell WORD[26].W (WORD32)
    port Do[2] of cell WORD[27].W (WORD32)
    port Do[2] of cell WORD[28].W (WORD32)
    port Do[2] of cell WORD[29].W (WORD32)
    port Do[2] of cell WORD[2].W (WORD32)
    port Do[2] of cell WORD[30].W (WORD32)
    port Do[2] of cell WORD[31].W (WORD32)
    port Do[2] of cell WORD[32].W (WORD32)
    port Do[2] of cell WORD[33].W (WORD32)
    port Do[2] of cell WORD[34].W (WORD32)
    port Do[2] of cell WORD[35].W (WORD32)
    port Do[2] of cell WORD[36].W (WORD32)
    port Do[2] of cell WORD[37].W (WORD32)
    port Do[2] of cell WORD[38].W (WORD32)
    port Do[2] of cell WORD[39].W (WORD32)
    port Do[2] of cell WORD[3].W (WORD32)
    port Do[2] of cell WORD[40].W (WORD32)
    port Do[2] of cell WORD[41].W (WORD32)
    port Do[2] of cell WORD[42].W (WORD32)
    port Do[2] of cell WORD[43].W (WORD32)
    port Do[2] of cell WORD[44].W (WORD32)
    port Do[2] of cell WORD[45].W (WORD32)
    port Do[2] of cell WORD[46].W (WORD32)
    port Do[2] of cell WORD[47].W (WORD32)
    port Do[2] of cell WORD[48].W (WORD32)
    port Do[2] of cell WORD[49].W (WORD32)
    port Do[2] of cell WORD[4].W (WORD32)
    port Do[2] of cell WORD[50].W (WORD32)
    port Do[2] of cell WORD[51].W (WORD32)
    port Do[2] of cell WORD[52].W (WORD32)
    port Do[2] of cell WORD[53].W (WORD32)
    port Do[2] of cell WORD[54].W (WORD32)
    port Do[2] of cell WORD[55].W (WORD32)
    port Do[2] of cell WORD[56].W (WORD32)
    port Do[2] of cell WORD[57].W (WORD32)
    port Do[2] of cell WORD[58].W (WORD32)
    port Do[2] of cell WORD[59].W (WORD32)
    port Do[2] of cell WORD[5].W (WORD32)
    port Do[2] of cell WORD[60].W (WORD32)
    port Do[2] of cell WORD[61].W (WORD32)
    port Do[2] of cell WORD[62].W (WORD32)
    port Do[2] of cell WORD[63].W (WORD32)
    port Do[2] of cell WORD[6].W (WORD32)
    port Do[2] of cell WORD[7].W (WORD32)
    port Do[2] of cell WORD[8].W (WORD32)
    port Do[2] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[29]:

    port Z[0] of cell FLOATBUF[29] (sky130_fd_sc_hd__ebufn_4)
    port Do[29] of cell WORD[0].W (WORD32)
    port Do[29] of cell WORD[10].W (WORD32)
    port Do[29] of cell WORD[11].W (WORD32)
    port Do[29] of cell WORD[12].W (WORD32)
    port Do[29] of cell WORD[13].W (WORD32)
    port Do[29] of cell WORD[14].W (WORD32)
    port Do[29] of cell WORD[15].W (WORD32)
    port Do[29] of cell WORD[16].W (WORD32)
    port Do[29] of cell WORD[17].W (WORD32)
    port Do[29] of cell WORD[18].W (WORD32)
    port Do[29] of cell WORD[19].W (WORD32)
    port Do[29] of cell WORD[1].W (WORD32)
    port Do[29] of cell WORD[20].W (WORD32)
    port Do[29] of cell WORD[21].W (WORD32)
    port Do[29] of cell WORD[22].W (WORD32)
    port Do[29] of cell WORD[23].W (WORD32)
    port Do[29] of cell WORD[24].W (WORD32)
    port Do[29] of cell WORD[25].W (WORD32)
    port Do[29] of cell WORD[26].W (WORD32)
    port Do[29] of cell WORD[27].W (WORD32)
    port Do[29] of cell WORD[28].W (WORD32)
    port Do[29] of cell WORD[29].W (WORD32)
    port Do[29] of cell WORD[2].W (WORD32)
    port Do[29] of cell WORD[30].W (WORD32)
    port Do[29] of cell WORD[31].W (WORD32)
    port Do[29] of cell WORD[32].W (WORD32)
    port Do[29] of cell WORD[33].W (WORD32)
    port Do[29] of cell WORD[34].W (WORD32)
    port Do[29] of cell WORD[35].W (WORD32)
    port Do[29] of cell WORD[36].W (WORD32)
    port Do[29] of cell WORD[37].W (WORD32)
    port Do[29] of cell WORD[38].W (WORD32)
    port Do[29] of cell WORD[39].W (WORD32)
    port Do[29] of cell WORD[3].W (WORD32)
    port Do[29] of cell WORD[40].W (WORD32)
    port Do[29] of cell WORD[41].W (WORD32)
    port Do[29] of cell WORD[42].W (WORD32)
    port Do[29] of cell WORD[43].W (WORD32)
    port Do[29] of cell WORD[44].W (WORD32)
    port Do[29] of cell WORD[45].W (WORD32)
    port Do[29] of cell WORD[46].W (WORD32)
    port Do[29] of cell WORD[47].W (WORD32)
    port Do[29] of cell WORD[48].W (WORD32)
    port Do[29] of cell WORD[49].W (WORD32)
    port Do[29] of cell WORD[4].W (WORD32)
    port Do[29] of cell WORD[50].W (WORD32)
    port Do[29] of cell WORD[51].W (WORD32)
    port Do[29] of cell WORD[52].W (WORD32)
    port Do[29] of cell WORD[53].W (WORD32)
    port Do[29] of cell WORD[54].W (WORD32)
    port Do[29] of cell WORD[55].W (WORD32)
    port Do[29] of cell WORD[56].W (WORD32)
    port Do[29] of cell WORD[57].W (WORD32)
    port Do[29] of cell WORD[58].W (WORD32)
    port Do[29] of cell WORD[59].W (WORD32)
    port Do[29] of cell WORD[5].W (WORD32)
    port Do[29] of cell WORD[60].W (WORD32)
    port Do[29] of cell WORD[61].W (WORD32)
    port Do[29] of cell WORD[62].W (WORD32)
    port Do[29] of cell WORD[63].W (WORD32)
    port Do[29] of cell WORD[6].W (WORD32)
    port Do[29] of cell WORD[7].W (WORD32)
    port Do[29] of cell WORD[8].W (WORD32)
    port Do[29] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[28]:

    port Z[0] of cell FLOATBUF[28] (sky130_fd_sc_hd__ebufn_4)
    port Do[28] of cell WORD[0].W (WORD32)
    port Do[28] of cell WORD[10].W (WORD32)
    port Do[28] of cell WORD[11].W (WORD32)
    port Do[28] of cell WORD[12].W (WORD32)
    port Do[28] of cell WORD[13].W (WORD32)
    port Do[28] of cell WORD[14].W (WORD32)
    port Do[28] of cell WORD[15].W (WORD32)
    port Do[28] of cell WORD[16].W (WORD32)
    port Do[28] of cell WORD[17].W (WORD32)
    port Do[28] of cell WORD[18].W (WORD32)
    port Do[28] of cell WORD[19].W (WORD32)
    port Do[28] of cell WORD[1].W (WORD32)
    port Do[28] of cell WORD[20].W (WORD32)
    port Do[28] of cell WORD[21].W (WORD32)
    port Do[28] of cell WORD[22].W (WORD32)
    port Do[28] of cell WORD[23].W (WORD32)
    port Do[28] of cell WORD[24].W (WORD32)
    port Do[28] of cell WORD[25].W (WORD32)
    port Do[28] of cell WORD[26].W (WORD32)
    port Do[28] of cell WORD[27].W (WORD32)
    port Do[28] of cell WORD[28].W (WORD32)
    port Do[28] of cell WORD[29].W (WORD32)
    port Do[28] of cell WORD[2].W (WORD32)
    port Do[28] of cell WORD[30].W (WORD32)
    port Do[28] of cell WORD[31].W (WORD32)
    port Do[28] of cell WORD[32].W (WORD32)
    port Do[28] of cell WORD[33].W (WORD32)
    port Do[28] of cell WORD[34].W (WORD32)
    port Do[28] of cell WORD[35].W (WORD32)
    port Do[28] of cell WORD[36].W (WORD32)
    port Do[28] of cell WORD[37].W (WORD32)
    port Do[28] of cell WORD[38].W (WORD32)
    port Do[28] of cell WORD[39].W (WORD32)
    port Do[28] of cell WORD[3].W (WORD32)
    port Do[28] of cell WORD[40].W (WORD32)
    port Do[28] of cell WORD[41].W (WORD32)
    port Do[28] of cell WORD[42].W (WORD32)
    port Do[28] of cell WORD[43].W (WORD32)
    port Do[28] of cell WORD[44].W (WORD32)
    port Do[28] of cell WORD[45].W (WORD32)
    port Do[28] of cell WORD[46].W (WORD32)
    port Do[28] of cell WORD[47].W (WORD32)
    port Do[28] of cell WORD[48].W (WORD32)
    port Do[28] of cell WORD[49].W (WORD32)
    port Do[28] of cell WORD[4].W (WORD32)
    port Do[28] of cell WORD[50].W (WORD32)
    port Do[28] of cell WORD[51].W (WORD32)
    port Do[28] of cell WORD[52].W (WORD32)
    port Do[28] of cell WORD[53].W (WORD32)
    port Do[28] of cell WORD[54].W (WORD32)
    port Do[28] of cell WORD[55].W (WORD32)
    port Do[28] of cell WORD[56].W (WORD32)
    port Do[28] of cell WORD[57].W (WORD32)
    port Do[28] of cell WORD[58].W (WORD32)
    port Do[28] of cell WORD[59].W (WORD32)
    port Do[28] of cell WORD[5].W (WORD32)
    port Do[28] of cell WORD[60].W (WORD32)
    port Do[28] of cell WORD[61].W (WORD32)
    port Do[28] of cell WORD[62].W (WORD32)
    port Do[28] of cell WORD[63].W (WORD32)
    port Do[28] of cell WORD[6].W (WORD32)
    port Do[28] of cell WORD[7].W (WORD32)
    port Do[28] of cell WORD[8].W (WORD32)
    port Do[28] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[27]:

    port Z[0] of cell FLOATBUF[27] (sky130_fd_sc_hd__ebufn_4)
    port Do[27] of cell WORD[0].W (WORD32)
    port Do[27] of cell WORD[10].W (WORD32)
    port Do[27] of cell WORD[11].W (WORD32)
    port Do[27] of cell WORD[12].W (WORD32)
    port Do[27] of cell WORD[13].W (WORD32)
    port Do[27] of cell WORD[14].W (WORD32)
    port Do[27] of cell WORD[15].W (WORD32)
    port Do[27] of cell WORD[16].W (WORD32)
    port Do[27] of cell WORD[17].W (WORD32)
    port Do[27] of cell WORD[18].W (WORD32)
    port Do[27] of cell WORD[19].W (WORD32)
    port Do[27] of cell WORD[1].W (WORD32)
    port Do[27] of cell WORD[20].W (WORD32)
    port Do[27] of cell WORD[21].W (WORD32)
    port Do[27] of cell WORD[22].W (WORD32)
    port Do[27] of cell WORD[23].W (WORD32)
    port Do[27] of cell WORD[24].W (WORD32)
    port Do[27] of cell WORD[25].W (WORD32)
    port Do[27] of cell WORD[26].W (WORD32)
    port Do[27] of cell WORD[27].W (WORD32)
    port Do[27] of cell WORD[28].W (WORD32)
    port Do[27] of cell WORD[29].W (WORD32)
    port Do[27] of cell WORD[2].W (WORD32)
    port Do[27] of cell WORD[30].W (WORD32)
    port Do[27] of cell WORD[31].W (WORD32)
    port Do[27] of cell WORD[32].W (WORD32)
    port Do[27] of cell WORD[33].W (WORD32)
    port Do[27] of cell WORD[34].W (WORD32)
    port Do[27] of cell WORD[35].W (WORD32)
    port Do[27] of cell WORD[36].W (WORD32)
    port Do[27] of cell WORD[37].W (WORD32)
    port Do[27] of cell WORD[38].W (WORD32)
    port Do[27] of cell WORD[39].W (WORD32)
    port Do[27] of cell WORD[3].W (WORD32)
    port Do[27] of cell WORD[40].W (WORD32)
    port Do[27] of cell WORD[41].W (WORD32)
    port Do[27] of cell WORD[42].W (WORD32)
    port Do[27] of cell WORD[43].W (WORD32)
    port Do[27] of cell WORD[44].W (WORD32)
    port Do[27] of cell WORD[45].W (WORD32)
    port Do[27] of cell WORD[46].W (WORD32)
    port Do[27] of cell WORD[47].W (WORD32)
    port Do[27] of cell WORD[48].W (WORD32)
    port Do[27] of cell WORD[49].W (WORD32)
    port Do[27] of cell WORD[4].W (WORD32)
    port Do[27] of cell WORD[50].W (WORD32)
    port Do[27] of cell WORD[51].W (WORD32)
    port Do[27] of cell WORD[52].W (WORD32)
    port Do[27] of cell WORD[53].W (WORD32)
    port Do[27] of cell WORD[54].W (WORD32)
    port Do[27] of cell WORD[55].W (WORD32)
    port Do[27] of cell WORD[56].W (WORD32)
    port Do[27] of cell WORD[57].W (WORD32)
    port Do[27] of cell WORD[58].W (WORD32)
    port Do[27] of cell WORD[59].W (WORD32)
    port Do[27] of cell WORD[5].W (WORD32)
    port Do[27] of cell WORD[60].W (WORD32)
    port Do[27] of cell WORD[61].W (WORD32)
    port Do[27] of cell WORD[62].W (WORD32)
    port Do[27] of cell WORD[63].W (WORD32)
    port Do[27] of cell WORD[6].W (WORD32)
    port Do[27] of cell WORD[7].W (WORD32)
    port Do[27] of cell WORD[8].W (WORD32)
    port Do[27] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[26]:

    port Z[0] of cell FLOATBUF[26] (sky130_fd_sc_hd__ebufn_4)
    port Do[26] of cell WORD[0].W (WORD32)
    port Do[26] of cell WORD[10].W (WORD32)
    port Do[26] of cell WORD[11].W (WORD32)
    port Do[26] of cell WORD[12].W (WORD32)
    port Do[26] of cell WORD[13].W (WORD32)
    port Do[26] of cell WORD[14].W (WORD32)
    port Do[26] of cell WORD[15].W (WORD32)
    port Do[26] of cell WORD[16].W (WORD32)
    port Do[26] of cell WORD[17].W (WORD32)
    port Do[26] of cell WORD[18].W (WORD32)
    port Do[26] of cell WORD[19].W (WORD32)
    port Do[26] of cell WORD[1].W (WORD32)
    port Do[26] of cell WORD[20].W (WORD32)
    port Do[26] of cell WORD[21].W (WORD32)
    port Do[26] of cell WORD[22].W (WORD32)
    port Do[26] of cell WORD[23].W (WORD32)
    port Do[26] of cell WORD[24].W (WORD32)
    port Do[26] of cell WORD[25].W (WORD32)
    port Do[26] of cell WORD[26].W (WORD32)
    port Do[26] of cell WORD[27].W (WORD32)
    port Do[26] of cell WORD[28].W (WORD32)
    port Do[26] of cell WORD[29].W (WORD32)
    port Do[26] of cell WORD[2].W (WORD32)
    port Do[26] of cell WORD[30].W (WORD32)
    port Do[26] of cell WORD[31].W (WORD32)
    port Do[26] of cell WORD[32].W (WORD32)
    port Do[26] of cell WORD[33].W (WORD32)
    port Do[26] of cell WORD[34].W (WORD32)
    port Do[26] of cell WORD[35].W (WORD32)
    port Do[26] of cell WORD[36].W (WORD32)
    port Do[26] of cell WORD[37].W (WORD32)
    port Do[26] of cell WORD[38].W (WORD32)
    port Do[26] of cell WORD[39].W (WORD32)
    port Do[26] of cell WORD[3].W (WORD32)
    port Do[26] of cell WORD[40].W (WORD32)
    port Do[26] of cell WORD[41].W (WORD32)
    port Do[26] of cell WORD[42].W (WORD32)
    port Do[26] of cell WORD[43].W (WORD32)
    port Do[26] of cell WORD[44].W (WORD32)
    port Do[26] of cell WORD[45].W (WORD32)
    port Do[26] of cell WORD[46].W (WORD32)
    port Do[26] of cell WORD[47].W (WORD32)
    port Do[26] of cell WORD[48].W (WORD32)
    port Do[26] of cell WORD[49].W (WORD32)
    port Do[26] of cell WORD[4].W (WORD32)
    port Do[26] of cell WORD[50].W (WORD32)
    port Do[26] of cell WORD[51].W (WORD32)
    port Do[26] of cell WORD[52].W (WORD32)
    port Do[26] of cell WORD[53].W (WORD32)
    port Do[26] of cell WORD[54].W (WORD32)
    port Do[26] of cell WORD[55].W (WORD32)
    port Do[26] of cell WORD[56].W (WORD32)
    port Do[26] of cell WORD[57].W (WORD32)
    port Do[26] of cell WORD[58].W (WORD32)
    port Do[26] of cell WORD[59].W (WORD32)
    port Do[26] of cell WORD[5].W (WORD32)
    port Do[26] of cell WORD[60].W (WORD32)
    port Do[26] of cell WORD[61].W (WORD32)
    port Do[26] of cell WORD[62].W (WORD32)
    port Do[26] of cell WORD[63].W (WORD32)
    port Do[26] of cell WORD[6].W (WORD32)
    port Do[26] of cell WORD[7].W (WORD32)
    port Do[26] of cell WORD[8].W (WORD32)
    port Do[26] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[25]:

    port Z[0] of cell FLOATBUF[25] (sky130_fd_sc_hd__ebufn_4)
    port Do[25] of cell WORD[0].W (WORD32)
    port Do[25] of cell WORD[10].W (WORD32)
    port Do[25] of cell WORD[11].W (WORD32)
    port Do[25] of cell WORD[12].W (WORD32)
    port Do[25] of cell WORD[13].W (WORD32)
    port Do[25] of cell WORD[14].W (WORD32)
    port Do[25] of cell WORD[15].W (WORD32)
    port Do[25] of cell WORD[16].W (WORD32)
    port Do[25] of cell WORD[17].W (WORD32)
    port Do[25] of cell WORD[18].W (WORD32)
    port Do[25] of cell WORD[19].W (WORD32)
    port Do[25] of cell WORD[1].W (WORD32)
    port Do[25] of cell WORD[20].W (WORD32)
    port Do[25] of cell WORD[21].W (WORD32)
    port Do[25] of cell WORD[22].W (WORD32)
    port Do[25] of cell WORD[23].W (WORD32)
    port Do[25] of cell WORD[24].W (WORD32)
    port Do[25] of cell WORD[25].W (WORD32)
    port Do[25] of cell WORD[26].W (WORD32)
    port Do[25] of cell WORD[27].W (WORD32)
    port Do[25] of cell WORD[28].W (WORD32)
    port Do[25] of cell WORD[29].W (WORD32)
    port Do[25] of cell WORD[2].W (WORD32)
    port Do[25] of cell WORD[30].W (WORD32)
    port Do[25] of cell WORD[31].W (WORD32)
    port Do[25] of cell WORD[32].W (WORD32)
    port Do[25] of cell WORD[33].W (WORD32)
    port Do[25] of cell WORD[34].W (WORD32)
    port Do[25] of cell WORD[35].W (WORD32)
    port Do[25] of cell WORD[36].W (WORD32)
    port Do[25] of cell WORD[37].W (WORD32)
    port Do[25] of cell WORD[38].W (WORD32)
    port Do[25] of cell WORD[39].W (WORD32)
    port Do[25] of cell WORD[3].W (WORD32)
    port Do[25] of cell WORD[40].W (WORD32)
    port Do[25] of cell WORD[41].W (WORD32)
    port Do[25] of cell WORD[42].W (WORD32)
    port Do[25] of cell WORD[43].W (WORD32)
    port Do[25] of cell WORD[44].W (WORD32)
    port Do[25] of cell WORD[45].W (WORD32)
    port Do[25] of cell WORD[46].W (WORD32)
    port Do[25] of cell WORD[47].W (WORD32)
    port Do[25] of cell WORD[48].W (WORD32)
    port Do[25] of cell WORD[49].W (WORD32)
    port Do[25] of cell WORD[4].W (WORD32)
    port Do[25] of cell WORD[50].W (WORD32)
    port Do[25] of cell WORD[51].W (WORD32)
    port Do[25] of cell WORD[52].W (WORD32)
    port Do[25] of cell WORD[53].W (WORD32)
    port Do[25] of cell WORD[54].W (WORD32)
    port Do[25] of cell WORD[55].W (WORD32)
    port Do[25] of cell WORD[56].W (WORD32)
    port Do[25] of cell WORD[57].W (WORD32)
    port Do[25] of cell WORD[58].W (WORD32)
    port Do[25] of cell WORD[59].W (WORD32)
    port Do[25] of cell WORD[5].W (WORD32)
    port Do[25] of cell WORD[60].W (WORD32)
    port Do[25] of cell WORD[61].W (WORD32)
    port Do[25] of cell WORD[62].W (WORD32)
    port Do[25] of cell WORD[63].W (WORD32)
    port Do[25] of cell WORD[6].W (WORD32)
    port Do[25] of cell WORD[7].W (WORD32)
    port Do[25] of cell WORD[8].W (WORD32)
    port Do[25] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[24]:

    port Z[0] of cell FLOATBUF[24] (sky130_fd_sc_hd__ebufn_4)
    port Do[24] of cell WORD[0].W (WORD32)
    port Do[24] of cell WORD[10].W (WORD32)
    port Do[24] of cell WORD[11].W (WORD32)
    port Do[24] of cell WORD[12].W (WORD32)
    port Do[24] of cell WORD[13].W (WORD32)
    port Do[24] of cell WORD[14].W (WORD32)
    port Do[24] of cell WORD[15].W (WORD32)
    port Do[24] of cell WORD[16].W (WORD32)
    port Do[24] of cell WORD[17].W (WORD32)
    port Do[24] of cell WORD[18].W (WORD32)
    port Do[24] of cell WORD[19].W (WORD32)
    port Do[24] of cell WORD[1].W (WORD32)
    port Do[24] of cell WORD[20].W (WORD32)
    port Do[24] of cell WORD[21].W (WORD32)
    port Do[24] of cell WORD[22].W (WORD32)
    port Do[24] of cell WORD[23].W (WORD32)
    port Do[24] of cell WORD[24].W (WORD32)
    port Do[24] of cell WORD[25].W (WORD32)
    port Do[24] of cell WORD[26].W (WORD32)
    port Do[24] of cell WORD[27].W (WORD32)
    port Do[24] of cell WORD[28].W (WORD32)
    port Do[24] of cell WORD[29].W (WORD32)
    port Do[24] of cell WORD[2].W (WORD32)
    port Do[24] of cell WORD[30].W (WORD32)
    port Do[24] of cell WORD[31].W (WORD32)
    port Do[24] of cell WORD[32].W (WORD32)
    port Do[24] of cell WORD[33].W (WORD32)
    port Do[24] of cell WORD[34].W (WORD32)
    port Do[24] of cell WORD[35].W (WORD32)
    port Do[24] of cell WORD[36].W (WORD32)
    port Do[24] of cell WORD[37].W (WORD32)
    port Do[24] of cell WORD[38].W (WORD32)
    port Do[24] of cell WORD[39].W (WORD32)
    port Do[24] of cell WORD[3].W (WORD32)
    port Do[24] of cell WORD[40].W (WORD32)
    port Do[24] of cell WORD[41].W (WORD32)
    port Do[24] of cell WORD[42].W (WORD32)
    port Do[24] of cell WORD[43].W (WORD32)
    port Do[24] of cell WORD[44].W (WORD32)
    port Do[24] of cell WORD[45].W (WORD32)
    port Do[24] of cell WORD[46].W (WORD32)
    port Do[24] of cell WORD[47].W (WORD32)
    port Do[24] of cell WORD[48].W (WORD32)
    port Do[24] of cell WORD[49].W (WORD32)
    port Do[24] of cell WORD[4].W (WORD32)
    port Do[24] of cell WORD[50].W (WORD32)
    port Do[24] of cell WORD[51].W (WORD32)
    port Do[24] of cell WORD[52].W (WORD32)
    port Do[24] of cell WORD[53].W (WORD32)
    port Do[24] of cell WORD[54].W (WORD32)
    port Do[24] of cell WORD[55].W (WORD32)
    port Do[24] of cell WORD[56].W (WORD32)
    port Do[24] of cell WORD[57].W (WORD32)
    port Do[24] of cell WORD[58].W (WORD32)
    port Do[24] of cell WORD[59].W (WORD32)
    port Do[24] of cell WORD[5].W (WORD32)
    port Do[24] of cell WORD[60].W (WORD32)
    port Do[24] of cell WORD[61].W (WORD32)
    port Do[24] of cell WORD[62].W (WORD32)
    port Do[24] of cell WORD[63].W (WORD32)
    port Do[24] of cell WORD[6].W (WORD32)
    port Do[24] of cell WORD[7].W (WORD32)
    port Do[24] of cell WORD[8].W (WORD32)
    port Do[24] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[23]:

    port Z[0] of cell FLOATBUF[23] (sky130_fd_sc_hd__ebufn_4)
    port Do[23] of cell WORD[0].W (WORD32)
    port Do[23] of cell WORD[10].W (WORD32)
    port Do[23] of cell WORD[11].W (WORD32)
    port Do[23] of cell WORD[12].W (WORD32)
    port Do[23] of cell WORD[13].W (WORD32)
    port Do[23] of cell WORD[14].W (WORD32)
    port Do[23] of cell WORD[15].W (WORD32)
    port Do[23] of cell WORD[16].W (WORD32)
    port Do[23] of cell WORD[17].W (WORD32)
    port Do[23] of cell WORD[18].W (WORD32)
    port Do[23] of cell WORD[19].W (WORD32)
    port Do[23] of cell WORD[1].W (WORD32)
    port Do[23] of cell WORD[20].W (WORD32)
    port Do[23] of cell WORD[21].W (WORD32)
    port Do[23] of cell WORD[22].W (WORD32)
    port Do[23] of cell WORD[23].W (WORD32)
    port Do[23] of cell WORD[24].W (WORD32)
    port Do[23] of cell WORD[25].W (WORD32)
    port Do[23] of cell WORD[26].W (WORD32)
    port Do[23] of cell WORD[27].W (WORD32)
    port Do[23] of cell WORD[28].W (WORD32)
    port Do[23] of cell WORD[29].W (WORD32)
    port Do[23] of cell WORD[2].W (WORD32)
    port Do[23] of cell WORD[30].W (WORD32)
    port Do[23] of cell WORD[31].W (WORD32)
    port Do[23] of cell WORD[32].W (WORD32)
    port Do[23] of cell WORD[33].W (WORD32)
    port Do[23] of cell WORD[34].W (WORD32)
    port Do[23] of cell WORD[35].W (WORD32)
    port Do[23] of cell WORD[36].W (WORD32)
    port Do[23] of cell WORD[37].W (WORD32)
    port Do[23] of cell WORD[38].W (WORD32)
    port Do[23] of cell WORD[39].W (WORD32)
    port Do[23] of cell WORD[3].W (WORD32)
    port Do[23] of cell WORD[40].W (WORD32)
    port Do[23] of cell WORD[41].W (WORD32)
    port Do[23] of cell WORD[42].W (WORD32)
    port Do[23] of cell WORD[43].W (WORD32)
    port Do[23] of cell WORD[44].W (WORD32)
    port Do[23] of cell WORD[45].W (WORD32)
    port Do[23] of cell WORD[46].W (WORD32)
    port Do[23] of cell WORD[47].W (WORD32)
    port Do[23] of cell WORD[48].W (WORD32)
    port Do[23] of cell WORD[49].W (WORD32)
    port Do[23] of cell WORD[4].W (WORD32)
    port Do[23] of cell WORD[50].W (WORD32)
    port Do[23] of cell WORD[51].W (WORD32)
    port Do[23] of cell WORD[52].W (WORD32)
    port Do[23] of cell WORD[53].W (WORD32)
    port Do[23] of cell WORD[54].W (WORD32)
    port Do[23] of cell WORD[55].W (WORD32)
    port Do[23] of cell WORD[56].W (WORD32)
    port Do[23] of cell WORD[57].W (WORD32)
    port Do[23] of cell WORD[58].W (WORD32)
    port Do[23] of cell WORD[59].W (WORD32)
    port Do[23] of cell WORD[5].W (WORD32)
    port Do[23] of cell WORD[60].W (WORD32)
    port Do[23] of cell WORD[61].W (WORD32)
    port Do[23] of cell WORD[62].W (WORD32)
    port Do[23] of cell WORD[63].W (WORD32)
    port Do[23] of cell WORD[6].W (WORD32)
    port Do[23] of cell WORD[7].W (WORD32)
    port Do[23] of cell WORD[8].W (WORD32)
    port Do[23] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[22]:

    port Z[0] of cell FLOATBUF[22] (sky130_fd_sc_hd__ebufn_4)
    port Do[22] of cell WORD[0].W (WORD32)
    port Do[22] of cell WORD[10].W (WORD32)
    port Do[22] of cell WORD[11].W (WORD32)
    port Do[22] of cell WORD[12].W (WORD32)
    port Do[22] of cell WORD[13].W (WORD32)
    port Do[22] of cell WORD[14].W (WORD32)
    port Do[22] of cell WORD[15].W (WORD32)
    port Do[22] of cell WORD[16].W (WORD32)
    port Do[22] of cell WORD[17].W (WORD32)
    port Do[22] of cell WORD[18].W (WORD32)
    port Do[22] of cell WORD[19].W (WORD32)
    port Do[22] of cell WORD[1].W (WORD32)
    port Do[22] of cell WORD[20].W (WORD32)
    port Do[22] of cell WORD[21].W (WORD32)
    port Do[22] of cell WORD[22].W (WORD32)
    port Do[22] of cell WORD[23].W (WORD32)
    port Do[22] of cell WORD[24].W (WORD32)
    port Do[22] of cell WORD[25].W (WORD32)
    port Do[22] of cell WORD[26].W (WORD32)
    port Do[22] of cell WORD[27].W (WORD32)
    port Do[22] of cell WORD[28].W (WORD32)
    port Do[22] of cell WORD[29].W (WORD32)
    port Do[22] of cell WORD[2].W (WORD32)
    port Do[22] of cell WORD[30].W (WORD32)
    port Do[22] of cell WORD[31].W (WORD32)
    port Do[22] of cell WORD[32].W (WORD32)
    port Do[22] of cell WORD[33].W (WORD32)
    port Do[22] of cell WORD[34].W (WORD32)
    port Do[22] of cell WORD[35].W (WORD32)
    port Do[22] of cell WORD[36].W (WORD32)
    port Do[22] of cell WORD[37].W (WORD32)
    port Do[22] of cell WORD[38].W (WORD32)
    port Do[22] of cell WORD[39].W (WORD32)
    port Do[22] of cell WORD[3].W (WORD32)
    port Do[22] of cell WORD[40].W (WORD32)
    port Do[22] of cell WORD[41].W (WORD32)
    port Do[22] of cell WORD[42].W (WORD32)
    port Do[22] of cell WORD[43].W (WORD32)
    port Do[22] of cell WORD[44].W (WORD32)
    port Do[22] of cell WORD[45].W (WORD32)
    port Do[22] of cell WORD[46].W (WORD32)
    port Do[22] of cell WORD[47].W (WORD32)
    port Do[22] of cell WORD[48].W (WORD32)
    port Do[22] of cell WORD[49].W (WORD32)
    port Do[22] of cell WORD[4].W (WORD32)
    port Do[22] of cell WORD[50].W (WORD32)
    port Do[22] of cell WORD[51].W (WORD32)
    port Do[22] of cell WORD[52].W (WORD32)
    port Do[22] of cell WORD[53].W (WORD32)
    port Do[22] of cell WORD[54].W (WORD32)
    port Do[22] of cell WORD[55].W (WORD32)
    port Do[22] of cell WORD[56].W (WORD32)
    port Do[22] of cell WORD[57].W (WORD32)
    port Do[22] of cell WORD[58].W (WORD32)
    port Do[22] of cell WORD[59].W (WORD32)
    port Do[22] of cell WORD[5].W (WORD32)
    port Do[22] of cell WORD[60].W (WORD32)
    port Do[22] of cell WORD[61].W (WORD32)
    port Do[22] of cell WORD[62].W (WORD32)
    port Do[22] of cell WORD[63].W (WORD32)
    port Do[22] of cell WORD[6].W (WORD32)
    port Do[22] of cell WORD[7].W (WORD32)
    port Do[22] of cell WORD[8].W (WORD32)
    port Do[22] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[21]:

    port Z[0] of cell FLOATBUF[21] (sky130_fd_sc_hd__ebufn_4)
    port Do[21] of cell WORD[0].W (WORD32)
    port Do[21] of cell WORD[10].W (WORD32)
    port Do[21] of cell WORD[11].W (WORD32)
    port Do[21] of cell WORD[12].W (WORD32)
    port Do[21] of cell WORD[13].W (WORD32)
    port Do[21] of cell WORD[14].W (WORD32)
    port Do[21] of cell WORD[15].W (WORD32)
    port Do[21] of cell WORD[16].W (WORD32)
    port Do[21] of cell WORD[17].W (WORD32)
    port Do[21] of cell WORD[18].W (WORD32)
    port Do[21] of cell WORD[19].W (WORD32)
    port Do[21] of cell WORD[1].W (WORD32)
    port Do[21] of cell WORD[20].W (WORD32)
    port Do[21] of cell WORD[21].W (WORD32)
    port Do[21] of cell WORD[22].W (WORD32)
    port Do[21] of cell WORD[23].W (WORD32)
    port Do[21] of cell WORD[24].W (WORD32)
    port Do[21] of cell WORD[25].W (WORD32)
    port Do[21] of cell WORD[26].W (WORD32)
    port Do[21] of cell WORD[27].W (WORD32)
    port Do[21] of cell WORD[28].W (WORD32)
    port Do[21] of cell WORD[29].W (WORD32)
    port Do[21] of cell WORD[2].W (WORD32)
    port Do[21] of cell WORD[30].W (WORD32)
    port Do[21] of cell WORD[31].W (WORD32)
    port Do[21] of cell WORD[32].W (WORD32)
    port Do[21] of cell WORD[33].W (WORD32)
    port Do[21] of cell WORD[34].W (WORD32)
    port Do[21] of cell WORD[35].W (WORD32)
    port Do[21] of cell WORD[36].W (WORD32)
    port Do[21] of cell WORD[37].W (WORD32)
    port Do[21] of cell WORD[38].W (WORD32)
    port Do[21] of cell WORD[39].W (WORD32)
    port Do[21] of cell WORD[3].W (WORD32)
    port Do[21] of cell WORD[40].W (WORD32)
    port Do[21] of cell WORD[41].W (WORD32)
    port Do[21] of cell WORD[42].W (WORD32)
    port Do[21] of cell WORD[43].W (WORD32)
    port Do[21] of cell WORD[44].W (WORD32)
    port Do[21] of cell WORD[45].W (WORD32)
    port Do[21] of cell WORD[46].W (WORD32)
    port Do[21] of cell WORD[47].W (WORD32)
    port Do[21] of cell WORD[48].W (WORD32)
    port Do[21] of cell WORD[49].W (WORD32)
    port Do[21] of cell WORD[4].W (WORD32)
    port Do[21] of cell WORD[50].W (WORD32)
    port Do[21] of cell WORD[51].W (WORD32)
    port Do[21] of cell WORD[52].W (WORD32)
    port Do[21] of cell WORD[53].W (WORD32)
    port Do[21] of cell WORD[54].W (WORD32)
    port Do[21] of cell WORD[55].W (WORD32)
    port Do[21] of cell WORD[56].W (WORD32)
    port Do[21] of cell WORD[57].W (WORD32)
    port Do[21] of cell WORD[58].W (WORD32)
    port Do[21] of cell WORD[59].W (WORD32)
    port Do[21] of cell WORD[5].W (WORD32)
    port Do[21] of cell WORD[60].W (WORD32)
    port Do[21] of cell WORD[61].W (WORD32)
    port Do[21] of cell WORD[62].W (WORD32)
    port Do[21] of cell WORD[63].W (WORD32)
    port Do[21] of cell WORD[6].W (WORD32)
    port Do[21] of cell WORD[7].W (WORD32)
    port Do[21] of cell WORD[8].W (WORD32)
    port Do[21] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[20]:

    port Z[0] of cell FLOATBUF[20] (sky130_fd_sc_hd__ebufn_4)
    port Do[20] of cell WORD[0].W (WORD32)
    port Do[20] of cell WORD[10].W (WORD32)
    port Do[20] of cell WORD[11].W (WORD32)
    port Do[20] of cell WORD[12].W (WORD32)
    port Do[20] of cell WORD[13].W (WORD32)
    port Do[20] of cell WORD[14].W (WORD32)
    port Do[20] of cell WORD[15].W (WORD32)
    port Do[20] of cell WORD[16].W (WORD32)
    port Do[20] of cell WORD[17].W (WORD32)
    port Do[20] of cell WORD[18].W (WORD32)
    port Do[20] of cell WORD[19].W (WORD32)
    port Do[20] of cell WORD[1].W (WORD32)
    port Do[20] of cell WORD[20].W (WORD32)
    port Do[20] of cell WORD[21].W (WORD32)
    port Do[20] of cell WORD[22].W (WORD32)
    port Do[20] of cell WORD[23].W (WORD32)
    port Do[20] of cell WORD[24].W (WORD32)
    port Do[20] of cell WORD[25].W (WORD32)
    port Do[20] of cell WORD[26].W (WORD32)
    port Do[20] of cell WORD[27].W (WORD32)
    port Do[20] of cell WORD[28].W (WORD32)
    port Do[20] of cell WORD[29].W (WORD32)
    port Do[20] of cell WORD[2].W (WORD32)
    port Do[20] of cell WORD[30].W (WORD32)
    port Do[20] of cell WORD[31].W (WORD32)
    port Do[20] of cell WORD[32].W (WORD32)
    port Do[20] of cell WORD[33].W (WORD32)
    port Do[20] of cell WORD[34].W (WORD32)
    port Do[20] of cell WORD[35].W (WORD32)
    port Do[20] of cell WORD[36].W (WORD32)
    port Do[20] of cell WORD[37].W (WORD32)
    port Do[20] of cell WORD[38].W (WORD32)
    port Do[20] of cell WORD[39].W (WORD32)
    port Do[20] of cell WORD[3].W (WORD32)
    port Do[20] of cell WORD[40].W (WORD32)
    port Do[20] of cell WORD[41].W (WORD32)
    port Do[20] of cell WORD[42].W (WORD32)
    port Do[20] of cell WORD[43].W (WORD32)
    port Do[20] of cell WORD[44].W (WORD32)
    port Do[20] of cell WORD[45].W (WORD32)
    port Do[20] of cell WORD[46].W (WORD32)
    port Do[20] of cell WORD[47].W (WORD32)
    port Do[20] of cell WORD[48].W (WORD32)
    port Do[20] of cell WORD[49].W (WORD32)
    port Do[20] of cell WORD[4].W (WORD32)
    port Do[20] of cell WORD[50].W (WORD32)
    port Do[20] of cell WORD[51].W (WORD32)
    port Do[20] of cell WORD[52].W (WORD32)
    port Do[20] of cell WORD[53].W (WORD32)
    port Do[20] of cell WORD[54].W (WORD32)
    port Do[20] of cell WORD[55].W (WORD32)
    port Do[20] of cell WORD[56].W (WORD32)
    port Do[20] of cell WORD[57].W (WORD32)
    port Do[20] of cell WORD[58].W (WORD32)
    port Do[20] of cell WORD[59].W (WORD32)
    port Do[20] of cell WORD[5].W (WORD32)
    port Do[20] of cell WORD[60].W (WORD32)
    port Do[20] of cell WORD[61].W (WORD32)
    port Do[20] of cell WORD[62].W (WORD32)
    port Do[20] of cell WORD[63].W (WORD32)
    port Do[20] of cell WORD[6].W (WORD32)
    port Do[20] of cell WORD[7].W (WORD32)
    port Do[20] of cell WORD[8].W (WORD32)
    port Do[20] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[1]:

    port Z[0] of cell FLOATBUF[1] (sky130_fd_sc_hd__ebufn_4)
    port Do[1] of cell WORD[0].W (WORD32)
    port Do[1] of cell WORD[10].W (WORD32)
    port Do[1] of cell WORD[11].W (WORD32)
    port Do[1] of cell WORD[12].W (WORD32)
    port Do[1] of cell WORD[13].W (WORD32)
    port Do[1] of cell WORD[14].W (WORD32)
    port Do[1] of cell WORD[15].W (WORD32)
    port Do[1] of cell WORD[16].W (WORD32)
    port Do[1] of cell WORD[17].W (WORD32)
    port Do[1] of cell WORD[18].W (WORD32)
    port Do[1] of cell WORD[19].W (WORD32)
    port Do[1] of cell WORD[1].W (WORD32)
    port Do[1] of cell WORD[20].W (WORD32)
    port Do[1] of cell WORD[21].W (WORD32)
    port Do[1] of cell WORD[22].W (WORD32)
    port Do[1] of cell WORD[23].W (WORD32)
    port Do[1] of cell WORD[24].W (WORD32)
    port Do[1] of cell WORD[25].W (WORD32)
    port Do[1] of cell WORD[26].W (WORD32)
    port Do[1] of cell WORD[27].W (WORD32)
    port Do[1] of cell WORD[28].W (WORD32)
    port Do[1] of cell WORD[29].W (WORD32)
    port Do[1] of cell WORD[2].W (WORD32)
    port Do[1] of cell WORD[30].W (WORD32)
    port Do[1] of cell WORD[31].W (WORD32)
    port Do[1] of cell WORD[32].W (WORD32)
    port Do[1] of cell WORD[33].W (WORD32)
    port Do[1] of cell WORD[34].W (WORD32)
    port Do[1] of cell WORD[35].W (WORD32)
    port Do[1] of cell WORD[36].W (WORD32)
    port Do[1] of cell WORD[37].W (WORD32)
    port Do[1] of cell WORD[38].W (WORD32)
    port Do[1] of cell WORD[39].W (WORD32)
    port Do[1] of cell WORD[3].W (WORD32)
    port Do[1] of cell WORD[40].W (WORD32)
    port Do[1] of cell WORD[41].W (WORD32)
    port Do[1] of cell WORD[42].W (WORD32)
    port Do[1] of cell WORD[43].W (WORD32)
    port Do[1] of cell WORD[44].W (WORD32)
    port Do[1] of cell WORD[45].W (WORD32)
    port Do[1] of cell WORD[46].W (WORD32)
    port Do[1] of cell WORD[47].W (WORD32)
    port Do[1] of cell WORD[48].W (WORD32)
    port Do[1] of cell WORD[49].W (WORD32)
    port Do[1] of cell WORD[4].W (WORD32)
    port Do[1] of cell WORD[50].W (WORD32)
    port Do[1] of cell WORD[51].W (WORD32)
    port Do[1] of cell WORD[52].W (WORD32)
    port Do[1] of cell WORD[53].W (WORD32)
    port Do[1] of cell WORD[54].W (WORD32)
    port Do[1] of cell WORD[55].W (WORD32)
    port Do[1] of cell WORD[56].W (WORD32)
    port Do[1] of cell WORD[57].W (WORD32)
    port Do[1] of cell WORD[58].W (WORD32)
    port Do[1] of cell WORD[59].W (WORD32)
    port Do[1] of cell WORD[5].W (WORD32)
    port Do[1] of cell WORD[60].W (WORD32)
    port Do[1] of cell WORD[61].W (WORD32)
    port Do[1] of cell WORD[62].W (WORD32)
    port Do[1] of cell WORD[63].W (WORD32)
    port Do[1] of cell WORD[6].W (WORD32)
    port Do[1] of cell WORD[7].W (WORD32)
    port Do[1] of cell WORD[8].W (WORD32)
    port Do[1] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[19]:

    port Z[0] of cell FLOATBUF[19] (sky130_fd_sc_hd__ebufn_4)
    port Do[19] of cell WORD[0].W (WORD32)
    port Do[19] of cell WORD[10].W (WORD32)
    port Do[19] of cell WORD[11].W (WORD32)
    port Do[19] of cell WORD[12].W (WORD32)
    port Do[19] of cell WORD[13].W (WORD32)
    port Do[19] of cell WORD[14].W (WORD32)
    port Do[19] of cell WORD[15].W (WORD32)
    port Do[19] of cell WORD[16].W (WORD32)
    port Do[19] of cell WORD[17].W (WORD32)
    port Do[19] of cell WORD[18].W (WORD32)
    port Do[19] of cell WORD[19].W (WORD32)
    port Do[19] of cell WORD[1].W (WORD32)
    port Do[19] of cell WORD[20].W (WORD32)
    port Do[19] of cell WORD[21].W (WORD32)
    port Do[19] of cell WORD[22].W (WORD32)
    port Do[19] of cell WORD[23].W (WORD32)
    port Do[19] of cell WORD[24].W (WORD32)
    port Do[19] of cell WORD[25].W (WORD32)
    port Do[19] of cell WORD[26].W (WORD32)
    port Do[19] of cell WORD[27].W (WORD32)
    port Do[19] of cell WORD[28].W (WORD32)
    port Do[19] of cell WORD[29].W (WORD32)
    port Do[19] of cell WORD[2].W (WORD32)
    port Do[19] of cell WORD[30].W (WORD32)
    port Do[19] of cell WORD[31].W (WORD32)
    port Do[19] of cell WORD[32].W (WORD32)
    port Do[19] of cell WORD[33].W (WORD32)
    port Do[19] of cell WORD[34].W (WORD32)
    port Do[19] of cell WORD[35].W (WORD32)
    port Do[19] of cell WORD[36].W (WORD32)
    port Do[19] of cell WORD[37].W (WORD32)
    port Do[19] of cell WORD[38].W (WORD32)
    port Do[19] of cell WORD[39].W (WORD32)
    port Do[19] of cell WORD[3].W (WORD32)
    port Do[19] of cell WORD[40].W (WORD32)
    port Do[19] of cell WORD[41].W (WORD32)
    port Do[19] of cell WORD[42].W (WORD32)
    port Do[19] of cell WORD[43].W (WORD32)
    port Do[19] of cell WORD[44].W (WORD32)
    port Do[19] of cell WORD[45].W (WORD32)
    port Do[19] of cell WORD[46].W (WORD32)
    port Do[19] of cell WORD[47].W (WORD32)
    port Do[19] of cell WORD[48].W (WORD32)
    port Do[19] of cell WORD[49].W (WORD32)
    port Do[19] of cell WORD[4].W (WORD32)
    port Do[19] of cell WORD[50].W (WORD32)
    port Do[19] of cell WORD[51].W (WORD32)
    port Do[19] of cell WORD[52].W (WORD32)
    port Do[19] of cell WORD[53].W (WORD32)
    port Do[19] of cell WORD[54].W (WORD32)
    port Do[19] of cell WORD[55].W (WORD32)
    port Do[19] of cell WORD[56].W (WORD32)
    port Do[19] of cell WORD[57].W (WORD32)
    port Do[19] of cell WORD[58].W (WORD32)
    port Do[19] of cell WORD[59].W (WORD32)
    port Do[19] of cell WORD[5].W (WORD32)
    port Do[19] of cell WORD[60].W (WORD32)
    port Do[19] of cell WORD[61].W (WORD32)
    port Do[19] of cell WORD[62].W (WORD32)
    port Do[19] of cell WORD[63].W (WORD32)
    port Do[19] of cell WORD[6].W (WORD32)
    port Do[19] of cell WORD[7].W (WORD32)
    port Do[19] of cell WORD[8].W (WORD32)
    port Do[19] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[18]:

    port Z[0] of cell FLOATBUF[18] (sky130_fd_sc_hd__ebufn_4)
    port Do[18] of cell WORD[0].W (WORD32)
    port Do[18] of cell WORD[10].W (WORD32)
    port Do[18] of cell WORD[11].W (WORD32)
    port Do[18] of cell WORD[12].W (WORD32)
    port Do[18] of cell WORD[13].W (WORD32)
    port Do[18] of cell WORD[14].W (WORD32)
    port Do[18] of cell WORD[15].W (WORD32)
    port Do[18] of cell WORD[16].W (WORD32)
    port Do[18] of cell WORD[17].W (WORD32)
    port Do[18] of cell WORD[18].W (WORD32)
    port Do[18] of cell WORD[19].W (WORD32)
    port Do[18] of cell WORD[1].W (WORD32)
    port Do[18] of cell WORD[20].W (WORD32)
    port Do[18] of cell WORD[21].W (WORD32)
    port Do[18] of cell WORD[22].W (WORD32)
    port Do[18] of cell WORD[23].W (WORD32)
    port Do[18] of cell WORD[24].W (WORD32)
    port Do[18] of cell WORD[25].W (WORD32)
    port Do[18] of cell WORD[26].W (WORD32)
    port Do[18] of cell WORD[27].W (WORD32)
    port Do[18] of cell WORD[28].W (WORD32)
    port Do[18] of cell WORD[29].W (WORD32)
    port Do[18] of cell WORD[2].W (WORD32)
    port Do[18] of cell WORD[30].W (WORD32)
    port Do[18] of cell WORD[31].W (WORD32)
    port Do[18] of cell WORD[32].W (WORD32)
    port Do[18] of cell WORD[33].W (WORD32)
    port Do[18] of cell WORD[34].W (WORD32)
    port Do[18] of cell WORD[35].W (WORD32)
    port Do[18] of cell WORD[36].W (WORD32)
    port Do[18] of cell WORD[37].W (WORD32)
    port Do[18] of cell WORD[38].W (WORD32)
    port Do[18] of cell WORD[39].W (WORD32)
    port Do[18] of cell WORD[3].W (WORD32)
    port Do[18] of cell WORD[40].W (WORD32)
    port Do[18] of cell WORD[41].W (WORD32)
    port Do[18] of cell WORD[42].W (WORD32)
    port Do[18] of cell WORD[43].W (WORD32)
    port Do[18] of cell WORD[44].W (WORD32)
    port Do[18] of cell WORD[45].W (WORD32)
    port Do[18] of cell WORD[46].W (WORD32)
    port Do[18] of cell WORD[47].W (WORD32)
    port Do[18] of cell WORD[48].W (WORD32)
    port Do[18] of cell WORD[49].W (WORD32)
    port Do[18] of cell WORD[4].W (WORD32)
    port Do[18] of cell WORD[50].W (WORD32)
    port Do[18] of cell WORD[51].W (WORD32)
    port Do[18] of cell WORD[52].W (WORD32)
    port Do[18] of cell WORD[53].W (WORD32)
    port Do[18] of cell WORD[54].W (WORD32)
    port Do[18] of cell WORD[55].W (WORD32)
    port Do[18] of cell WORD[56].W (WORD32)
    port Do[18] of cell WORD[57].W (WORD32)
    port Do[18] of cell WORD[58].W (WORD32)
    port Do[18] of cell WORD[59].W (WORD32)
    port Do[18] of cell WORD[5].W (WORD32)
    port Do[18] of cell WORD[60].W (WORD32)
    port Do[18] of cell WORD[61].W (WORD32)
    port Do[18] of cell WORD[62].W (WORD32)
    port Do[18] of cell WORD[63].W (WORD32)
    port Do[18] of cell WORD[6].W (WORD32)
    port Do[18] of cell WORD[7].W (WORD32)
    port Do[18] of cell WORD[8].W (WORD32)
    port Do[18] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[17]:

    port Z[0] of cell FLOATBUF[17] (sky130_fd_sc_hd__ebufn_4)
    port Do[17] of cell WORD[0].W (WORD32)
    port Do[17] of cell WORD[10].W (WORD32)
    port Do[17] of cell WORD[11].W (WORD32)
    port Do[17] of cell WORD[12].W (WORD32)
    port Do[17] of cell WORD[13].W (WORD32)
    port Do[17] of cell WORD[14].W (WORD32)
    port Do[17] of cell WORD[15].W (WORD32)
    port Do[17] of cell WORD[16].W (WORD32)
    port Do[17] of cell WORD[17].W (WORD32)
    port Do[17] of cell WORD[18].W (WORD32)
    port Do[17] of cell WORD[19].W (WORD32)
    port Do[17] of cell WORD[1].W (WORD32)
    port Do[17] of cell WORD[20].W (WORD32)
    port Do[17] of cell WORD[21].W (WORD32)
    port Do[17] of cell WORD[22].W (WORD32)
    port Do[17] of cell WORD[23].W (WORD32)
    port Do[17] of cell WORD[24].W (WORD32)
    port Do[17] of cell WORD[25].W (WORD32)
    port Do[17] of cell WORD[26].W (WORD32)
    port Do[17] of cell WORD[27].W (WORD32)
    port Do[17] of cell WORD[28].W (WORD32)
    port Do[17] of cell WORD[29].W (WORD32)
    port Do[17] of cell WORD[2].W (WORD32)
    port Do[17] of cell WORD[30].W (WORD32)
    port Do[17] of cell WORD[31].W (WORD32)
    port Do[17] of cell WORD[32].W (WORD32)
    port Do[17] of cell WORD[33].W (WORD32)
    port Do[17] of cell WORD[34].W (WORD32)
    port Do[17] of cell WORD[35].W (WORD32)
    port Do[17] of cell WORD[36].W (WORD32)
    port Do[17] of cell WORD[37].W (WORD32)
    port Do[17] of cell WORD[38].W (WORD32)
    port Do[17] of cell WORD[39].W (WORD32)
    port Do[17] of cell WORD[3].W (WORD32)
    port Do[17] of cell WORD[40].W (WORD32)
    port Do[17] of cell WORD[41].W (WORD32)
    port Do[17] of cell WORD[42].W (WORD32)
    port Do[17] of cell WORD[43].W (WORD32)
    port Do[17] of cell WORD[44].W (WORD32)
    port Do[17] of cell WORD[45].W (WORD32)
    port Do[17] of cell WORD[46].W (WORD32)
    port Do[17] of cell WORD[47].W (WORD32)
    port Do[17] of cell WORD[48].W (WORD32)
    port Do[17] of cell WORD[49].W (WORD32)
    port Do[17] of cell WORD[4].W (WORD32)
    port Do[17] of cell WORD[50].W (WORD32)
    port Do[17] of cell WORD[51].W (WORD32)
    port Do[17] of cell WORD[52].W (WORD32)
    port Do[17] of cell WORD[53].W (WORD32)
    port Do[17] of cell WORD[54].W (WORD32)
    port Do[17] of cell WORD[55].W (WORD32)
    port Do[17] of cell WORD[56].W (WORD32)
    port Do[17] of cell WORD[57].W (WORD32)
    port Do[17] of cell WORD[58].W (WORD32)
    port Do[17] of cell WORD[59].W (WORD32)
    port Do[17] of cell WORD[5].W (WORD32)
    port Do[17] of cell WORD[60].W (WORD32)
    port Do[17] of cell WORD[61].W (WORD32)
    port Do[17] of cell WORD[62].W (WORD32)
    port Do[17] of cell WORD[63].W (WORD32)
    port Do[17] of cell WORD[6].W (WORD32)
    port Do[17] of cell WORD[7].W (WORD32)
    port Do[17] of cell WORD[8].W (WORD32)
    port Do[17] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[16]:

    port Z[0] of cell FLOATBUF[16] (sky130_fd_sc_hd__ebufn_4)
    port Do[16] of cell WORD[0].W (WORD32)
    port Do[16] of cell WORD[10].W (WORD32)
    port Do[16] of cell WORD[11].W (WORD32)
    port Do[16] of cell WORD[12].W (WORD32)
    port Do[16] of cell WORD[13].W (WORD32)
    port Do[16] of cell WORD[14].W (WORD32)
    port Do[16] of cell WORD[15].W (WORD32)
    port Do[16] of cell WORD[16].W (WORD32)
    port Do[16] of cell WORD[17].W (WORD32)
    port Do[16] of cell WORD[18].W (WORD32)
    port Do[16] of cell WORD[19].W (WORD32)
    port Do[16] of cell WORD[1].W (WORD32)
    port Do[16] of cell WORD[20].W (WORD32)
    port Do[16] of cell WORD[21].W (WORD32)
    port Do[16] of cell WORD[22].W (WORD32)
    port Do[16] of cell WORD[23].W (WORD32)
    port Do[16] of cell WORD[24].W (WORD32)
    port Do[16] of cell WORD[25].W (WORD32)
    port Do[16] of cell WORD[26].W (WORD32)
    port Do[16] of cell WORD[27].W (WORD32)
    port Do[16] of cell WORD[28].W (WORD32)
    port Do[16] of cell WORD[29].W (WORD32)
    port Do[16] of cell WORD[2].W (WORD32)
    port Do[16] of cell WORD[30].W (WORD32)
    port Do[16] of cell WORD[31].W (WORD32)
    port Do[16] of cell WORD[32].W (WORD32)
    port Do[16] of cell WORD[33].W (WORD32)
    port Do[16] of cell WORD[34].W (WORD32)
    port Do[16] of cell WORD[35].W (WORD32)
    port Do[16] of cell WORD[36].W (WORD32)
    port Do[16] of cell WORD[37].W (WORD32)
    port Do[16] of cell WORD[38].W (WORD32)
    port Do[16] of cell WORD[39].W (WORD32)
    port Do[16] of cell WORD[3].W (WORD32)
    port Do[16] of cell WORD[40].W (WORD32)
    port Do[16] of cell WORD[41].W (WORD32)
    port Do[16] of cell WORD[42].W (WORD32)
    port Do[16] of cell WORD[43].W (WORD32)
    port Do[16] of cell WORD[44].W (WORD32)
    port Do[16] of cell WORD[45].W (WORD32)
    port Do[16] of cell WORD[46].W (WORD32)
    port Do[16] of cell WORD[47].W (WORD32)
    port Do[16] of cell WORD[48].W (WORD32)
    port Do[16] of cell WORD[49].W (WORD32)
    port Do[16] of cell WORD[4].W (WORD32)
    port Do[16] of cell WORD[50].W (WORD32)
    port Do[16] of cell WORD[51].W (WORD32)
    port Do[16] of cell WORD[52].W (WORD32)
    port Do[16] of cell WORD[53].W (WORD32)
    port Do[16] of cell WORD[54].W (WORD32)
    port Do[16] of cell WORD[55].W (WORD32)
    port Do[16] of cell WORD[56].W (WORD32)
    port Do[16] of cell WORD[57].W (WORD32)
    port Do[16] of cell WORD[58].W (WORD32)
    port Do[16] of cell WORD[59].W (WORD32)
    port Do[16] of cell WORD[5].W (WORD32)
    port Do[16] of cell WORD[60].W (WORD32)
    port Do[16] of cell WORD[61].W (WORD32)
    port Do[16] of cell WORD[62].W (WORD32)
    port Do[16] of cell WORD[63].W (WORD32)
    port Do[16] of cell WORD[6].W (WORD32)
    port Do[16] of cell WORD[7].W (WORD32)
    port Do[16] of cell WORD[8].W (WORD32)
    port Do[16] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[15]:

    port Z[0] of cell FLOATBUF[15] (sky130_fd_sc_hd__ebufn_4)
    port Do[15] of cell WORD[0].W (WORD32)
    port Do[15] of cell WORD[10].W (WORD32)
    port Do[15] of cell WORD[11].W (WORD32)
    port Do[15] of cell WORD[12].W (WORD32)
    port Do[15] of cell WORD[13].W (WORD32)
    port Do[15] of cell WORD[14].W (WORD32)
    port Do[15] of cell WORD[15].W (WORD32)
    port Do[15] of cell WORD[16].W (WORD32)
    port Do[15] of cell WORD[17].W (WORD32)
    port Do[15] of cell WORD[18].W (WORD32)
    port Do[15] of cell WORD[19].W (WORD32)
    port Do[15] of cell WORD[1].W (WORD32)
    port Do[15] of cell WORD[20].W (WORD32)
    port Do[15] of cell WORD[21].W (WORD32)
    port Do[15] of cell WORD[22].W (WORD32)
    port Do[15] of cell WORD[23].W (WORD32)
    port Do[15] of cell WORD[24].W (WORD32)
    port Do[15] of cell WORD[25].W (WORD32)
    port Do[15] of cell WORD[26].W (WORD32)
    port Do[15] of cell WORD[27].W (WORD32)
    port Do[15] of cell WORD[28].W (WORD32)
    port Do[15] of cell WORD[29].W (WORD32)
    port Do[15] of cell WORD[2].W (WORD32)
    port Do[15] of cell WORD[30].W (WORD32)
    port Do[15] of cell WORD[31].W (WORD32)
    port Do[15] of cell WORD[32].W (WORD32)
    port Do[15] of cell WORD[33].W (WORD32)
    port Do[15] of cell WORD[34].W (WORD32)
    port Do[15] of cell WORD[35].W (WORD32)
    port Do[15] of cell WORD[36].W (WORD32)
    port Do[15] of cell WORD[37].W (WORD32)
    port Do[15] of cell WORD[38].W (WORD32)
    port Do[15] of cell WORD[39].W (WORD32)
    port Do[15] of cell WORD[3].W (WORD32)
    port Do[15] of cell WORD[40].W (WORD32)
    port Do[15] of cell WORD[41].W (WORD32)
    port Do[15] of cell WORD[42].W (WORD32)
    port Do[15] of cell WORD[43].W (WORD32)
    port Do[15] of cell WORD[44].W (WORD32)
    port Do[15] of cell WORD[45].W (WORD32)
    port Do[15] of cell WORD[46].W (WORD32)
    port Do[15] of cell WORD[47].W (WORD32)
    port Do[15] of cell WORD[48].W (WORD32)
    port Do[15] of cell WORD[49].W (WORD32)
    port Do[15] of cell WORD[4].W (WORD32)
    port Do[15] of cell WORD[50].W (WORD32)
    port Do[15] of cell WORD[51].W (WORD32)
    port Do[15] of cell WORD[52].W (WORD32)
    port Do[15] of cell WORD[53].W (WORD32)
    port Do[15] of cell WORD[54].W (WORD32)
    port Do[15] of cell WORD[55].W (WORD32)
    port Do[15] of cell WORD[56].W (WORD32)
    port Do[15] of cell WORD[57].W (WORD32)
    port Do[15] of cell WORD[58].W (WORD32)
    port Do[15] of cell WORD[59].W (WORD32)
    port Do[15] of cell WORD[5].W (WORD32)
    port Do[15] of cell WORD[60].W (WORD32)
    port Do[15] of cell WORD[61].W (WORD32)
    port Do[15] of cell WORD[62].W (WORD32)
    port Do[15] of cell WORD[63].W (WORD32)
    port Do[15] of cell WORD[6].W (WORD32)
    port Do[15] of cell WORD[7].W (WORD32)
    port Do[15] of cell WORD[8].W (WORD32)
    port Do[15] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[14]:

    port Z[0] of cell FLOATBUF[14] (sky130_fd_sc_hd__ebufn_4)
    port Do[14] of cell WORD[0].W (WORD32)
    port Do[14] of cell WORD[10].W (WORD32)
    port Do[14] of cell WORD[11].W (WORD32)
    port Do[14] of cell WORD[12].W (WORD32)
    port Do[14] of cell WORD[13].W (WORD32)
    port Do[14] of cell WORD[14].W (WORD32)
    port Do[14] of cell WORD[15].W (WORD32)
    port Do[14] of cell WORD[16].W (WORD32)
    port Do[14] of cell WORD[17].W (WORD32)
    port Do[14] of cell WORD[18].W (WORD32)
    port Do[14] of cell WORD[19].W (WORD32)
    port Do[14] of cell WORD[1].W (WORD32)
    port Do[14] of cell WORD[20].W (WORD32)
    port Do[14] of cell WORD[21].W (WORD32)
    port Do[14] of cell WORD[22].W (WORD32)
    port Do[14] of cell WORD[23].W (WORD32)
    port Do[14] of cell WORD[24].W (WORD32)
    port Do[14] of cell WORD[25].W (WORD32)
    port Do[14] of cell WORD[26].W (WORD32)
    port Do[14] of cell WORD[27].W (WORD32)
    port Do[14] of cell WORD[28].W (WORD32)
    port Do[14] of cell WORD[29].W (WORD32)
    port Do[14] of cell WORD[2].W (WORD32)
    port Do[14] of cell WORD[30].W (WORD32)
    port Do[14] of cell WORD[31].W (WORD32)
    port Do[14] of cell WORD[32].W (WORD32)
    port Do[14] of cell WORD[33].W (WORD32)
    port Do[14] of cell WORD[34].W (WORD32)
    port Do[14] of cell WORD[35].W (WORD32)
    port Do[14] of cell WORD[36].W (WORD32)
    port Do[14] of cell WORD[37].W (WORD32)
    port Do[14] of cell WORD[38].W (WORD32)
    port Do[14] of cell WORD[39].W (WORD32)
    port Do[14] of cell WORD[3].W (WORD32)
    port Do[14] of cell WORD[40].W (WORD32)
    port Do[14] of cell WORD[41].W (WORD32)
    port Do[14] of cell WORD[42].W (WORD32)
    port Do[14] of cell WORD[43].W (WORD32)
    port Do[14] of cell WORD[44].W (WORD32)
    port Do[14] of cell WORD[45].W (WORD32)
    port Do[14] of cell WORD[46].W (WORD32)
    port Do[14] of cell WORD[47].W (WORD32)
    port Do[14] of cell WORD[48].W (WORD32)
    port Do[14] of cell WORD[49].W (WORD32)
    port Do[14] of cell WORD[4].W (WORD32)
    port Do[14] of cell WORD[50].W (WORD32)
    port Do[14] of cell WORD[51].W (WORD32)
    port Do[14] of cell WORD[52].W (WORD32)
    port Do[14] of cell WORD[53].W (WORD32)
    port Do[14] of cell WORD[54].W (WORD32)
    port Do[14] of cell WORD[55].W (WORD32)
    port Do[14] of cell WORD[56].W (WORD32)
    port Do[14] of cell WORD[57].W (WORD32)
    port Do[14] of cell WORD[58].W (WORD32)
    port Do[14] of cell WORD[59].W (WORD32)
    port Do[14] of cell WORD[5].W (WORD32)
    port Do[14] of cell WORD[60].W (WORD32)
    port Do[14] of cell WORD[61].W (WORD32)
    port Do[14] of cell WORD[62].W (WORD32)
    port Do[14] of cell WORD[63].W (WORD32)
    port Do[14] of cell WORD[6].W (WORD32)
    port Do[14] of cell WORD[7].W (WORD32)
    port Do[14] of cell WORD[8].W (WORD32)
    port Do[14] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[13]:

    port Z[0] of cell FLOATBUF[13] (sky130_fd_sc_hd__ebufn_4)
    port Do[13] of cell WORD[0].W (WORD32)
    port Do[13] of cell WORD[10].W (WORD32)
    port Do[13] of cell WORD[11].W (WORD32)
    port Do[13] of cell WORD[12].W (WORD32)
    port Do[13] of cell WORD[13].W (WORD32)
    port Do[13] of cell WORD[14].W (WORD32)
    port Do[13] of cell WORD[15].W (WORD32)
    port Do[13] of cell WORD[16].W (WORD32)
    port Do[13] of cell WORD[17].W (WORD32)
    port Do[13] of cell WORD[18].W (WORD32)
    port Do[13] of cell WORD[19].W (WORD32)
    port Do[13] of cell WORD[1].W (WORD32)
    port Do[13] of cell WORD[20].W (WORD32)
    port Do[13] of cell WORD[21].W (WORD32)
    port Do[13] of cell WORD[22].W (WORD32)
    port Do[13] of cell WORD[23].W (WORD32)
    port Do[13] of cell WORD[24].W (WORD32)
    port Do[13] of cell WORD[25].W (WORD32)
    port Do[13] of cell WORD[26].W (WORD32)
    port Do[13] of cell WORD[27].W (WORD32)
    port Do[13] of cell WORD[28].W (WORD32)
    port Do[13] of cell WORD[29].W (WORD32)
    port Do[13] of cell WORD[2].W (WORD32)
    port Do[13] of cell WORD[30].W (WORD32)
    port Do[13] of cell WORD[31].W (WORD32)
    port Do[13] of cell WORD[32].W (WORD32)
    port Do[13] of cell WORD[33].W (WORD32)
    port Do[13] of cell WORD[34].W (WORD32)
    port Do[13] of cell WORD[35].W (WORD32)
    port Do[13] of cell WORD[36].W (WORD32)
    port Do[13] of cell WORD[37].W (WORD32)
    port Do[13] of cell WORD[38].W (WORD32)
    port Do[13] of cell WORD[39].W (WORD32)
    port Do[13] of cell WORD[3].W (WORD32)
    port Do[13] of cell WORD[40].W (WORD32)
    port Do[13] of cell WORD[41].W (WORD32)
    port Do[13] of cell WORD[42].W (WORD32)
    port Do[13] of cell WORD[43].W (WORD32)
    port Do[13] of cell WORD[44].W (WORD32)
    port Do[13] of cell WORD[45].W (WORD32)
    port Do[13] of cell WORD[46].W (WORD32)
    port Do[13] of cell WORD[47].W (WORD32)
    port Do[13] of cell WORD[48].W (WORD32)
    port Do[13] of cell WORD[49].W (WORD32)
    port Do[13] of cell WORD[4].W (WORD32)
    port Do[13] of cell WORD[50].W (WORD32)
    port Do[13] of cell WORD[51].W (WORD32)
    port Do[13] of cell WORD[52].W (WORD32)
    port Do[13] of cell WORD[53].W (WORD32)
    port Do[13] of cell WORD[54].W (WORD32)
    port Do[13] of cell WORD[55].W (WORD32)
    port Do[13] of cell WORD[56].W (WORD32)
    port Do[13] of cell WORD[57].W (WORD32)
    port Do[13] of cell WORD[58].W (WORD32)
    port Do[13] of cell WORD[59].W (WORD32)
    port Do[13] of cell WORD[5].W (WORD32)
    port Do[13] of cell WORD[60].W (WORD32)
    port Do[13] of cell WORD[61].W (WORD32)
    port Do[13] of cell WORD[62].W (WORD32)
    port Do[13] of cell WORD[63].W (WORD32)
    port Do[13] of cell WORD[6].W (WORD32)
    port Do[13] of cell WORD[7].W (WORD32)
    port Do[13] of cell WORD[8].W (WORD32)
    port Do[13] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[12]:

    port Z[0] of cell FLOATBUF[12] (sky130_fd_sc_hd__ebufn_4)
    port Do[12] of cell WORD[0].W (WORD32)
    port Do[12] of cell WORD[10].W (WORD32)
    port Do[12] of cell WORD[11].W (WORD32)
    port Do[12] of cell WORD[12].W (WORD32)
    port Do[12] of cell WORD[13].W (WORD32)
    port Do[12] of cell WORD[14].W (WORD32)
    port Do[12] of cell WORD[15].W (WORD32)
    port Do[12] of cell WORD[16].W (WORD32)
    port Do[12] of cell WORD[17].W (WORD32)
    port Do[12] of cell WORD[18].W (WORD32)
    port Do[12] of cell WORD[19].W (WORD32)
    port Do[12] of cell WORD[1].W (WORD32)
    port Do[12] of cell WORD[20].W (WORD32)
    port Do[12] of cell WORD[21].W (WORD32)
    port Do[12] of cell WORD[22].W (WORD32)
    port Do[12] of cell WORD[23].W (WORD32)
    port Do[12] of cell WORD[24].W (WORD32)
    port Do[12] of cell WORD[25].W (WORD32)
    port Do[12] of cell WORD[26].W (WORD32)
    port Do[12] of cell WORD[27].W (WORD32)
    port Do[12] of cell WORD[28].W (WORD32)
    port Do[12] of cell WORD[29].W (WORD32)
    port Do[12] of cell WORD[2].W (WORD32)
    port Do[12] of cell WORD[30].W (WORD32)
    port Do[12] of cell WORD[31].W (WORD32)
    port Do[12] of cell WORD[32].W (WORD32)
    port Do[12] of cell WORD[33].W (WORD32)
    port Do[12] of cell WORD[34].W (WORD32)
    port Do[12] of cell WORD[35].W (WORD32)
    port Do[12] of cell WORD[36].W (WORD32)
    port Do[12] of cell WORD[37].W (WORD32)
    port Do[12] of cell WORD[38].W (WORD32)
    port Do[12] of cell WORD[39].W (WORD32)
    port Do[12] of cell WORD[3].W (WORD32)
    port Do[12] of cell WORD[40].W (WORD32)
    port Do[12] of cell WORD[41].W (WORD32)
    port Do[12] of cell WORD[42].W (WORD32)
    port Do[12] of cell WORD[43].W (WORD32)
    port Do[12] of cell WORD[44].W (WORD32)
    port Do[12] of cell WORD[45].W (WORD32)
    port Do[12] of cell WORD[46].W (WORD32)
    port Do[12] of cell WORD[47].W (WORD32)
    port Do[12] of cell WORD[48].W (WORD32)
    port Do[12] of cell WORD[49].W (WORD32)
    port Do[12] of cell WORD[4].W (WORD32)
    port Do[12] of cell WORD[50].W (WORD32)
    port Do[12] of cell WORD[51].W (WORD32)
    port Do[12] of cell WORD[52].W (WORD32)
    port Do[12] of cell WORD[53].W (WORD32)
    port Do[12] of cell WORD[54].W (WORD32)
    port Do[12] of cell WORD[55].W (WORD32)
    port Do[12] of cell WORD[56].W (WORD32)
    port Do[12] of cell WORD[57].W (WORD32)
    port Do[12] of cell WORD[58].W (WORD32)
    port Do[12] of cell WORD[59].W (WORD32)
    port Do[12] of cell WORD[5].W (WORD32)
    port Do[12] of cell WORD[60].W (WORD32)
    port Do[12] of cell WORD[61].W (WORD32)
    port Do[12] of cell WORD[62].W (WORD32)
    port Do[12] of cell WORD[63].W (WORD32)
    port Do[12] of cell WORD[6].W (WORD32)
    port Do[12] of cell WORD[7].W (WORD32)
    port Do[12] of cell WORD[8].W (WORD32)
    port Do[12] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[11]:

    port Z[0] of cell FLOATBUF[11] (sky130_fd_sc_hd__ebufn_4)
    port Do[11] of cell WORD[0].W (WORD32)
    port Do[11] of cell WORD[10].W (WORD32)
    port Do[11] of cell WORD[11].W (WORD32)
    port Do[11] of cell WORD[12].W (WORD32)
    port Do[11] of cell WORD[13].W (WORD32)
    port Do[11] of cell WORD[14].W (WORD32)
    port Do[11] of cell WORD[15].W (WORD32)
    port Do[11] of cell WORD[16].W (WORD32)
    port Do[11] of cell WORD[17].W (WORD32)
    port Do[11] of cell WORD[18].W (WORD32)
    port Do[11] of cell WORD[19].W (WORD32)
    port Do[11] of cell WORD[1].W (WORD32)
    port Do[11] of cell WORD[20].W (WORD32)
    port Do[11] of cell WORD[21].W (WORD32)
    port Do[11] of cell WORD[22].W (WORD32)
    port Do[11] of cell WORD[23].W (WORD32)
    port Do[11] of cell WORD[24].W (WORD32)
    port Do[11] of cell WORD[25].W (WORD32)
    port Do[11] of cell WORD[26].W (WORD32)
    port Do[11] of cell WORD[27].W (WORD32)
    port Do[11] of cell WORD[28].W (WORD32)
    port Do[11] of cell WORD[29].W (WORD32)
    port Do[11] of cell WORD[2].W (WORD32)
    port Do[11] of cell WORD[30].W (WORD32)
    port Do[11] of cell WORD[31].W (WORD32)
    port Do[11] of cell WORD[32].W (WORD32)
    port Do[11] of cell WORD[33].W (WORD32)
    port Do[11] of cell WORD[34].W (WORD32)
    port Do[11] of cell WORD[35].W (WORD32)
    port Do[11] of cell WORD[36].W (WORD32)
    port Do[11] of cell WORD[37].W (WORD32)
    port Do[11] of cell WORD[38].W (WORD32)
    port Do[11] of cell WORD[39].W (WORD32)
    port Do[11] of cell WORD[3].W (WORD32)
    port Do[11] of cell WORD[40].W (WORD32)
    port Do[11] of cell WORD[41].W (WORD32)
    port Do[11] of cell WORD[42].W (WORD32)
    port Do[11] of cell WORD[43].W (WORD32)
    port Do[11] of cell WORD[44].W (WORD32)
    port Do[11] of cell WORD[45].W (WORD32)
    port Do[11] of cell WORD[46].W (WORD32)
    port Do[11] of cell WORD[47].W (WORD32)
    port Do[11] of cell WORD[48].W (WORD32)
    port Do[11] of cell WORD[49].W (WORD32)
    port Do[11] of cell WORD[4].W (WORD32)
    port Do[11] of cell WORD[50].W (WORD32)
    port Do[11] of cell WORD[51].W (WORD32)
    port Do[11] of cell WORD[52].W (WORD32)
    port Do[11] of cell WORD[53].W (WORD32)
    port Do[11] of cell WORD[54].W (WORD32)
    port Do[11] of cell WORD[55].W (WORD32)
    port Do[11] of cell WORD[56].W (WORD32)
    port Do[11] of cell WORD[57].W (WORD32)
    port Do[11] of cell WORD[58].W (WORD32)
    port Do[11] of cell WORD[59].W (WORD32)
    port Do[11] of cell WORD[5].W (WORD32)
    port Do[11] of cell WORD[60].W (WORD32)
    port Do[11] of cell WORD[61].W (WORD32)
    port Do[11] of cell WORD[62].W (WORD32)
    port Do[11] of cell WORD[63].W (WORD32)
    port Do[11] of cell WORD[6].W (WORD32)
    port Do[11] of cell WORD[7].W (WORD32)
    port Do[11] of cell WORD[8].W (WORD32)
    port Do[11] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[10]:

    port Z[0] of cell FLOATBUF[10] (sky130_fd_sc_hd__ebufn_4)
    port Do[10] of cell WORD[0].W (WORD32)
    port Do[10] of cell WORD[10].W (WORD32)
    port Do[10] of cell WORD[11].W (WORD32)
    port Do[10] of cell WORD[12].W (WORD32)
    port Do[10] of cell WORD[13].W (WORD32)
    port Do[10] of cell WORD[14].W (WORD32)
    port Do[10] of cell WORD[15].W (WORD32)
    port Do[10] of cell WORD[16].W (WORD32)
    port Do[10] of cell WORD[17].W (WORD32)
    port Do[10] of cell WORD[18].W (WORD32)
    port Do[10] of cell WORD[19].W (WORD32)
    port Do[10] of cell WORD[1].W (WORD32)
    port Do[10] of cell WORD[20].W (WORD32)
    port Do[10] of cell WORD[21].W (WORD32)
    port Do[10] of cell WORD[22].W (WORD32)
    port Do[10] of cell WORD[23].W (WORD32)
    port Do[10] of cell WORD[24].W (WORD32)
    port Do[10] of cell WORD[25].W (WORD32)
    port Do[10] of cell WORD[26].W (WORD32)
    port Do[10] of cell WORD[27].W (WORD32)
    port Do[10] of cell WORD[28].W (WORD32)
    port Do[10] of cell WORD[29].W (WORD32)
    port Do[10] of cell WORD[2].W (WORD32)
    port Do[10] of cell WORD[30].W (WORD32)
    port Do[10] of cell WORD[31].W (WORD32)
    port Do[10] of cell WORD[32].W (WORD32)
    port Do[10] of cell WORD[33].W (WORD32)
    port Do[10] of cell WORD[34].W (WORD32)
    port Do[10] of cell WORD[35].W (WORD32)
    port Do[10] of cell WORD[36].W (WORD32)
    port Do[10] of cell WORD[37].W (WORD32)
    port Do[10] of cell WORD[38].W (WORD32)
    port Do[10] of cell WORD[39].W (WORD32)
    port Do[10] of cell WORD[3].W (WORD32)
    port Do[10] of cell WORD[40].W (WORD32)
    port Do[10] of cell WORD[41].W (WORD32)
    port Do[10] of cell WORD[42].W (WORD32)
    port Do[10] of cell WORD[43].W (WORD32)
    port Do[10] of cell WORD[44].W (WORD32)
    port Do[10] of cell WORD[45].W (WORD32)
    port Do[10] of cell WORD[46].W (WORD32)
    port Do[10] of cell WORD[47].W (WORD32)
    port Do[10] of cell WORD[48].W (WORD32)
    port Do[10] of cell WORD[49].W (WORD32)
    port Do[10] of cell WORD[4].W (WORD32)
    port Do[10] of cell WORD[50].W (WORD32)
    port Do[10] of cell WORD[51].W (WORD32)
    port Do[10] of cell WORD[52].W (WORD32)
    port Do[10] of cell WORD[53].W (WORD32)
    port Do[10] of cell WORD[54].W (WORD32)
    port Do[10] of cell WORD[55].W (WORD32)
    port Do[10] of cell WORD[56].W (WORD32)
    port Do[10] of cell WORD[57].W (WORD32)
    port Do[10] of cell WORD[58].W (WORD32)
    port Do[10] of cell WORD[59].W (WORD32)
    port Do[10] of cell WORD[5].W (WORD32)
    port Do[10] of cell WORD[60].W (WORD32)
    port Do[10] of cell WORD[61].W (WORD32)
    port Do[10] of cell WORD[62].W (WORD32)
    port Do[10] of cell WORD[63].W (WORD32)
    port Do[10] of cell WORD[6].W (WORD32)
    port Do[10] of cell WORD[7].W (WORD32)
    port Do[10] of cell WORD[8].W (WORD32)
    port Do[10] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[0]:

    port Z[0] of cell FLOATBUF[0] (sky130_fd_sc_hd__ebufn_4)
    port Do[0] of cell WORD[0].W (WORD32)
    port Do[0] of cell WORD[10].W (WORD32)
    port Do[0] of cell WORD[11].W (WORD32)
    port Do[0] of cell WORD[12].W (WORD32)
    port Do[0] of cell WORD[13].W (WORD32)
    port Do[0] of cell WORD[14].W (WORD32)
    port Do[0] of cell WORD[15].W (WORD32)
    port Do[0] of cell WORD[16].W (WORD32)
    port Do[0] of cell WORD[17].W (WORD32)
    port Do[0] of cell WORD[18].W (WORD32)
    port Do[0] of cell WORD[19].W (WORD32)
    port Do[0] of cell WORD[1].W (WORD32)
    port Do[0] of cell WORD[20].W (WORD32)
    port Do[0] of cell WORD[21].W (WORD32)
    port Do[0] of cell WORD[22].W (WORD32)
    port Do[0] of cell WORD[23].W (WORD32)
    port Do[0] of cell WORD[24].W (WORD32)
    port Do[0] of cell WORD[25].W (WORD32)
    port Do[0] of cell WORD[26].W (WORD32)
    port Do[0] of cell WORD[27].W (WORD32)
    port Do[0] of cell WORD[28].W (WORD32)
    port Do[0] of cell WORD[29].W (WORD32)
    port Do[0] of cell WORD[2].W (WORD32)
    port Do[0] of cell WORD[30].W (WORD32)
    port Do[0] of cell WORD[31].W (WORD32)
    port Do[0] of cell WORD[32].W (WORD32)
    port Do[0] of cell WORD[33].W (WORD32)
    port Do[0] of cell WORD[34].W (WORD32)
    port Do[0] of cell WORD[35].W (WORD32)
    port Do[0] of cell WORD[36].W (WORD32)
    port Do[0] of cell WORD[37].W (WORD32)
    port Do[0] of cell WORD[38].W (WORD32)
    port Do[0] of cell WORD[39].W (WORD32)
    port Do[0] of cell WORD[3].W (WORD32)
    port Do[0] of cell WORD[40].W (WORD32)
    port Do[0] of cell WORD[41].W (WORD32)
    port Do[0] of cell WORD[42].W (WORD32)
    port Do[0] of cell WORD[43].W (WORD32)
    port Do[0] of cell WORD[44].W (WORD32)
    port Do[0] of cell WORD[45].W (WORD32)
    port Do[0] of cell WORD[46].W (WORD32)
    port Do[0] of cell WORD[47].W (WORD32)
    port Do[0] of cell WORD[48].W (WORD32)
    port Do[0] of cell WORD[49].W (WORD32)
    port Do[0] of cell WORD[4].W (WORD32)
    port Do[0] of cell WORD[50].W (WORD32)
    port Do[0] of cell WORD[51].W (WORD32)
    port Do[0] of cell WORD[52].W (WORD32)
    port Do[0] of cell WORD[53].W (WORD32)
    port Do[0] of cell WORD[54].W (WORD32)
    port Do[0] of cell WORD[55].W (WORD32)
    port Do[0] of cell WORD[56].W (WORD32)
    port Do[0] of cell WORD[57].W (WORD32)
    port Do[0] of cell WORD[58].W (WORD32)
    port Do[0] of cell WORD[59].W (WORD32)
    port Do[0] of cell WORD[5].W (WORD32)
    port Do[0] of cell WORD[60].W (WORD32)
    port Do[0] of cell WORD[61].W (WORD32)
    port Do[0] of cell WORD[62].W (WORD32)
    port Do[0] of cell WORD[63].W (WORD32)
    port Do[0] of cell WORD[6].W (WORD32)
    port Do[0] of cell WORD[7].W (WORD32)
    port Do[0] of cell WORD[8].W (WORD32)
    port Do[0] of cell WORD[9].W (WORD32)
checking module WORD32..
found and reported 32 problems.

10. Printing statistics.

=== BYTE ===

   Number of wires:                 16
   Number of wire bits:             30
   Number of public wires:          16
   Number of public wire bits:      30
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     sky130_fd_sc_hd__and2_1         1
     sky130_fd_sc_hd__dfxtp_1        8
     sky130_fd_sc_hd__dlclkp_1       1
     sky130_fd_sc_hd__ebufn_2        8
     sky130_fd_sc_hd__inv_1          1

   Area for cell type \sky130_fd_sc_hd__and2_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__dfxtp_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__dlclkp_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__ebufn_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__inv_1 is unknown!

=== DEC2x4 ===

   Number of wires:                  3
   Number of wire bits:              7
   Number of public wires:           3
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     sky130_fd_sc_hd__and3_4         1
     sky130_fd_sc_hd__and3b_4        2
     sky130_fd_sc_hd__nor3b_4        1

   Area for cell type \sky130_fd_sc_hd__and3b_4 is unknown!
   Area for cell type \sky130_fd_sc_hd__nor3b_4 is unknown!

   Chip area for module '\DEC2x4': 11.260800

=== DEC3x8 ===

   Number of wires:                  3
   Number of wire bits:             12
   Number of public wires:           3
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  8
     sky130_fd_sc_hd__and4_2         1
     sky130_fd_sc_hd__and4b_2        3
     sky130_fd_sc_hd__and4bb_2       3
     sky130_fd_sc_hd__nor4b_2        1

   Area for cell type \sky130_fd_sc_hd__and4_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__and4b_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__and4bb_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__nor4b_2 is unknown!

=== DEC6x64 ===

   Number of wires:                 14
   Number of wire bits:             82
   Number of public wires:          14
   Number of public wire bits:      82
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 12
     DEC3x8                          9
     sky130_fd_sc_hd__clkbuf_16      3

   Area for cell type \sky130_fd_sc_hd__clkbuf_16 is unknown!
   Area for cell type \DEC3x8 is unknown!

=== DFFRAM ===

   Number of wires:                 71
   Number of wire bits:            143
   Number of public wires:          71
   Number of public wire bits:     143
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 35
     DFFRAM_COL4                     1
     PASS                            1
     sky130_fd_sc_hd__clkbuf_4      33

   Area for cell type \sky130_fd_sc_hd__clkbuf_4 is unknown!
   Area for cell type \DFFRAM_COL4 is unknown!
   Area for cell type \PASS is unknown!

=== DFFRAM_COL4 ===

   Number of wires:                210
   Number of wire bits:            282
   Number of public wires:         210
   Number of public wire bits:     282
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 46
     DEC2x4                          1
     MUX4x1_32                       1
     SRAM64x32                       4
     sky130_fd_sc_hd__clkbuf_16      3
     sky130_fd_sc_hd__clkbuf_8      37

   Area for cell type \sky130_fd_sc_hd__clkbuf_16 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkbuf_8 is unknown!
   Area for cell type \DEC2x4 is unknown!
   Area for cell type \MUX4x1_32 is unknown!
   Area for cell type \SRAM64x32 is unknown!

=== MUX4x1_32 ===

   Number of wires:                  6
   Number of wire bits:            162
   Number of public wires:           6
   Number of public wire bits:     162
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     sky130_fd_sc_hd__mux4_1        32

   Area for cell type \sky130_fd_sc_hd__mux4_1 is unknown!

=== PASS ===

   Number of wires:                  2
   Number of wire bits:             64
   Number of public wires:           2
   Number of public wire bits:      64
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== SRAM64x32 ===

   Number of wires:                141
   Number of wire bits:            211
   Number of public wires:         141
   Number of public wire bits:     211
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                168
     DEC6x64                         1
     WORD32                         64
     sky130_fd_sc_hd__clkbuf_16     37
     sky130_fd_sc_hd__clkbuf_4       1
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfxtp_1       32
     sky130_fd_sc_hd__ebufn_4       32

   Area for cell type \sky130_fd_sc_hd__clkbuf_16 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkbuf_4 is unknown!
   Area for cell type \sky130_fd_sc_hd__dfxtp_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__ebufn_4 is unknown!
   Area for cell type \WORD32 is unknown!
   Area for cell type \DEC6x64 is unknown!

   Chip area for module '\SRAM64x32': 3.753600

=== WORD32 ===

   Number of wires:                  5
   Number of wire bits:             70
   Number of public wires:           5
   Number of public wire bits:      70
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     BYTE                            4

   Area for cell type \BYTE is unknown!

=== design hierarchy ===

   DFFRAM                            1
     DFFRAM_COL4                     1
       DEC2x4                        1
       MUX4x1_32                     1
       SRAM64x32                     4
         DEC6x64                     1
           DEC3x8                    9
         WORD32                     64
           BYTE                      4
     PASS                            1

   Number of wires:              18684
   Number of wire bits:          50902
   Number of public wires:       18684
   Number of public wire bits:   50902
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              20277
     sky130_fd_sc_hd__and2_1      1024
     sky130_fd_sc_hd__and3_4         1
     sky130_fd_sc_hd__and3b_4        2
     sky130_fd_sc_hd__and4_2        36
     sky130_fd_sc_hd__and4b_2      108
     sky130_fd_sc_hd__and4bb_2     108
     sky130_fd_sc_hd__clkbuf_16    163
     sky130_fd_sc_hd__clkbuf_4      37
     sky130_fd_sc_hd__clkbuf_8      37
     sky130_fd_sc_hd__conb_1         4
     sky130_fd_sc_hd__dfxtp_1     8320
     sky130_fd_sc_hd__dlclkp_1    1024
     sky130_fd_sc_hd__ebufn_2     8192
     sky130_fd_sc_hd__ebufn_4      128
     sky130_fd_sc_hd__inv_1       1024
     sky130_fd_sc_hd__mux4_1        32
     sky130_fd_sc_hd__nor3b_4        1
     sky130_fd_sc_hd__nor4b_2       36

   Chip area for top module '\DFFRAM': 26.275200

11. Executing Verilog backend.
Dumping module `\BYTE'.
Dumping module `\DEC2x4'.
Dumping module `\DEC3x8'.
Dumping module `\DEC6x64'.
Dumping module `\DFFRAM'.
Dumping module `\DFFRAM_COL4'.
Dumping module `\MUX4x1_32'.
Dumping module `\PASS'.
Dumping module `\SRAM64x32'.
Dumping module `\WORD32'.

Warnings: 32 unique messages, 32 total

End of script. Logfile hash: 93ef28fe03, CPU: user 1.91s system 0.04s, MEM: 42.19 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 48% 2x write_verilog (0 sec), 41% 2x read_liberty (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/DFFRAM/runs/DFFRAM/results/synthesis/DFFRAM.synthesis.v

[INFO]: Running Static Timing Analysis...

OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.

create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Synthesis was successful


[INFO]: Running Floorplanning...

[INFO]: Running Initial Floorplanning...

OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.

Notice 0: Reading LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell

Info: Added 185 rows of 1606 sites.
[INFO]: Floorplanning was successful


[INFO]: Core area width: 738.96

[INFO]: Core area height: 503.24

[INFO]: Changing layout from 0 to /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def

Notice 0: Reading LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef

Notice 0: 
Reading DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: DFFRAM
Notice 0:     Created 78 pins.
Notice 0:     Created 20277 components and 100828 component-terminals.
Notice 0:     Created 12163 nets and 60270 connections.
Notice 0: Finished DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def

Top-level design name: DFFRAM
Block boundaries: 0 0 750000 525000
Writing /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def to /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def

[INFO]: Running Tap/Decap Insertion...

OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef

Notice 0: 
Reading DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def
Notice 0: Design: DFFRAM
Notice 0:     Created 78 pins.
Notice 0:     Created 20277 components and 100828 component-terminals.
Notice 0:     Created 12163 nets and 60270 connections.
Notice 0: Finished DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def

Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 0
[INFO] #Original rows: 185
[INFO] #Cut rows: 0
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 370
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 4860
Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def to /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def

[INFO]: Running Placement...

[INFO]: Running Global Placement...

OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef

Notice 0: 
Reading DEF file: /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def
Notice 0: Design: DFFRAM
Notice 0:     Created 78 pins.
Notice 0:     Created 25507 components and 111288 component-terminals.
Notice 0:     Created 12163 nets and 60270 connections.
Notice 0: Finished DEF file: /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def

[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (744280, 514080)
[INFO] NumInstances = 25507
[INFO] NumPlaceInstances = 20277
[INFO] NumFixedInstances = 5230
[INFO] NumDummyInstances = 0
[INFO] NumNets = 12163
[INFO] NumPins = 60348
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (750000, 525000)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (744280, 514080)
[INFO] CoreArea = 371744032000
[INFO] NonPlaceInstsArea = 7469664000
[INFO] PlaceInstsArea = 298322364800
[INFO] Util(%) = 81.894974
[INFO] StdInstsArea = 298322364800
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 0.00127764 HPWL: 161817324

[InitialPlace]  Iter: 2 CG Error: 0.000647573 HPWL: 184741169

[InitialPlace]  Iter: 3 CG Error: 0.000195701 HPWL: 189760398

[InitialPlace]  Iter: 4 CG Error: 0.000103155 HPWL: 190814756

[InitialPlace]  Iter: 5 CG Error: 0.000107622 HPWL: 190736005

[InitialPlace]  Iter: 6 CG Error: 0.000729092 HPWL: 190804761

[InitialPlace]  Iter: 7 CG Error: 6.74333e-05 HPWL: 190489892

[InitialPlace]  Iter: 8 CG Error: 6.94999e-05 HPWL: 190662552

[InitialPlace]  Iter: 9 CG Error: 3.36633e-05 HPWL: 190512094

[InitialPlace]  Iter: 10 CG Error: 5.18533e-05 HPWL: 190610472

[InitialPlace]  Iter: 11 CG Error: 5.30023e-05 HPWL: 190560818

[InitialPlace]  Iter: 12 CG Error: 5.6628e-05 HPWL: 190648774

[InitialPlace]  Iter: 13 CG Error: 2.82688e-05 HPWL: 190494353

[InitialPlace]  Iter: 14 CG Error: 4.78211e-05 HPWL: 190642021

[InitialPlace]  Iter: 15 CG Error: 7.76779e-05 HPWL: 190535584

[InitialPlace]  Iter: 16 CG Error: 5.8144e-05 HPWL: 190662477

[InitialPlace]  Iter: 17 CG Error: 4.74044e-05 HPWL: 190534521

[InitialPlace]  Iter: 18 CG Error: 8.7525e-05 HPWL: 190605707

[InitialPlace]  Iter: 19 CG Error: 4.43859e-05 HPWL: 190518095

[InitialPlace]  Iter: 20 CG Error: 3.95577e-05 HPWL: 190642137

[INFO] FillerInit: NumGCells = 21032
[INFO] FillerInit: NumGNets = 12163
[INFO] FillerInit: NumGPins = 60348
[INFO] TargetDensity = 0.850000
[INFO] AveragePlaceInstArea = 14712352
[INFO] IdealBinArea = 17308648
[INFO] IdealBinCnt = 21477
[INFO] TotalBinArea = 371744032000
[INFO] BinCnt = (128, 128)
[INFO] BinSize = (5772, 3932)
[INFO] NumBins = 16384
[NesterovSolve] Iter: 1 overflow: 0.995306 HPWL: 43130518
[NesterovSolve] Iter: 10 overflow: 0.977331 HPWL: 99726567
[NesterovSolve] Iter: 20 overflow: 0.975976 HPWL: 107110791
[NesterovSolve] Iter: 30 overflow: 0.976886 HPWL: 105711777
[NesterovSolve] Iter: 40 overflow: 0.976318 HPWL: 106278897
[NesterovSolve] Iter: 50 overflow: 0.976224 HPWL: 107071456
[NesterovSolve] Iter: 60 overflow: 0.976781 HPWL: 106594415
[NesterovSolve] Iter: 70 overflow: 0.976044 HPWL: 106516226
[NesterovSolve] Iter: 80 overflow: 0.975906 HPWL: 106341252
[NesterovSolve] Iter: 90 overflow: 0.975995 HPWL: 106302937
[NesterovSolve] Iter: 100 overflow: 0.976049 HPWL: 106538513
[NesterovSolve] Iter: 110 overflow: 0.976237 HPWL: 106896123
[NesterovSolve] Iter: 120 overflow: 0.976414 HPWL: 107342467
[NesterovSolve] Iter: 130 overflow: 0.976962 HPWL: 107997356
[NesterovSolve] Iter: 140 overflow: 0.976717 HPWL: 109054210
[NesterovSolve] Iter: 150 overflow: 0.976401 HPWL: 110676803
[NesterovSolve] Iter: 160 overflow: 0.975101 HPWL: 113533106
[NesterovSolve] Iter: 170 overflow: 0.971804 HPWL: 117182924
[NesterovSolve] Iter: 180 overflow: 0.96735 HPWL: 119399228
[NesterovSolve] Iter: 190 overflow: 0.964292 HPWL: 120165690
[NesterovSolve] Iter: 200 overflow: 0.962187 HPWL: 122262991
[NesterovSolve] Iter: 210 overflow: 0.958776 HPWL: 129199761
[NesterovSolve] Iter: 220 overflow: 0.95496 HPWL: 138924197
[NesterovSolve] Iter: 230 overflow: 0.945282 HPWL: 149995824
[NesterovSolve] Iter: 240 overflow: 0.934061 HPWL: 161813746
[NesterovSolve] Iter: 250 overflow: 0.918891 HPWL: 177567756
[NesterovSolve] Iter: 260 overflow: 0.892171 HPWL: 195242312
[NesterovSolve] Iter: 270 overflow: 0.862029 HPWL: 211007793
[NesterovSolve] Iter: 280 overflow: 0.831092 HPWL: 226141550
[NesterovSolve] Iter: 290 overflow: 0.794426 HPWL: 240337866
[NesterovSolve] Iter: 300 overflow: 0.753771 HPWL: 252452894
[NesterovSolve] Iter: 310 overflow: 0.711305 HPWL: 261970837
[NesterovSolve] Iter: 320 overflow: 0.663584 HPWL: 268990076
[NesterovSolve] Iter: 330 overflow: 0.614988 HPWL: 286063253
[NesterovSolve] Iter: 340 overflow: 0.577547 HPWL: 295354800
[NesterovSolve] Iter: 350 overflow: 0.550713 HPWL: 289612266
[NesterovSolve] Iter: 360 overflow: 0.538835 HPWL: 283307432
[NesterovSolve] Iter: 370 overflow: 0.521607 HPWL: 280647967
[NesterovSolve] Iter: 380 overflow: 0.503481 HPWL: 278605790
[NesterovSolve] Iter: 390 overflow: 0.453249 HPWL: 275931027
[NesterovSolve] Iter: 400 overflow: 0.398416 HPWL: 272872388
[NesterovSolve] Iter: 410 overflow: 0.354364 HPWL: 271433471
[NesterovSolve] Iter: 420 overflow: 0.315779 HPWL: 269484710
[NesterovSolve] Iter: 430 overflow: 0.28182 HPWL: 271082485
[NesterovSolve] Iter: 440 overflow: 0.250037 HPWL: 273088649
[NesterovSolve] Iter: 450 overflow: 0.213562 HPWL: 274578155
[NesterovSolve] Iter: 460 overflow: 0.177968 HPWL: 276412564
[NesterovSolve] Iter: 470 overflow: 0.142648 HPWL: 277649984
[NesterovSolve] Iter: 480 overflow: 0.114138 HPWL: 279039612
[NesterovSolve] Finished with Overflow: 0.0988869

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.

create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
[INFO]: Global placement was successful


[INFO]: Changing layout from /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def to /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def

[INFO]: Running Detailed Placement...

===========================================================================
   Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 >    
   Developers : SangGi Do, Mingyu Woo                                      
===========================================================================
Parsed 10000 number of lines!!
Parsed 20000 number of lines!!
Parsed 30000 number of lines!!
Parsed 40000 number of lines!!
Parsed 50000 number of lines!!
Parsed 60000 number of lines!!
Reading /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef is Done

-------------------- INPUT FILES ----------------------------------
 benchmark name    : placement
 directory         : /project/openlane/DFFRAM/runs/DFFRAM/tmp
 lef               : /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
 def               : /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def
-------------------------------------------------------------------
Parsed 10000 number of lines!!
Parsed 20000 number of lines!!
Parsed 30000 number of lines!!
Parsed 40000 number of lines!!
CoreArea: 
5520.000000 : 10880.000000 - 744280.000000 : 514080.000000
DieArea: 
0.000000 : 0.000000 - 738760.000000 : 503200.000000
Reading /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def is Done
-------------------- DESIGN ANALYSIS ------------------------------
  total cells              : 25507
  multi cells              : 0
  fixed cells              : 5230
  total nets               : 12163
  design area              : 3.71744e+11
  total f_area             : 7.46966e+09
  total m_area             : 2.98322e+11
  design util              : 81.895
  num rows                 : 185
  row height               : 2720
-------------------------------------------------------------------
 non_group_cell_region_assign done ..
 - - - - - - - - - - - - - - - - - - - - - - - - 
 non_group_cell_placement done .. 
 - - - - - - - - - - - - - - - - - - - - - - - - 
Reading /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def is Done
 DEF file write success !! 

 location : /project/openlane/DFFRAM/runs/DFFRAM/results/placement/DFFRAM.placement.def
-------------------------------------------------------------------
 tasks                          Wtime      Ctime
 Parser                         1.120      1.110
 resgin assign                  1.124      1.110
 pre-placement                  1.124      1.110
 non Group cell placement       1.215      1.200
 All                            1.224      1.210
 - - - - - EVALUATION - - - - - 
 AVG_displacement : 2936.64
 SUM_displacement : 7.49049e+07
 MAX_displacement : 49550
 - - - - - - - - - - - - - - - - 
[ERROR]: during executing: "opendp -lef /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef -def /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def -output_def /project/openlane/DFFRAM/runs/DFFRAM/results/placement/DFFRAM.placement.def |& tee >&@stdout /project/openlane/DFFRAM/runs/DFFRAM/logs/placement/opendp.log"


[ERROR]: Exit code: 1


[ERROR]: Last 10 lines:


child killed: segmentation violation



[ERROR]: Please check opendp  log file


[ERROR]: Dumping to /project/openlane/DFFRAM/runs/DFFRAM/error.log




    while executing

"try_catch opendp  -lef $::env(MERGED_LEF)  -def $::env(CURRENT_DEF)  -output_def $::env(opendp_result_file_tag).def  |& tee $::env(TERMINAL_OUTPUT) $:..."

    (procedure "detailed_placement" line 4)

    invoked from within

"detailed_placement"

    (procedure "run_placement" line 16)

    invoked from within

"run_placement"

    (procedure "run_non_interactive_mode" line 13)

    invoked from within

"run_non_interactive_mode {*}$argv"

    invoked from within

"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {

	puts_info "Running interactively"

	if { [info exists arg_values(-file)..."

    (file "/openLANE_flow/flow.tcl" line 164)

make: *** [Makefile:26: DFFRAM] Fehler 1

Submodule: digital_pll

###############################################
/bin/sh: 1: [[: not found
[INFO]: 

	___   ____   ___  ____   _       ____  ____     ___

	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]

	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_

	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]

	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_

	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|





[INFO]: Version: rc4

[INFO]: Running non-interactively

[INFO]: Using design configuration at /project/openlane/digital_pll/config.tcl

[INFO]: Sourcing Configurations from /project/openlane/digital_pll/config.tcl

[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A

[INFO]: PDK: sky130A

[INFO]: Standard Cell Library: sky130_fd_sc_hd

[INFO]: Sourcing Configurations from /project/openlane/digital_pll/config.tcl

[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.


[INFO]: Current run directory is /project/openlane/digital_pll/runs/digital_pll

[WARNING]: Removing exisiting run /project/openlane/digital_pll/runs/digital_pll


[INFO]: Preparing LEF Files

mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 1.84
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished

[INFO]: Trimming Liberty...

[INFO]: Preparation complete

[INFO]: Running Synthesis...


 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/digital_pll/../../verilog/rtl/digital_pll.v
Parsing Verilog input from `/project/openlane/digital_pll/../../verilog/rtl/digital_pll.v' to AST representation.
Generating RTLIL representation for module `\digital_pll_controller'.
Generating RTLIL representation for module `\delay_stage'.
Generating RTLIL representation for module `\start_stage'.
Generating RTLIL representation for module `\ring_osc2x13'.
Generating RTLIL representation for module `\digital_pll'.
Successfully finished Verilog frontend.


3. Executing HIERARCHY pass (managing design hierarchy).

3.1. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage

3.2. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage
Removed 0 unused modules.

4. Executing SYNTH pass.

4.1. Executing HIERARCHY pass (managing design hierarchy).

4.1.1. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage

4.1.2. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage
Removed 0 unused modules.

4.2. Executing PROC pass (convert processes to netlists).

4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 3 switch rules as full_case in process $proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54 in module digital_pll_controller.
Removed a total of 0 dead cases.

4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 0 assignments to connections.

4.2.4. Executing PROC_INIT pass (extract init attributes).

4.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \reset in `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.

4.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
     1/5: $0\oscbuf[2:0]
     2/5: $0\tval[6:0]
     3/5: $0\count1[4:0]
     4/5: $0\count0[4:0]
     5/5: $0\prep[2:0]

4.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

4.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\digital_pll_controller.\oscbuf' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$98' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\prep' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$99' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\count0' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$100' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\count1' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$101' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\tval' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$102' with positive edge clock and positive level reset.

4.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 7 empty switches in `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
Removing empty process `digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
Cleaned up 7 empty switches.

4.3. Executing FLATTEN pass (flatten design).
Deleting now unused module ring_osc2x13.
Deleting now unused module start_stage.
Deleting now unused module delay_stage.
Deleting now unused module digital_pll_controller.


4.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 2 unused cells and 23 unused wires.


4.6. Executing CHECK pass (checking for obvious problems).
checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:

    port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:

    port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8)
    port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:

    port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:

    port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:

    port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:

    port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:

    port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:

    port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:

    port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:

    port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:

    port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:

    port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:

    port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:

    port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:

    port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:

    port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:

    port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:

    port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:

    port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:

    port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:

    port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:

    port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:

    port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:

    port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:

    port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:

    port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
found and reported 26 problems.

4.7. Executing OPT pass (performing simple optimizations).

4.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.7.6. Executing OPT_DFF pass (perform DFF optimizations).

4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.7.9. Finished OPT passes. (There is nothing left to do.)


4.8. Executing FSM pass (extract and optimize FSM).

4.8.1. Executing FSM_DETECT pass (finding FSMs in design).

4.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

4.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

4.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

4.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

4.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

4.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

4.9. Executing OPT pass (performing simple optimizations).

4.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.9.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\pll_control.$procdff$99 ($adff) from module digital_pll (D = { \pll_control.prep [1:0] 1'1 }, Q = \pll_control.prep).
Adding EN signal on $flatten\pll_control.$procdff$102 ($adff) from module digital_pll (D = $flatten\pll_control.$procmux$81_Y, Q = \pll_control.tval).
Adding EN signal on $flatten\pll_control.$procdff$101 ($adff) from module digital_pll (D = \pll_control.count0, Q = \pll_control.count1).
Adding EN signal on $flatten\pll_control.$procdff$100 ($adff) from module digital_pll (D = $flatten\pll_control.$0\count0[4:0], Q = \pll_control.count0).

4.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 4 unused cells and 4 unused wires.


4.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.9.9. Rerunning OPT passes. (Maybe there is more to do..)

4.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.9.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.9.13. Executing OPT_DFF pass (perform DFF optimizations).

4.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.9.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.9.16. Finished OPT passes. (There is nothing left to do.)


4.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 1 bits (of 3) from port B of cell digital_pll.$auto$opt_dff.cc:218:make_patterns_logic$105 ($ne).
Removed cell digital_pll.$flatten\pll_control.$procmux$90 ($mux).
Removed cell digital_pll.$flatten\pll_control.$procmux$79 ($mux).
Removed cell digital_pll.$flatten\pll_control.$procmux$76 ($mux).
Removed cell digital_pll.$flatten\pll_control.$procmux$74 ($mux).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add).
Removed top 27 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub).
Removed top 25 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62 ($gt).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add).
Removed top 25 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add).
Removed top 25 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59 ($lt).
Removed top 5 bits (of 26) from mux cell digital_pll.$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28 ($mux).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$17 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$16 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$15 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$14 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$13 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$12 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$11 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$10 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$9 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$8 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$7 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$6 ($eq).
Removed top 3 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$5 ($eq).
Removed top 3 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$4 ($eq).
Removed top 4 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$3 ($eq).
Removed top 5 bits (of 26) from wire digital_pll.$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28_Y.

4.11. Executing PEEPOPT pass (run peephole optimizers).

4.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 5 unused wires.


4.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module digital_pll:
  creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add).
  creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add).
  creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1 ($add).
  creating $macc model for $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub).
  creating $alu model for $macc $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63.
  creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1.
  creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65.
  creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60.
  creating $alu model for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58 ($gt): new $alu
  creating $alu model for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62 ($gt): new $alu
  creating $alu model for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59 ($lt): new $alu
  creating $alu model for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:106$61 ($lt): merged with $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58.
  creating $alu cell for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59: $auto$alumacc.cc:485:replace_alu$121
  creating $alu cell for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62: $auto$alumacc.cc:485:replace_alu$126
  creating $alu cell for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58, $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:106$61: $auto$alumacc.cc:485:replace_alu$131
  creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60: $auto$alumacc.cc:485:replace_alu$142
  creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65: $auto$alumacc.cc:485:replace_alu$145
  creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1: $auto$alumacc.cc:485:replace_alu$148
  creating $alu cell for $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63: $auto$alumacc.cc:485:replace_alu$151
  created 7 $alu and 0 $macc cells.

4.14. Executing SHARE pass (SAT-based resource sharing).

4.15. Executing OPT pass (performing simple optimizations).

4.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.15.6. Executing OPT_DFF pass (perform DFF optimizations).

4.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 4 unused wires.


4.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.15.9. Rerunning OPT passes. (Maybe there is more to do..)

4.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.15.13. Executing OPT_DFF pass (perform DFF optimizations).

4.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.15.16. Finished OPT passes. (There is nothing left to do.)


4.16. Executing MEMORY pass.

4.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

4.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

4.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

4.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.18. Executing OPT pass (performing simple optimizations).

4.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.18.3. Executing OPT_DFF pass (perform DFF optimizations).

4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.18.5. Finished fast OPT passes.


4.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

4.20. Executing OPT pass (performing simple optimizations).

4.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29:
      Old ports: A={ 5'11111 $auto$wreduce.cc:454:run$117 [20:0] }, B=26'11111011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y
      New ports: A=$auto$wreduce.cc:454:run$117 [20:0], B=21'011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [25:21] = 5'11111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28:
      Old ports: A=21'111111111111111111111, B=21'011111111111111111111, Y=$auto$wreduce.cc:454:run$117 [20:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$117 [20]
      New connections: $auto$wreduce.cc:454:run$117 [19:0] = 20'11111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y, B=26'10111011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0] }, B=22'0011111011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [23:21] } = 4'1111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29:
      Old ports: A=$auto$wreduce.cc:454:run$117 [20:0], B=21'011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0]
      New ports: A={ $auto$wreduce.cc:454:run$117 [20] 1'1 }, B=2'00, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [19:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [13:0] } = 19'1111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y, B=26'10111011011011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }, B=22'0011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [23:21] } = 4'1111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30:
      Old ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0] }, B=22'0011111011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [14] }, B=3'000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [19:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [13:0] } = 19'1111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y, B=26'10101011011011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }, B=23'00011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [21] } = 3'111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }, B=22'0011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [14] }, B=4'0000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [16:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [13:0] } = 18'111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y, B=26'10101011010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }, B=23'00011010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [21] } = 3'111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }, B=23'00011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [14] }, B=5'00000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [16:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [13:0] } = 18'111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y, B=26'10101010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }, B=23'00010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [21] } = 3'111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }, B=23'00011010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [17] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [14] }, B=6'000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [13:0] } = 17'11111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y, B=26'00101010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }, B=24'000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [21] } = 2'11
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }, B=23'00010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [15:14] }, B=7'0000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [13:0] } = 16'1111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y, B=26'00100010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }, B=25'0000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [23] = 1'1
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35:
      Old ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }, B=24'000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [15:14] }, B=8'00000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [13:0] } = 16'1111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y, B=26'00100010000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }, B=25'0000010000011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:0] }
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [23] = 1'1
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }, B=25'0000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [15:14] }, B=9'000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [13:0] } = 16'1111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }, B=25'0000010000011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [18:17] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [15:14] }, B=10'0000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [18:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [13:0] } = 15'111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y, B=26'00000010000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [18:14] }, B=11'00000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [25:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [18:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [13:0] } = 15'111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y, B=26'00000000000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [25:20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [18:14] }, B=12'000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [25:14]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [13:0] = 14'11111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y, B=26'00000000000001111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [25:14] 1'1 }, B=13'0000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [25:13]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [12:0] = 13'1111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y, B=26'00000000000001111101111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [25:13] 1'1 }, B=14'00000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [7] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [12:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [6:0] } = 12'111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y, B=26'00000000000001111101111101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [7] 1'1 }, B=15'000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [12:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [6:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [0] } = 11'11111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y, B=26'00000000000001011101111101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [25:13] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [1] }, B=16'0000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [10:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [6:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [0] } = 10'1111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y, B=26'00000000000001011101101101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [1] }, B=17'00000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [10:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [3:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [0] } = 9'111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y, B=26'00000000000001010101101101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [11] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [1] }, B=18'000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [3:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [0] } = 8'11111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y, B=26'00000000000001010101101001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [4] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [1] }, B=19'0000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [0] } = 7'1111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y, B=26'00000000000001010101001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [2:1] }, B=20'00000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [0] } = 6'111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y, B=26'00000000000000010101001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [25:13] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [2:1] }, B=21'000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [0] } = 5'11111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y, B=26'00000000000000010001001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [9] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [2:1] }, B=22'0000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [0] } = 4'1111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y, B=26'00000000000000010001000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [5:4] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [2:1] }, B=23'00000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [5:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [0] } = 3'111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y, B=26'00000000000000000001000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [25:11] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [5:1] }, B=24'000000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [25:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [5:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [0] } = 2'11
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y, B=26'00000000000000000000000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [25:7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [5:1] }, B=25'0000000000000000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y [25:1]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y [0] = 1'1
  Optimizing cells in module \digital_pll.
Performed a total of 34 changes.

4.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.20.6. Executing OPT_SHARE pass.
    Found cells that share an operand and can be merged by moving the $mux $flatten\pll_control.$procmux$81 in front of them:
        $auto$alumacc.cc:485:replace_alu$151
        $auto$alumacc.cc:485:replace_alu$142

4.20.7. Executing OPT_DFF pass (perform DFF optimizations).

4.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 6 unused wires.


4.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.20.10. Rerunning OPT passes. (Maybe there is more to do..)

4.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $auto$opt_share.cc:241:merge_operators$157:
      Old ports: A=$auto$rtlil.cc:2123:Neg$155, B=7'0000001, Y=$auto$rtlil.cc:2218:Mux$158
      New ports: A=1'1, B=1'0, Y=$auto$rtlil.cc:2218:Mux$158 [1]
      New connections: { $auto$rtlil.cc:2218:Mux$158 [6:2] $auto$rtlil.cc:2218:Mux$158 [0] } = { $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] 1'1 }
  Optimizing cells in module \digital_pll.
Performed a total of 1 changes.

4.20.13. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.20.14. Executing OPT_SHARE pass.

4.20.15. Executing OPT_DFF pass (perform DFF optimizations).

4.20.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 2 unused wires.


4.20.17. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.20.18. Rerunning OPT passes. (Maybe there is more to do..)

4.20.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.20.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.20.21. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.

Removed a total of 1 cells.

4.20.22. Executing OPT_SHARE pass.

4.20.23. Executing OPT_DFF pass (perform DFF optimizations).

4.20.24. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 1 unused wires.


4.20.25. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.20.26. Rerunning OPT passes. (Maybe there is more to do..)

4.20.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.20.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.20.29. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.20.30. Executing OPT_SHARE pass.

4.20.31. Executing OPT_DFF pass (perform DFF optimizations).

4.20.32. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.20.33. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.20.34. Finished OPT passes. (There is nothing left to do.)


4.21. Executing TECHMAP pass (map to technology primitives).

4.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.


4.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
Using extmapper simplemap for cells of type $adffe.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $adff.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $and.
Using template $paramod\_90_lcu\WIDTH=7 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=6 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=5 for cells of type $lcu.
No more expansions possible.


4.22. Executing OPT pass (performing simple optimizations).

4.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.

Removed a total of 121 cells.

4.22.3. Executing OPT_DFF pass (perform DFF optimizations).

4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 61 unused cells and 376 unused wires.


4.22.5. Finished fast OPT passes.


4.23. Executing ABC pass (technology mapping using ABC).

4.23.1. Extracting gate netlist of module `\digital_pll' to `/input.blif'..
Extracted 556 gates and 614 wires to a netlist network with 56 inputs and 43 outputs.

4.23.1.1. Executing ABC.
Running ABC command: /yosys-abc -s -f /abc.script 2>&1
ABC: ABC command line: "source /abc.script".
ABC: 
ABC: + read_blif /input.blif 
ABC: + read_library /stdcells.genlib 
ABC: Entered genlib library with 13 gates from file "/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif /output.blif 

4.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        4
ABC RESULTS:            ANDNOT cells:       89
ABC RESULTS:               MUX cells:       27
ABC RESULTS:              NAND cells:       17
ABC RESULTS:               NOR cells:       11
ABC RESULTS:               NOT cells:        6
ABC RESULTS:                OR cells:      331
ABC RESULTS:             ORNOT cells:       10
ABC RESULTS:              XNOR cells:       12
ABC RESULTS:               XOR cells:       19
ABC RESULTS:        internal signals:      515
ABC RESULTS:           input signals:       56
ABC RESULTS:          output signals:       43
Removing temp directory.

4.24. Executing OPT pass (performing simple optimizations).

4.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.24.3. Executing OPT_DFF pass (perform DFF optimizations).

4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 242 unused wires.


4.24.5. Finished fast OPT passes.


4.25. Executing HIERARCHY pass (managing design hierarchy).

4.25.1. Analyzing design hierarchy..
Top module:  \digital_pll

4.25.2. Analyzing design hierarchy..
Top module:  \digital_pll
Removed 0 unused modules.

4.26. Printing statistics.

=== digital_pll ===

   Number of wires:                613
   Number of wire bits:            808
   Number of public wires:         120
   Number of public wire bits:     303
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                646
     $_ANDNOT_                      89
     $_AND_                          4
     $_DFFE_PP0N_                    8
     $_DFFE_PP0P_                   12
     $_DFF_PP0_                      3
     $_MUX_                         27
     $_NAND_                        17
     $_NOR_                         11
     $_NOT_                          6
     $_ORNOT_                       10
     $_OR_                         331
     $_XNOR_                        12
     $_XOR_                         19
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__or2_2          1

4.27. Executing CHECK pass (checking for obvious problems).
checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:

    port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:

    port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8)
    port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:

    port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:

    port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:

    port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:

    port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:

    port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:

    port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:

    port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:

    port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:

    port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:

    port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:

    port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:

    port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:

    port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:

    port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:

    port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:

    port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:

    port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:

    port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:

    port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:

    port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:

    port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:

    port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:

    port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:

    port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
found and reported 26 problems.

5. Executing SHARE pass (SAT-based resource sharing).

6. Executing OPT pass (performing simple optimizations).

6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

6.6. Executing OPT_DFF pass (perform DFF optimizations).

6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

6.9. Finished OPT passes. (There is nothing left to do.)


7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 24 unused wires.


8. Printing statistics.

=== digital_pll ===

   Number of wires:                589
   Number of wire bits:            667
   Number of public wires:          96
   Number of public wire bits:     162
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                646
     $_ANDNOT_                      89
     $_AND_                          4
     $_DFFE_PP0N_                    8
     $_DFFE_PP0P_                   12
     $_DFF_PP0_                      3
     $_MUX_                         27
     $_NAND_                        17
     $_NOR_                         11
     $_NOT_                          6
     $_ORNOT_                       10
     $_OR_                         331
     $_XNOR_                        12
     $_XOR_                         19
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__or2_2          1

9. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

9.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\digital_pll':
  mapped 23 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells.

10. Printing statistics.
[INFO]: ABC: WireLoad : S_2

=== digital_pll ===

   Number of wires:                632
   Number of wire bits:            710
   Number of public wires:          96
   Number of public wire bits:     162
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                689
     $_ANDNOT_                      89
     $_AND_                          4
     $_MUX_                         47
     $_NAND_                        17
     $_NOR_                         11
     $_NOT_                         29
     $_ORNOT_                       10
     $_OR_                         331
     $_XNOR_                        12
     $_XOR_                         19
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfrtp_4       23
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__or2_2          1

11. Executing ABC pass (technology mapping using ABC).

11.1. Extracting gate netlist of module `\digital_pll' to `/tmp/yosys-abc-LXniTP/input.blif'..
Extracted 569 gates and 626 wires to a netlist network with 56 inputs and 70 outputs.

11.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-LXniTP/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-LXniTP/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-LXniTP/input.blif 
ABC: + read_lib -w /project/openlane/digital_pll/runs/digital_pll/tmp/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.06 sec

ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/digital_pll/runs/digital_pll/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.08 sec
ABC: Memory =    1.92 MB. Time =     0.08 sec
ABC: + read_constr -v /project/openlane/digital_pll/runs/digital_pll/tmp/synthesis/yosys.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
ABC: Setting output load to be 17.650000.
ABC: + read_constr /project/openlane/digital_pll/runs/digital_pll/tmp/synthesis/yosys.sdc 
ABC: + fx 
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 10000 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.

ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 10000 
ABC: + 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =    270 ( 20.7 %)   Cap = 13.9 ff (  0.0 %)   Area =     3324.44 (100.0 %)   Delay =  3638.60 ps  (  8.1 %)               
ABC: Path  0 --       7 : 0    3 pi                        A =   0.00  Df =  27.5  -17.7 ps  S =  45.0 ps  Cin =  0.0 ff  Cout =  23.6 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --     133 : 1    5 sky130_fd_sc_hd__inv_8    A =  11.26  Df =  60.8   -2.8 ps  S =  44.0 ps  Cin = 17.7 ff  Cout =  22.9 ff  Cmax =1035.5 ff  G =  123  
ABC: Path  2 --     170 : 4    2 sky130_fd_sc_hd__o22a_4   A =  17.52  Df = 517.5  -65.9 ps  S =  80.4 ps  Cin =  4.6 ff  Cout =  22.0 ff  Cmax = 530.1 ff  G =  461  
ABC: Path  3 --     171 : 4    3 sky130_fd_sc_hd__o22a_4   A =  17.52  Df = 720.7 -118.1 ps  S =  58.3 ps  Cin =  4.6 ff  Cout =  13.8 ff  Cmax = 530.1 ff  G =  286  
ABC: Path  4 --     172 : 4    3 sky130_fd_sc_hd__a2bb2o_4 A =  20.02  Df = 945.1   -0.3 ps  S =  73.9 ps  Cin =  4.6 ff  Cout =  19.1 ff  Cmax = 502.6 ff  G =  388  
ABC: Path  5 --     176 : 3    2 sky130_fd_sc_hd__a21bo_4  A =  16.27  Df =1163.4  -87.3 ps  S =  48.1 ps  Cin =  3.9 ff  Cout =   9.5 ff  Cmax = 475.2 ff  G =  231  
ABC: Path  6 --     178 : 4    2 sky130_fd_sc_hd__a211o_4  A =  17.52  Df =1466.3 -257.2 ps  S =  92.2 ps  Cin =  4.6 ff  Cout =  27.6 ff  Cmax = 559.4 ff  G =  570  
ABC: Path  7 --     179 : 1    1 sky130_fd_sc_hd__inv_8    A =  11.26  Df =1519.7 -284.1 ps  S =  27.9 ps  Cin = 17.7 ff  Cout =   4.7 ff  Cmax =1035.5 ff  G =   25  
ABC: Path  8 --     180 : 3    1 sky130_fd_sc_hd__o21a_4   A =  15.01  Df =1634.2 -293.6 ps  S =  47.3 ps  Cin =  4.6 ff  Cout =   9.0 ff  Cmax = 510.0 ff  G =  182  
ABC: Path  9 --     186 : 3    1 sky130_fd_sc_hd__nor3_4   A =  16.27  Df =1663.8 -205.4 ps  S = 106.7 ps  Cin =  8.7 ff  Cout =   2.5 ff  Cmax = 153.8 ff  G =   27  
ABC: Path 10 --     189 : 2   10 sky130_fd_sc_hd__or2_4    A =   8.76  Df =1987.6 -274.2 ps  S = 202.1 ps  Cin =  2.4 ff  Cout =  64.6 ff  Cmax = 514.5 ff  G = 2551  
ABC: Path 11 --     207 : 3    3 sky130_fd_sc_hd__o21ai_4  A =  16.27  Df =2390.9   -7.7 ps  S = 170.3 ps  Cin =  8.8 ff  Cout =  16.1 ff  Cmax = 224.3 ff  G =  175  
ABC: Path 12 --     215 : 5    3 sky130_fd_sc_hd__a32o_4   A =  21.27  Df =2729.1  -98.3 ps  S =  79.2 ps  Cin =  4.3 ff  Cout =  16.1 ff  Cmax = 536.5 ff  G =  355  
ABC: Path 13 --     219 : 5    2 sky130_fd_sc_hd__a32o_4   A =  21.27  Df =3056.4 -210.9 ps  S =  66.1 ps  Cin =  4.3 ff  Cout =  11.3 ff  Cmax = 536.5 ff  G =  252  
ABC: Path 14 --     221 : 2    1 sky130_fd_sc_hd__or2_4    A =   8.76  Df =3301.2 -342.4 ps  S =  46.3 ps  Cin =  2.4 ff  Cout =   4.7 ff  Cmax = 514.5 ff  G =  186  
ABC: Path 15 --     223 : 5    1 sky130_fd_sc_hd__a32o_4   A =  21.27  Df =3638.6 -310.4 ps  S =  83.1 ps  Cin =  4.3 ff  Cout =  17.6 ff  Cmax = 536.5 ff  G =  407  
ABC: Start-point = pi6 (\pll_control.count0 [1]).  End-point = po16 ($auto$rtlil.cc:2290:MuxGate$2331).
ABC: + print_stats -m 
ABC: netlist                       : i/o =   56/   70  lat =    0  nd =   270  edge =    709  area =3324.55  delay =20.00  lev = 20
ABC: + write_blif /tmp/yosys-abc-LXniTP/output.blif 

11.1.2. Re-integrating ABC results.
ABC RESULTS:   sky130_fd_sc_hd__a211o_4 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__a21bo_4 cells:       21
ABC RESULTS:   sky130_fd_sc_hd__a21o_4 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__a21oi_4 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__a2bb2o_4 cells:       13
ABC RESULTS:   sky130_fd_sc_hd__a32o_4 cells:       10
ABC RESULTS:   sky130_fd_sc_hd__and2_4 cells:       11
ABC RESULTS:   sky130_fd_sc_hd__and3_4 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__and4_4 cells:       21
ABC RESULTS:   sky130_fd_sc_hd__buf_1 cells:       22
ABC RESULTS:   sky130_fd_sc_hd__inv_8 cells:       34
ABC RESULTS:   sky130_fd_sc_hd__nand2_4 cells:        8
ABC RESULTS:   sky130_fd_sc_hd__nand4_4 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__nor2_4 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__nor3_4 cells:        6
ABC RESULTS:   sky130_fd_sc_hd__nor4_4 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__o21a_4 cells:        7
ABC RESULTS:   sky130_fd_sc_hd__o21ai_4 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__o22a_4 cells:       11
ABC RESULTS:   sky130_fd_sc_hd__o32a_4 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__or2_4 cells:       55
ABC RESULTS:   sky130_fd_sc_hd__or3_4 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__or4_4 cells:       15
ABC RESULTS:   sky130_fd_sc_hd__xnor2_4 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__xor2_4 cells:        1
ABC RESULTS:        internal signals:      500
ABC RESULTS:           input signals:       56
ABC RESULTS:          output signals:       70
Removing temp directory.

12. Executing SETUNDEF pass (replace undef values with defined constants).

13. Executing HILOMAP pass (mapping to constant drivers).

14. Executing SPLITNETS pass (splitting up multi-bit signals).

15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 637 unused wires.


16. Executing INSBUF pass (insert buffer cells for connected wires).
Added digital_pll.$auto$insbuf.cc:79:execute$2637: \pll_control.clock -> \clockp [0]

17. Executing CHECK pass (checking for obvious problems).
checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:

    port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:

    port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8)
    port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:

    port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:

    port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:

    port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:

    port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:

    port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:

    port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:

    port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:

    port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:

    port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:

    port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:

    port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:

    port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:

    port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:

    port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:

    port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:

    port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:

    port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:

    port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:

    port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:

    port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:

    port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:

    port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:

    port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:

    port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
found and reported 26 problems.

18. Printing statistics.

=== digital_pll ===

   Number of wires:                369
   Number of wire bits:            399
   Number of public wires:         126
   Number of public wire bits:     156
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                391
     sky130_fd_sc_hd__a211o_4        4
     sky130_fd_sc_hd__a21bo_4       21
     sky130_fd_sc_hd__a21o_4         4
     sky130_fd_sc_hd__a21oi_4        2
     sky130_fd_sc_hd__a2bb2o_4      13
     sky130_fd_sc_hd__a32o_4        10
     sky130_fd_sc_hd__and2_4        11
     sky130_fd_sc_hd__and3_4         3
     sky130_fd_sc_hd__and4_4        21
     sky130_fd_sc_hd__buf_1         22
     sky130_fd_sc_hd__buf_2          1
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfrtp_4       23
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__inv_8         34
     sky130_fd_sc_hd__nand2_4        8
     sky130_fd_sc_hd__nand4_4        1
     sky130_fd_sc_hd__nor2_4         5
     sky130_fd_sc_hd__nor3_4         6
     sky130_fd_sc_hd__nor4_4         3
     sky130_fd_sc_hd__o21a_4         7
     sky130_fd_sc_hd__o21ai_4        5
     sky130_fd_sc_hd__o22a_4        11
     sky130_fd_sc_hd__o32a_4         2
     sky130_fd_sc_hd__or2_2          1
     sky130_fd_sc_hd__or2_4         55
     sky130_fd_sc_hd__or3_4          5
     sky130_fd_sc_hd__or4_4         15
     sky130_fd_sc_hd__xnor2_4        1
     sky130_fd_sc_hd__xor2_4         1

   Area for cell type \sky130_fd_sc_hd__buf_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkbuf_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkbuf_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkinv_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkinv_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkinv_8 is unknown!
   Area for cell type \sky130_fd_sc_hd__einvn_4 is unknown!
   Area for cell type \sky130_fd_sc_hd__einvn_8 is unknown!
   Area for cell type \sky130_fd_sc_hd__einvp_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__einvp_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__or2_2 is unknown!

   Chip area for module '\digital_pll': 3990.076800

19. Executing Verilog backend.
Dumping module `\digital_pll'.

Warnings: 26 unique messages, 78 total

End of script. Logfile hash: 835af948d2, CPU: user 3.12s system 0.08s, MEM: 43.74 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 45% 2x abc (2 sec), 10% 2x read_liberty (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis.v

[INFO]: Running Static Timing Analysis...

OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.

create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable

tns 0.00
wns 0.00
[INFO]: Synthesis was successful


[INFO]: Running Floorplanning...

[INFO]: Running Initial Floorplanning...

OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.

Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell

Info: Added 43 rows of 254 sites.
[INFO] Extracting DIE_AREA and CORE_AREA from the floorplan
[INFO] Floorplanned on a die area of 0.0 0.0 128.205 138.925 (microns). Saving to /project/openlane/digital_pll/runs/digital_pll/reports/floorplan/verilog2def.die_area.rpt.
[INFO] Floorplanned on a core area of 5.52 10.88 122.36 127.84 (microns). Saving to /project/openlane/digital_pll/runs/digital_pll/reports/floorplan/verilog2def.core_area.rpt.
[INFO]: Floorplanning was successful


[INFO]: Core area width: 116.84

[INFO]: Core area height: 116.96000000000001

[INFO]: Changing layout from 0 to /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def

[INFO]: Running IO Placement...

OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef

Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 391 components and 2103 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def

#Macro blocks found: 0
Warning: using the default boundaries offset (5 microns)

Warning: using the default min distance between IO pins (2 tracks)

WARNING: force pin spread option has no effect when using random pin placement

 > Running IO placement
 * Num of slots          458
 * Num of I/O            37
 * Num of I/O w/sink     37
 * Num of I/O w/o sink   0
 * Slots Per Section     200
 * Slots Increase Factor 0.01
 * Usage Per Section     0.8
 * Usage Increase Factor 0.01
 * Force Pin Spread      1

WARNING: running random pin placement

RandomMode Even
 > IO placement done.
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def to /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def

[INFO]: Running Tap/Decap Insertion...

OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef

Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 391 components and 2103 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def

Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 0
[INFO] #Original rows: 43
[INFO] #Cut rows: 0
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 86
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 180
Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def to /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def

[INFO]: Running Placement...

[INFO]: Running Global Placement...

OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef

Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 657 components and 2635 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def

[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (122360, 127840)
[INFO] NumInstances = 657
[INFO] NumPlaceInstances = 391
[INFO] NumFixedInstances = 266
[INFO] NumDummyInstances = 0
[INFO] NumNets = 399
[INFO] NumPins = 1357
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (128205, 138925)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (122360, 127840)
[INFO] CoreArea = 13665606400
[INFO] NonPlaceInstsArea = 548025600
[INFO] PlaceInstsArea = 4907206400
[INFO] Util(%) = 37.409386
[INFO] StdInstsArea = 4907206400
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 9.07291e-08 HPWL: 8510935

[InitialPlace]  Iter: 2 CG Error: 1.08554e-07 HPWL: 7551106

[InitialPlace]  Iter: 3 CG Error: 3.58893e-08 HPWL: 7577907

[InitialPlace]  Iter: 4 CG Error: 7.62758e-08 HPWL: 7586893

[InitialPlace]  Iter: 5 CG Error: 9.26014e-08 HPWL: 7594502

[INFO] FillerInit: NumGCells = 581
[INFO] FillerInit: NumGNets = 399
[INFO] FillerInit: NumGPins = 1357
[INFO] TargetDensity = 0.550000
[INFO] AveragePlaceInstArea = 12550400
[INFO] IdealBinArea = 22818908
[INFO] IdealBinCnt = 598
[INFO] TotalBinArea = 13665606400
[INFO] BinCnt = (16, 16)
[INFO] BinSize = (7303, 7310)
[INFO] NumBins = 256
[NesterovSolve] Iter: 1 overflow: 0.829049 HPWL: 5120479
[NesterovSolve] Iter: 10 overflow: 0.659243 HPWL: 6422500
[NesterovSolve] Iter: 20 overflow: 0.645066 HPWL: 6376095
[NesterovSolve] Iter: 30 overflow: 0.639655 HPWL: 6359602
[NesterovSolve] Iter: 40 overflow: 0.639009 HPWL: 6355749
[NesterovSolve] Iter: 50 overflow: 0.639255 HPWL: 6356390
[NesterovSolve] Iter: 60 overflow: 0.639833 HPWL: 6356298
[NesterovSolve] Iter: 70 overflow: 0.639345 HPWL: 6354037
[NesterovSolve] Iter: 80 overflow: 0.638459 HPWL: 6354082
[NesterovSolve] Iter: 90 overflow: 0.63835 HPWL: 6354720
[NesterovSolve] Iter: 100 overflow: 0.638407 HPWL: 6354278
[NesterovSolve] Iter: 110 overflow: 0.638583 HPWL: 6354843
[NesterovSolve] Iter: 120 overflow: 0.63842 HPWL: 6355911
[NesterovSolve] Iter: 130 overflow: 0.637903 HPWL: 6357122
[NesterovSolve] Iter: 140 overflow: 0.637205 HPWL: 6360954
[NesterovSolve] Iter: 150 overflow: 0.636317 HPWL: 6366812
[NesterovSolve] Iter: 160 overflow: 0.63491 HPWL: 6375721
[NesterovSolve] Iter: 170 overflow: 0.632598 HPWL: 6386753
[NesterovSolve] Iter: 180 overflow: 0.628515 HPWL: 6399743
[NesterovSolve] Iter: 190 overflow: 0.618267 HPWL: 6418631
[NesterovSolve] Iter: 200 overflow: 0.607508 HPWL: 6453097
[NesterovSolve] Iter: 210 overflow: 0.59483 HPWL: 6507751
[NesterovSolve] Iter: 220 overflow: 0.57804 HPWL: 6568625
[NesterovSolve] Iter: 230 overflow: 0.55541 HPWL: 6671420
[NesterovSolve] Iter: 240 overflow: 0.527597 HPWL: 6779189
[NesterovSolve] Iter: 250 overflow: 0.488521 HPWL: 6864908
[NesterovSolve] Iter: 260 overflow: 0.448009 HPWL: 6870369
[NesterovSolve] Iter: 270 overflow: 0.411036 HPWL: 6921435
[NesterovSolve] Iter: 280 overflow: 0.371938 HPWL: 7007490
[NesterovSolve] Iter: 290 overflow: 0.333982 HPWL: 7099616
[NesterovSolve] Iter: 300 overflow: 0.298876 HPWL: 7183504
[NesterovSolve] Iter: 310 overflow: 0.259567 HPWL: 7236857
[NesterovSolve] Iter: 320 overflow: 0.228557 HPWL: 7325040
[NesterovSolve] Iter: 330 overflow: 0.201717 HPWL: 7429722
[NesterovSolve] Iter: 340 overflow: 0.168847 HPWL: 7491825
[NesterovSolve] Iter: 350 overflow: 0.143018 HPWL: 7541160
[NesterovSolve] Iter: 360 overflow: 0.123883 HPWL: 7593098
[NesterovSolve] Iter: 370 overflow: 0.0987641 HPWL: 7634093
[NesterovSolve] Finished with Overflow: 0.0987641

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro

Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.

create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable

[INFO]: Global placement was successful


[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def to /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def

[INFO]: Running OpenPhySyn Timing Optimization...

[INFO]: Trimming Liberty...

[OpenPhySyn] [2020-11-20 15:12:40.015] [info] Loaded 6 transforms.
[OpenPhySyn] [2020-11-20 15:12:42.302] [info] OpenPhySyn: 1.8.1
Warning: /project/openlane/digital_pll/runs/digital_pll/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.

Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef

Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 657 components and 2635 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def

Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable

=============== Initial Reports =============
No paths found.
Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Initial area: 54552 um2
OpenPhySyn timing repair:
[OpenPhySyn] [2020-11-20 15:13:42.186] [info] Invoking repair_timing transform
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Buffer library: sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_1
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Inverter library: None
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Buffering: enabled
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Driver sizing: enabled
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Pin-swapping: enabled
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Mode: Timing-Driven
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Iteration 1
[OpenPhySyn] [2020-11-20 15:13:42.424] [info] No more violations or cannot find more optimal buffer
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Runtime: 0s
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Buffers: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Resize up: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Resize down: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Pin Swap: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Buffered nets: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Fanout violations: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Transition violations: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Capacitance violations: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Slack gain: 0.0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Initial area: 5455
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] New area: 5455
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Finished repair_timing transform (0)

Added/updated 0 cells
=============== Final Reports =============
No paths found.
Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Final area: 54552 um2
Export optimized design
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def to /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def

[INFO]: Writing Verilog...

OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef

Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 657 components and 2635 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def

[INFO]: Changing netlist from /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis.v to /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis_optimized.v

[INFO]: Running Static Timing Analysis...

OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.

Warning: /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis_optimized.v, line 1422 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found.  Creating black box for PHY_86.

create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable

tns 0.00
wns 0.00
[INFO]: Running Detailed Placement...

===========================================================================
   Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 >    
   Developers : SangGi Do, Mingyu Woo                                      
===========================================================================
Parsed 10000 number of lines!!
Parsed 20000 number of lines!!
Parsed 30000 number of lines!!
Parsed 40000 number of lines!!
Parsed 50000 number of lines!!
Parsed 60000 number of lines!!
Reading /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef is Done

-------------------- INPUT FILES ----------------------------------
 benchmark name    : placement
 directory         : /project/openlane/digital_pll/runs/digital_pll/tmp
 lef               : /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
 def               : /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def
-------------------------------------------------------------------
CoreArea: 
5520.000000 : 10880.000000 - 122360.000000 : 127840.000000
DieArea: 
0.000000 : 0.000000 - 116840.000000 : 116960.000000
Reading /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def is Done
-------------------- DESIGN ANALYSIS ------------------------------
  total cells              : 657
  multi cells              : 0
  fixed cells              : 266
  total nets               : 399
  design area              : 1.36656e+10
  total f_area             : 5.48026e+08
  total m_area             : 6.86408e+09
  design util              : 52.3274
  num rows                 : 43
  row height               : 2720
-------------------------------------------------------------------
 non_group_cell_region_assign done ..
 - - - - - - - - - - - - - - - - - - - - - - - - 
 non_group_cell_placement done .. 
 - - - - - - - - - - - - - - - - - - - - - - - - 
Reading /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def is Done
 DEF file write success !! 

 location : /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def
-------------------------------------------------------------------
 tasks                          Wtime      Ctime
 Parser                         0.198      0.180
 resgin assign                  0.198      0.180
 pre-placement                  0.198      0.180
 non Group cell placement       0.200      0.190
 All                            0.200      0.190
 - - - - - EVALUATION - - - - - 
 AVG_displacement : 2566.91
 SUM_displacement : 1.68646e+06
 MAX_displacement : 34227
 - - - - - - - - - - - - - - - - 
 GP HPWL          : 7781.67
 HPWL             : 9750.33
 avg_Disp_site    : 5.58023
 avg_Disp_row     : 0.943716
 delta_HPWL       : 25.2987
 ==== CHECK LEGALITY ==== 
 row_check ==>> PASS 
 site_check ==>> PASS 
 power_check ==>> PASS 
 edge_check ==>> PASS 
 placed_check ==>> PASS 
 overlap_check ==>> PASS 
 - - - - - < Program END > - - - - - 
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def to /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def

[INFO]: ::env(CLOCK_PORT) is not set

[WARNING]: Skipping CTS...


[INFO]: Generating PDN...

OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef

Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 657 components and 2635 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def

[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /project/openlane/digital_pll/pdn.tcl
Error: pdn.tcl, 20 can't read "::env(FP_PDN_CORE_RING_HWIDTH)": no such variable

[INFO] [PDNG-0008] Design Name is digital_pll
[INFO] [PDNG-0009] Reading technology data
[CRIT] [PDNG-0017] No stdcell grid specification found - no rails can be inserted
Execution stopped
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/new_pdn.tcl |& tee >&@stdout /project/openlane/digital_pll/runs/digital_pll/logs/floorplan/pdn.log"


[ERROR]: Exit code: 1


[ERROR]: Last 10 lines:


child process exited abnormally



[ERROR]: Please check openroad  log file


[ERROR]: Dumping to /project/openlane/digital_pll/runs/digital_pll/error.log




    while executing

"try_catch openroad -exit $::env(SCRIPTS_DIR)/new_pdn.tcl  |& tee $::env(TERMINAL_OUTPUT) $::env(pdn_log_file_tag).log"

    (procedure "gen_pdn" line 8)

    invoked from within

"gen_pdn"

    (procedure "run_non_interactive_mode" line 15)

    invoked from within

"run_non_interactive_mode {*}$argv"

    invoked from within

"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {

	puts_info "Running interactively"

	if { [info exists arg_values(-file)..."

    (file "/openLANE_flow/flow.tcl" line 164)

make: *** [Makefile:26: digital_pll] Fehler 1

Submodule: gpio_control_block