[INFO]:
___ ____ ___ ____ _ ____ ____ ___
/ \ | \ / _]| \ | | / || \ / _]
| || o ) [_ | _ || | | o || _ | / [_
| O || _/ _]| | || |___ | || | || _]
| || | | [_ | | || || _ || | || [_
\___/ |__| |_____||__|__||_____||__|__||__|__||_____|
[INFO]: Version: v0.15
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/pdk
[INFO]: PDK: sky130A
[INFO]: Setting PDKPATH to /media/philipp/Daten/skywater/pdk/sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_ls
[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl
[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example
[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example
[INFO]: Preparing LEF Files
[INFO]: Extracting the number of available metal layers from /media/philipp/Daten/skywater/pdk/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef
[INFO]: The number of available metal layers is 6
[INFO]: The available metal layers are li1 met1 met2 met3 met4 met5
[INFO]: Merging LEF Files...
mergeLef.py : Merging LEFs
sky130_fd_sc_ls.lef: SITEs matched found: 0
sky130_fd_sc_ls.lef: MACROs matched found: 399
mergeLef.py : Merging LEFs complete
mergeLef.py : Merging LEFs
INVX8.lef: SITEs matched found: 0
INVX8.lef: MACROs matched found: 1
INVX4.lef: SITEs matched found: 0
INVX4.lef: MACROs matched found: 1
BUFX4.lef: SITEs matched found: 0
BUFX4.lef: MACROs matched found: 1
HAX1.lef: SITEs matched found: 0
HAX1.lef: MACROs matched found: 1
LATCH.lef: SITEs matched found: 0
LATCH.lef: MACROs matched found: 1
AOI21X1.lef: SITEs matched found: 0
AOI21X1.lef: MACROs matched found: 1
BUFX2.lef: SITEs matched found: 0
BUFX2.lef: MACROs matched found: 1
INVX2.lef: SITEs matched found: 0
INVX2.lef: MACROs matched found: 1
AND2X2.lef: SITEs matched found: 0
AND2X2.lef: MACROs matched found: 1
AOI22X1.lef: SITEs matched found: 0
AOI22X1.lef: MACROs matched found: 1
CLKBUF1.lef: SITEs matched found: 0
CLKBUF1.lef: MACROs matched found: 1
AND2X1.lef: SITEs matched found: 0
AND2X1.lef: MACROs matched found: 1
INVX1.lef: SITEs matched found: 0
INVX1.lef: MACROs matched found: 1
INV.lef: SITEs matched found: 0
INV.lef: MACROs matched found: 1
mergeLef.py : Merging LEFs complete
[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/INVX8.lef /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/BUFX4.lef /project/openlane/user_proj_example/../../cells/lef/HAX1.lef /project/openlane/user_proj_example/../../cells/lef/LATCH.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef /project/openlane/user_proj_example/../../cells/lef/CLKBUF1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef
[INFO]: Trimming Liberty...
[INFO]: Generating Exclude List...
[INFO]: Storing configs into config.tcl ...
[INFO]: Preparation complete
[INFO]: Running Synthesis...
[INFO]: current step index: 1
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
Reading /project/openlane/user_proj_example/runs/user_proj_example/tmp/sky130_fd_sc_ls__tt_025C_1v80.no_pg.lib as a blackbox
1. Executing Liberty frontend.
Imported 386 cell types from liberty file.
2. Executing Liberty frontend.
Imported 1 cell types from liberty file.
3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation.
Generating RTLIL representation for module `\AND2X1'.
Generating RTLIL representation for module `\AND2X2'.
Generating RTLIL representation for module `\AOI21X1'.
Generating RTLIL representation for module `\AOI22X1'.
Generating RTLIL representation for module `\BUFX2'.
Generating RTLIL representation for module `\BUFX4'.
Generating RTLIL representation for module `\CLKBUF1'.
Generating RTLIL representation for module `\HAX1'.
Generating RTLIL representation for module `\INV'.
Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:91.1-97.10.
Generating RTLIL representation for module `\INVX1'.
Generating RTLIL representation for module `\INVX2'.
Generating RTLIL representation for module `\INVX4'.
Generating RTLIL representation for module `\INVX8'.
Generating RTLIL representation for module `\LATCH'.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
Successfully finished Verilog frontend.
6. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/hierarchy.dot'.
Dumping module user_proj_example to page 1.
7. Executing HIERARCHY pass (managing design hierarchy).
7.1. Analyzing design hierarchy..
Top module: \user_proj_example
7.2. Analyzing design hierarchy..
Top module: \user_proj_example
Removed 0 unused modules.
8. Executing TRIBUF pass.
9. Executing SYNTH pass.
9.1. Executing HIERARCHY pass (managing design hierarchy).
9.1.1. Analyzing design hierarchy..
Top module: \user_proj_example
9.1.2. Analyzing design hierarchy..
Top module: \user_proj_example
Removed 0 unused modules.
9.2. Executing PROC pass (convert processes to netlists).
9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
9.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
9.2.4. Executing PROC_INIT pass (extract init attributes).
9.2.5. Executing PROC_ARST pass (detect async resets in processes).
9.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
9.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
9.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
9.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
9.3. Executing FLATTEN pass (flatten design).
9.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.6. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.
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Warning: Wire user_proj_example.\io_out [36] is used but has no driver.
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Warning: Wire user_proj_example.\io_out [1] is used but has no driver.
Warning: Wire user_proj_example.\io_out [0] is used but has no driver.
found and reported 184 problems.
9.7. Executing OPT pass (performing simple optimizations).
9.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.7.6. Executing OPT_DFF pass (perform DFF optimizations).
9.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.7.9. Finished OPT passes. (There is nothing left to do.)
9.8. Executing FSM pass (extract and optimize FSM).
9.8.1. Executing FSM_DETECT pass (finding FSMs in design).
9.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
9.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
9.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
9.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
9.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
9.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
9.9. Executing OPT pass (performing simple optimizations).
9.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.9.6. Executing OPT_DFF pass (perform DFF optimizations).
9.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.9.9. Finished OPT passes. (There is nothing left to do.)
9.10. Executing WREDUCE pass (reducing word size of cells).
9.11. Executing PEEPOPT pass (run peephole optimizers).
9.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module user_proj_example:
created 0 $alu and 0 $macc cells.
9.14. Executing SHARE pass (SAT-based resource sharing).
9.15. Executing OPT pass (performing simple optimizations).
9.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.15.6. Executing OPT_DFF pass (perform DFF optimizations).
9.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.15.9. Finished OPT passes. (There is nothing left to do.)
9.16. Executing MEMORY pass.
9.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
9.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
9.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
9.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
9.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.18. Executing OPT pass (performing simple optimizations).
9.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
<suppressed ~68 debug messages>
9.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.18.3. Executing OPT_DFF pass (perform DFF optimizations).
9.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.18.5. Finished fast OPT passes.
9.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
9.20. Executing OPT pass (performing simple optimizations).
9.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.20.6. Executing OPT_SHARE pass.
9.20.7. Executing OPT_DFF pass (perform DFF optimizations).
9.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.20.10. Finished OPT passes. (There is nothing left to do.)
9.21. Executing TECHMAP pass (map to technology primitives).
9.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
9.21.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~67 debug messages>
9.22. Executing OPT pass (performing simple optimizations).
9.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.22.3. Executing OPT_DFF pass (perform DFF optimizations).
9.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.22.5. Finished fast OPT passes.
9.23. Executing ABC pass (technology mapping using ABC).
9.23.1. Extracting gate netlist of module `\user_proj_example' to `<abc-temp-dir>/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
9.24. Executing OPT pass (performing simple optimizations).
9.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.24.3. Executing OPT_DFF pass (perform DFF optimizations).
9.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.24.5. Finished fast OPT passes.
9.25. Executing HIERARCHY pass (managing design hierarchy).
9.25.1. Analyzing design hierarchy..
Top module: \user_proj_example
9.25.2. Analyzing design hierarchy..
Top module: \user_proj_example
Removed 0 unused modules.
9.26. Printing statistics.
=== user_proj_example ===
Number of wires: 16
Number of wire bits: 604
Number of public wires: 16
Number of public wire bits: 604
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 14
AND2X1 1
AND2X2 1
AOI21X1 1
AOI22X1 1
BUFX2 1
BUFX4 1
CLKBUF1 1
HAX1 1
INV 1
INVX1 1
INVX2 1
INVX4 1
INVX8 1
LATCH 1
9.27. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.
10. Executing SHARE pass (SAT-based resource sharing).
11. Executing OPT pass (performing simple optimizations).
11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
11.6. Executing OPT_DFF pass (perform DFF optimizations).
11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
11.9. Finished OPT passes. (There is nothing left to do.)
12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
13. Printing statistics.
=== user_proj_example ===
Number of wires: 16
Number of wire bits: 604
Number of public wires: 16
Number of public wire bits: 604
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 14
AND2X1 1
AND2X2 1
AOI21X1 1
AOI22X1 1
BUFX2 1
BUFX4 1
CLKBUF1 1
HAX1 1
INV 1
INVX1 1
INVX2 1
INVX4 1
INVX8 1
LATCH 1
mapping tbuf
14. Executing TECHMAP pass (map to technology primitives).
14.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_ls/tribuff_map.v
Parsing Verilog input from `/media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_ls/tribuff_map.v' to AST representation.
Generating RTLIL representation for module `\$_TBUF_'.
Successfully finished Verilog frontend.
14.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
15. Executing SIMPLEMAP pass (map simple cells to gate primitives).
16. Executing MUXCOVER pass (mapping to wider MUXes).
Covering MUX trees in module user_proj_example..
Treeifying 0 MUXes:
Finished treeification: Found 0 trees.
Covering trees:
Added a total of 0 decoder MUXes.
<suppressed ~1 debug messages>
17. Executing TECHMAP pass (map to technology primitives).
17.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux4_map.v
Parsing Verilog input from `/media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux4_map.v' to AST representation.
Generating RTLIL representation for module `\$_MUX4_'.
Successfully finished Verilog frontend.
17.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
18. Executing SIMPLEMAP pass (map simple cells to gate primitives).
19. Executing TECHMAP pass (map to technology primitives).
19.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux2_map.v
Parsing Verilog input from `/media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux2_map.v' to AST representation.
Generating RTLIL representation for module `\$_MUX_'.
Successfully finished Verilog frontend.
19.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
20. Executing SIMPLEMAP pass (map simple cells to gate primitives).
21. Executing TECHMAP pass (map to technology primitives).
21.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_ls/latch_map.v
Parsing Verilog input from `/media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_ls/latch_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Successfully finished Verilog frontend.
21.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
22. Executing SIMPLEMAP pass (map simple cells to gate primitives).
23. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell sky130_fd_sc_ls__dfxtp_2 (noninv, pins=3, area=28.77) is a direct match for cell type $_DFF_P_.
cell sky130_fd_sc_ls__dfrtp_2 (noninv, pins=4, area=38.36) is a direct match for cell type $_DFF_PN0_.
cell sky130_fd_sc_ls__dfstp_2 (noninv, pins=4, area=39.96) is a direct match for cell type $_DFF_PN1_.
cell sky130_fd_sc_ls__dfbbn_2 (noninv, pins=6, area=47.95) is a direct match for cell type $_DFFSR_NNN_.
final dff cell mappings:
unmapped dff cell: $_DFF_N_
\sky130_fd_sc_ls__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
unmapped dff cell: $_DFF_NN0_
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\sky130_fd_sc_ls__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
\sky130_fd_sc_ls__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
\sky130_fd_sc_ls__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
unmapped dff cell: $_DFFSR_PNN_
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
23.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\user_proj_example':
24. Printing statistics.
=== user_proj_example ===
Number of wires: 16
Number of wire bits: 604
Number of public wires: 16
Number of public wire bits: 604
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 14
AND2X1 1
AND2X2 1
AOI21X1 1
AOI22X1 1
BUFX2 1
BUFX4 1
CLKBUF1 1
HAX1 1
INV 1
INVX1 1
INVX2 1
INVX4 1
INVX8 1
LATCH 1
[INFO]: ABC: WireLoad : S_4
25. Executing ABC pass (technology mapping using ABC).
25.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-PybZYo/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
26. Executing SETUNDEF pass (replace undef values with defined constants).
27. Executing HILOMAP pass (mapping to constant drivers).
28. Executing SPLITNETS pass (splitting up multi-bit signals).
29. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 0 unused cells and 222 unused wires.
<suppressed ~1 debug messages>
30. Executing INSBUF pass (insert buffer cells for connected wires).
31. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.
32. Printing statistics.
=== user_proj_example ===
Number of wires: 16
Number of wire bits: 604
Number of public wires: 16
Number of public wire bits: 604
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 236
AND2X1 1
AND2X2 1
AOI21X1 1
AOI22X1 1
BUFX2 1
BUFX4 1
CLKBUF1 1
HAX1 1
INV 1
INVX1 1
INVX2 1
INVX4 1
INVX8 1
LATCH 1
sky130_fd_sc_ls__conb_1 222
Area for cell type \INVX1 is unknown!
Area for cell type \AND2X1 is unknown!
Area for cell type \AND2X2 is unknown!
Area for cell type \AOI21X1 is unknown!
Area for cell type \AOI22X1 is unknown!
Area for cell type \BUFX2 is unknown!
Area for cell type \BUFX4 is unknown!
Area for cell type \CLKBUF1 is unknown!
Area for cell type \HAX1 is unknown!
Area for cell type \INV is unknown!
Area for cell type \INVX2 is unknown!
Area for cell type \INVX4 is unknown!
Area for cell type \INVX8 is unknown!
Area for cell type \LATCH is unknown!
Chip area for module '\user_proj_example': 1064.534400
33. Executing Verilog backend.
Dumping module `\user_proj_example'.
Warnings: 184 unique messages, 184 total
End of script. Logfile hash: db7c61a443, CPU: user 21.50s system 0.80s, MEM: 386.48 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 38% 4x read_liberty (8 sec), 37% 4x stat (8 sec), 21% 1x dfflibmap (4 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v
[INFO]: Running Static Timing Analysis...
[INFO]: current step index: 2
OpenSTA 2.3.0 38b40303a8 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details.
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/pdk/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/pdk/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 686, module AND2X1 not found. Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 691, module AND2X2 not found. Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 696, module AOI21X1 not found. Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 702, module AOI22X1 not found. Creating black box for AOI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 709, module BUFX2 not found. Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 713, module BUFX4 not found. Creating black box for BUFX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 717, module CLKBUF1 not found. Creating black box for CLKBUF1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 721, module HAX1 not found. Creating black box for HAX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 727, module INV not found. Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 731, module INVX1 not found. Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 735, module INVX2 not found. Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 739, module INVX4 not found. Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 743, module INVX8 not found. Creating black box for INVX8.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 747, module LATCH not found. Creating black box for LATCH.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.02205
set_load $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
[INFO]: current step index: 3
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 413 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
[WARNING ORD-1000] LEF master AND2X1 has no liberty cell.
[WARNING ORD-1000] LEF master AND2X2 has no liberty cell.
[WARNING ORD-1000] LEF master AOI21X1 has no liberty cell.
[WARNING ORD-1000] LEF master AOI22X1 has no liberty cell.
[WARNING ORD-1000] LEF master BUFX2 has no liberty cell.
[WARNING ORD-1000] LEF master BUFX4 has no liberty cell.
[WARNING ORD-1000] LEF master CLKBUF1 has no liberty cell.
[WARNING ORD-1000] LEF master HAX1 has no liberty cell.
[WARNING ORD-1000] LEF master INV has no liberty cell.
[WARNING ORD-1000] LEF master INVX1 has no liberty cell.
[WARNING ORD-1000] LEF master INVX2 has no liberty cell.
[WARNING ORD-1000] LEF master INVX4 has no liberty cell.
[WARNING ORD-1000] LEF master INVX8 has no liberty cell.
[WARNING ORD-1000] LEF master LATCH has no liberty cell.
[INFO IFP-0001] Added 82 rows of 601 sites.
[INFO]: Core area width: 288.48
[INFO]: Core area height: 273.36
[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def
[INFO]: current step index: 4
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 413 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 236 components and 1398 component-terminals.
Notice 0: Created 604 nets and 260 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def
Top-level design name: user_proj_example
Block boundaries: 0 0 300000 300000
Writing /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def
[INFO]: Manual Macro Placement...
[INFO]: current step index: 5
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 413 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 236 components and 1398 component-terminals.
Notice 0: Created 604 nets and 260 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def
Placing the following macros:
{'AND2X1': ['40480', '13600', 'N'], 'AND2X2': ['40480', '19040', 'N'], 'AOI21X1': ['40480', '24480', 'N'], 'AOI22X1': ['40480', '29920', 'N'], 'BUFX2': ['40480', '35360', 'N'], 'BUFX4': ['40480', '40800', 'N'], 'CLKBUF1': ['40480', '46240', 'N'], 'HAX1': ['40480', '51680', 'N'], 'INV': ['40480', '57120', 'N'], 'INVX1': ['40480', '62560', 'N'], 'INVX2': ['40480', '68000', 'N'], 'INVX4': ['40480', '73440', 'N'], 'INVX8': ['40480', '78880', 'N'], 'LATCH': ['40480', '84320', 'N']}
Design name: user_proj_example
Placing AND2X1
Placing AND2X2
Placing AOI21X1
Placing AOI22X1
Placing BUFX2
Placing BUFX4
Placing CLKBUF1
Placing HAX1
Placing INV
Placing INVX1
Placing INVX2
Placing INVX4
Placing INVX8
Placing LATCH
Successfully placed 14 instances
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def
[INFO]: Running Tap/Decap Insertion...
[INFO]: current step index: 6
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 413 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 236 components and 1398 component-terminals.
Notice 0: Created 604 nets and 260 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def
Step 1: Cut rows...
[INFO TAP-0001] Macro blocks found: 0
[INFO TAP-0002] #Original rows: 82
[INFO TAP-0003] #Cut rows: 0
Step 2: Insert endcaps...
[INFO TAP-0004] #Endcaps inserted: 164
Step 3: Insert tapcells...
[INFO TAP-0005] #Tapcells inserted: 882
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def to /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO]: Taking a Screenshot of the Layout Using Klayout...
[INFO]: current step index: 7
Using Techfile: /media/philipp/Daten/skywater/pdk/sky130A/libs.tech/klayout/sky130A.lyt
Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk/sky130A/libs.tech/klayout/sky130A.lyt
[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def.png'
Done
[INFO]: Screenshot taken.
[INFO]: Power planning the following nets
[INFO]: Power: vccd1 vccd2 vdda1 vdda2
[INFO]: Ground: vssd1 vssd2 vssa1 vssa2
[INFO]: Generating PDN...
[INFO]: current step index: 8
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 413 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 1282 components and 3818 component-terminals.
Notice 0: Created 604 nets and 260 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_proj_example
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Layer: met1 - width: 0.480 pitch: 3.330 offset: 0.000
Straps
Layer: met4 - width: 1.600 pitch: 153.600 offset: 16.320
Connect: {met1 met4}
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vccd1 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vccd1.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (22.080um, 10.800um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (175.680um, 10.800um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (175.680um, 10.800um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (175.680um, 151.200um).
[INFO PSM-0031] Number of nodes on net vccd1 = 2876.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vccd1.
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vssd1 is not explicitly set.
[WARNING PSM-0021] Using voltage 0.000V for ground network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vssd1.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (98.880um, 10.800um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (98.880um, 10.800um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (252.480um, 10.800um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (252.480um, 151.200um).
[INFO PSM-0031] Number of nodes on net vssd1 = 2810.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vssd1.
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def
[INFO]: Generating PDN...
[INFO]: current step index: 9
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 413 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def
Notice 0: Design: user_proj_example
Notice 0: Created 606 pins.
Notice 0: Created 1282 components and 3818 component-terminals.
Notice 0: Created 2 special nets and 0 connections.
Notice 0: Created 604 nets and 260 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_proj_example
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Straps
Layer: met4 - width: 1.600 pitch: 153.600 offset: 19.620
Connect:
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vccd2 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vccd2.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (21.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (172.800um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).
[INFO PSM-0031] Number of nodes on net vccd2 = 3.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vccd2.
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vssd2 is not explicitly set.
[WARNING PSM-0021] Using voltage 0.000V for ground network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vssd2.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (97.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (253.800um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (253.800um, 149.850um).
[INFO PSM-0031] Number of nodes on net vssd2 = 3.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vssd2.
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def
[INFO]: Generating PDN...
[INFO]: current step index: 10
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 413 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def
Notice 0: Design: user_proj_example
Notice 0: Created 608 pins.
Notice 0: Created 1282 components and 3818 component-terminals.
Notice 0: Created 4 special nets and 0 connections.
Notice 0: Created 604 nets and 260 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_proj_example
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Straps
Layer: met4 - width: 1.600 pitch: 153.600 offset: 22.920
Connect:
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vdda1 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vdda1.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (27.000um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).
[INFO PSM-0031] Number of nodes on net vdda1 = 2.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vdda1.
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vssa1 is not explicitly set.
[WARNING PSM-0021] Using voltage 0.000V for ground network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vssa1.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).
[INFO PSM-0031] Number of nodes on net vssa1 = 3.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vssa1.
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def
[INFO]: Generating PDN...
[INFO]: current step index: 11
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 413 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def
Notice 0: Design: user_proj_example
Notice 0: Created 610 pins.
Notice 0: Created 1282 components and 3818 component-terminals.
Notice 0: Created 6 special nets and 0 connections.
Notice 0: Created 604 nets and 260 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_proj_example
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Straps
Layer: met4 - width: 1.600 pitch: 153.600 offset: 26.220
Connect:
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vdda2 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vdda2.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (27.000um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (183.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (183.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (183.600um, 149.850um).
[INFO PSM-0031] Number of nodes on net vdda2 = 3.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vdda2.
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vssa2 is not explicitly set.
[WARNING PSM-0021] Using voltage 0.000V for ground network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vssa2.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (108.000um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).
[INFO PSM-0031] Number of nodes on net vssa2 = 3.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vssa2.
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def
[INFO]: Running Placement...
[INFO]: Running Global Placement...
[INFO]: current step index: 12
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 413 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 1282 components and 3818 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 604 nets and 260 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: 480 3330
[INFO GPL-0004] CoreAreaLxLy: 5760 13320
[INFO GPL-0005] CoreAreaUxUy: 294240 286380
[INFO GPL-0006] NumInstances: 1282
[INFO GPL-0007] NumPlaceInstances: 222
[INFO GPL-0008] NumFixedInstances: 1060
[INFO GPL-0009] NumDummyInstances: 0
[INFO GPL-0010] NumNets: 604
[INFO GPL-0011] NumPins: 864
[INFO GPL-0012] DieAreaLxLy: 0 0
[INFO GPL-0013] DieAreaUxUy: 300000 300000
[INFO GPL-0014] CoreAreaLxLy: 5760 13320
[INFO GPL-0015] CoreAreaUxUy: 294240 286380
[INFO GPL-0016] CoreArea: 78772348800
[INFO GPL-0017] NonPlaceInstsArea: 2770027200
[INFO GPL-0018] PlaceInstsArea: 1064534400
[INFO GPL-0019] Util(%): 1.40
[INFO GPL-0020] StdInstsArea: 1064534400
[INFO GPL-0021] MacroInstsArea: 0
Begin InitialPlace
[InitialPlace] Iter: 1 CG Error: 0.00000010 HPWL: 67830840
[InitialPlace] Iter: 2 CG Error: 0.00000000 HPWL: 16746127
[InitialPlace] Iter: 3 CG Error: 0.00000000 HPWL: 16746150
[InitialPlace] Iter: 4 CG Error: 0.00000000 HPWL: 16746150
[InitialPlace] Iter: 5 CG Error: 0.00000000 HPWL: 16746150
End InitialPlace
[INFO GPL-0031] FillerInit: NumGCells: 2377
[INFO GPL-0032] FillerInit: NumGNets: 604
[INFO GPL-0033] FillerInit: NumGPins: 864
[INFO GPL-0023] TargetDensity: 0.15
[INFO GPL-0024] AveragePlaceInstArea: 4795200
[INFO GPL-0025] IdealBinArea: 31967998
[INFO GPL-0026] IdealBinCnt: 2464
[INFO GPL-0027] TotalBinArea: 78772348800
[INFO GPL-0028] BinCnt: 32 32
[INFO GPL-0029] BinSize: 9015 8534
[INFO GPL-0030] NumBins: 1024
Begin NesterovInit
End NesterovInit
[ERROR GPL-0000]
Error: or_replace.tcl, 94 GPL-0000
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_replace.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/user_proj_example/logs/placement/12-replace.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
[ERROR]: Please check openroad log file
[ERROR]: Dumping to /project/openlane/user_proj_example/runs/user_proj_example/error.log
[INFO]: Calculating Runtime From the Start...
[INFO]: Flow failed for user_proj_example/17-05_15-25 in 0h2m53s
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: user_proj_example
Run Directory: /project/openlane/user_proj_example/runs/user_proj_example
Source not found.
----------------------------------------
LVS Summary:
Source: /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs_parsed.gds.log
Source not found.
----------------------------------------
Antenna Summary:
No antenna report found.
[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv
[ERROR]: Flow Failed.
while executing
"try_catch openroad -exit $::env(SCRIPTS_DIR)/openroad/or_replace.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(replaceio_log_file_tag).log 0]"
(procedure "global_placement_or" line 14)
invoked from within
"global_placement_or"
(procedure "run_placement" line 17)
invoked from within
"run_placement"
(procedure "run_non_interactive_mode" line 16)
invoked from within
"run_non_interactive_mode {*}$argv"
invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
puts_info "Running interactively"
if { [info exists arg_values(-file)..."
(file "/openLANE_flow/flow.tcl" line 223)
make[1]: *** [Makefile:43: user_proj_example] Fehler 1