Reports:


Submodule: caravel

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/bin/sh: 1: [[: not found
[INFO]: ___ ____ ___ ____ _ ____ ____ ___ / \ | \ / _]| \ | | / || \ / _] | || o ) [_ | _ || | | o || _ | / [_ | O || _/ _]| | || |___ | || | || _] | || | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____|
[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/caravel/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/caravel/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hvl
no files matched glob pattern "/media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hvl/lef/*.lef" while executing "glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"" invoked from within "set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"]" (file "/media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/openlane/config.tcl" line 13) invoked from within "source $pdk_config" (procedure "prep" line 124) invoked from within "prep {*}$args" (procedure "run_non_interactive_mode" line 9) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { puts_info "Running interactively" if { [info exists arg_values(-file)..." (file "/openLANE_flow/flow.tcl" line 164) make: *** [Makefile:26: caravel] Fehler 1

Submodule: chip_io

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/bin/sh: 1: [[: not found
[INFO]: ___ ____ ___ ____ _ ____ ____ ___ / \ | \ / _]| \ | | / || \ / _] | || o ) [_ | _ || | | o || _ | / [_ | O || _/ _]| | || |___ | || | || _] | || | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____|
[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/chip_io/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/chip_io/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/chip_io/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/chip_io/runs/chip_io
[WARNING]: Removing exisiting run /project/openlane/chip_io/runs/chip_io
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs sky130_fd_sc_hd.lef: SITEs matched found: 0 sky130_fd_sc_hd.lef: MACROs matched found: 437 mergeLef.py : Merging LEFs complete padLefMacro.py : Padding technology lef file Derived SITE width (microns): 0.46 Derived SITE height (microns): 5.44 Right cell padding (microns): 3.68 Left cell padding (microns): 0.0 Top cell padding (microns): 0.0 Bottom cell padding (microns): 0.0 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd2_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_12 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_3 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_6 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_2 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvpwrvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Merging the following GPIO LEF views: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef
[INFO]: Trimming Liberty...
[WARNING]: GPIO_PADS_VERILOG is not set; cannot read as a blackbox
[INFO]: Preparation complete
[INFO]: Running Synthesis...
/----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. 1. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/stubs/sky130_fd_io__top_xres4v2.v Parsing Verilog input from `/project/openlane/chip_io/../../verilog/stubs/sky130_fd_io__top_xres4v2.v' to AST representation. Generating RTLIL representation for module `\sky130_fd_io__top_xres4v2'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/defines.v Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/pads.v Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/pads.v' to AST representation.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/mprj_io.v Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/mprj_io.v' to AST representation. Generating RTLIL representation for module `\mprj_io'.
Successfully finished Verilog frontend.
5. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/chip_io.v Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/chip_io.v' to AST representation. Generating RTLIL representation for module `\chip_io'.
/project/openlane/chip_io/../../verilog/rtl/chip_io.v:173: Warning: Identifier `\loop_gpio' is implicitly declared.
/project/openlane/chip_io/../../verilog/rtl/chip_io.v:178: Warning: Identifier `\loop_flash_io0' is implicitly declared.
/project/openlane/chip_io/../../verilog/rtl/chip_io.v:181: Warning: Identifier `\loop_flash_io1' is implicitly declared.
/project/openlane/chip_io/../../verilog/rtl/chip_io.v:196: Warning: Identifier `\xresloop' is implicitly declared.
Successfully finished Verilog frontend.
6. Executing HIERARCHY pass (managing design hierarchy). 6.1. Analyzing design hierarchy..
ERROR: Module `\sky130_ef_io__gpiov2_pad' referenced in module `\mprj_io' in cell `\area2_io_pad[19]' is not part of the design.
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/chip_io/runs/chip_io/logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
[ERROR]: Please check yosys log file
[ERROR]: Dumping to /project/openlane/chip_io/runs/chip_io/error.log
while executing "try_catch [get_yosys_bin] -c $::env(SYNTH_SCRIPT) -l $::env(yosys_log_file_tag).log |& tee $::env(TERMINAL_OUTPUT)" (procedure "run_yosys" line 18) invoked from within "run_yosys" (procedure "run_synthesis" line 4) invoked from within "run_synthesis" (procedure "run_non_interactive_mode" line 11) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { puts_info "Running interactively" if { [info exists arg_values(-file)..." (file "/openLANE_flow/flow.tcl" line 164) make: *** [Makefile:26: chip_io] Fehler 1

Submodule: DFFRAM

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/bin/sh: 1: [[: not found
[INFO]: ___ ____ ___ ____ _ ____ ____ ___ / \ | \ / _]| \ | | / || \ / _] | || o ) [_ | _ || | | o || _ | / [_ | O || _/ _]| | || |___ | || | || _] | || | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____|
[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/DFFRAM/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/DFFRAM/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/DFFRAM/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/DFFRAM/runs/DFFRAM
[WARNING]: Removing exisiting run /project/openlane/DFFRAM/runs/DFFRAM
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs sky130_fd_sc_hd.lef: SITEs matched found: 0 sky130_fd_sc_hd.lef: MACROs matched found: 437 mergeLef.py : Merging LEFs complete padLefMacro.py : Padding technology lef file Derived SITE width (microns): 0.46 Derived SITE height (microns): 5.44 Right cell padding (microns): 0.0 Left cell padding (microns): 0.0 Top cell padding (microns): 0.0 Bottom cell padding (microns): 0.0 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd2_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_12 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_3 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_6 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_2 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvpwrvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...
/----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. 1. Executing Liberty frontend. Imported 428 cell types from liberty file. 2. Executing Verilog-2005 frontend: /project/openlane/DFFRAM/../../verilog/rtl/defines.v Parsing Verilog input from `/project/openlane/DFFRAM/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: /project/openlane/DFFRAM/../../verilog/rtl/DFFRAM.v Parsing Verilog input from `/project/openlane/DFFRAM/../../verilog/rtl/DFFRAM.v' to AST representation. Generating RTLIL representation for module `\DFFRAM'.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: /project/openlane/DFFRAM/../../verilog/rtl/DFFRAMBB.v Parsing Verilog input from `/project/openlane/DFFRAM/../../verilog/rtl/DFFRAMBB.v' to AST representation. Generating RTLIL representation for module `\BYTE'. Generating RTLIL representation for module `\WORD32'. Generating RTLIL representation for module `\DEC1x2'. Generating RTLIL representation for module `\DEC2x4'. Generating RTLIL representation for module `\DEC3x8'. Generating RTLIL representation for module `\DEC6x64'. Generating RTLIL representation for module `\MUX2x1_32'. Generating RTLIL representation for module `\MUX4x1_32'. Generating RTLIL representation for module `\PASS'. Generating RTLIL representation for module `\SRAM64x32'. Generating RTLIL representation for module `\DFFRAM_COL4'.
Successfully finished Verilog frontend.
5. Executing HIERARCHY pass (managing design hierarchy). 5.1. Analyzing design hierarchy.. Top module: \DFFRAM Used module: \PASS Used module: \DFFRAM_COL4 Used module: \MUX4x1_32 Used module: \SRAM64x32 Used module: \WORD32 Used module: \BYTE Used module: \DEC6x64 Used module: \DEC3x8 Used module: \DEC2x4 5.2. Analyzing design hierarchy.. Top module: \DFFRAM Used module: \PASS Used module: \DFFRAM_COL4 Used module: \MUX4x1_32 Used module: \SRAM64x32 Used module: \WORD32 Used module: \BYTE Used module: \DEC6x64 Used module: \DEC3x8 Used module: \DEC2x4 Removing unused module `\MUX2x1_32'. Removing unused module `\DEC1x2'. Removed 2 unused modules. 6. Printing statistics. === PASS === Number of wires: 2 Number of wire bits: 64 Number of public wires: 2 Number of public wire bits: 64 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 0 === MUX4x1_32 === Number of wires: 6 Number of wire bits: 162 Number of public wires: 6 Number of public wire bits: 162 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 32 sky130_fd_sc_hd__mux4_1 32 === DFFRAM_COL4 === Number of wires: 16 Number of wire bits: 282 Number of public wires: 16 Number of public wire bits: 282 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 46 DEC2x4 1 MUX4x1_32 1 SRAM64x32 4 sky130_fd_sc_hd__clkbuf_16 3 sky130_fd_sc_hd__clkbuf_8 37 === DEC6x64 === Number of wires: 5 Number of wire bits: 82 Number of public wires: 5 Number of public wire bits: 82 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 12 DEC3x8 9 sky130_fd_sc_hd__clkbuf_16 3 === DEC3x8 === Number of wires: 3 Number of wire bits: 12 Number of public wires: 3 Number of public wire bits: 12 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 8 sky130_fd_sc_hd__and4_2 1 sky130_fd_sc_hd__and4b_2 3 sky130_fd_sc_hd__and4bb_2 3 sky130_fd_sc_hd__nor4b_2 1 === DEC2x4 === Number of wires: 3 Number of wire bits: 7 Number of public wires: 3 Number of public wire bits: 7 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 4 sky130_fd_sc_hd__and3_4 1 sky130_fd_sc_hd__and3b_4 2 sky130_fd_sc_hd__nor3b_4 1 === SRAM64x32 === Number of wires: 13 Number of wire bits: 211 Number of public wires: 13 Number of public wire bits: 211 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 168 DEC6x64 1 WORD32 64 sky130_fd_sc_hd__clkbuf_16 37 sky130_fd_sc_hd__clkbuf_4 1 sky130_fd_sc_hd__conb_1 1 sky130_fd_sc_hd__dfxtp_1 32 sky130_fd_sc_hd__ebufn_4 32 === WORD32 === Number of wires: 5 Number of wire bits: 70 Number of public wires: 5 Number of public wire bits: 70 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 4 BYTE 4 === BYTE === Number of wires: 9 Number of wire bits: 30 Number of public wires: 9 Number of public wire bits: 30 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 19 sky130_fd_sc_hd__and2_1 1 sky130_fd_sc_hd__dfxtp_1 8 sky130_fd_sc_hd__dlclkp_1 1 sky130_fd_sc_hd__ebufn_2 8 sky130_fd_sc_hd__inv_1 1 === DFFRAM === Number of wires: 9 Number of wire bits: 143 Number of public wires: 9 Number of public wire bits: 143 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 35 DFFRAM_COL4 1 PASS 1 sky130_fd_sc_hd__clkbuf_4 33 === design hierarchy === DFFRAM 1 DFFRAM_COL4 1 DEC2x4 1 MUX4x1_32 1 SRAM64x32 4 DEC6x64 1 DEC3x8 9 WORD32 64 BYTE 4 PASS 1 Number of wires: 10712 Number of wire bits: 50902 Number of public wires: 10712 Number of public wire bits: 50902 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 20277 sky130_fd_sc_hd__and2_1 1024 sky130_fd_sc_hd__and3_4 1 sky130_fd_sc_hd__and3b_4 2 sky130_fd_sc_hd__and4_2 36 sky130_fd_sc_hd__and4b_2 108 sky130_fd_sc_hd__and4bb_2 108 sky130_fd_sc_hd__clkbuf_16 163 sky130_fd_sc_hd__clkbuf_4 37 sky130_fd_sc_hd__clkbuf_8 37 sky130_fd_sc_hd__conb_1 4 sky130_fd_sc_hd__dfxtp_1 8320 sky130_fd_sc_hd__dlclkp_1 1024 sky130_fd_sc_hd__ebufn_2 8192 sky130_fd_sc_hd__ebufn_4 128 sky130_fd_sc_hd__inv_1 1024 sky130_fd_sc_hd__mux4_1 32 sky130_fd_sc_hd__nor3b_4 1 sky130_fd_sc_hd__nor4b_2 36 7. Executing SPLITNETS pass (splitting up multi-bit signals). 8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \PASS.. Finding unused cells or wires in module \MUX4x1_32.. Finding unused cells or wires in module \DFFRAM_COL4.. Finding unused cells or wires in module \DEC6x64.. Finding unused cells or wires in module \DEC3x8.. Finding unused cells or wires in module \DEC2x4.. Finding unused cells or wires in module \SRAM64x32.. Finding unused cells or wires in module \WORD32.. Finding unused cells or wires in module \BYTE.. Finding unused cells or wires in module \DFFRAM.. 9. Executing CHECK pass (checking for obvious problems). checking module BYTE.. checking module DEC2x4.. checking module DEC3x8.. checking module DEC6x64.. checking module DFFRAM.. checking module DFFRAM_COL4.. checking module MUX4x1_32.. checking module PASS.. checking module SRAM64x32..
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[9]:
port Z[0] of cell FLOATBUF[9] (sky130_fd_sc_hd__ebufn_4) port Do[9] of cell WORD[0].W (WORD32) port Do[9] of cell WORD[10].W (WORD32) port Do[9] of cell WORD[11].W (WORD32) port Do[9] of cell WORD[12].W (WORD32) port Do[9] of cell WORD[13].W (WORD32) port Do[9] of cell WORD[14].W (WORD32) port Do[9] of cell WORD[15].W (WORD32) port Do[9] of cell WORD[16].W (WORD32) port Do[9] of cell WORD[17].W (WORD32) port Do[9] of cell WORD[18].W (WORD32) port Do[9] of cell WORD[19].W (WORD32) port Do[9] of cell WORD[1].W (WORD32) port Do[9] of cell WORD[20].W (WORD32) port Do[9] of cell WORD[21].W (WORD32) port Do[9] of cell WORD[22].W (WORD32) port Do[9] of cell WORD[23].W (WORD32) port Do[9] of cell WORD[24].W (WORD32) port Do[9] of cell WORD[25].W (WORD32) port Do[9] of cell WORD[26].W (WORD32) port Do[9] of cell WORD[27].W (WORD32) port Do[9] of cell WORD[28].W (WORD32) port Do[9] of cell WORD[29].W (WORD32) port Do[9] of cell WORD[2].W (WORD32) port Do[9] of cell WORD[30].W (WORD32) port Do[9] of cell WORD[31].W (WORD32) port Do[9] of cell WORD[32].W (WORD32) port Do[9] of cell WORD[33].W (WORD32) port Do[9] of cell WORD[34].W (WORD32) port Do[9] of cell WORD[35].W (WORD32) port Do[9] of cell WORD[36].W (WORD32) port Do[9] of cell WORD[37].W (WORD32) port Do[9] of cell WORD[38].W (WORD32) port Do[9] of cell WORD[39].W (WORD32) port Do[9] of cell WORD[3].W (WORD32) port Do[9] of cell WORD[40].W (WORD32) port Do[9] of cell WORD[41].W (WORD32) port Do[9] of cell WORD[42].W (WORD32) port Do[9] of cell WORD[43].W (WORD32) port Do[9] of cell WORD[44].W (WORD32) port Do[9] of cell WORD[45].W (WORD32) port Do[9] of cell WORD[46].W (WORD32) port Do[9] of cell WORD[47].W (WORD32) port Do[9] of cell WORD[48].W (WORD32) port Do[9] of cell WORD[49].W (WORD32) port Do[9] of cell WORD[4].W (WORD32) port Do[9] of cell WORD[50].W (WORD32) port Do[9] of cell WORD[51].W (WORD32) port Do[9] of cell WORD[52].W (WORD32) port Do[9] of cell WORD[53].W (WORD32) port Do[9] of cell WORD[54].W (WORD32) port Do[9] of cell WORD[55].W (WORD32) port Do[9] of cell WORD[56].W (WORD32) port Do[9] of cell WORD[57].W (WORD32) port Do[9] of cell WORD[58].W (WORD32) port Do[9] of cell WORD[59].W (WORD32) port Do[9] of cell WORD[5].W (WORD32) port Do[9] of cell WORD[60].W (WORD32) port Do[9] of cell WORD[61].W (WORD32) port Do[9] of cell WORD[62].W (WORD32) port Do[9] of cell WORD[63].W (WORD32) port Do[9] of cell WORD[6].W (WORD32) port Do[9] of cell WORD[7].W (WORD32) port Do[9] of cell WORD[8].W (WORD32) port Do[9] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[8]:
port Z[0] of cell FLOATBUF[8] (sky130_fd_sc_hd__ebufn_4) port Do[8] of cell WORD[0].W (WORD32) port Do[8] of cell WORD[10].W (WORD32) port Do[8] of cell WORD[11].W (WORD32) port Do[8] of cell WORD[12].W (WORD32) port Do[8] of cell WORD[13].W (WORD32) port Do[8] of cell WORD[14].W (WORD32) port Do[8] of cell WORD[15].W (WORD32) port Do[8] of cell WORD[16].W (WORD32) port Do[8] of cell WORD[17].W (WORD32) port Do[8] of cell WORD[18].W (WORD32) port Do[8] of cell WORD[19].W (WORD32) port Do[8] of cell WORD[1].W (WORD32) port Do[8] of cell WORD[20].W (WORD32) port Do[8] of cell WORD[21].W (WORD32) port Do[8] of cell WORD[22].W (WORD32) port Do[8] of cell WORD[23].W (WORD32) port Do[8] of cell WORD[24].W (WORD32) port Do[8] of cell WORD[25].W (WORD32) port Do[8] of cell WORD[26].W (WORD32) port Do[8] of cell WORD[27].W (WORD32) port Do[8] of cell WORD[28].W (WORD32) port Do[8] of cell WORD[29].W (WORD32) port Do[8] of cell WORD[2].W (WORD32) port Do[8] of cell WORD[30].W (WORD32) port Do[8] of cell WORD[31].W (WORD32) port Do[8] of cell WORD[32].W (WORD32) port Do[8] of cell WORD[33].W (WORD32) port Do[8] of cell WORD[34].W (WORD32) port Do[8] of cell WORD[35].W (WORD32) port Do[8] of cell WORD[36].W (WORD32) port Do[8] of cell WORD[37].W (WORD32) port Do[8] of cell WORD[38].W (WORD32) port Do[8] of cell WORD[39].W (WORD32) port Do[8] of cell WORD[3].W (WORD32) port Do[8] of cell WORD[40].W (WORD32) port Do[8] of cell WORD[41].W (WORD32) port Do[8] of cell WORD[42].W (WORD32) port Do[8] of cell WORD[43].W (WORD32) port Do[8] of cell WORD[44].W (WORD32) port Do[8] of cell WORD[45].W (WORD32) port Do[8] of cell WORD[46].W (WORD32) port Do[8] of cell WORD[47].W (WORD32) port Do[8] of cell WORD[48].W (WORD32) port Do[8] of cell WORD[49].W (WORD32) port Do[8] of cell WORD[4].W (WORD32) port Do[8] of cell WORD[50].W (WORD32) port Do[8] of cell WORD[51].W (WORD32) port Do[8] of cell WORD[52].W (WORD32) port Do[8] of cell WORD[53].W (WORD32) port Do[8] of cell WORD[54].W (WORD32) port Do[8] of cell WORD[55].W (WORD32) port Do[8] of cell WORD[56].W (WORD32) port Do[8] of cell WORD[57].W (WORD32) port Do[8] of cell WORD[58].W (WORD32) port Do[8] of cell WORD[59].W (WORD32) port Do[8] of cell WORD[5].W (WORD32) port Do[8] of cell WORD[60].W (WORD32) port Do[8] of cell WORD[61].W (WORD32) port Do[8] of cell WORD[62].W (WORD32) port Do[8] of cell WORD[63].W (WORD32) port Do[8] of cell WORD[6].W (WORD32) port Do[8] of cell WORD[7].W (WORD32) port Do[8] of cell WORD[8].W (WORD32) port Do[8] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[7]:
port Z[0] of cell FLOATBUF[7] (sky130_fd_sc_hd__ebufn_4) port Do[7] of cell WORD[0].W (WORD32) port Do[7] of cell WORD[10].W (WORD32) port Do[7] of cell WORD[11].W (WORD32) port Do[7] of cell WORD[12].W (WORD32) port Do[7] of cell WORD[13].W (WORD32) port Do[7] of cell WORD[14].W (WORD32) port Do[7] of cell WORD[15].W (WORD32) port Do[7] of cell WORD[16].W (WORD32) port Do[7] of cell WORD[17].W (WORD32) port Do[7] of cell WORD[18].W (WORD32) port Do[7] of cell WORD[19].W (WORD32) port Do[7] of cell WORD[1].W (WORD32) port Do[7] of cell WORD[20].W (WORD32) port Do[7] of cell WORD[21].W (WORD32) port Do[7] of cell WORD[22].W (WORD32) port Do[7] of cell WORD[23].W (WORD32) port Do[7] of cell WORD[24].W (WORD32) port Do[7] of cell WORD[25].W (WORD32) port Do[7] of cell WORD[26].W (WORD32) port Do[7] of cell WORD[27].W (WORD32) port Do[7] of cell WORD[28].W (WORD32) port Do[7] of cell WORD[29].W (WORD32) port Do[7] of cell WORD[2].W (WORD32) port Do[7] of cell WORD[30].W (WORD32) port Do[7] of cell WORD[31].W (WORD32) port Do[7] of cell WORD[32].W (WORD32) port Do[7] of cell WORD[33].W (WORD32) port Do[7] of cell WORD[34].W (WORD32) port Do[7] of cell WORD[35].W (WORD32) port Do[7] of cell WORD[36].W (WORD32) port Do[7] of cell WORD[37].W (WORD32) port Do[7] of cell WORD[38].W (WORD32) port Do[7] of cell WORD[39].W (WORD32) port Do[7] of cell WORD[3].W (WORD32) port Do[7] of cell WORD[40].W (WORD32) port Do[7] of cell WORD[41].W (WORD32) port Do[7] of cell WORD[42].W (WORD32) port Do[7] of cell WORD[43].W (WORD32) port Do[7] of cell WORD[44].W (WORD32) port Do[7] of cell WORD[45].W (WORD32) port Do[7] of cell WORD[46].W (WORD32) port Do[7] of cell WORD[47].W (WORD32) port Do[7] of cell WORD[48].W (WORD32) port Do[7] of cell WORD[49].W (WORD32) port Do[7] of cell WORD[4].W (WORD32) port Do[7] of cell WORD[50].W (WORD32) port Do[7] of cell WORD[51].W (WORD32) port Do[7] of cell WORD[52].W (WORD32) port Do[7] of cell WORD[53].W (WORD32) port Do[7] of cell WORD[54].W (WORD32) port Do[7] of cell WORD[55].W (WORD32) port Do[7] of cell WORD[56].W (WORD32) port Do[7] of cell WORD[57].W (WORD32) port Do[7] of cell WORD[58].W (WORD32) port Do[7] of cell WORD[59].W (WORD32) port Do[7] of cell WORD[5].W (WORD32) port Do[7] of cell WORD[60].W (WORD32) port Do[7] of cell WORD[61].W (WORD32) port Do[7] of cell WORD[62].W (WORD32) port Do[7] of cell WORD[63].W (WORD32) port Do[7] of cell WORD[6].W (WORD32) port Do[7] of cell WORD[7].W (WORD32) port Do[7] of cell WORD[8].W (WORD32) port Do[7] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[6]:
port Z[0] of cell FLOATBUF[6] (sky130_fd_sc_hd__ebufn_4) port Do[6] of cell WORD[0].W (WORD32) port Do[6] of cell WORD[10].W (WORD32) port Do[6] of cell WORD[11].W (WORD32) port Do[6] of cell WORD[12].W (WORD32) port Do[6] of cell WORD[13].W (WORD32) port Do[6] of cell WORD[14].W (WORD32) port Do[6] of cell WORD[15].W (WORD32) port Do[6] of cell WORD[16].W (WORD32) port Do[6] of cell WORD[17].W (WORD32) port Do[6] of cell WORD[18].W (WORD32) port Do[6] of cell WORD[19].W (WORD32) port Do[6] of cell WORD[1].W (WORD32) port Do[6] of cell WORD[20].W (WORD32) port Do[6] of cell WORD[21].W (WORD32) port Do[6] of cell WORD[22].W (WORD32) port Do[6] of cell WORD[23].W (WORD32) port Do[6] of cell WORD[24].W (WORD32) port Do[6] of cell WORD[25].W (WORD32) port Do[6] of cell WORD[26].W (WORD32) port Do[6] of cell WORD[27].W (WORD32) port Do[6] of cell WORD[28].W (WORD32) port Do[6] of cell WORD[29].W (WORD32) port Do[6] of cell WORD[2].W (WORD32) port Do[6] of cell WORD[30].W (WORD32) port Do[6] of cell WORD[31].W (WORD32) port Do[6] of cell WORD[32].W (WORD32) port Do[6] of cell WORD[33].W (WORD32) port Do[6] of cell WORD[34].W (WORD32) port Do[6] of cell WORD[35].W (WORD32) port Do[6] of cell WORD[36].W (WORD32) port Do[6] of cell WORD[37].W (WORD32) port Do[6] of cell WORD[38].W (WORD32) port Do[6] of cell WORD[39].W (WORD32) port Do[6] of cell WORD[3].W (WORD32) port Do[6] of cell WORD[40].W (WORD32) port Do[6] of cell WORD[41].W (WORD32) port Do[6] of cell WORD[42].W (WORD32) port Do[6] of cell WORD[43].W (WORD32) port Do[6] of cell WORD[44].W (WORD32) port Do[6] of cell WORD[45].W (WORD32) port Do[6] of cell WORD[46].W (WORD32) port Do[6] of cell WORD[47].W (WORD32) port Do[6] of cell WORD[48].W (WORD32) port Do[6] of cell WORD[49].W (WORD32) port Do[6] of cell WORD[4].W (WORD32) port Do[6] of cell WORD[50].W (WORD32) port Do[6] of cell WORD[51].W (WORD32) port Do[6] of cell WORD[52].W (WORD32) port Do[6] of cell WORD[53].W (WORD32) port Do[6] of cell WORD[54].W (WORD32) port Do[6] of cell WORD[55].W (WORD32) port Do[6] of cell WORD[56].W (WORD32) port Do[6] of cell WORD[57].W (WORD32) port Do[6] of cell WORD[58].W (WORD32) port Do[6] of cell WORD[59].W (WORD32) port Do[6] of cell WORD[5].W (WORD32) port Do[6] of cell WORD[60].W (WORD32) port Do[6] of cell WORD[61].W (WORD32) port Do[6] of cell WORD[62].W (WORD32) port Do[6] of cell WORD[63].W (WORD32) port Do[6] of cell WORD[6].W (WORD32) port Do[6] of cell WORD[7].W (WORD32) port Do[6] of cell WORD[8].W (WORD32) port Do[6] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[5]:
port Z[0] of cell FLOATBUF[5] (sky130_fd_sc_hd__ebufn_4) port Do[5] of cell WORD[0].W (WORD32) port Do[5] of cell WORD[10].W (WORD32) port Do[5] of cell WORD[11].W (WORD32) port Do[5] of cell WORD[12].W (WORD32) port Do[5] of cell WORD[13].W (WORD32) port Do[5] of cell WORD[14].W (WORD32) port Do[5] of cell WORD[15].W (WORD32) port Do[5] of cell WORD[16].W (WORD32) port Do[5] of cell WORD[17].W (WORD32) port Do[5] of cell WORD[18].W (WORD32) port Do[5] of cell WORD[19].W (WORD32) port Do[5] of cell WORD[1].W (WORD32) port Do[5] of cell WORD[20].W (WORD32) port Do[5] of cell WORD[21].W (WORD32) port Do[5] of cell WORD[22].W (WORD32) port Do[5] of cell WORD[23].W (WORD32) port Do[5] of cell WORD[24].W (WORD32) port Do[5] of cell WORD[25].W (WORD32) port Do[5] of cell WORD[26].W (WORD32) port Do[5] of cell WORD[27].W (WORD32) port Do[5] of cell WORD[28].W (WORD32) port Do[5] of cell WORD[29].W (WORD32) port Do[5] of cell WORD[2].W (WORD32) port Do[5] of cell WORD[30].W (WORD32) port Do[5] of cell WORD[31].W (WORD32) port Do[5] of cell WORD[32].W (WORD32) port Do[5] of cell WORD[33].W (WORD32) port Do[5] of cell WORD[34].W (WORD32) port Do[5] of cell WORD[35].W (WORD32) port Do[5] of cell WORD[36].W (WORD32) port Do[5] of cell WORD[37].W (WORD32) port Do[5] of cell WORD[38].W (WORD32) port Do[5] of cell WORD[39].W (WORD32) port Do[5] of cell WORD[3].W (WORD32) port Do[5] of cell WORD[40].W (WORD32) port Do[5] of cell WORD[41].W (WORD32) port Do[5] of cell WORD[42].W (WORD32) port Do[5] of cell WORD[43].W (WORD32) port Do[5] of cell WORD[44].W (WORD32) port Do[5] of cell WORD[45].W (WORD32) port Do[5] of cell WORD[46].W (WORD32) port Do[5] of cell WORD[47].W (WORD32) port Do[5] of cell WORD[48].W (WORD32) port Do[5] of cell WORD[49].W (WORD32) port Do[5] of cell WORD[4].W (WORD32) port Do[5] of cell WORD[50].W (WORD32) port Do[5] of cell WORD[51].W (WORD32) port Do[5] of cell WORD[52].W (WORD32) port Do[5] of cell WORD[53].W (WORD32) port Do[5] of cell WORD[54].W (WORD32) port Do[5] of cell WORD[55].W (WORD32) port Do[5] of cell WORD[56].W (WORD32) port Do[5] of cell WORD[57].W (WORD32) port Do[5] of cell WORD[58].W (WORD32) port Do[5] of cell WORD[59].W (WORD32) port Do[5] of cell WORD[5].W (WORD32) port Do[5] of cell WORD[60].W (WORD32) port Do[5] of cell WORD[61].W (WORD32) port Do[5] of cell WORD[62].W (WORD32) port Do[5] of cell WORD[63].W (WORD32) port Do[5] of cell WORD[6].W (WORD32) port Do[5] of cell WORD[7].W (WORD32) port Do[5] of cell WORD[8].W (WORD32) port Do[5] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[4]:
port Z[0] of cell FLOATBUF[4] (sky130_fd_sc_hd__ebufn_4) port Do[4] of cell WORD[0].W (WORD32) port Do[4] of cell WORD[10].W (WORD32) port Do[4] of cell WORD[11].W (WORD32) port Do[4] of cell WORD[12].W (WORD32) port Do[4] of cell WORD[13].W (WORD32) port Do[4] of cell WORD[14].W (WORD32) port Do[4] of cell WORD[15].W (WORD32) port Do[4] of cell WORD[16].W (WORD32) port Do[4] of cell WORD[17].W (WORD32) port Do[4] of cell WORD[18].W (WORD32) port Do[4] of cell WORD[19].W (WORD32) port Do[4] of cell WORD[1].W (WORD32) port Do[4] of cell WORD[20].W (WORD32) port Do[4] of cell WORD[21].W (WORD32) port Do[4] of cell WORD[22].W (WORD32) port Do[4] of cell WORD[23].W (WORD32) port Do[4] of cell WORD[24].W (WORD32) port Do[4] of cell WORD[25].W (WORD32) port Do[4] of cell WORD[26].W (WORD32) port Do[4] of cell WORD[27].W (WORD32) port Do[4] of cell WORD[28].W (WORD32) port Do[4] of cell WORD[29].W (WORD32) port Do[4] of cell WORD[2].W (WORD32) port Do[4] of cell WORD[30].W (WORD32) port Do[4] of cell WORD[31].W (WORD32) port Do[4] of cell WORD[32].W (WORD32) port Do[4] of cell WORD[33].W (WORD32) port Do[4] of cell WORD[34].W (WORD32) port Do[4] of cell WORD[35].W (WORD32) port Do[4] of cell WORD[36].W (WORD32) port Do[4] of cell WORD[37].W (WORD32) port Do[4] of cell WORD[38].W (WORD32) port Do[4] of cell WORD[39].W (WORD32) port Do[4] of cell WORD[3].W (WORD32) port Do[4] of cell WORD[40].W (WORD32) port Do[4] of cell WORD[41].W (WORD32) port Do[4] of cell WORD[42].W (WORD32) port Do[4] of cell WORD[43].W (WORD32) port Do[4] of cell WORD[44].W (WORD32) port Do[4] of cell WORD[45].W (WORD32) port Do[4] of cell WORD[46].W (WORD32) port Do[4] of cell WORD[47].W (WORD32) port Do[4] of cell WORD[48].W (WORD32) port Do[4] of cell WORD[49].W (WORD32) port Do[4] of cell WORD[4].W (WORD32) port Do[4] of cell WORD[50].W (WORD32) port Do[4] of cell WORD[51].W (WORD32) port Do[4] of cell WORD[52].W (WORD32) port Do[4] of cell WORD[53].W (WORD32) port Do[4] of cell WORD[54].W (WORD32) port Do[4] of cell WORD[55].W (WORD32) port Do[4] of cell WORD[56].W (WORD32) port Do[4] of cell WORD[57].W (WORD32) port Do[4] of cell WORD[58].W (WORD32) port Do[4] of cell WORD[59].W (WORD32) port Do[4] of cell WORD[5].W (WORD32) port Do[4] of cell WORD[60].W (WORD32) port Do[4] of cell WORD[61].W (WORD32) port Do[4] of cell WORD[62].W (WORD32) port Do[4] of cell WORD[63].W (WORD32) port Do[4] of cell WORD[6].W (WORD32) port Do[4] of cell WORD[7].W (WORD32) port Do[4] of cell WORD[8].W (WORD32) port Do[4] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[3]:
port Z[0] of cell FLOATBUF[3] (sky130_fd_sc_hd__ebufn_4) port Do[3] of cell WORD[0].W (WORD32) port Do[3] of cell WORD[10].W (WORD32) port Do[3] of cell WORD[11].W (WORD32) port Do[3] of cell WORD[12].W (WORD32) port Do[3] of cell WORD[13].W (WORD32) port Do[3] of cell WORD[14].W (WORD32) port Do[3] of cell WORD[15].W (WORD32) port Do[3] of cell WORD[16].W (WORD32) port Do[3] of cell WORD[17].W (WORD32) port Do[3] of cell WORD[18].W (WORD32) port Do[3] of cell WORD[19].W (WORD32) port Do[3] of cell WORD[1].W (WORD32) port Do[3] of cell WORD[20].W (WORD32) port Do[3] of cell WORD[21].W (WORD32) port Do[3] of cell WORD[22].W (WORD32) port Do[3] of cell WORD[23].W (WORD32) port Do[3] of cell WORD[24].W (WORD32) port Do[3] of cell WORD[25].W (WORD32) port Do[3] of cell WORD[26].W (WORD32) port Do[3] of cell WORD[27].W (WORD32) port Do[3] of cell WORD[28].W (WORD32) port Do[3] of cell WORD[29].W (WORD32) port Do[3] of cell WORD[2].W (WORD32) port Do[3] of cell WORD[30].W (WORD32) port Do[3] of cell WORD[31].W (WORD32) port Do[3] of cell WORD[32].W (WORD32) port Do[3] of cell WORD[33].W (WORD32) port Do[3] of cell WORD[34].W (WORD32) port Do[3] of cell WORD[35].W (WORD32) port Do[3] of cell WORD[36].W (WORD32) port Do[3] of cell WORD[37].W (WORD32) port Do[3] of cell WORD[38].W (WORD32) port Do[3] of cell WORD[39].W (WORD32) port Do[3] of cell WORD[3].W (WORD32) port Do[3] of cell WORD[40].W (WORD32) port Do[3] of cell WORD[41].W (WORD32) port Do[3] of cell WORD[42].W (WORD32) port Do[3] of cell WORD[43].W (WORD32) port Do[3] of cell WORD[44].W (WORD32) port Do[3] of cell WORD[45].W (WORD32) port Do[3] of cell WORD[46].W (WORD32) port Do[3] of cell WORD[47].W (WORD32) port Do[3] of cell WORD[48].W (WORD32) port Do[3] of cell WORD[49].W (WORD32) port Do[3] of cell WORD[4].W (WORD32) port Do[3] of cell WORD[50].W (WORD32) port Do[3] of cell WORD[51].W (WORD32) port Do[3] of cell WORD[52].W (WORD32) port Do[3] of cell WORD[53].W (WORD32) port Do[3] of cell WORD[54].W (WORD32) port Do[3] of cell WORD[55].W (WORD32) port Do[3] of cell WORD[56].W (WORD32) port Do[3] of cell WORD[57].W (WORD32) port Do[3] of cell WORD[58].W (WORD32) port Do[3] of cell WORD[59].W (WORD32) port Do[3] of cell WORD[5].W (WORD32) port Do[3] of cell WORD[60].W (WORD32) port Do[3] of cell WORD[61].W (WORD32) port Do[3] of cell WORD[62].W (WORD32) port Do[3] of cell WORD[63].W (WORD32) port Do[3] of cell WORD[6].W (WORD32) port Do[3] of cell WORD[7].W (WORD32) port Do[3] of cell WORD[8].W (WORD32) port Do[3] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[31]:
port Z[0] of cell FLOATBUF[31] (sky130_fd_sc_hd__ebufn_4) port Do[31] of cell WORD[0].W (WORD32) port Do[31] of cell WORD[10].W (WORD32) port Do[31] of cell WORD[11].W (WORD32) port Do[31] of cell WORD[12].W (WORD32) port Do[31] of cell WORD[13].W (WORD32) port Do[31] of cell WORD[14].W (WORD32) port Do[31] of cell WORD[15].W (WORD32) port Do[31] of cell WORD[16].W (WORD32) port Do[31] of cell WORD[17].W (WORD32) port Do[31] of cell WORD[18].W (WORD32) port Do[31] of cell WORD[19].W (WORD32) port Do[31] of cell WORD[1].W (WORD32) port Do[31] of cell WORD[20].W (WORD32) port Do[31] of cell WORD[21].W (WORD32) port Do[31] of cell WORD[22].W (WORD32) port Do[31] of cell WORD[23].W (WORD32) port Do[31] of cell WORD[24].W (WORD32) port Do[31] of cell WORD[25].W (WORD32) port Do[31] of cell WORD[26].W (WORD32) port Do[31] of cell WORD[27].W (WORD32) port Do[31] of cell WORD[28].W (WORD32) port Do[31] of cell WORD[29].W (WORD32) port Do[31] of cell WORD[2].W (WORD32) port Do[31] of cell WORD[30].W (WORD32) port Do[31] of cell WORD[31].W (WORD32) port Do[31] of cell WORD[32].W (WORD32) port Do[31] of cell WORD[33].W (WORD32) port Do[31] of cell WORD[34].W (WORD32) port Do[31] of cell WORD[35].W (WORD32) port Do[31] of cell WORD[36].W (WORD32) port Do[31] of cell WORD[37].W (WORD32) port Do[31] of cell WORD[38].W (WORD32) port Do[31] of cell WORD[39].W (WORD32) port Do[31] of cell WORD[3].W (WORD32) port Do[31] of cell WORD[40].W (WORD32) port Do[31] of cell WORD[41].W (WORD32) port Do[31] of cell WORD[42].W (WORD32) port Do[31] of cell WORD[43].W (WORD32) port Do[31] of cell WORD[44].W (WORD32) port Do[31] of cell WORD[45].W (WORD32) port Do[31] of cell WORD[46].W (WORD32) port Do[31] of cell WORD[47].W (WORD32) port Do[31] of cell WORD[48].W (WORD32) port Do[31] of cell WORD[49].W (WORD32) port Do[31] of cell WORD[4].W (WORD32) port Do[31] of cell WORD[50].W (WORD32) port Do[31] of cell WORD[51].W (WORD32) port Do[31] of cell WORD[52].W (WORD32) port Do[31] of cell WORD[53].W (WORD32) port Do[31] of cell WORD[54].W (WORD32) port Do[31] of cell WORD[55].W (WORD32) port Do[31] of cell WORD[56].W (WORD32) port Do[31] of cell WORD[57].W (WORD32) port Do[31] of cell WORD[58].W (WORD32) port Do[31] of cell WORD[59].W (WORD32) port Do[31] of cell WORD[5].W (WORD32) port Do[31] of cell WORD[60].W (WORD32) port Do[31] of cell WORD[61].W (WORD32) port Do[31] of cell WORD[62].W (WORD32) port Do[31] of cell WORD[63].W (WORD32) port Do[31] of cell WORD[6].W (WORD32) port Do[31] of cell WORD[7].W (WORD32) port Do[31] of cell WORD[8].W (WORD32) port Do[31] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[30]:
port Z[0] of cell FLOATBUF[30] (sky130_fd_sc_hd__ebufn_4) port Do[30] of cell WORD[0].W (WORD32) port Do[30] of cell WORD[10].W (WORD32) port Do[30] of cell WORD[11].W (WORD32) port Do[30] of cell WORD[12].W (WORD32) port Do[30] of cell WORD[13].W (WORD32) port Do[30] of cell WORD[14].W (WORD32) port Do[30] of cell WORD[15].W (WORD32) port Do[30] of cell WORD[16].W (WORD32) port Do[30] of cell WORD[17].W (WORD32) port Do[30] of cell WORD[18].W (WORD32) port Do[30] of cell WORD[19].W (WORD32) port Do[30] of cell WORD[1].W (WORD32) port Do[30] of cell WORD[20].W (WORD32) port Do[30] of cell WORD[21].W (WORD32) port Do[30] of cell WORD[22].W (WORD32) port Do[30] of cell WORD[23].W (WORD32) port Do[30] of cell WORD[24].W (WORD32) port Do[30] of cell WORD[25].W (WORD32) port Do[30] of cell WORD[26].W (WORD32) port Do[30] of cell WORD[27].W (WORD32) port Do[30] of cell WORD[28].W (WORD32) port Do[30] of cell WORD[29].W (WORD32) port Do[30] of cell WORD[2].W (WORD32) port Do[30] of cell WORD[30].W (WORD32) port Do[30] of cell WORD[31].W (WORD32) port Do[30] of cell WORD[32].W (WORD32) port Do[30] of cell WORD[33].W (WORD32) port Do[30] of cell WORD[34].W (WORD32) port Do[30] of cell WORD[35].W (WORD32) port Do[30] of cell WORD[36].W (WORD32) port Do[30] of cell WORD[37].W (WORD32) port Do[30] of cell WORD[38].W (WORD32) port Do[30] of cell WORD[39].W (WORD32) port Do[30] of cell WORD[3].W (WORD32) port Do[30] of cell WORD[40].W (WORD32) port Do[30] of cell WORD[41].W (WORD32) port Do[30] of cell WORD[42].W (WORD32) port Do[30] of cell WORD[43].W (WORD32) port Do[30] of cell WORD[44].W (WORD32) port Do[30] of cell WORD[45].W (WORD32) port Do[30] of cell WORD[46].W (WORD32) port Do[30] of cell WORD[47].W (WORD32) port Do[30] of cell WORD[48].W (WORD32) port Do[30] of cell WORD[49].W (WORD32) port Do[30] of cell WORD[4].W (WORD32) port Do[30] of cell WORD[50].W (WORD32) port Do[30] of cell WORD[51].W (WORD32) port Do[30] of cell WORD[52].W (WORD32) port Do[30] of cell WORD[53].W (WORD32) port Do[30] of cell WORD[54].W (WORD32) port Do[30] of cell WORD[55].W (WORD32) port Do[30] of cell WORD[56].W (WORD32) port Do[30] of cell WORD[57].W (WORD32) port Do[30] of cell WORD[58].W (WORD32) port Do[30] of cell WORD[59].W (WORD32) port Do[30] of cell WORD[5].W (WORD32) port Do[30] of cell WORD[60].W (WORD32) port Do[30] of cell WORD[61].W (WORD32) port Do[30] of cell WORD[62].W (WORD32) port Do[30] of cell WORD[63].W (WORD32) port Do[30] of cell WORD[6].W (WORD32) port Do[30] of cell WORD[7].W (WORD32) port Do[30] of cell WORD[8].W (WORD32) port Do[30] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[2]:
port Z[0] of cell FLOATBUF[2] (sky130_fd_sc_hd__ebufn_4) port Do[2] of cell WORD[0].W (WORD32) port Do[2] of cell WORD[10].W (WORD32) port Do[2] of cell WORD[11].W (WORD32) port Do[2] of cell WORD[12].W (WORD32) port Do[2] of cell WORD[13].W (WORD32) port Do[2] of cell WORD[14].W (WORD32) port Do[2] of cell WORD[15].W (WORD32) port Do[2] of cell WORD[16].W (WORD32) port Do[2] of cell WORD[17].W (WORD32) port Do[2] of cell WORD[18].W (WORD32) port Do[2] of cell WORD[19].W (WORD32) port Do[2] of cell WORD[1].W (WORD32) port Do[2] of cell WORD[20].W (WORD32) port Do[2] of cell WORD[21].W (WORD32) port Do[2] of cell WORD[22].W (WORD32) port Do[2] of cell WORD[23].W (WORD32) port Do[2] of cell WORD[24].W (WORD32) port Do[2] of cell WORD[25].W (WORD32) port Do[2] of cell WORD[26].W (WORD32) port Do[2] of cell WORD[27].W (WORD32) port Do[2] of cell WORD[28].W (WORD32) port Do[2] of cell WORD[29].W (WORD32) port Do[2] of cell WORD[2].W (WORD32) port Do[2] of cell WORD[30].W (WORD32) port Do[2] of cell WORD[31].W (WORD32) port Do[2] of cell WORD[32].W (WORD32) port Do[2] of cell WORD[33].W (WORD32) port Do[2] of cell WORD[34].W (WORD32) port Do[2] of cell WORD[35].W (WORD32) port Do[2] of cell WORD[36].W (WORD32) port Do[2] of cell WORD[37].W (WORD32) port Do[2] of cell WORD[38].W (WORD32) port Do[2] of cell WORD[39].W (WORD32) port Do[2] of cell WORD[3].W (WORD32) port Do[2] of cell WORD[40].W (WORD32) port Do[2] of cell WORD[41].W (WORD32) port Do[2] of cell WORD[42].W (WORD32) port Do[2] of cell WORD[43].W (WORD32) port Do[2] of cell WORD[44].W (WORD32) port Do[2] of cell WORD[45].W (WORD32) port Do[2] of cell WORD[46].W (WORD32) port Do[2] of cell WORD[47].W (WORD32) port Do[2] of cell WORD[48].W (WORD32) port Do[2] of cell WORD[49].W (WORD32) port Do[2] of cell WORD[4].W (WORD32) port Do[2] of cell WORD[50].W (WORD32) port Do[2] of cell WORD[51].W (WORD32) port Do[2] of cell WORD[52].W (WORD32) port Do[2] of cell WORD[53].W (WORD32) port Do[2] of cell WORD[54].W (WORD32) port Do[2] of cell WORD[55].W (WORD32) port Do[2] of cell WORD[56].W (WORD32) port Do[2] of cell WORD[57].W (WORD32) port Do[2] of cell WORD[58].W (WORD32) port Do[2] of cell WORD[59].W (WORD32) port Do[2] of cell WORD[5].W (WORD32) port Do[2] of cell WORD[60].W (WORD32) port Do[2] of cell WORD[61].W (WORD32) port Do[2] of cell WORD[62].W (WORD32) port Do[2] of cell WORD[63].W (WORD32) port Do[2] of cell WORD[6].W (WORD32) port Do[2] of cell WORD[7].W (WORD32) port Do[2] of cell WORD[8].W (WORD32) port Do[2] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[29]:
port Z[0] of cell FLOATBUF[29] (sky130_fd_sc_hd__ebufn_4) port Do[29] of cell WORD[0].W (WORD32) port Do[29] of cell WORD[10].W (WORD32) port Do[29] of cell WORD[11].W (WORD32) port Do[29] of cell WORD[12].W (WORD32) port Do[29] of cell WORD[13].W (WORD32) port Do[29] of cell WORD[14].W (WORD32) port Do[29] of cell WORD[15].W (WORD32) port Do[29] of cell WORD[16].W (WORD32) port Do[29] of cell WORD[17].W (WORD32) port Do[29] of cell WORD[18].W (WORD32) port Do[29] of cell WORD[19].W (WORD32) port Do[29] of cell WORD[1].W (WORD32) port Do[29] of cell WORD[20].W (WORD32) port Do[29] of cell WORD[21].W (WORD32) port Do[29] of cell WORD[22].W (WORD32) port Do[29] of cell WORD[23].W (WORD32) port Do[29] of cell WORD[24].W (WORD32) port Do[29] of cell WORD[25].W (WORD32) port Do[29] of cell WORD[26].W (WORD32) port Do[29] of cell WORD[27].W (WORD32) port Do[29] of cell WORD[28].W (WORD32) port Do[29] of cell WORD[29].W (WORD32) port Do[29] of cell WORD[2].W (WORD32) port Do[29] of cell WORD[30].W (WORD32) port Do[29] of cell WORD[31].W (WORD32) port Do[29] of cell WORD[32].W (WORD32) port Do[29] of cell WORD[33].W (WORD32) port Do[29] of cell WORD[34].W (WORD32) port Do[29] of cell WORD[35].W (WORD32) port Do[29] of cell WORD[36].W (WORD32) port Do[29] of cell WORD[37].W (WORD32) port Do[29] of cell WORD[38].W (WORD32) port Do[29] of cell WORD[39].W (WORD32) port Do[29] of cell WORD[3].W (WORD32) port Do[29] of cell WORD[40].W (WORD32) port Do[29] of cell WORD[41].W (WORD32) port Do[29] of cell WORD[42].W (WORD32) port Do[29] of cell WORD[43].W (WORD32) port Do[29] of cell WORD[44].W (WORD32) port Do[29] of cell WORD[45].W (WORD32) port Do[29] of cell WORD[46].W (WORD32) port Do[29] of cell WORD[47].W (WORD32) port Do[29] of cell WORD[48].W (WORD32) port Do[29] of cell WORD[49].W (WORD32) port Do[29] of cell WORD[4].W (WORD32) port Do[29] of cell WORD[50].W (WORD32) port Do[29] of cell WORD[51].W (WORD32) port Do[29] of cell WORD[52].W (WORD32) port Do[29] of cell WORD[53].W (WORD32) port Do[29] of cell WORD[54].W (WORD32) port Do[29] of cell WORD[55].W (WORD32) port Do[29] of cell WORD[56].W (WORD32) port Do[29] of cell WORD[57].W (WORD32) port Do[29] of cell WORD[58].W (WORD32) port Do[29] of cell WORD[59].W (WORD32) port Do[29] of cell WORD[5].W (WORD32) port Do[29] of cell WORD[60].W (WORD32) port Do[29] of cell WORD[61].W (WORD32) port Do[29] of cell WORD[62].W (WORD32) port Do[29] of cell WORD[63].W (WORD32) port Do[29] of cell WORD[6].W (WORD32) port Do[29] of cell WORD[7].W (WORD32) port Do[29] of cell WORD[8].W (WORD32) port Do[29] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[28]:
port Z[0] of cell FLOATBUF[28] (sky130_fd_sc_hd__ebufn_4) port Do[28] of cell WORD[0].W (WORD32) port Do[28] of cell WORD[10].W (WORD32) port Do[28] of cell WORD[11].W (WORD32) port Do[28] of cell WORD[12].W (WORD32) port Do[28] of cell WORD[13].W (WORD32) port Do[28] of cell WORD[14].W (WORD32) port Do[28] of cell WORD[15].W (WORD32) port Do[28] of cell WORD[16].W (WORD32) port Do[28] of cell WORD[17].W (WORD32) port Do[28] of cell WORD[18].W (WORD32) port Do[28] of cell WORD[19].W (WORD32) port Do[28] of cell WORD[1].W (WORD32) port Do[28] of cell WORD[20].W (WORD32) port Do[28] of cell WORD[21].W (WORD32) port Do[28] of cell WORD[22].W (WORD32) port Do[28] of cell WORD[23].W (WORD32) port Do[28] of cell WORD[24].W (WORD32) port Do[28] of cell WORD[25].W (WORD32) port Do[28] of cell WORD[26].W (WORD32) port Do[28] of cell WORD[27].W (WORD32) port Do[28] of cell WORD[28].W (WORD32) port Do[28] of cell WORD[29].W (WORD32) port Do[28] of cell WORD[2].W (WORD32) port Do[28] of cell WORD[30].W (WORD32) port Do[28] of cell WORD[31].W (WORD32) port Do[28] of cell WORD[32].W (WORD32) port Do[28] of cell WORD[33].W (WORD32) port Do[28] of cell WORD[34].W (WORD32) port Do[28] of cell WORD[35].W (WORD32) port Do[28] of cell WORD[36].W (WORD32) port Do[28] of cell WORD[37].W (WORD32) port Do[28] of cell WORD[38].W (WORD32) port Do[28] of cell WORD[39].W (WORD32) port Do[28] of cell WORD[3].W (WORD32) port Do[28] of cell WORD[40].W (WORD32) port Do[28] of cell WORD[41].W (WORD32) port Do[28] of cell WORD[42].W (WORD32) port Do[28] of cell WORD[43].W (WORD32) port Do[28] of cell WORD[44].W (WORD32) port Do[28] of cell WORD[45].W (WORD32) port Do[28] of cell WORD[46].W (WORD32) port Do[28] of cell WORD[47].W (WORD32) port Do[28] of cell WORD[48].W (WORD32) port Do[28] of cell WORD[49].W (WORD32) port Do[28] of cell WORD[4].W (WORD32) port Do[28] of cell WORD[50].W (WORD32) port Do[28] of cell WORD[51].W (WORD32) port Do[28] of cell WORD[52].W (WORD32) port Do[28] of cell WORD[53].W (WORD32) port Do[28] of cell WORD[54].W (WORD32) port Do[28] of cell WORD[55].W (WORD32) port Do[28] of cell WORD[56].W (WORD32) port Do[28] of cell WORD[57].W (WORD32) port Do[28] of cell WORD[58].W (WORD32) port Do[28] of cell WORD[59].W (WORD32) port Do[28] of cell WORD[5].W (WORD32) port Do[28] of cell WORD[60].W (WORD32) port Do[28] of cell WORD[61].W (WORD32) port Do[28] of cell WORD[62].W (WORD32) port Do[28] of cell WORD[63].W (WORD32) port Do[28] of cell WORD[6].W (WORD32) port Do[28] of cell WORD[7].W (WORD32) port Do[28] of cell WORD[8].W (WORD32) port Do[28] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[27]:
port Z[0] of cell FLOATBUF[27] (sky130_fd_sc_hd__ebufn_4) port Do[27] of cell WORD[0].W (WORD32) port Do[27] of cell WORD[10].W (WORD32) port Do[27] of cell WORD[11].W (WORD32) port Do[27] of cell WORD[12].W (WORD32) port Do[27] of cell WORD[13].W (WORD32) port Do[27] of cell WORD[14].W (WORD32) port Do[27] of cell WORD[15].W (WORD32) port Do[27] of cell WORD[16].W (WORD32) port Do[27] of cell WORD[17].W (WORD32) port Do[27] of cell WORD[18].W (WORD32) port Do[27] of cell WORD[19].W (WORD32) port Do[27] of cell WORD[1].W (WORD32) port Do[27] of cell WORD[20].W (WORD32) port Do[27] of cell WORD[21].W (WORD32) port Do[27] of cell WORD[22].W (WORD32) port Do[27] of cell WORD[23].W (WORD32) port Do[27] of cell WORD[24].W (WORD32) port Do[27] of cell WORD[25].W (WORD32) port Do[27] of cell WORD[26].W (WORD32) port Do[27] of cell WORD[27].W (WORD32) port Do[27] of cell WORD[28].W (WORD32) port Do[27] of cell WORD[29].W (WORD32) port Do[27] of cell WORD[2].W (WORD32) port Do[27] of cell WORD[30].W (WORD32) port Do[27] of cell WORD[31].W (WORD32) port Do[27] of cell WORD[32].W (WORD32) port Do[27] of cell WORD[33].W (WORD32) port Do[27] of cell WORD[34].W (WORD32) port Do[27] of cell WORD[35].W (WORD32) port Do[27] of cell WORD[36].W (WORD32) port Do[27] of cell WORD[37].W (WORD32) port Do[27] of cell WORD[38].W (WORD32) port Do[27] of cell WORD[39].W (WORD32) port Do[27] of cell WORD[3].W (WORD32) port Do[27] of cell WORD[40].W (WORD32) port Do[27] of cell WORD[41].W (WORD32) port Do[27] of cell WORD[42].W (WORD32) port Do[27] of cell WORD[43].W (WORD32) port Do[27] of cell WORD[44].W (WORD32) port Do[27] of cell WORD[45].W (WORD32) port Do[27] of cell WORD[46].W (WORD32) port Do[27] of cell WORD[47].W (WORD32) port Do[27] of cell WORD[48].W (WORD32) port Do[27] of cell WORD[49].W (WORD32) port Do[27] of cell WORD[4].W (WORD32) port Do[27] of cell WORD[50].W (WORD32) port Do[27] of cell WORD[51].W (WORD32) port Do[27] of cell WORD[52].W (WORD32) port Do[27] of cell WORD[53].W (WORD32) port Do[27] of cell WORD[54].W (WORD32) port Do[27] of cell WORD[55].W (WORD32) port Do[27] of cell WORD[56].W (WORD32) port Do[27] of cell WORD[57].W (WORD32) port Do[27] of cell WORD[58].W (WORD32) port Do[27] of cell WORD[59].W (WORD32) port Do[27] of cell WORD[5].W (WORD32) port Do[27] of cell WORD[60].W (WORD32) port Do[27] of cell WORD[61].W (WORD32) port Do[27] of cell WORD[62].W (WORD32) port Do[27] of cell WORD[63].W (WORD32) port Do[27] of cell WORD[6].W (WORD32) port Do[27] of cell WORD[7].W (WORD32) port Do[27] of cell WORD[8].W (WORD32) port Do[27] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[26]:
port Z[0] of cell FLOATBUF[26] (sky130_fd_sc_hd__ebufn_4) port Do[26] of cell WORD[0].W (WORD32) port Do[26] of cell WORD[10].W (WORD32) port Do[26] of cell WORD[11].W (WORD32) port Do[26] of cell WORD[12].W (WORD32) port Do[26] of cell WORD[13].W (WORD32) port Do[26] of cell WORD[14].W (WORD32) port Do[26] of cell WORD[15].W (WORD32) port Do[26] of cell WORD[16].W (WORD32) port Do[26] of cell WORD[17].W (WORD32) port Do[26] of cell WORD[18].W (WORD32) port Do[26] of cell WORD[19].W (WORD32) port Do[26] of cell WORD[1].W (WORD32) port Do[26] of cell WORD[20].W (WORD32) port Do[26] of cell WORD[21].W (WORD32) port Do[26] of cell WORD[22].W (WORD32) port Do[26] of cell WORD[23].W (WORD32) port Do[26] of cell WORD[24].W (WORD32) port Do[26] of cell WORD[25].W (WORD32) port Do[26] of cell WORD[26].W (WORD32) port Do[26] of cell WORD[27].W (WORD32) port Do[26] of cell WORD[28].W (WORD32) port Do[26] of cell WORD[29].W (WORD32) port Do[26] of cell WORD[2].W (WORD32) port Do[26] of cell WORD[30].W (WORD32) port Do[26] of cell WORD[31].W (WORD32) port Do[26] of cell WORD[32].W (WORD32) port Do[26] of cell WORD[33].W (WORD32) port Do[26] of cell WORD[34].W (WORD32) port Do[26] of cell WORD[35].W (WORD32) port Do[26] of cell WORD[36].W (WORD32) port Do[26] of cell WORD[37].W (WORD32) port Do[26] of cell WORD[38].W (WORD32) port Do[26] of cell WORD[39].W (WORD32) port Do[26] of cell WORD[3].W (WORD32) port Do[26] of cell WORD[40].W (WORD32) port Do[26] of cell WORD[41].W (WORD32) port Do[26] of cell WORD[42].W (WORD32) port Do[26] of cell WORD[43].W (WORD32) port Do[26] of cell WORD[44].W (WORD32) port Do[26] of cell WORD[45].W (WORD32) port Do[26] of cell WORD[46].W (WORD32) port Do[26] of cell WORD[47].W (WORD32) port Do[26] of cell WORD[48].W (WORD32) port Do[26] of cell WORD[49].W (WORD32) port Do[26] of cell WORD[4].W (WORD32) port Do[26] of cell WORD[50].W (WORD32) port Do[26] of cell WORD[51].W (WORD32) port Do[26] of cell WORD[52].W (WORD32) port Do[26] of cell WORD[53].W (WORD32) port Do[26] of cell WORD[54].W (WORD32) port Do[26] of cell WORD[55].W (WORD32) port Do[26] of cell WORD[56].W (WORD32) port Do[26] of cell WORD[57].W (WORD32) port Do[26] of cell WORD[58].W (WORD32) port Do[26] of cell WORD[59].W (WORD32) port Do[26] of cell WORD[5].W (WORD32) port Do[26] of cell WORD[60].W (WORD32) port Do[26] of cell WORD[61].W (WORD32) port Do[26] of cell WORD[62].W (WORD32) port Do[26] of cell WORD[63].W (WORD32) port Do[26] of cell WORD[6].W (WORD32) port Do[26] of cell WORD[7].W (WORD32) port Do[26] of cell WORD[8].W (WORD32) port Do[26] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[25]:
port Z[0] of cell FLOATBUF[25] (sky130_fd_sc_hd__ebufn_4) port Do[25] of cell WORD[0].W (WORD32) port Do[25] of cell WORD[10].W (WORD32) port Do[25] of cell WORD[11].W (WORD32) port Do[25] of cell WORD[12].W (WORD32) port Do[25] of cell WORD[13].W (WORD32) port Do[25] of cell WORD[14].W (WORD32) port Do[25] of cell WORD[15].W (WORD32) port Do[25] of cell WORD[16].W (WORD32) port Do[25] of cell WORD[17].W (WORD32) port Do[25] of cell WORD[18].W (WORD32) port Do[25] of cell WORD[19].W (WORD32) port Do[25] of cell WORD[1].W (WORD32) port Do[25] of cell WORD[20].W (WORD32) port Do[25] of cell WORD[21].W (WORD32) port Do[25] of cell WORD[22].W (WORD32) port Do[25] of cell WORD[23].W (WORD32) port Do[25] of cell WORD[24].W (WORD32) port Do[25] of cell WORD[25].W (WORD32) port Do[25] of cell WORD[26].W (WORD32) port Do[25] of cell WORD[27].W (WORD32) port Do[25] of cell WORD[28].W (WORD32) port Do[25] of cell WORD[29].W (WORD32) port Do[25] of cell WORD[2].W (WORD32) port Do[25] of cell WORD[30].W (WORD32) port Do[25] of cell WORD[31].W (WORD32) port Do[25] of cell WORD[32].W (WORD32) port Do[25] of cell WORD[33].W (WORD32) port Do[25] of cell WORD[34].W (WORD32) port Do[25] of cell WORD[35].W (WORD32) port Do[25] of cell WORD[36].W (WORD32) port Do[25] of cell WORD[37].W (WORD32) port Do[25] of cell WORD[38].W (WORD32) port Do[25] of cell WORD[39].W (WORD32) port Do[25] of cell WORD[3].W (WORD32) port Do[25] of cell WORD[40].W (WORD32) port Do[25] of cell WORD[41].W (WORD32) port Do[25] of cell WORD[42].W (WORD32) port Do[25] of cell WORD[43].W (WORD32) port Do[25] of cell WORD[44].W (WORD32) port Do[25] of cell WORD[45].W (WORD32) port Do[25] of cell WORD[46].W (WORD32) port Do[25] of cell WORD[47].W (WORD32) port Do[25] of cell WORD[48].W (WORD32) port Do[25] of cell WORD[49].W (WORD32) port Do[25] of cell WORD[4].W (WORD32) port Do[25] of cell WORD[50].W (WORD32) port Do[25] of cell WORD[51].W (WORD32) port Do[25] of cell WORD[52].W (WORD32) port Do[25] of cell WORD[53].W (WORD32) port Do[25] of cell WORD[54].W (WORD32) port Do[25] of cell WORD[55].W (WORD32) port Do[25] of cell WORD[56].W (WORD32) port Do[25] of cell WORD[57].W (WORD32) port Do[25] of cell WORD[58].W (WORD32) port Do[25] of cell WORD[59].W (WORD32) port Do[25] of cell WORD[5].W (WORD32) port Do[25] of cell WORD[60].W (WORD32) port Do[25] of cell WORD[61].W (WORD32) port Do[25] of cell WORD[62].W (WORD32) port Do[25] of cell WORD[63].W (WORD32) port Do[25] of cell WORD[6].W (WORD32) port Do[25] of cell WORD[7].W (WORD32) port Do[25] of cell WORD[8].W (WORD32) port Do[25] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[24]:
port Z[0] of cell FLOATBUF[24] (sky130_fd_sc_hd__ebufn_4) port Do[24] of cell WORD[0].W (WORD32) port Do[24] of cell WORD[10].W (WORD32) port Do[24] of cell WORD[11].W (WORD32) port Do[24] of cell WORD[12].W (WORD32) port Do[24] of cell WORD[13].W (WORD32) port Do[24] of cell WORD[14].W (WORD32) port Do[24] of cell WORD[15].W (WORD32) port Do[24] of cell WORD[16].W (WORD32) port Do[24] of cell WORD[17].W (WORD32) port Do[24] of cell WORD[18].W (WORD32) port Do[24] of cell WORD[19].W (WORD32) port Do[24] of cell WORD[1].W (WORD32) port Do[24] of cell WORD[20].W (WORD32) port Do[24] of cell WORD[21].W (WORD32) port Do[24] of cell WORD[22].W (WORD32) port Do[24] of cell WORD[23].W (WORD32) port Do[24] of cell WORD[24].W (WORD32) port Do[24] of cell WORD[25].W (WORD32) port Do[24] of cell WORD[26].W (WORD32) port Do[24] of cell WORD[27].W (WORD32) port Do[24] of cell WORD[28].W (WORD32) port Do[24] of cell WORD[29].W (WORD32) port Do[24] of cell WORD[2].W (WORD32) port Do[24] of cell WORD[30].W (WORD32) port Do[24] of cell WORD[31].W (WORD32) port Do[24] of cell WORD[32].W (WORD32) port Do[24] of cell WORD[33].W (WORD32) port Do[24] of cell WORD[34].W (WORD32) port Do[24] of cell WORD[35].W (WORD32) port Do[24] of cell WORD[36].W (WORD32) port Do[24] of cell WORD[37].W (WORD32) port Do[24] of cell WORD[38].W (WORD32) port Do[24] of cell WORD[39].W (WORD32) port Do[24] of cell WORD[3].W (WORD32) port Do[24] of cell WORD[40].W (WORD32) port Do[24] of cell WORD[41].W (WORD32) port Do[24] of cell WORD[42].W (WORD32) port Do[24] of cell WORD[43].W (WORD32) port Do[24] of cell WORD[44].W (WORD32) port Do[24] of cell WORD[45].W (WORD32) port Do[24] of cell WORD[46].W (WORD32) port Do[24] of cell WORD[47].W (WORD32) port Do[24] of cell WORD[48].W (WORD32) port Do[24] of cell WORD[49].W (WORD32) port Do[24] of cell WORD[4].W (WORD32) port Do[24] of cell WORD[50].W (WORD32) port Do[24] of cell WORD[51].W (WORD32) port Do[24] of cell WORD[52].W (WORD32) port Do[24] of cell WORD[53].W (WORD32) port Do[24] of cell WORD[54].W (WORD32) port Do[24] of cell WORD[55].W (WORD32) port Do[24] of cell WORD[56].W (WORD32) port Do[24] of cell WORD[57].W (WORD32) port Do[24] of cell WORD[58].W (WORD32) port Do[24] of cell WORD[59].W (WORD32) port Do[24] of cell WORD[5].W (WORD32) port Do[24] of cell WORD[60].W (WORD32) port Do[24] of cell WORD[61].W (WORD32) port Do[24] of cell WORD[62].W (WORD32) port Do[24] of cell WORD[63].W (WORD32) port Do[24] of cell WORD[6].W (WORD32) port Do[24] of cell WORD[7].W (WORD32) port Do[24] of cell WORD[8].W (WORD32) port Do[24] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[23]:
port Z[0] of cell FLOATBUF[23] (sky130_fd_sc_hd__ebufn_4) port Do[23] of cell WORD[0].W (WORD32) port Do[23] of cell WORD[10].W (WORD32) port Do[23] of cell WORD[11].W (WORD32) port Do[23] of cell WORD[12].W (WORD32) port Do[23] of cell WORD[13].W (WORD32) port Do[23] of cell WORD[14].W (WORD32) port Do[23] of cell WORD[15].W (WORD32) port Do[23] of cell WORD[16].W (WORD32) port Do[23] of cell WORD[17].W (WORD32) port Do[23] of cell WORD[18].W (WORD32) port Do[23] of cell WORD[19].W (WORD32) port Do[23] of cell WORD[1].W (WORD32) port Do[23] of cell WORD[20].W (WORD32) port Do[23] of cell WORD[21].W (WORD32) port Do[23] of cell WORD[22].W (WORD32) port Do[23] of cell WORD[23].W (WORD32) port Do[23] of cell WORD[24].W (WORD32) port Do[23] of cell WORD[25].W (WORD32) port Do[23] of cell WORD[26].W (WORD32) port Do[23] of cell WORD[27].W (WORD32) port Do[23] of cell WORD[28].W (WORD32) port Do[23] of cell WORD[29].W (WORD32) port Do[23] of cell WORD[2].W (WORD32) port Do[23] of cell WORD[30].W (WORD32) port Do[23] of cell WORD[31].W (WORD32) port Do[23] of cell WORD[32].W (WORD32) port Do[23] of cell WORD[33].W (WORD32) port Do[23] of cell WORD[34].W (WORD32) port Do[23] of cell WORD[35].W (WORD32) port Do[23] of cell WORD[36].W (WORD32) port Do[23] of cell WORD[37].W (WORD32) port Do[23] of cell WORD[38].W (WORD32) port Do[23] of cell WORD[39].W (WORD32) port Do[23] of cell WORD[3].W (WORD32) port Do[23] of cell WORD[40].W (WORD32) port Do[23] of cell WORD[41].W (WORD32) port Do[23] of cell WORD[42].W (WORD32) port Do[23] of cell WORD[43].W (WORD32) port Do[23] of cell WORD[44].W (WORD32) port Do[23] of cell WORD[45].W (WORD32) port Do[23] of cell WORD[46].W (WORD32) port Do[23] of cell WORD[47].W (WORD32) port Do[23] of cell WORD[48].W (WORD32) port Do[23] of cell WORD[49].W (WORD32) port Do[23] of cell WORD[4].W (WORD32) port Do[23] of cell WORD[50].W (WORD32) port Do[23] of cell WORD[51].W (WORD32) port Do[23] of cell WORD[52].W (WORD32) port Do[23] of cell WORD[53].W (WORD32) port Do[23] of cell WORD[54].W (WORD32) port Do[23] of cell WORD[55].W (WORD32) port Do[23] of cell WORD[56].W (WORD32) port Do[23] of cell WORD[57].W (WORD32) port Do[23] of cell WORD[58].W (WORD32) port Do[23] of cell WORD[59].W (WORD32) port Do[23] of cell WORD[5].W (WORD32) port Do[23] of cell WORD[60].W (WORD32) port Do[23] of cell WORD[61].W (WORD32) port Do[23] of cell WORD[62].W (WORD32) port Do[23] of cell WORD[63].W (WORD32) port Do[23] of cell WORD[6].W (WORD32) port Do[23] of cell WORD[7].W (WORD32) port Do[23] of cell WORD[8].W (WORD32) port Do[23] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[22]:
port Z[0] of cell FLOATBUF[22] (sky130_fd_sc_hd__ebufn_4) port Do[22] of cell WORD[0].W (WORD32) port Do[22] of cell WORD[10].W (WORD32) port Do[22] of cell WORD[11].W (WORD32) port Do[22] of cell WORD[12].W (WORD32) port Do[22] of cell WORD[13].W (WORD32) port Do[22] of cell WORD[14].W (WORD32) port Do[22] of cell WORD[15].W (WORD32) port Do[22] of cell WORD[16].W (WORD32) port Do[22] of cell WORD[17].W (WORD32) port Do[22] of cell WORD[18].W (WORD32) port Do[22] of cell WORD[19].W (WORD32) port Do[22] of cell WORD[1].W (WORD32) port Do[22] of cell WORD[20].W (WORD32) port Do[22] of cell WORD[21].W (WORD32) port Do[22] of cell WORD[22].W (WORD32) port Do[22] of cell WORD[23].W (WORD32) port Do[22] of cell WORD[24].W (WORD32) port Do[22] of cell WORD[25].W (WORD32) port Do[22] of cell WORD[26].W (WORD32) port Do[22] of cell WORD[27].W (WORD32) port Do[22] of cell WORD[28].W (WORD32) port Do[22] of cell WORD[29].W (WORD32) port Do[22] of cell WORD[2].W (WORD32) port Do[22] of cell WORD[30].W (WORD32) port Do[22] of cell WORD[31].W (WORD32) port Do[22] of cell WORD[32].W (WORD32) port Do[22] of cell WORD[33].W (WORD32) port Do[22] of cell WORD[34].W (WORD32) port Do[22] of cell WORD[35].W (WORD32) port Do[22] of cell WORD[36].W (WORD32) port Do[22] of cell WORD[37].W (WORD32) port Do[22] of cell WORD[38].W (WORD32) port Do[22] of cell WORD[39].W (WORD32) port Do[22] of cell WORD[3].W (WORD32) port Do[22] of cell WORD[40].W (WORD32) port Do[22] of cell WORD[41].W (WORD32) port Do[22] of cell WORD[42].W (WORD32) port Do[22] of cell WORD[43].W (WORD32) port Do[22] of cell WORD[44].W (WORD32) port Do[22] of cell WORD[45].W (WORD32) port Do[22] of cell WORD[46].W (WORD32) port Do[22] of cell WORD[47].W (WORD32) port Do[22] of cell WORD[48].W (WORD32) port Do[22] of cell WORD[49].W (WORD32) port Do[22] of cell WORD[4].W (WORD32) port Do[22] of cell WORD[50].W (WORD32) port Do[22] of cell WORD[51].W (WORD32) port Do[22] of cell WORD[52].W (WORD32) port Do[22] of cell WORD[53].W (WORD32) port Do[22] of cell WORD[54].W (WORD32) port Do[22] of cell WORD[55].W (WORD32) port Do[22] of cell WORD[56].W (WORD32) port Do[22] of cell WORD[57].W (WORD32) port Do[22] of cell WORD[58].W (WORD32) port Do[22] of cell WORD[59].W (WORD32) port Do[22] of cell WORD[5].W (WORD32) port Do[22] of cell WORD[60].W (WORD32) port Do[22] of cell WORD[61].W (WORD32) port Do[22] of cell WORD[62].W (WORD32) port Do[22] of cell WORD[63].W (WORD32) port Do[22] of cell WORD[6].W (WORD32) port Do[22] of cell WORD[7].W (WORD32) port Do[22] of cell WORD[8].W (WORD32) port Do[22] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[21]:
port Z[0] of cell FLOATBUF[21] (sky130_fd_sc_hd__ebufn_4) port Do[21] of cell WORD[0].W (WORD32) port Do[21] of cell WORD[10].W (WORD32) port Do[21] of cell WORD[11].W (WORD32) port Do[21] of cell WORD[12].W (WORD32) port Do[21] of cell WORD[13].W (WORD32) port Do[21] of cell WORD[14].W (WORD32) port Do[21] of cell WORD[15].W (WORD32) port Do[21] of cell WORD[16].W (WORD32) port Do[21] of cell WORD[17].W (WORD32) port Do[21] of cell WORD[18].W (WORD32) port Do[21] of cell WORD[19].W (WORD32) port Do[21] of cell WORD[1].W (WORD32) port Do[21] of cell WORD[20].W (WORD32) port Do[21] of cell WORD[21].W (WORD32) port Do[21] of cell WORD[22].W (WORD32) port Do[21] of cell WORD[23].W (WORD32) port Do[21] of cell WORD[24].W (WORD32) port Do[21] of cell WORD[25].W (WORD32) port Do[21] of cell WORD[26].W (WORD32) port Do[21] of cell WORD[27].W (WORD32) port Do[21] of cell WORD[28].W (WORD32) port Do[21] of cell WORD[29].W (WORD32) port Do[21] of cell WORD[2].W (WORD32) port Do[21] of cell WORD[30].W (WORD32) port Do[21] of cell WORD[31].W (WORD32) port Do[21] of cell WORD[32].W (WORD32) port Do[21] of cell WORD[33].W (WORD32) port Do[21] of cell WORD[34].W (WORD32) port Do[21] of cell WORD[35].W (WORD32) port Do[21] of cell WORD[36].W (WORD32) port Do[21] of cell WORD[37].W (WORD32) port Do[21] of cell WORD[38].W (WORD32) port Do[21] of cell WORD[39].W (WORD32) port Do[21] of cell WORD[3].W (WORD32) port Do[21] of cell WORD[40].W (WORD32) port Do[21] of cell WORD[41].W (WORD32) port Do[21] of cell WORD[42].W (WORD32) port Do[21] of cell WORD[43].W (WORD32) port Do[21] of cell WORD[44].W (WORD32) port Do[21] of cell WORD[45].W (WORD32) port Do[21] of cell WORD[46].W (WORD32) port Do[21] of cell WORD[47].W (WORD32) port Do[21] of cell WORD[48].W (WORD32) port Do[21] of cell WORD[49].W (WORD32) port Do[21] of cell WORD[4].W (WORD32) port Do[21] of cell WORD[50].W (WORD32) port Do[21] of cell WORD[51].W (WORD32) port Do[21] of cell WORD[52].W (WORD32) port Do[21] of cell WORD[53].W (WORD32) port Do[21] of cell WORD[54].W (WORD32) port Do[21] of cell WORD[55].W (WORD32) port Do[21] of cell WORD[56].W (WORD32) port Do[21] of cell WORD[57].W (WORD32) port Do[21] of cell WORD[58].W (WORD32) port Do[21] of cell WORD[59].W (WORD32) port Do[21] of cell WORD[5].W (WORD32) port Do[21] of cell WORD[60].W (WORD32) port Do[21] of cell WORD[61].W (WORD32) port Do[21] of cell WORD[62].W (WORD32) port Do[21] of cell WORD[63].W (WORD32) port Do[21] of cell WORD[6].W (WORD32) port Do[21] of cell WORD[7].W (WORD32) port Do[21] of cell WORD[8].W (WORD32) port Do[21] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[20]:
port Z[0] of cell FLOATBUF[20] (sky130_fd_sc_hd__ebufn_4) port Do[20] of cell WORD[0].W (WORD32) port Do[20] of cell WORD[10].W (WORD32) port Do[20] of cell WORD[11].W (WORD32) port Do[20] of cell WORD[12].W (WORD32) port Do[20] of cell WORD[13].W (WORD32) port Do[20] of cell WORD[14].W (WORD32) port Do[20] of cell WORD[15].W (WORD32) port Do[20] of cell WORD[16].W (WORD32) port Do[20] of cell WORD[17].W (WORD32) port Do[20] of cell WORD[18].W (WORD32) port Do[20] of cell WORD[19].W (WORD32) port Do[20] of cell WORD[1].W (WORD32) port Do[20] of cell WORD[20].W (WORD32) port Do[20] of cell WORD[21].W (WORD32) port Do[20] of cell WORD[22].W (WORD32) port Do[20] of cell WORD[23].W (WORD32) port Do[20] of cell WORD[24].W (WORD32) port Do[20] of cell WORD[25].W (WORD32) port Do[20] of cell WORD[26].W (WORD32) port Do[20] of cell WORD[27].W (WORD32) port Do[20] of cell WORD[28].W (WORD32) port Do[20] of cell WORD[29].W (WORD32) port Do[20] of cell WORD[2].W (WORD32) port Do[20] of cell WORD[30].W (WORD32) port Do[20] of cell WORD[31].W (WORD32) port Do[20] of cell WORD[32].W (WORD32) port Do[20] of cell WORD[33].W (WORD32) port Do[20] of cell WORD[34].W (WORD32) port Do[20] of cell WORD[35].W (WORD32) port Do[20] of cell WORD[36].W (WORD32) port Do[20] of cell WORD[37].W (WORD32) port Do[20] of cell WORD[38].W (WORD32) port Do[20] of cell WORD[39].W (WORD32) port Do[20] of cell WORD[3].W (WORD32) port Do[20] of cell WORD[40].W (WORD32) port Do[20] of cell WORD[41].W (WORD32) port Do[20] of cell WORD[42].W (WORD32) port Do[20] of cell WORD[43].W (WORD32) port Do[20] of cell WORD[44].W (WORD32) port Do[20] of cell WORD[45].W (WORD32) port Do[20] of cell WORD[46].W (WORD32) port Do[20] of cell WORD[47].W (WORD32) port Do[20] of cell WORD[48].W (WORD32) port Do[20] of cell WORD[49].W (WORD32) port Do[20] of cell WORD[4].W (WORD32) port Do[20] of cell WORD[50].W (WORD32) port Do[20] of cell WORD[51].W (WORD32) port Do[20] of cell WORD[52].W (WORD32) port Do[20] of cell WORD[53].W (WORD32) port Do[20] of cell WORD[54].W (WORD32) port Do[20] of cell WORD[55].W (WORD32) port Do[20] of cell WORD[56].W (WORD32) port Do[20] of cell WORD[57].W (WORD32) port Do[20] of cell WORD[58].W (WORD32) port Do[20] of cell WORD[59].W (WORD32) port Do[20] of cell WORD[5].W (WORD32) port Do[20] of cell WORD[60].W (WORD32) port Do[20] of cell WORD[61].W (WORD32) port Do[20] of cell WORD[62].W (WORD32) port Do[20] of cell WORD[63].W (WORD32) port Do[20] of cell WORD[6].W (WORD32) port Do[20] of cell WORD[7].W (WORD32) port Do[20] of cell WORD[8].W (WORD32) port Do[20] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[1]:
port Z[0] of cell FLOATBUF[1] (sky130_fd_sc_hd__ebufn_4) port Do[1] of cell WORD[0].W (WORD32) port Do[1] of cell WORD[10].W (WORD32) port Do[1] of cell WORD[11].W (WORD32) port Do[1] of cell WORD[12].W (WORD32) port Do[1] of cell WORD[13].W (WORD32) port Do[1] of cell WORD[14].W (WORD32) port Do[1] of cell WORD[15].W (WORD32) port Do[1] of cell WORD[16].W (WORD32) port Do[1] of cell WORD[17].W (WORD32) port Do[1] of cell WORD[18].W (WORD32) port Do[1] of cell WORD[19].W (WORD32) port Do[1] of cell WORD[1].W (WORD32) port Do[1] of cell WORD[20].W (WORD32) port Do[1] of cell WORD[21].W (WORD32) port Do[1] of cell WORD[22].W (WORD32) port Do[1] of cell WORD[23].W (WORD32) port Do[1] of cell WORD[24].W (WORD32) port Do[1] of cell WORD[25].W (WORD32) port Do[1] of cell WORD[26].W (WORD32) port Do[1] of cell WORD[27].W (WORD32) port Do[1] of cell WORD[28].W (WORD32) port Do[1] of cell WORD[29].W (WORD32) port Do[1] of cell WORD[2].W (WORD32) port Do[1] of cell WORD[30].W (WORD32) port Do[1] of cell WORD[31].W (WORD32) port Do[1] of cell WORD[32].W (WORD32) port Do[1] of cell WORD[33].W (WORD32) port Do[1] of cell WORD[34].W (WORD32) port Do[1] of cell WORD[35].W (WORD32) port Do[1] of cell WORD[36].W (WORD32) port Do[1] of cell WORD[37].W (WORD32) port Do[1] of cell WORD[38].W (WORD32) port Do[1] of cell WORD[39].W (WORD32) port Do[1] of cell WORD[3].W (WORD32) port Do[1] of cell WORD[40].W (WORD32) port Do[1] of cell WORD[41].W (WORD32) port Do[1] of cell WORD[42].W (WORD32) port Do[1] of cell WORD[43].W (WORD32) port Do[1] of cell WORD[44].W (WORD32) port Do[1] of cell WORD[45].W (WORD32) port Do[1] of cell WORD[46].W (WORD32) port Do[1] of cell WORD[47].W (WORD32) port Do[1] of cell WORD[48].W (WORD32) port Do[1] of cell WORD[49].W (WORD32) port Do[1] of cell WORD[4].W (WORD32) port Do[1] of cell WORD[50].W (WORD32) port Do[1] of cell WORD[51].W (WORD32) port Do[1] of cell WORD[52].W (WORD32) port Do[1] of cell WORD[53].W (WORD32) port Do[1] of cell WORD[54].W (WORD32) port Do[1] of cell WORD[55].W (WORD32) port Do[1] of cell WORD[56].W (WORD32) port Do[1] of cell WORD[57].W (WORD32) port Do[1] of cell WORD[58].W (WORD32) port Do[1] of cell WORD[59].W (WORD32) port Do[1] of cell WORD[5].W (WORD32) port Do[1] of cell WORD[60].W (WORD32) port Do[1] of cell WORD[61].W (WORD32) port Do[1] of cell WORD[62].W (WORD32) port Do[1] of cell WORD[63].W (WORD32) port Do[1] of cell WORD[6].W (WORD32) port Do[1] of cell WORD[7].W (WORD32) port Do[1] of cell WORD[8].W (WORD32) port Do[1] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[19]:
port Z[0] of cell FLOATBUF[19] (sky130_fd_sc_hd__ebufn_4) port Do[19] of cell WORD[0].W (WORD32) port Do[19] of cell WORD[10].W (WORD32) port Do[19] of cell WORD[11].W (WORD32) port Do[19] of cell WORD[12].W (WORD32) port Do[19] of cell WORD[13].W (WORD32) port Do[19] of cell WORD[14].W (WORD32) port Do[19] of cell WORD[15].W (WORD32) port Do[19] of cell WORD[16].W (WORD32) port Do[19] of cell WORD[17].W (WORD32) port Do[19] of cell WORD[18].W (WORD32) port Do[19] of cell WORD[19].W (WORD32) port Do[19] of cell WORD[1].W (WORD32) port Do[19] of cell WORD[20].W (WORD32) port Do[19] of cell WORD[21].W (WORD32) port Do[19] of cell WORD[22].W (WORD32) port Do[19] of cell WORD[23].W (WORD32) port Do[19] of cell WORD[24].W (WORD32) port Do[19] of cell WORD[25].W (WORD32) port Do[19] of cell WORD[26].W (WORD32) port Do[19] of cell WORD[27].W (WORD32) port Do[19] of cell WORD[28].W (WORD32) port Do[19] of cell WORD[29].W (WORD32) port Do[19] of cell WORD[2].W (WORD32) port Do[19] of cell WORD[30].W (WORD32) port Do[19] of cell WORD[31].W (WORD32) port Do[19] of cell WORD[32].W (WORD32) port Do[19] of cell WORD[33].W (WORD32) port Do[19] of cell WORD[34].W (WORD32) port Do[19] of cell WORD[35].W (WORD32) port Do[19] of cell WORD[36].W (WORD32) port Do[19] of cell WORD[37].W (WORD32) port Do[19] of cell WORD[38].W (WORD32) port Do[19] of cell WORD[39].W (WORD32) port Do[19] of cell WORD[3].W (WORD32) port Do[19] of cell WORD[40].W (WORD32) port Do[19] of cell WORD[41].W (WORD32) port Do[19] of cell WORD[42].W (WORD32) port Do[19] of cell WORD[43].W (WORD32) port Do[19] of cell WORD[44].W (WORD32) port Do[19] of cell WORD[45].W (WORD32) port Do[19] of cell WORD[46].W (WORD32) port Do[19] of cell WORD[47].W (WORD32) port Do[19] of cell WORD[48].W (WORD32) port Do[19] of cell WORD[49].W (WORD32) port Do[19] of cell WORD[4].W (WORD32) port Do[19] of cell WORD[50].W (WORD32) port Do[19] of cell WORD[51].W (WORD32) port Do[19] of cell WORD[52].W (WORD32) port Do[19] of cell WORD[53].W (WORD32) port Do[19] of cell WORD[54].W (WORD32) port Do[19] of cell WORD[55].W (WORD32) port Do[19] of cell WORD[56].W (WORD32) port Do[19] of cell WORD[57].W (WORD32) port Do[19] of cell WORD[58].W (WORD32) port Do[19] of cell WORD[59].W (WORD32) port Do[19] of cell WORD[5].W (WORD32) port Do[19] of cell WORD[60].W (WORD32) port Do[19] of cell WORD[61].W (WORD32) port Do[19] of cell WORD[62].W (WORD32) port Do[19] of cell WORD[63].W (WORD32) port Do[19] of cell WORD[6].W (WORD32) port Do[19] of cell WORD[7].W (WORD32) port Do[19] of cell WORD[8].W (WORD32) port Do[19] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[18]:
port Z[0] of cell FLOATBUF[18] (sky130_fd_sc_hd__ebufn_4) port Do[18] of cell WORD[0].W (WORD32) port Do[18] of cell WORD[10].W (WORD32) port Do[18] of cell WORD[11].W (WORD32) port Do[18] of cell WORD[12].W (WORD32) port Do[18] of cell WORD[13].W (WORD32) port Do[18] of cell WORD[14].W (WORD32) port Do[18] of cell WORD[15].W (WORD32) port Do[18] of cell WORD[16].W (WORD32) port Do[18] of cell WORD[17].W (WORD32) port Do[18] of cell WORD[18].W (WORD32) port Do[18] of cell WORD[19].W (WORD32) port Do[18] of cell WORD[1].W (WORD32) port Do[18] of cell WORD[20].W (WORD32) port Do[18] of cell WORD[21].W (WORD32) port Do[18] of cell WORD[22].W (WORD32) port Do[18] of cell WORD[23].W (WORD32) port Do[18] of cell WORD[24].W (WORD32) port Do[18] of cell WORD[25].W (WORD32) port Do[18] of cell WORD[26].W (WORD32) port Do[18] of cell WORD[27].W (WORD32) port Do[18] of cell WORD[28].W (WORD32) port Do[18] of cell WORD[29].W (WORD32) port Do[18] of cell WORD[2].W (WORD32) port Do[18] of cell WORD[30].W (WORD32) port Do[18] of cell WORD[31].W (WORD32) port Do[18] of cell WORD[32].W (WORD32) port Do[18] of cell WORD[33].W (WORD32) port Do[18] of cell WORD[34].W (WORD32) port Do[18] of cell WORD[35].W (WORD32) port Do[18] of cell WORD[36].W (WORD32) port Do[18] of cell WORD[37].W (WORD32) port Do[18] of cell WORD[38].W (WORD32) port Do[18] of cell WORD[39].W (WORD32) port Do[18] of cell WORD[3].W (WORD32) port Do[18] of cell WORD[40].W (WORD32) port Do[18] of cell WORD[41].W (WORD32) port Do[18] of cell WORD[42].W (WORD32) port Do[18] of cell WORD[43].W (WORD32) port Do[18] of cell WORD[44].W (WORD32) port Do[18] of cell WORD[45].W (WORD32) port Do[18] of cell WORD[46].W (WORD32) port Do[18] of cell WORD[47].W (WORD32) port Do[18] of cell WORD[48].W (WORD32) port Do[18] of cell WORD[49].W (WORD32) port Do[18] of cell WORD[4].W (WORD32) port Do[18] of cell WORD[50].W (WORD32) port Do[18] of cell WORD[51].W (WORD32) port Do[18] of cell WORD[52].W (WORD32) port Do[18] of cell WORD[53].W (WORD32) port Do[18] of cell WORD[54].W (WORD32) port Do[18] of cell WORD[55].W (WORD32) port Do[18] of cell WORD[56].W (WORD32) port Do[18] of cell WORD[57].W (WORD32) port Do[18] of cell WORD[58].W (WORD32) port Do[18] of cell WORD[59].W (WORD32) port Do[18] of cell WORD[5].W (WORD32) port Do[18] of cell WORD[60].W (WORD32) port Do[18] of cell WORD[61].W (WORD32) port Do[18] of cell WORD[62].W (WORD32) port Do[18] of cell WORD[63].W (WORD32) port Do[18] of cell WORD[6].W (WORD32) port Do[18] of cell WORD[7].W (WORD32) port Do[18] of cell WORD[8].W (WORD32) port Do[18] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[17]:
port Z[0] of cell FLOATBUF[17] (sky130_fd_sc_hd__ebufn_4) port Do[17] of cell WORD[0].W (WORD32) port Do[17] of cell WORD[10].W (WORD32) port Do[17] of cell WORD[11].W (WORD32) port Do[17] of cell WORD[12].W (WORD32) port Do[17] of cell WORD[13].W (WORD32) port Do[17] of cell WORD[14].W (WORD32) port Do[17] of cell WORD[15].W (WORD32) port Do[17] of cell WORD[16].W (WORD32) port Do[17] of cell WORD[17].W (WORD32) port Do[17] of cell WORD[18].W (WORD32) port Do[17] of cell WORD[19].W (WORD32) port Do[17] of cell WORD[1].W (WORD32) port Do[17] of cell WORD[20].W (WORD32) port Do[17] of cell WORD[21].W (WORD32) port Do[17] of cell WORD[22].W (WORD32) port Do[17] of cell WORD[23].W (WORD32) port Do[17] of cell WORD[24].W (WORD32) port Do[17] of cell WORD[25].W (WORD32) port Do[17] of cell WORD[26].W (WORD32) port Do[17] of cell WORD[27].W (WORD32) port Do[17] of cell WORD[28].W (WORD32) port Do[17] of cell WORD[29].W (WORD32) port Do[17] of cell WORD[2].W (WORD32) port Do[17] of cell WORD[30].W (WORD32) port Do[17] of cell WORD[31].W (WORD32) port Do[17] of cell WORD[32].W (WORD32) port Do[17] of cell WORD[33].W (WORD32) port Do[17] of cell WORD[34].W (WORD32) port Do[17] of cell WORD[35].W (WORD32) port Do[17] of cell WORD[36].W (WORD32) port Do[17] of cell WORD[37].W (WORD32) port Do[17] of cell WORD[38].W (WORD32) port Do[17] of cell WORD[39].W (WORD32) port Do[17] of cell WORD[3].W (WORD32) port Do[17] of cell WORD[40].W (WORD32) port Do[17] of cell WORD[41].W (WORD32) port Do[17] of cell WORD[42].W (WORD32) port Do[17] of cell WORD[43].W (WORD32) port Do[17] of cell WORD[44].W (WORD32) port Do[17] of cell WORD[45].W (WORD32) port Do[17] of cell WORD[46].W (WORD32) port Do[17] of cell WORD[47].W (WORD32) port Do[17] of cell WORD[48].W (WORD32) port Do[17] of cell WORD[49].W (WORD32) port Do[17] of cell WORD[4].W (WORD32) port Do[17] of cell WORD[50].W (WORD32) port Do[17] of cell WORD[51].W (WORD32) port Do[17] of cell WORD[52].W (WORD32) port Do[17] of cell WORD[53].W (WORD32) port Do[17] of cell WORD[54].W (WORD32) port Do[17] of cell WORD[55].W (WORD32) port Do[17] of cell WORD[56].W (WORD32) port Do[17] of cell WORD[57].W (WORD32) port Do[17] of cell WORD[58].W (WORD32) port Do[17] of cell WORD[59].W (WORD32) port Do[17] of cell WORD[5].W (WORD32) port Do[17] of cell WORD[60].W (WORD32) port Do[17] of cell WORD[61].W (WORD32) port Do[17] of cell WORD[62].W (WORD32) port Do[17] of cell WORD[63].W (WORD32) port Do[17] of cell WORD[6].W (WORD32) port Do[17] of cell WORD[7].W (WORD32) port Do[17] of cell WORD[8].W (WORD32) port Do[17] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[16]:
port Z[0] of cell FLOATBUF[16] (sky130_fd_sc_hd__ebufn_4) port Do[16] of cell WORD[0].W (WORD32) port Do[16] of cell WORD[10].W (WORD32) port Do[16] of cell WORD[11].W (WORD32) port Do[16] of cell WORD[12].W (WORD32) port Do[16] of cell WORD[13].W (WORD32) port Do[16] of cell WORD[14].W (WORD32) port Do[16] of cell WORD[15].W (WORD32) port Do[16] of cell WORD[16].W (WORD32) port Do[16] of cell WORD[17].W (WORD32) port Do[16] of cell WORD[18].W (WORD32) port Do[16] of cell WORD[19].W (WORD32) port Do[16] of cell WORD[1].W (WORD32) port Do[16] of cell WORD[20].W (WORD32) port Do[16] of cell WORD[21].W (WORD32) port Do[16] of cell WORD[22].W (WORD32) port Do[16] of cell WORD[23].W (WORD32) port Do[16] of cell WORD[24].W (WORD32) port Do[16] of cell WORD[25].W (WORD32) port Do[16] of cell WORD[26].W (WORD32) port Do[16] of cell WORD[27].W (WORD32) port Do[16] of cell WORD[28].W (WORD32) port Do[16] of cell WORD[29].W (WORD32) port Do[16] of cell WORD[2].W (WORD32) port Do[16] of cell WORD[30].W (WORD32) port Do[16] of cell WORD[31].W (WORD32) port Do[16] of cell WORD[32].W (WORD32) port Do[16] of cell WORD[33].W (WORD32) port Do[16] of cell WORD[34].W (WORD32) port Do[16] of cell WORD[35].W (WORD32) port Do[16] of cell WORD[36].W (WORD32) port Do[16] of cell WORD[37].W (WORD32) port Do[16] of cell WORD[38].W (WORD32) port Do[16] of cell WORD[39].W (WORD32) port Do[16] of cell WORD[3].W (WORD32) port Do[16] of cell WORD[40].W (WORD32) port Do[16] of cell WORD[41].W (WORD32) port Do[16] of cell WORD[42].W (WORD32) port Do[16] of cell WORD[43].W (WORD32) port Do[16] of cell WORD[44].W (WORD32) port Do[16] of cell WORD[45].W (WORD32) port Do[16] of cell WORD[46].W (WORD32) port Do[16] of cell WORD[47].W (WORD32) port Do[16] of cell WORD[48].W (WORD32) port Do[16] of cell WORD[49].W (WORD32) port Do[16] of cell WORD[4].W (WORD32) port Do[16] of cell WORD[50].W (WORD32) port Do[16] of cell WORD[51].W (WORD32) port Do[16] of cell WORD[52].W (WORD32) port Do[16] of cell WORD[53].W (WORD32) port Do[16] of cell WORD[54].W (WORD32) port Do[16] of cell WORD[55].W (WORD32) port Do[16] of cell WORD[56].W (WORD32) port Do[16] of cell WORD[57].W (WORD32) port Do[16] of cell WORD[58].W (WORD32) port Do[16] of cell WORD[59].W (WORD32) port Do[16] of cell WORD[5].W (WORD32) port Do[16] of cell WORD[60].W (WORD32) port Do[16] of cell WORD[61].W (WORD32) port Do[16] of cell WORD[62].W (WORD32) port Do[16] of cell WORD[63].W (WORD32) port Do[16] of cell WORD[6].W (WORD32) port Do[16] of cell WORD[7].W (WORD32) port Do[16] of cell WORD[8].W (WORD32) port Do[16] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[15]:
port Z[0] of cell FLOATBUF[15] (sky130_fd_sc_hd__ebufn_4) port Do[15] of cell WORD[0].W (WORD32) port Do[15] of cell WORD[10].W (WORD32) port Do[15] of cell WORD[11].W (WORD32) port Do[15] of cell WORD[12].W (WORD32) port Do[15] of cell WORD[13].W (WORD32) port Do[15] of cell WORD[14].W (WORD32) port Do[15] of cell WORD[15].W (WORD32) port Do[15] of cell WORD[16].W (WORD32) port Do[15] of cell WORD[17].W (WORD32) port Do[15] of cell WORD[18].W (WORD32) port Do[15] of cell WORD[19].W (WORD32) port Do[15] of cell WORD[1].W (WORD32) port Do[15] of cell WORD[20].W (WORD32) port Do[15] of cell WORD[21].W (WORD32) port Do[15] of cell WORD[22].W (WORD32) port Do[15] of cell WORD[23].W (WORD32) port Do[15] of cell WORD[24].W (WORD32) port Do[15] of cell WORD[25].W (WORD32) port Do[15] of cell WORD[26].W (WORD32) port Do[15] of cell WORD[27].W (WORD32) port Do[15] of cell WORD[28].W (WORD32) port Do[15] of cell WORD[29].W (WORD32) port Do[15] of cell WORD[2].W (WORD32) port Do[15] of cell WORD[30].W (WORD32) port Do[15] of cell WORD[31].W (WORD32) port Do[15] of cell WORD[32].W (WORD32) port Do[15] of cell WORD[33].W (WORD32) port Do[15] of cell WORD[34].W (WORD32) port Do[15] of cell WORD[35].W (WORD32) port Do[15] of cell WORD[36].W (WORD32) port Do[15] of cell WORD[37].W (WORD32) port Do[15] of cell WORD[38].W (WORD32) port Do[15] of cell WORD[39].W (WORD32) port Do[15] of cell WORD[3].W (WORD32) port Do[15] of cell WORD[40].W (WORD32) port Do[15] of cell WORD[41].W (WORD32) port Do[15] of cell WORD[42].W (WORD32) port Do[15] of cell WORD[43].W (WORD32) port Do[15] of cell WORD[44].W (WORD32) port Do[15] of cell WORD[45].W (WORD32) port Do[15] of cell WORD[46].W (WORD32) port Do[15] of cell WORD[47].W (WORD32) port Do[15] of cell WORD[48].W (WORD32) port Do[15] of cell WORD[49].W (WORD32) port Do[15] of cell WORD[4].W (WORD32) port Do[15] of cell WORD[50].W (WORD32) port Do[15] of cell WORD[51].W (WORD32) port Do[15] of cell WORD[52].W (WORD32) port Do[15] of cell WORD[53].W (WORD32) port Do[15] of cell WORD[54].W (WORD32) port Do[15] of cell WORD[55].W (WORD32) port Do[15] of cell WORD[56].W (WORD32) port Do[15] of cell WORD[57].W (WORD32) port Do[15] of cell WORD[58].W (WORD32) port Do[15] of cell WORD[59].W (WORD32) port Do[15] of cell WORD[5].W (WORD32) port Do[15] of cell WORD[60].W (WORD32) port Do[15] of cell WORD[61].W (WORD32) port Do[15] of cell WORD[62].W (WORD32) port Do[15] of cell WORD[63].W (WORD32) port Do[15] of cell WORD[6].W (WORD32) port Do[15] of cell WORD[7].W (WORD32) port Do[15] of cell WORD[8].W (WORD32) port Do[15] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[14]:
port Z[0] of cell FLOATBUF[14] (sky130_fd_sc_hd__ebufn_4) port Do[14] of cell WORD[0].W (WORD32) port Do[14] of cell WORD[10].W (WORD32) port Do[14] of cell WORD[11].W (WORD32) port Do[14] of cell WORD[12].W (WORD32) port Do[14] of cell WORD[13].W (WORD32) port Do[14] of cell WORD[14].W (WORD32) port Do[14] of cell WORD[15].W (WORD32) port Do[14] of cell WORD[16].W (WORD32) port Do[14] of cell WORD[17].W (WORD32) port Do[14] of cell WORD[18].W (WORD32) port Do[14] of cell WORD[19].W (WORD32) port Do[14] of cell WORD[1].W (WORD32) port Do[14] of cell WORD[20].W (WORD32) port Do[14] of cell WORD[21].W (WORD32) port Do[14] of cell WORD[22].W (WORD32) port Do[14] of cell WORD[23].W (WORD32) port Do[14] of cell WORD[24].W (WORD32) port Do[14] of cell WORD[25].W (WORD32) port Do[14] of cell WORD[26].W (WORD32) port Do[14] of cell WORD[27].W (WORD32) port Do[14] of cell WORD[28].W (WORD32) port Do[14] of cell WORD[29].W (WORD32) port Do[14] of cell WORD[2].W (WORD32) port Do[14] of cell WORD[30].W (WORD32) port Do[14] of cell WORD[31].W (WORD32) port Do[14] of cell WORD[32].W (WORD32) port Do[14] of cell WORD[33].W (WORD32) port Do[14] of cell WORD[34].W (WORD32) port Do[14] of cell WORD[35].W (WORD32) port Do[14] of cell WORD[36].W (WORD32) port Do[14] of cell WORD[37].W (WORD32) port Do[14] of cell WORD[38].W (WORD32) port Do[14] of cell WORD[39].W (WORD32) port Do[14] of cell WORD[3].W (WORD32) port Do[14] of cell WORD[40].W (WORD32) port Do[14] of cell WORD[41].W (WORD32) port Do[14] of cell WORD[42].W (WORD32) port Do[14] of cell WORD[43].W (WORD32) port Do[14] of cell WORD[44].W (WORD32) port Do[14] of cell WORD[45].W (WORD32) port Do[14] of cell WORD[46].W (WORD32) port Do[14] of cell WORD[47].W (WORD32) port Do[14] of cell WORD[48].W (WORD32) port Do[14] of cell WORD[49].W (WORD32) port Do[14] of cell WORD[4].W (WORD32) port Do[14] of cell WORD[50].W (WORD32) port Do[14] of cell WORD[51].W (WORD32) port Do[14] of cell WORD[52].W (WORD32) port Do[14] of cell WORD[53].W (WORD32) port Do[14] of cell WORD[54].W (WORD32) port Do[14] of cell WORD[55].W (WORD32) port Do[14] of cell WORD[56].W (WORD32) port Do[14] of cell WORD[57].W (WORD32) port Do[14] of cell WORD[58].W (WORD32) port Do[14] of cell WORD[59].W (WORD32) port Do[14] of cell WORD[5].W (WORD32) port Do[14] of cell WORD[60].W (WORD32) port Do[14] of cell WORD[61].W (WORD32) port Do[14] of cell WORD[62].W (WORD32) port Do[14] of cell WORD[63].W (WORD32) port Do[14] of cell WORD[6].W (WORD32) port Do[14] of cell WORD[7].W (WORD32) port Do[14] of cell WORD[8].W (WORD32) port Do[14] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[13]:
port Z[0] of cell FLOATBUF[13] (sky130_fd_sc_hd__ebufn_4) port Do[13] of cell WORD[0].W (WORD32) port Do[13] of cell WORD[10].W (WORD32) port Do[13] of cell WORD[11].W (WORD32) port Do[13] of cell WORD[12].W (WORD32) port Do[13] of cell WORD[13].W (WORD32) port Do[13] of cell WORD[14].W (WORD32) port Do[13] of cell WORD[15].W (WORD32) port Do[13] of cell WORD[16].W (WORD32) port Do[13] of cell WORD[17].W (WORD32) port Do[13] of cell WORD[18].W (WORD32) port Do[13] of cell WORD[19].W (WORD32) port Do[13] of cell WORD[1].W (WORD32) port Do[13] of cell WORD[20].W (WORD32) port Do[13] of cell WORD[21].W (WORD32) port Do[13] of cell WORD[22].W (WORD32) port Do[13] of cell WORD[23].W (WORD32) port Do[13] of cell WORD[24].W (WORD32) port Do[13] of cell WORD[25].W (WORD32) port Do[13] of cell WORD[26].W (WORD32) port Do[13] of cell WORD[27].W (WORD32) port Do[13] of cell WORD[28].W (WORD32) port Do[13] of cell WORD[29].W (WORD32) port Do[13] of cell WORD[2].W (WORD32) port Do[13] of cell WORD[30].W (WORD32) port Do[13] of cell WORD[31].W (WORD32) port Do[13] of cell WORD[32].W (WORD32) port Do[13] of cell WORD[33].W (WORD32) port Do[13] of cell WORD[34].W (WORD32) port Do[13] of cell WORD[35].W (WORD32) port Do[13] of cell WORD[36].W (WORD32) port Do[13] of cell WORD[37].W (WORD32) port Do[13] of cell WORD[38].W (WORD32) port Do[13] of cell WORD[39].W (WORD32) port Do[13] of cell WORD[3].W (WORD32) port Do[13] of cell WORD[40].W (WORD32) port Do[13] of cell WORD[41].W (WORD32) port Do[13] of cell WORD[42].W (WORD32) port Do[13] of cell WORD[43].W (WORD32) port Do[13] of cell WORD[44].W (WORD32) port Do[13] of cell WORD[45].W (WORD32) port Do[13] of cell WORD[46].W (WORD32) port Do[13] of cell WORD[47].W (WORD32) port Do[13] of cell WORD[48].W (WORD32) port Do[13] of cell WORD[49].W (WORD32) port Do[13] of cell WORD[4].W (WORD32) port Do[13] of cell WORD[50].W (WORD32) port Do[13] of cell WORD[51].W (WORD32) port Do[13] of cell WORD[52].W (WORD32) port Do[13] of cell WORD[53].W (WORD32) port Do[13] of cell WORD[54].W (WORD32) port Do[13] of cell WORD[55].W (WORD32) port Do[13] of cell WORD[56].W (WORD32) port Do[13] of cell WORD[57].W (WORD32) port Do[13] of cell WORD[58].W (WORD32) port Do[13] of cell WORD[59].W (WORD32) port Do[13] of cell WORD[5].W (WORD32) port Do[13] of cell WORD[60].W (WORD32) port Do[13] of cell WORD[61].W (WORD32) port Do[13] of cell WORD[62].W (WORD32) port Do[13] of cell WORD[63].W (WORD32) port Do[13] of cell WORD[6].W (WORD32) port Do[13] of cell WORD[7].W (WORD32) port Do[13] of cell WORD[8].W (WORD32) port Do[13] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[12]:
port Z[0] of cell FLOATBUF[12] (sky130_fd_sc_hd__ebufn_4) port Do[12] of cell WORD[0].W (WORD32) port Do[12] of cell WORD[10].W (WORD32) port Do[12] of cell WORD[11].W (WORD32) port Do[12] of cell WORD[12].W (WORD32) port Do[12] of cell WORD[13].W (WORD32) port Do[12] of cell WORD[14].W (WORD32) port Do[12] of cell WORD[15].W (WORD32) port Do[12] of cell WORD[16].W (WORD32) port Do[12] of cell WORD[17].W (WORD32) port Do[12] of cell WORD[18].W (WORD32) port Do[12] of cell WORD[19].W (WORD32) port Do[12] of cell WORD[1].W (WORD32) port Do[12] of cell WORD[20].W (WORD32) port Do[12] of cell WORD[21].W (WORD32) port Do[12] of cell WORD[22].W (WORD32) port Do[12] of cell WORD[23].W (WORD32) port Do[12] of cell WORD[24].W (WORD32) port Do[12] of cell WORD[25].W (WORD32) port Do[12] of cell WORD[26].W (WORD32) port Do[12] of cell WORD[27].W (WORD32) port Do[12] of cell WORD[28].W (WORD32) port Do[12] of cell WORD[29].W (WORD32) port Do[12] of cell WORD[2].W (WORD32) port Do[12] of cell WORD[30].W (WORD32) port Do[12] of cell WORD[31].W (WORD32) port Do[12] of cell WORD[32].W (WORD32) port Do[12] of cell WORD[33].W (WORD32) port Do[12] of cell WORD[34].W (WORD32) port Do[12] of cell WORD[35].W (WORD32) port Do[12] of cell WORD[36].W (WORD32) port Do[12] of cell WORD[37].W (WORD32) port Do[12] of cell WORD[38].W (WORD32) port Do[12] of cell WORD[39].W (WORD32) port Do[12] of cell WORD[3].W (WORD32) port Do[12] of cell WORD[40].W (WORD32) port Do[12] of cell WORD[41].W (WORD32) port Do[12] of cell WORD[42].W (WORD32) port Do[12] of cell WORD[43].W (WORD32) port Do[12] of cell WORD[44].W (WORD32) port Do[12] of cell WORD[45].W (WORD32) port Do[12] of cell WORD[46].W (WORD32) port Do[12] of cell WORD[47].W (WORD32) port Do[12] of cell WORD[48].W (WORD32) port Do[12] of cell WORD[49].W (WORD32) port Do[12] of cell WORD[4].W (WORD32) port Do[12] of cell WORD[50].W (WORD32) port Do[12] of cell WORD[51].W (WORD32) port Do[12] of cell WORD[52].W (WORD32) port Do[12] of cell WORD[53].W (WORD32) port Do[12] of cell WORD[54].W (WORD32) port Do[12] of cell WORD[55].W (WORD32) port Do[12] of cell WORD[56].W (WORD32) port Do[12] of cell WORD[57].W (WORD32) port Do[12] of cell WORD[58].W (WORD32) port Do[12] of cell WORD[59].W (WORD32) port Do[12] of cell WORD[5].W (WORD32) port Do[12] of cell WORD[60].W (WORD32) port Do[12] of cell WORD[61].W (WORD32) port Do[12] of cell WORD[62].W (WORD32) port Do[12] of cell WORD[63].W (WORD32) port Do[12] of cell WORD[6].W (WORD32) port Do[12] of cell WORD[7].W (WORD32) port Do[12] of cell WORD[8].W (WORD32) port Do[12] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[11]:
port Z[0] of cell FLOATBUF[11] (sky130_fd_sc_hd__ebufn_4) port Do[11] of cell WORD[0].W (WORD32) port Do[11] of cell WORD[10].W (WORD32) port Do[11] of cell WORD[11].W (WORD32) port Do[11] of cell WORD[12].W (WORD32) port Do[11] of cell WORD[13].W (WORD32) port Do[11] of cell WORD[14].W (WORD32) port Do[11] of cell WORD[15].W (WORD32) port Do[11] of cell WORD[16].W (WORD32) port Do[11] of cell WORD[17].W (WORD32) port Do[11] of cell WORD[18].W (WORD32) port Do[11] of cell WORD[19].W (WORD32) port Do[11] of cell WORD[1].W (WORD32) port Do[11] of cell WORD[20].W (WORD32) port Do[11] of cell WORD[21].W (WORD32) port Do[11] of cell WORD[22].W (WORD32) port Do[11] of cell WORD[23].W (WORD32) port Do[11] of cell WORD[24].W (WORD32) port Do[11] of cell WORD[25].W (WORD32) port Do[11] of cell WORD[26].W (WORD32) port Do[11] of cell WORD[27].W (WORD32) port Do[11] of cell WORD[28].W (WORD32) port Do[11] of cell WORD[29].W (WORD32) port Do[11] of cell WORD[2].W (WORD32) port Do[11] of cell WORD[30].W (WORD32) port Do[11] of cell WORD[31].W (WORD32) port Do[11] of cell WORD[32].W (WORD32) port Do[11] of cell WORD[33].W (WORD32) port Do[11] of cell WORD[34].W (WORD32) port Do[11] of cell WORD[35].W (WORD32) port Do[11] of cell WORD[36].W (WORD32) port Do[11] of cell WORD[37].W (WORD32) port Do[11] of cell WORD[38].W (WORD32) port Do[11] of cell WORD[39].W (WORD32) port Do[11] of cell WORD[3].W (WORD32) port Do[11] of cell WORD[40].W (WORD32) port Do[11] of cell WORD[41].W (WORD32) port Do[11] of cell WORD[42].W (WORD32) port Do[11] of cell WORD[43].W (WORD32) port Do[11] of cell WORD[44].W (WORD32) port Do[11] of cell WORD[45].W (WORD32) port Do[11] of cell WORD[46].W (WORD32) port Do[11] of cell WORD[47].W (WORD32) port Do[11] of cell WORD[48].W (WORD32) port Do[11] of cell WORD[49].W (WORD32) port Do[11] of cell WORD[4].W (WORD32) port Do[11] of cell WORD[50].W (WORD32) port Do[11] of cell WORD[51].W (WORD32) port Do[11] of cell WORD[52].W (WORD32) port Do[11] of cell WORD[53].W (WORD32) port Do[11] of cell WORD[54].W (WORD32) port Do[11] of cell WORD[55].W (WORD32) port Do[11] of cell WORD[56].W (WORD32) port Do[11] of cell WORD[57].W (WORD32) port Do[11] of cell WORD[58].W (WORD32) port Do[11] of cell WORD[59].W (WORD32) port Do[11] of cell WORD[5].W (WORD32) port Do[11] of cell WORD[60].W (WORD32) port Do[11] of cell WORD[61].W (WORD32) port Do[11] of cell WORD[62].W (WORD32) port Do[11] of cell WORD[63].W (WORD32) port Do[11] of cell WORD[6].W (WORD32) port Do[11] of cell WORD[7].W (WORD32) port Do[11] of cell WORD[8].W (WORD32) port Do[11] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[10]:
port Z[0] of cell FLOATBUF[10] (sky130_fd_sc_hd__ebufn_4) port Do[10] of cell WORD[0].W (WORD32) port Do[10] of cell WORD[10].W (WORD32) port Do[10] of cell WORD[11].W (WORD32) port Do[10] of cell WORD[12].W (WORD32) port Do[10] of cell WORD[13].W (WORD32) port Do[10] of cell WORD[14].W (WORD32) port Do[10] of cell WORD[15].W (WORD32) port Do[10] of cell WORD[16].W (WORD32) port Do[10] of cell WORD[17].W (WORD32) port Do[10] of cell WORD[18].W (WORD32) port Do[10] of cell WORD[19].W (WORD32) port Do[10] of cell WORD[1].W (WORD32) port Do[10] of cell WORD[20].W (WORD32) port Do[10] of cell WORD[21].W (WORD32) port Do[10] of cell WORD[22].W (WORD32) port Do[10] of cell WORD[23].W (WORD32) port Do[10] of cell WORD[24].W (WORD32) port Do[10] of cell WORD[25].W (WORD32) port Do[10] of cell WORD[26].W (WORD32) port Do[10] of cell WORD[27].W (WORD32) port Do[10] of cell WORD[28].W (WORD32) port Do[10] of cell WORD[29].W (WORD32) port Do[10] of cell WORD[2].W (WORD32) port Do[10] of cell WORD[30].W (WORD32) port Do[10] of cell WORD[31].W (WORD32) port Do[10] of cell WORD[32].W (WORD32) port Do[10] of cell WORD[33].W (WORD32) port Do[10] of cell WORD[34].W (WORD32) port Do[10] of cell WORD[35].W (WORD32) port Do[10] of cell WORD[36].W (WORD32) port Do[10] of cell WORD[37].W (WORD32) port Do[10] of cell WORD[38].W (WORD32) port Do[10] of cell WORD[39].W (WORD32) port Do[10] of cell WORD[3].W (WORD32) port Do[10] of cell WORD[40].W (WORD32) port Do[10] of cell WORD[41].W (WORD32) port Do[10] of cell WORD[42].W (WORD32) port Do[10] of cell WORD[43].W (WORD32) port Do[10] of cell WORD[44].W (WORD32) port Do[10] of cell WORD[45].W (WORD32) port Do[10] of cell WORD[46].W (WORD32) port Do[10] of cell WORD[47].W (WORD32) port Do[10] of cell WORD[48].W (WORD32) port Do[10] of cell WORD[49].W (WORD32) port Do[10] of cell WORD[4].W (WORD32) port Do[10] of cell WORD[50].W (WORD32) port Do[10] of cell WORD[51].W (WORD32) port Do[10] of cell WORD[52].W (WORD32) port Do[10] of cell WORD[53].W (WORD32) port Do[10] of cell WORD[54].W (WORD32) port Do[10] of cell WORD[55].W (WORD32) port Do[10] of cell WORD[56].W (WORD32) port Do[10] of cell WORD[57].W (WORD32) port Do[10] of cell WORD[58].W (WORD32) port Do[10] of cell WORD[59].W (WORD32) port Do[10] of cell WORD[5].W (WORD32) port Do[10] of cell WORD[60].W (WORD32) port Do[10] of cell WORD[61].W (WORD32) port Do[10] of cell WORD[62].W (WORD32) port Do[10] of cell WORD[63].W (WORD32) port Do[10] of cell WORD[6].W (WORD32) port Do[10] of cell WORD[7].W (WORD32) port Do[10] of cell WORD[8].W (WORD32) port Do[10] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[0]:
port Z[0] of cell FLOATBUF[0] (sky130_fd_sc_hd__ebufn_4) port Do[0] of cell WORD[0].W (WORD32) port Do[0] of cell WORD[10].W (WORD32) port Do[0] of cell WORD[11].W (WORD32) port Do[0] of cell WORD[12].W (WORD32) port Do[0] of cell WORD[13].W (WORD32) port Do[0] of cell WORD[14].W (WORD32) port Do[0] of cell WORD[15].W (WORD32) port Do[0] of cell WORD[16].W (WORD32) port Do[0] of cell WORD[17].W (WORD32) port Do[0] of cell WORD[18].W (WORD32) port Do[0] of cell WORD[19].W (WORD32) port Do[0] of cell WORD[1].W (WORD32) port Do[0] of cell WORD[20].W (WORD32) port Do[0] of cell WORD[21].W (WORD32) port Do[0] of cell WORD[22].W (WORD32) port Do[0] of cell WORD[23].W (WORD32) port Do[0] of cell WORD[24].W (WORD32) port Do[0] of cell WORD[25].W (WORD32) port Do[0] of cell WORD[26].W (WORD32) port Do[0] of cell WORD[27].W (WORD32) port Do[0] of cell WORD[28].W (WORD32) port Do[0] of cell WORD[29].W (WORD32) port Do[0] of cell WORD[2].W (WORD32) port Do[0] of cell WORD[30].W (WORD32) port Do[0] of cell WORD[31].W (WORD32) port Do[0] of cell WORD[32].W (WORD32) port Do[0] of cell WORD[33].W (WORD32) port Do[0] of cell WORD[34].W (WORD32) port Do[0] of cell WORD[35].W (WORD32) port Do[0] of cell WORD[36].W (WORD32) port Do[0] of cell WORD[37].W (WORD32) port Do[0] of cell WORD[38].W (WORD32) port Do[0] of cell WORD[39].W (WORD32) port Do[0] of cell WORD[3].W (WORD32) port Do[0] of cell WORD[40].W (WORD32) port Do[0] of cell WORD[41].W (WORD32) port Do[0] of cell WORD[42].W (WORD32) port Do[0] of cell WORD[43].W (WORD32) port Do[0] of cell WORD[44].W (WORD32) port Do[0] of cell WORD[45].W (WORD32) port Do[0] of cell WORD[46].W (WORD32) port Do[0] of cell WORD[47].W (WORD32) port Do[0] of cell WORD[48].W (WORD32) port Do[0] of cell WORD[49].W (WORD32) port Do[0] of cell WORD[4].W (WORD32) port Do[0] of cell WORD[50].W (WORD32) port Do[0] of cell WORD[51].W (WORD32) port Do[0] of cell WORD[52].W (WORD32) port Do[0] of cell WORD[53].W (WORD32) port Do[0] of cell WORD[54].W (WORD32) port Do[0] of cell WORD[55].W (WORD32) port Do[0] of cell WORD[56].W (WORD32) port Do[0] of cell WORD[57].W (WORD32) port Do[0] of cell WORD[58].W (WORD32) port Do[0] of cell WORD[59].W (WORD32) port Do[0] of cell WORD[5].W (WORD32) port Do[0] of cell WORD[60].W (WORD32) port Do[0] of cell WORD[61].W (WORD32) port Do[0] of cell WORD[62].W (WORD32) port Do[0] of cell WORD[63].W (WORD32) port Do[0] of cell WORD[6].W (WORD32) port Do[0] of cell WORD[7].W (WORD32) port Do[0] of cell WORD[8].W (WORD32) port Do[0] of cell WORD[9].W (WORD32) checking module WORD32.. found and reported 32 problems. 10. Printing statistics. === BYTE === Number of wires: 16 Number of wire bits: 30 Number of public wires: 16 Number of public wire bits: 30 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 19 sky130_fd_sc_hd__and2_1 1 sky130_fd_sc_hd__dfxtp_1 8 sky130_fd_sc_hd__dlclkp_1 1 sky130_fd_sc_hd__ebufn_2 8 sky130_fd_sc_hd__inv_1 1 Area for cell type \sky130_fd_sc_hd__and2_1 is unknown! Area for cell type \sky130_fd_sc_hd__dfxtp_1 is unknown! Area for cell type \sky130_fd_sc_hd__dlclkp_1 is unknown! Area for cell type \sky130_fd_sc_hd__ebufn_2 is unknown! Area for cell type \sky130_fd_sc_hd__inv_1 is unknown! === DEC2x4 === Number of wires: 3 Number of wire bits: 7 Number of public wires: 3 Number of public wire bits: 7 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 4 sky130_fd_sc_hd__and3_4 1 sky130_fd_sc_hd__and3b_4 2 sky130_fd_sc_hd__nor3b_4 1 Area for cell type \sky130_fd_sc_hd__and3b_4 is unknown! Area for cell type \sky130_fd_sc_hd__nor3b_4 is unknown! Chip area for module '\DEC2x4': 11.260800 === DEC3x8 === Number of wires: 3 Number of wire bits: 12 Number of public wires: 3 Number of public wire bits: 12 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 8 sky130_fd_sc_hd__and4_2 1 sky130_fd_sc_hd__and4b_2 3 sky130_fd_sc_hd__and4bb_2 3 sky130_fd_sc_hd__nor4b_2 1 Area for cell type \sky130_fd_sc_hd__and4_2 is unknown! Area for cell type \sky130_fd_sc_hd__and4b_2 is unknown! Area for cell type \sky130_fd_sc_hd__and4bb_2 is unknown! Area for cell type \sky130_fd_sc_hd__nor4b_2 is unknown! === DEC6x64 === Number of wires: 14 Number of wire bits: 82 Number of public wires: 14 Number of public wire bits: 82 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 12 DEC3x8 9 sky130_fd_sc_hd__clkbuf_16 3 Area for cell type \sky130_fd_sc_hd__clkbuf_16 is unknown! Area for cell type \DEC3x8 is unknown! === DFFRAM === Number of wires: 71 Number of wire bits: 143 Number of public wires: 71 Number of public wire bits: 143 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 35 DFFRAM_COL4 1 PASS 1 sky130_fd_sc_hd__clkbuf_4 33 Area for cell type \sky130_fd_sc_hd__clkbuf_4 is unknown! Area for cell type \DFFRAM_COL4 is unknown! Area for cell type \PASS is unknown! === DFFRAM_COL4 === Number of wires: 210 Number of wire bits: 282 Number of public wires: 210 Number of public wire bits: 282 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 46 DEC2x4 1 MUX4x1_32 1 SRAM64x32 4 sky130_fd_sc_hd__clkbuf_16 3 sky130_fd_sc_hd__clkbuf_8 37 Area for cell type \sky130_fd_sc_hd__clkbuf_16 is unknown! Area for cell type \sky130_fd_sc_hd__clkbuf_8 is unknown! Area for cell type \DEC2x4 is unknown! Area for cell type \MUX4x1_32 is unknown! Area for cell type \SRAM64x32 is unknown! === MUX4x1_32 === Number of wires: 6 Number of wire bits: 162 Number of public wires: 6 Number of public wire bits: 162 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 32 sky130_fd_sc_hd__mux4_1 32 Area for cell type \sky130_fd_sc_hd__mux4_1 is unknown! === PASS === Number of wires: 2 Number of wire bits: 64 Number of public wires: 2 Number of public wire bits: 64 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 0 === SRAM64x32 === Number of wires: 141 Number of wire bits: 211 Number of public wires: 141 Number of public wire bits: 211 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 168 DEC6x64 1 WORD32 64 sky130_fd_sc_hd__clkbuf_16 37 sky130_fd_sc_hd__clkbuf_4 1 sky130_fd_sc_hd__conb_1 1 sky130_fd_sc_hd__dfxtp_1 32 sky130_fd_sc_hd__ebufn_4 32 Area for cell type \sky130_fd_sc_hd__clkbuf_16 is unknown! Area for cell type \sky130_fd_sc_hd__clkbuf_4 is unknown! Area for cell type \sky130_fd_sc_hd__dfxtp_1 is unknown! Area for cell type \sky130_fd_sc_hd__ebufn_4 is unknown! Area for cell type \WORD32 is unknown! Area for cell type \DEC6x64 is unknown! Chip area for module '\SRAM64x32': 3.753600 === WORD32 === Number of wires: 5 Number of wire bits: 70 Number of public wires: 5 Number of public wire bits: 70 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 4 BYTE 4 Area for cell type \BYTE is unknown! === design hierarchy === DFFRAM 1 DFFRAM_COL4 1 DEC2x4 1 MUX4x1_32 1 SRAM64x32 4 DEC6x64 1 DEC3x8 9 WORD32 64 BYTE 4 PASS 1 Number of wires: 18684 Number of wire bits: 50902 Number of public wires: 18684 Number of public wire bits: 50902 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 20277 sky130_fd_sc_hd__and2_1 1024 sky130_fd_sc_hd__and3_4 1 sky130_fd_sc_hd__and3b_4 2 sky130_fd_sc_hd__and4_2 36 sky130_fd_sc_hd__and4b_2 108 sky130_fd_sc_hd__and4bb_2 108 sky130_fd_sc_hd__clkbuf_16 163 sky130_fd_sc_hd__clkbuf_4 37 sky130_fd_sc_hd__clkbuf_8 37 sky130_fd_sc_hd__conb_1 4 sky130_fd_sc_hd__dfxtp_1 8320 sky130_fd_sc_hd__dlclkp_1 1024 sky130_fd_sc_hd__ebufn_2 8192 sky130_fd_sc_hd__ebufn_4 128 sky130_fd_sc_hd__inv_1 1024 sky130_fd_sc_hd__mux4_1 32 sky130_fd_sc_hd__nor3b_4 1 sky130_fd_sc_hd__nor4b_2 36 Chip area for top module '\DFFRAM': 26.275200 11. Executing Verilog backend. Dumping module `\BYTE'. Dumping module `\DEC2x4'. Dumping module `\DEC3x8'. Dumping module `\DEC6x64'. Dumping module `\DFFRAM'. Dumping module `\DFFRAM_COL4'. Dumping module `\MUX4x1_32'. Dumping module `\PASS'. Dumping module `\SRAM64x32'. Dumping module `\WORD32'.
Warnings: 32 unique messages, 32 total
End of script. Logfile hash: 93ef28fe03, CPU: user 1.91s system 0.04s, MEM: 42.19 MB peak Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) Time spent: 48% 2x write_verilog (0 sec), 41% 2x read_liberty (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/DFFRAM/runs/DFFRAM/results/synthesis/DFFRAM.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc. License GPLv3: GNU GPL version 3 This is free software, and you are free to change and redistribute it under certain conditions; type `show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) set IO_PCT 0.2 set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] puts "\[INFO\]: Setting output delay to: $output_delay_value" [INFO]: Setting output delay to: 2.0 puts "\[INFO\]: Setting input delay to: $input_delay_value" [INFO]: Setting input delay to: 2.0 set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] #set rst_indx [lsearch [all_inputs] [get_port resetn]] set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] set all_inputs_wo_clk_rst $all_inputs_wo_clk # correct resetn set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] # TODO set this as parameter set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "\[INFO\]: Setting load to: $cap_load" [INFO]: Setting load to: 0.01765 set_load $cap_load [all_outputs] tns 0.00 wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Info: Added 185 rows of 1606 sites.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 738.96
[INFO]: Core area height: 503.24
[INFO]: Changing layout from 0 to /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def
Notice 0: Reading LEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
Notice 0: Reading DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def Notice 0: Design: DFFRAM Notice 0: Created 78 pins. Notice 0: Created 20277 components and 100828 component-terminals. Notice 0: Created 12163 nets and 60270 connections.
Notice 0: Finished DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def
Top-level design name: DFFRAM Block boundaries: 0 0 750000 525000 Writing /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def to /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def Notice 0: Design: DFFRAM Notice 0: Created 78 pins. Notice 0: Created 20277 components and 100828 component-terminals. Notice 0: Created 12163 nets and 60270 connections.
Notice 0: Finished DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def
Running tapcell... Step 1: Cut rows... [INFO] Macro blocks found: 0 [INFO] #Original rows: 185 [INFO] #Cut rows: 0 Step 2: Insert endcaps... [INFO] #Endcaps inserted: 370 Step 3: Insert tapcells... [INFO] #Tapcells inserted: 4860 Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def to /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def
[INFO]: Running Placement...
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def Notice 0: Design: DFFRAM Notice 0: Created 78 pins. Notice 0: Created 25507 components and 111288 component-terminals. Notice 0: Created 12163 nets and 60270 connections.
Notice 0: Finished DEF file: /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def
[INFO] DBU = 1000 [INFO] SiteSize = (460, 2720) [INFO] CoreAreaLxLy = (5520, 10880) [INFO] CoreAreaUxUy = (744280, 514080) [INFO] NumInstances = 25507 [INFO] NumPlaceInstances = 20277 [INFO] NumFixedInstances = 5230 [INFO] NumDummyInstances = 0 [INFO] NumNets = 12163 [INFO] NumPins = 60348 [INFO] DieAreaLxLy = (0, 0) [INFO] DieAreaUxUy = (750000, 525000) [INFO] CoreAreaLxLy = (5520, 10880) [INFO] CoreAreaUxUy = (744280, 514080) [INFO] CoreArea = 371744032000 [INFO] NonPlaceInstsArea = 7469664000 [INFO] PlaceInstsArea = 298322364800 [INFO] Util(%) = 81.894974 [INFO] StdInstsArea = 298322364800 [INFO] MacroInstsArea = 0
[InitialPlace] Iter: 1 CG Error: 0.00127764 HPWL: 161817324
[InitialPlace] Iter: 2 CG Error: 0.000647573 HPWL: 184741169
[InitialPlace] Iter: 3 CG Error: 0.000195701 HPWL: 189760398
[InitialPlace] Iter: 4 CG Error: 0.000103155 HPWL: 190814756
[InitialPlace] Iter: 5 CG Error: 0.000107622 HPWL: 190736005
[InitialPlace] Iter: 6 CG Error: 0.000729092 HPWL: 190804761
[InitialPlace] Iter: 7 CG Error: 6.74333e-05 HPWL: 190489892
[InitialPlace] Iter: 8 CG Error: 6.94999e-05 HPWL: 190662552
[InitialPlace] Iter: 9 CG Error: 3.36633e-05 HPWL: 190512094
[InitialPlace] Iter: 10 CG Error: 5.18533e-05 HPWL: 190610472
[InitialPlace] Iter: 11 CG Error: 5.30023e-05 HPWL: 190560818
[InitialPlace] Iter: 12 CG Error: 5.6628e-05 HPWL: 190648774
[InitialPlace] Iter: 13 CG Error: 2.82688e-05 HPWL: 190494353
[InitialPlace] Iter: 14 CG Error: 4.78211e-05 HPWL: 190642021
[InitialPlace] Iter: 15 CG Error: 7.76779e-05 HPWL: 190535584
[InitialPlace] Iter: 16 CG Error: 5.8144e-05 HPWL: 190662477
[InitialPlace] Iter: 17 CG Error: 4.74044e-05 HPWL: 190534521
[InitialPlace] Iter: 18 CG Error: 8.7525e-05 HPWL: 190605707
[InitialPlace] Iter: 19 CG Error: 4.43859e-05 HPWL: 190518095
[InitialPlace] Iter: 20 CG Error: 3.95577e-05 HPWL: 190642137
[INFO] FillerInit: NumGCells = 21032 [INFO] FillerInit: NumGNets = 12163 [INFO] FillerInit: NumGPins = 60348 [INFO] TargetDensity = 0.850000 [INFO] AveragePlaceInstArea = 14712352 [INFO] IdealBinArea = 17308648 [INFO] IdealBinCnt = 21477 [INFO] TotalBinArea = 371744032000 [INFO] BinCnt = (128, 128) [INFO] BinSize = (5772, 3932) [INFO] NumBins = 16384 [NesterovSolve] Iter: 1 overflow: 0.995306 HPWL: 43130518 [NesterovSolve] Iter: 10 overflow: 0.977331 HPWL: 99726567 [NesterovSolve] Iter: 20 overflow: 0.975976 HPWL: 107110791 [NesterovSolve] Iter: 30 overflow: 0.976886 HPWL: 105711777 [NesterovSolve] Iter: 40 overflow: 0.976318 HPWL: 106278897 [NesterovSolve] Iter: 50 overflow: 0.976224 HPWL: 107071456 [NesterovSolve] Iter: 60 overflow: 0.976781 HPWL: 106594415 [NesterovSolve] Iter: 70 overflow: 0.976044 HPWL: 106516226 [NesterovSolve] Iter: 80 overflow: 0.975906 HPWL: 106341252 [NesterovSolve] Iter: 90 overflow: 0.975995 HPWL: 106302937 [NesterovSolve] Iter: 100 overflow: 0.976049 HPWL: 106538513 [NesterovSolve] Iter: 110 overflow: 0.976237 HPWL: 106896123 [NesterovSolve] Iter: 120 overflow: 0.976414 HPWL: 107342467 [NesterovSolve] Iter: 130 overflow: 0.976962 HPWL: 107997356 [NesterovSolve] Iter: 140 overflow: 0.976717 HPWL: 109054210 [NesterovSolve] Iter: 150 overflow: 0.976401 HPWL: 110676803 [NesterovSolve] Iter: 160 overflow: 0.975101 HPWL: 113533106 [NesterovSolve] Iter: 170 overflow: 0.971804 HPWL: 117182924 [NesterovSolve] Iter: 180 overflow: 0.96735 HPWL: 119399228 [NesterovSolve] Iter: 190 overflow: 0.964292 HPWL: 120165690 [NesterovSolve] Iter: 200 overflow: 0.962187 HPWL: 122262991 [NesterovSolve] Iter: 210 overflow: 0.958776 HPWL: 129199761 [NesterovSolve] Iter: 220 overflow: 0.95496 HPWL: 138924197 [NesterovSolve] Iter: 230 overflow: 0.945282 HPWL: 149995824 [NesterovSolve] Iter: 240 overflow: 0.934061 HPWL: 161813746 [NesterovSolve] Iter: 250 overflow: 0.918891 HPWL: 177567756 [NesterovSolve] Iter: 260 overflow: 0.892171 HPWL: 195242312 [NesterovSolve] Iter: 270 overflow: 0.862029 HPWL: 211007793 [NesterovSolve] Iter: 280 overflow: 0.831092 HPWL: 226141550 [NesterovSolve] Iter: 290 overflow: 0.794426 HPWL: 240337866 [NesterovSolve] Iter: 300 overflow: 0.753771 HPWL: 252452894 [NesterovSolve] Iter: 310 overflow: 0.711305 HPWL: 261970837 [NesterovSolve] Iter: 320 overflow: 0.663584 HPWL: 268990076 [NesterovSolve] Iter: 330 overflow: 0.614988 HPWL: 286063253 [NesterovSolve] Iter: 340 overflow: 0.577547 HPWL: 295354800 [NesterovSolve] Iter: 350 overflow: 0.550713 HPWL: 289612266 [NesterovSolve] Iter: 360 overflow: 0.538835 HPWL: 283307432 [NesterovSolve] Iter: 370 overflow: 0.521607 HPWL: 280647967 [NesterovSolve] Iter: 380 overflow: 0.503481 HPWL: 278605790 [NesterovSolve] Iter: 390 overflow: 0.453249 HPWL: 275931027 [NesterovSolve] Iter: 400 overflow: 0.398416 HPWL: 272872388 [NesterovSolve] Iter: 410 overflow: 0.354364 HPWL: 271433471 [NesterovSolve] Iter: 420 overflow: 0.315779 HPWL: 269484710 [NesterovSolve] Iter: 430 overflow: 0.28182 HPWL: 271082485 [NesterovSolve] Iter: 440 overflow: 0.250037 HPWL: 273088649 [NesterovSolve] Iter: 450 overflow: 0.213562 HPWL: 274578155 [NesterovSolve] Iter: 460 overflow: 0.177968 HPWL: 276412564 [NesterovSolve] Iter: 470 overflow: 0.142648 HPWL: 277649984 [NesterovSolve] Iter: 480 overflow: 0.114138 HPWL: 279039612
[NesterovSolve] Finished with Overflow: 0.0988869
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) set IO_PCT 0.2 set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] puts "\[INFO\]: Setting output delay to: $output_delay_value" [INFO]: Setting output delay to: 2.0 puts "\[INFO\]: Setting input delay to: $input_delay_value" [INFO]: Setting input delay to: 2.0 set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] #set rst_indx [lsearch [all_inputs] [get_port resetn]] set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] set all_inputs_wo_clk_rst $all_inputs_wo_clk # correct resetn set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] # TODO set this as parameter set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "\[INFO\]: Setting load to: $cap_load" [INFO]: Setting load to: 0.01765 set_load $cap_load [all_outputs]
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def to /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def
[INFO]: Running Detailed Placement...
=========================================================================== Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 > Developers : SangGi Do, Mingyu Woo =========================================================================== Parsed 10000 number of lines!! Parsed 20000 number of lines!! Parsed 30000 number of lines!! Parsed 40000 number of lines!! Parsed 50000 number of lines!! Parsed 60000 number of lines!! Reading /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef is Done -------------------- INPUT FILES ---------------------------------- benchmark name : placement directory : /project/openlane/DFFRAM/runs/DFFRAM/tmp lef : /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef def : /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def ------------------------------------------------------------------- Parsed 10000 number of lines!! Parsed 20000 number of lines!! Parsed 30000 number of lines!! Parsed 40000 number of lines!! CoreArea: 5520.000000 : 10880.000000 - 744280.000000 : 514080.000000 DieArea: 0.000000 : 0.000000 - 738760.000000 : 503200.000000 Reading /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def is Done -------------------- DESIGN ANALYSIS ------------------------------ total cells : 25507 multi cells : 0 fixed cells : 5230 total nets : 12163 design area : 3.71744e+11 total f_area : 7.46966e+09 total m_area : 2.98322e+11 design util : 81.895 num rows : 185 row height : 2720 ------------------------------------------------------------------- non_group_cell_region_assign done .. - - - - - - - - - - - - - - - - - - - - - - - - non_group_cell_placement done .. - - - - - - - - - - - - - - - - - - - - - - - - Reading /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def is Done
DEF file write success !!
location : /project/openlane/DFFRAM/runs/DFFRAM/results/placement/DFFRAM.placement.def ------------------------------------------------------------------- tasks Wtime Ctime Parser 1.120 1.110 resgin assign 1.124 1.110 pre-placement 1.124 1.110 non Group cell placement 1.215 1.200 All 1.224 1.210 - - - - - EVALUATION - - - - - AVG_displacement : 2936.64 SUM_displacement : 7.49049e+07 MAX_displacement : 49550 - - - - - - - - - - - - - - - -
[ERROR]: during executing: "opendp -lef /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef -def /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def -output_def /project/openlane/DFFRAM/runs/DFFRAM/results/placement/DFFRAM.placement.def |& tee >&@stdout /project/openlane/DFFRAM/runs/DFFRAM/logs/placement/opendp.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: segmentation violation
[ERROR]: Please check opendp log file
[ERROR]: Dumping to /project/openlane/DFFRAM/runs/DFFRAM/error.log
while executing "try_catch opendp -lef $::env(MERGED_LEF) -def $::env(CURRENT_DEF) -output_def $::env(opendp_result_file_tag).def |& tee $::env(TERMINAL_OUTPUT) $:..." (procedure "detailed_placement" line 4) invoked from within "detailed_placement" (procedure "run_placement" line 16) invoked from within "run_placement" (procedure "run_non_interactive_mode" line 13) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { puts_info "Running interactively" if { [info exists arg_values(-file)..." (file "/openLANE_flow/flow.tcl" line 164) make: *** [Makefile:26: DFFRAM] Fehler 1

Submodule: digital_pll

###############################################
/bin/sh: 1: [[: not found
[INFO]: ___ ____ ___ ____ _ ____ ____ ___ / \ | \ / _]| \ | | / || \ / _] | || o ) [_ | _ || | | o || _ | / [_ | O || _/ _]| | || |___ | || | || _] | || | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____|
[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/digital_pll/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/digital_pll/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/digital_pll/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/digital_pll/runs/digital_pll
[WARNING]: Removing exisiting run /project/openlane/digital_pll/runs/digital_pll
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs sky130_fd_sc_hd.lef: SITEs matched found: 0 sky130_fd_sc_hd.lef: MACROs matched found: 437 mergeLef.py : Merging LEFs complete padLefMacro.py : Padding technology lef file Derived SITE width (microns): 0.46 Derived SITE height (microns): 5.44 Right cell padding (microns): 1.84 Left cell padding (microns): 0.0 Top cell padding (microns): 0.0 Bottom cell padding (microns): 0.0 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd2_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_12 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_3 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_6 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_2 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvpwrvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...
/----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. 1. Executing Liberty frontend. Imported 428 cell types from liberty file. 2. Executing Verilog-2005 frontend: /project/openlane/digital_pll/../../verilog/rtl/digital_pll.v Parsing Verilog input from `/project/openlane/digital_pll/../../verilog/rtl/digital_pll.v' to AST representation. Generating RTLIL representation for module `\digital_pll_controller'. Generating RTLIL representation for module `\delay_stage'. Generating RTLIL representation for module `\start_stage'. Generating RTLIL representation for module `\ring_osc2x13'. Generating RTLIL representation for module `\digital_pll'.
Successfully finished Verilog frontend.
3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \digital_pll Used module: \digital_pll_controller Used module: \ring_osc2x13 Used module: \delay_stage Used module: \start_stage 3.2. Analyzing design hierarchy.. Top module: \digital_pll Used module: \digital_pll_controller Used module: \ring_osc2x13 Used module: \delay_stage Used module: \start_stage Removed 0 unused modules. 4. Executing SYNTH pass. 4.1. Executing HIERARCHY pass (managing design hierarchy). 4.1.1. Analyzing design hierarchy.. Top module: \digital_pll Used module: \digital_pll_controller Used module: \ring_osc2x13 Used module: \delay_stage Used module: \start_stage 4.1.2. Analyzing design hierarchy.. Top module: \digital_pll Used module: \digital_pll_controller Used module: \ring_osc2x13 Used module: \delay_stage Used module: \start_stage Removed 0 unused modules. 4.2. Executing PROC pass (convert processes to netlists). 4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 3 switch rules as full_case in process $proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54 in module digital_pll_controller. Removed a total of 0 dead cases. 4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 0 assignments to connections. 4.2.4. Executing PROC_INIT pass (extract init attributes). 4.2.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \reset in `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'. 4.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'. 1/5: $0\oscbuf[2:0] 2/5: $0\tval[6:0] 3/5: $0\count1[4:0] 4/5: $0\count0[4:0] 5/5: $0\prep[2:0] 4.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). 4.2.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\digital_pll_controller.\oscbuf' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'. created $adff cell `$procdff$98' with positive edge clock and positive level reset. Creating register for signal `\digital_pll_controller.\prep' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'. created $adff cell `$procdff$99' with positive edge clock and positive level reset. Creating register for signal `\digital_pll_controller.\count0' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'. created $adff cell `$procdff$100' with positive edge clock and positive level reset. Creating register for signal `\digital_pll_controller.\count1' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'. created $adff cell `$procdff$101' with positive edge clock and positive level reset. Creating register for signal `\digital_pll_controller.\tval' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'. created $adff cell `$procdff$102' with positive edge clock and positive level reset. 4.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 7 empty switches in `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'. Removing empty process `digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'. Cleaned up 7 empty switches. 4.3. Executing FLATTEN pass (flatten design). Deleting now unused module ring_osc2x13. Deleting now unused module start_stage. Deleting now unused module delay_stage. Deleting now unused module digital_pll_controller. 4.4. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 2 unused cells and 23 unused wires. 4.6. Executing CHECK pass (checking for obvious problems). checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:
port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:
port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8) port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:
port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:
port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:
port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:
port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:
port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:
port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:
port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:
port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:
port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:
port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:
port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:
port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:
port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:
port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:
port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:
port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:
port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:
port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:
port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:
port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:
port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:
port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:
port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:
port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8) found and reported 26 problems. 4.7. Executing OPT pass (performing simple optimizations). 4.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \digital_pll.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \digital_pll. Performed a total of 0 changes. 4.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.7.6. Executing OPT_DFF pass (perform DFF optimizations). 4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. 4.7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll.
4.7.9. Finished OPT passes. (There is nothing left to do.)
4.8. Executing FSM pass (extract and optimize FSM). 4.8.1. Executing FSM_DETECT pass (finding FSMs in design). 4.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). 4.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). 4.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. 4.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). 4.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 4.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 4.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 4.9. Executing OPT pass (performing simple optimizations). 4.9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \digital_pll.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \digital_pll. Performed a total of 0 changes. 4.9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.9.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\pll_control.$procdff$99 ($adff) from module digital_pll (D = { \pll_control.prep [1:0] 1'1 }, Q = \pll_control.prep). Adding EN signal on $flatten\pll_control.$procdff$102 ($adff) from module digital_pll (D = $flatten\pll_control.$procmux$81_Y, Q = \pll_control.tval). Adding EN signal on $flatten\pll_control.$procdff$101 ($adff) from module digital_pll (D = \pll_control.count0, Q = \pll_control.count1). Adding EN signal on $flatten\pll_control.$procdff$100 ($adff) from module digital_pll (D = $flatten\pll_control.$0\count0[4:0], Q = \pll_control.count0). 4.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 4 unused cells and 4 unused wires. 4.9.8. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.9.9. Rerunning OPT passes. (Maybe there is more to do..) 4.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \digital_pll.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \digital_pll. Performed a total of 0 changes. 4.9.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.9.13. Executing OPT_DFF pass (perform DFF optimizations). 4.9.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. 4.9.15. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll.
4.9.16. Finished OPT passes. (There is nothing left to do.)
4.10. Executing WREDUCE pass (reducing word size of cells). Removed top 1 bits (of 3) from port B of cell digital_pll.$auto$opt_dff.cc:218:make_patterns_logic$105 ($ne). Removed cell digital_pll.$flatten\pll_control.$procmux$90 ($mux). Removed cell digital_pll.$flatten\pll_control.$procmux$79 ($mux). Removed cell digital_pll.$flatten\pll_control.$procmux$76 ($mux). Removed cell digital_pll.$flatten\pll_control.$procmux$74 ($mux). Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add). Removed top 27 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add). Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub). Removed top 25 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub). Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62 ($gt). Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add). Removed top 25 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add). Removed top 25 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59 ($lt). Removed top 5 bits (of 26) from mux cell digital_pll.$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28 ($mux). Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$17 ($eq). Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$16 ($eq). Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$15 ($eq). Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$14 ($eq). Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$13 ($eq). Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$12 ($eq). Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$11 ($eq). Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$10 ($eq). Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$9 ($eq). Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$8 ($eq). Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$7 ($eq). Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$6 ($eq). Removed top 3 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$5 ($eq). Removed top 3 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$4 ($eq). Removed top 4 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$3 ($eq). Removed top 5 bits (of 26) from wire digital_pll.$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28_Y. 4.11. Executing PEEPOPT pass (run peephole optimizers). 4.12. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 0 unused cells and 5 unused wires. 4.13. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module digital_pll: creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add). creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add). creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1 ($add). creating $macc model for $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub). creating $alu model for $macc $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63. creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1. creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65. creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60. creating $alu model for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58 ($gt): new $alu creating $alu model for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62 ($gt): new $alu creating $alu model for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59 ($lt): new $alu creating $alu model for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:106$61 ($lt): merged with $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58. creating $alu cell for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59: $auto$alumacc.cc:485:replace_alu$121 creating $alu cell for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62: $auto$alumacc.cc:485:replace_alu$126 creating $alu cell for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58, $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:106$61: $auto$alumacc.cc:485:replace_alu$131 creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60: $auto$alumacc.cc:485:replace_alu$142 creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65: $auto$alumacc.cc:485:replace_alu$145 creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1: $auto$alumacc.cc:485:replace_alu$148 creating $alu cell for $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63: $auto$alumacc.cc:485:replace_alu$151 created 7 $alu and 0 $macc cells. 4.14. Executing SHARE pass (SAT-based resource sharing). 4.15. Executing OPT pass (performing simple optimizations). 4.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \digital_pll.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \digital_pll. Performed a total of 0 changes. 4.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.15.6. Executing OPT_DFF pass (perform DFF optimizations). 4.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 0 unused cells and 4 unused wires. 4.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.15.9. Rerunning OPT passes. (Maybe there is more to do..) 4.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \digital_pll.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \digital_pll. Performed a total of 0 changes. 4.15.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.15.13. Executing OPT_DFF pass (perform DFF optimizations). 4.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. 4.15.15. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll.
4.15.16. Finished OPT passes. (There is nothing left to do.)
4.16. Executing MEMORY pass. 4.16.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 4.16.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. 4.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.16.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. 4.16.6. Executing MEMORY_COLLECT pass (generating $mem cells). 4.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. 4.18. Executing OPT pass (performing simple optimizations). 4.18.1. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.18.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.18.3. Executing OPT_DFF pass (perform DFF optimizations). 4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll..
4.18.5. Finished fast OPT passes.
4.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 4.20. Executing OPT pass (performing simple optimizations). 4.20.1. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.20.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \digital_pll.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29: Old ports: A={ 5'11111 $auto$wreduce.cc:454:run$117 [20:0] }, B=26'11111011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y New ports: A=$auto$wreduce.cc:454:run$117 [20:0], B=21'011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0] New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [25:21] = 5'11111 Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28: Old ports: A=21'111111111111111111111, B=21'011111111111111111111, Y=$auto$wreduce.cc:454:run$117 [20:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$117 [20] New connections: $auto$wreduce.cc:454:run$117 [19:0] = 20'11111111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y, B=26'10111011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0] }, B=22'0011111011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [23:21] } = 4'1111 Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29: Old ports: A=$auto$wreduce.cc:454:run$117 [20:0], B=21'011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0] New ports: A={ $auto$wreduce.cc:454:run$117 [20] 1'1 }, B=2'00, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [14] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [19:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [13:0] } = 19'1111111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y, B=26'10111011011011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }, B=22'0011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [23:21] } = 4'1111 Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30: Old ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0] }, B=22'0011111011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] } New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [14] }, B=3'000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [14] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [19:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [13:0] } = 19'1111111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y, B=26'10101011011011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }, B=23'00011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [21] } = 3'111 Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31: Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }, B=22'0011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] } New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [14] }, B=4'0000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [14] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [16:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [13:0] } = 18'111111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y, B=26'10101011010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }, B=23'00011010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [21] } = 3'111 Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32: Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }, B=23'00011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] } New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [14] }, B=5'00000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [14] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [16:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [13:0] } = 18'111111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y, B=26'10101010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }, B=23'00010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [21] } = 3'111 Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33: Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }, B=23'00011010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] } New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [17] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [14] }, B=6'000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [15:14] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [13:0] } = 17'11111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y, B=26'00101010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }, B=24'000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [21] } = 2'11 Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34: Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }, B=23'00010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] } New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [15:14] }, B=7'0000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [15:14] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [13:0] } = 16'1111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y, B=26'00100010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }, B=25'0000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] } New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [23] = 1'1 Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35: Old ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }, B=24'000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] } New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [15:14] }, B=8'00000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [15:14] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [13:0] } = 16'1111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y, B=26'00100010000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }, B=25'0000010000011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:0] } New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [23] = 1'1 Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36: Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }, B=25'0000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] } New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [15:14] }, B=9'000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [15:14] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [13:0] } = 16'1111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37: Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }, B=25'0000010000011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:0] } New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [18:17] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [15:14] }, B=10'0000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [18:14] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [13:0] } = 15'111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y, B=26'00000010000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [18:14] }, B=11'00000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [25:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [18:14] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [13:0] } = 15'111111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y, B=26'00000000000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [25:20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [18:14] }, B=12'000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [25:14] New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [13:0] = 14'11111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y, B=26'00000000000001111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [25:14] 1'1 }, B=13'0000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [25:13] New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [12:0] = 13'1111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y, B=26'00000000000001111101111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [25:13] 1'1 }, B=14'00000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [7] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [12:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [6:0] } = 12'111111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y, B=26'00000000000001111101111101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [7] 1'1 }, B=15'000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [1] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [12:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [6:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [0] } = 11'11111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y, B=26'00000000000001011101111101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [25:13] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [1] }, B=16'0000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [1] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [10:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [6:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [0] } = 10'1111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y, B=26'00000000000001011101101101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [1] }, B=17'00000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [1] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [10:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [3:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [0] } = 9'111111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y, B=26'00000000000001010101101101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [11] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [1] }, B=18'000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [1] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [3:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [0] } = 8'11111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y, B=26'00000000000001010101101001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [4] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [1] }, B=19'0000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [2:1] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [0] } = 7'1111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y, B=26'00000000000001010101001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [2:1] }, B=20'00000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [2:1] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [0] } = 6'111111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y, B=26'00000000000000010101001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [25:13] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [2:1] }, B=21'000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [2:1] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [0] } = 5'11111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y, B=26'00000000000000010001001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [9] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [2:1] }, B=22'0000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [2:1] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [0] } = 4'1111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y, B=26'00000000000000010001000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [5:4] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [2:1] }, B=23'00000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [5:1] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [0] } = 3'111 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y, B=26'00000000000000000001000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [25:11] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [5:1] }, B=24'000000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [25:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [5:1] } New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [0] } = 2'11 Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52: Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y, B=26'00000000000000000000000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [25:7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [5:1] }, B=25'0000000000000000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y [25:1] New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y [0] = 1'1 Optimizing cells in module \digital_pll. Performed a total of 34 changes. 4.20.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.20.6. Executing OPT_SHARE pass. Found cells that share an operand and can be merged by moving the $mux $flatten\pll_control.$procmux$81 in front of them: $auto$alumacc.cc:485:replace_alu$151 $auto$alumacc.cc:485:replace_alu$142 4.20.7. Executing OPT_DFF pass (perform DFF optimizations). 4.20.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 0 unused cells and 6 unused wires. 4.20.9. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.20.10. Rerunning OPT passes. (Maybe there is more to do..) 4.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \digital_pll.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \digital_pll. Consolidated identical input bits for $mux cell $auto$opt_share.cc:241:merge_operators$157: Old ports: A=$auto$rtlil.cc:2123:Neg$155, B=7'0000001, Y=$auto$rtlil.cc:2218:Mux$158 New ports: A=1'1, B=1'0, Y=$auto$rtlil.cc:2218:Mux$158 [1] New connections: { $auto$rtlil.cc:2218:Mux$158 [6:2] $auto$rtlil.cc:2218:Mux$158 [0] } = { $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] 1'1 } Optimizing cells in module \digital_pll. Performed a total of 1 changes. 4.20.13. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.20.14. Executing OPT_SHARE pass. 4.20.15. Executing OPT_DFF pass (perform DFF optimizations). 4.20.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 0 unused cells and 2 unused wires. 4.20.17. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.20.18. Rerunning OPT passes. (Maybe there is more to do..) 4.20.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \digital_pll.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.20.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \digital_pll. Performed a total of 0 changes. 4.20.21. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 1 cells. 4.20.22. Executing OPT_SHARE pass. 4.20.23. Executing OPT_DFF pass (perform DFF optimizations). 4.20.24. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 0 unused cells and 1 unused wires. 4.20.25. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.20.26. Rerunning OPT passes. (Maybe there is more to do..) 4.20.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \digital_pll.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.20.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \digital_pll. Performed a total of 0 changes. 4.20.29. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.20.30. Executing OPT_SHARE pass. 4.20.31. Executing OPT_DFF pass (perform DFF optimizations). 4.20.32. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. 4.20.33. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll.
4.20.34. Finished OPT passes. (There is nothing left to do.)
4.21. Executing TECHMAP pass (map to technology primitives). 4.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
4.21.2. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu. Using extmapper simplemap for cells of type $adffe. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $adff. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $and. Using template $paramod\_90_lcu\WIDTH=7 for cells of type $lcu. Using template $paramod\_90_lcu\WIDTH=6 for cells of type $lcu. Using template $paramod\_90_lcu\WIDTH=5 for cells of type $lcu. No more expansions possible. 4.22. Executing OPT pass (performing simple optimizations). 4.22.1. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.22.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 121 cells. 4.22.3. Executing OPT_DFF pass (perform DFF optimizations). 4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 61 unused cells and 376 unused wires.
4.22.5. Finished fast OPT passes.
4.23. Executing ABC pass (technology mapping using ABC). 4.23.1. Extracting gate netlist of module `\digital_pll' to `/input.blif'.. Extracted 556 gates and 614 wires to a netlist network with 56 inputs and 43 outputs. 4.23.1.1. Executing ABC. Running ABC command: /yosys-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: Entered genlib library with 13 gates from file "/stdcells.genlib". ABC: + strash ABC: + dretime ABC: + map ABC: + write_blif /output.blif 4.23.1.2. Re-integrating ABC results. ABC RESULTS: AND cells: 4 ABC RESULTS: ANDNOT cells: 89 ABC RESULTS: MUX cells: 27 ABC RESULTS: NAND cells: 17 ABC RESULTS: NOR cells: 11 ABC RESULTS: NOT cells: 6 ABC RESULTS: OR cells: 331 ABC RESULTS: ORNOT cells: 10 ABC RESULTS: XNOR cells: 12 ABC RESULTS: XOR cells: 19 ABC RESULTS: internal signals: 515 ABC RESULTS: input signals: 56 ABC RESULTS: output signals: 43 Removing temp directory. 4.24. Executing OPT pass (performing simple optimizations). 4.24.1. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 4.24.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 4.24.3. Executing OPT_DFF pass (perform DFF optimizations). 4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 0 unused cells and 242 unused wires.
4.24.5. Finished fast OPT passes.
4.25. Executing HIERARCHY pass (managing design hierarchy). 4.25.1. Analyzing design hierarchy.. Top module: \digital_pll 4.25.2. Analyzing design hierarchy.. Top module: \digital_pll Removed 0 unused modules. 4.26. Printing statistics. === digital_pll === Number of wires: 613 Number of wire bits: 808 Number of public wires: 120 Number of public wire bits: 303 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 646 $_ANDNOT_ 89 $_AND_ 4 $_DFFE_PP0N_ 8 $_DFFE_PP0P_ 12 $_DFF_PP0_ 3 $_MUX_ 27 $_NAND_ 17 $_NOR_ 11 $_NOT_ 6 $_ORNOT_ 10 $_OR_ 331 $_XNOR_ 12 $_XOR_ 19 sky130_fd_sc_hd__clkbuf_1 13 sky130_fd_sc_hd__clkbuf_2 12 sky130_fd_sc_hd__clkinv_1 13 sky130_fd_sc_hd__clkinv_2 2 sky130_fd_sc_hd__clkinv_8 2 sky130_fd_sc_hd__conb_1 1 sky130_fd_sc_hd__einvn_4 13 sky130_fd_sc_hd__einvn_8 13 sky130_fd_sc_hd__einvp_1 1 sky130_fd_sc_hd__einvp_2 26 sky130_fd_sc_hd__or2_2 1 4.27. Executing CHECK pass (checking for obvious problems). checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:
port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:
port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8) port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:
port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:
port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:
port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:
port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:
port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:
port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:
port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:
port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:
port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:
port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:
port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:
port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:
port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:
port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:
port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:
port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:
port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:
port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:
port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:
port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:
port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:
port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:
port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:
port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8) found and reported 26 problems. 5. Executing SHARE pass (SAT-based resource sharing). 6. Executing OPT pass (performing simple optimizations). 6.1. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll. 6.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \digital_pll.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \digital_pll. Performed a total of 0 changes. 6.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\digital_pll'. Removed a total of 0 cells. 6.6. Executing OPT_DFF pass (perform DFF optimizations). 6.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. 6.8. Executing OPT_EXPR pass (perform const folding). Optimizing module digital_pll.
6.9. Finished OPT passes. (There is nothing left to do.)
7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 0 unused cells and 24 unused wires. 8. Printing statistics. === digital_pll === Number of wires: 589 Number of wire bits: 667 Number of public wires: 96 Number of public wire bits: 162 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 646 $_ANDNOT_ 89 $_AND_ 4 $_DFFE_PP0N_ 8 $_DFFE_PP0P_ 12 $_DFF_PP0_ 3 $_MUX_ 27 $_NAND_ 17 $_NOR_ 11 $_NOT_ 6 $_ORNOT_ 10 $_OR_ 331 $_XNOR_ 12 $_XOR_ 19 sky130_fd_sc_hd__clkbuf_1 13 sky130_fd_sc_hd__clkbuf_2 12 sky130_fd_sc_hd__clkinv_1 13 sky130_fd_sc_hd__clkinv_2 2 sky130_fd_sc_hd__clkinv_8 2 sky130_fd_sc_hd__conb_1 1 sky130_fd_sc_hd__einvn_4 13 sky130_fd_sc_hd__einvn_8 13 sky130_fd_sc_hd__einvp_1 1 sky130_fd_sc_hd__einvp_2 26 sky130_fd_sc_hd__or2_2 1 9. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_. cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_. cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_. cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_. final dff cell mappings: unmapped dff cell: $_DFF_N_ \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q)); unmapped dff cell: $_DFF_NN0_ unmapped dff cell: $_DFF_NN1_ unmapped dff cell: $_DFF_NP0_ unmapped dff cell: $_DFF_NP1_ \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R)); \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R)); unmapped dff cell: $_DFF_PP0_ unmapped dff cell: $_DFF_PP1_ \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); unmapped dff cell: $_DFFSR_NNP_ unmapped dff cell: $_DFFSR_NPN_ unmapped dff cell: $_DFFSR_NPP_ unmapped dff cell: $_DFFSR_PNN_ unmapped dff cell: $_DFFSR_PNP_ unmapped dff cell: $_DFFSR_PPN_ unmapped dff cell: $_DFFSR_PPP_ 9.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Mapping DFF cells in module `\digital_pll': mapped 23 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells. 10. Printing statistics. [INFO]: ABC: WireLoad : S_2 === digital_pll === Number of wires: 632 Number of wire bits: 710 Number of public wires: 96 Number of public wire bits: 162 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 689 $_ANDNOT_ 89 $_AND_ 4 $_MUX_ 47 $_NAND_ 17 $_NOR_ 11 $_NOT_ 29 $_ORNOT_ 10 $_OR_ 331 $_XNOR_ 12 $_XOR_ 19 sky130_fd_sc_hd__clkbuf_1 13 sky130_fd_sc_hd__clkbuf_2 12 sky130_fd_sc_hd__clkinv_1 13 sky130_fd_sc_hd__clkinv_2 2 sky130_fd_sc_hd__clkinv_8 2 sky130_fd_sc_hd__conb_1 1 sky130_fd_sc_hd__dfrtp_4 23 sky130_fd_sc_hd__einvn_4 13 sky130_fd_sc_hd__einvn_8 13 sky130_fd_sc_hd__einvp_1 1 sky130_fd_sc_hd__einvp_2 26 sky130_fd_sc_hd__or2_2 1 11. Executing ABC pass (technology mapping using ABC). 11.1. Extracting gate netlist of module `\digital_pll' to `/tmp/yosys-abc-LXniTP/input.blif'.. Extracted 569 gates and 626 wires to a netlist network with 56 inputs and 70 outputs. 11.1.1. Executing ABC. Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-LXniTP/abc.script 2>&1 ABC: ABC command line: "source /tmp/yosys-abc-LXniTP/abc.script". ABC: ABC: + read_blif /tmp/yosys-abc-LXniTP/input.blif ABC: + read_lib -w /project/openlane/digital_pll/runs/digital_pll/tmp/trimmed.lib
ABC: Parsing finished successfully. Parsing time = 0.06 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/digital_pll/runs/digital_pll/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.08 sec ABC: Memory = 1.92 MB. Time = 0.08 sec ABC: + read_constr -v /project/openlane/digital_pll/runs/digital_pll/tmp/synthesis/yosys.sdc ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8". ABC: Setting output load to be 17.650000. ABC: + read_constr /project/openlane/digital_pll/runs/digital_pll/tmp/synthesis/yosys.sdc ABC: + fx ABC: + mfs ABC: + strash ABC: + refactor ABC: + balance ABC: + rewrite ABC: + refactor ABC: + balance ABC: + rewrite ABC: + rewrite -z ABC: + balance ABC: + refactor -z ABC: + rewrite -z ABC: + balance ABC: + retime -D -D 10000 -M 5 ABC: + scleanup
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 ABC: + retime -D -D 10000 ABC: + ABC: + stime -p ABC: WireLoad = "none" Gates = 270 ( 20.7 %) Cap = 13.9 ff ( 0.0 %) Area = 3324.44 (100.0 %) Delay = 3638.60 ps ( 8.1 %) ABC: Path 0 -- 7 : 0 3 pi A = 0.00 Df = 27.5 -17.7 ps S = 45.0 ps Cin = 0.0 ff Cout = 23.6 ff Cmax = 0.0 ff G = 0 ABC: Path 1 -- 133 : 1 5 sky130_fd_sc_hd__inv_8 A = 11.26 Df = 60.8 -2.8 ps S = 44.0 ps Cin = 17.7 ff Cout = 22.9 ff Cmax =1035.5 ff G = 123 ABC: Path 2 -- 170 : 4 2 sky130_fd_sc_hd__o22a_4 A = 17.52 Df = 517.5 -65.9 ps S = 80.4 ps Cin = 4.6 ff Cout = 22.0 ff Cmax = 530.1 ff G = 461 ABC: Path 3 -- 171 : 4 3 sky130_fd_sc_hd__o22a_4 A = 17.52 Df = 720.7 -118.1 ps S = 58.3 ps Cin = 4.6 ff Cout = 13.8 ff Cmax = 530.1 ff G = 286 ABC: Path 4 -- 172 : 4 3 sky130_fd_sc_hd__a2bb2o_4 A = 20.02 Df = 945.1 -0.3 ps S = 73.9 ps Cin = 4.6 ff Cout = 19.1 ff Cmax = 502.6 ff G = 388 ABC: Path 5 -- 176 : 3 2 sky130_fd_sc_hd__a21bo_4 A = 16.27 Df =1163.4 -87.3 ps S = 48.1 ps Cin = 3.9 ff Cout = 9.5 ff Cmax = 475.2 ff G = 231 ABC: Path 6 -- 178 : 4 2 sky130_fd_sc_hd__a211o_4 A = 17.52 Df =1466.3 -257.2 ps S = 92.2 ps Cin = 4.6 ff Cout = 27.6 ff Cmax = 559.4 ff G = 570 ABC: Path 7 -- 179 : 1 1 sky130_fd_sc_hd__inv_8 A = 11.26 Df =1519.7 -284.1 ps S = 27.9 ps Cin = 17.7 ff Cout = 4.7 ff Cmax =1035.5 ff G = 25 ABC: Path 8 -- 180 : 3 1 sky130_fd_sc_hd__o21a_4 A = 15.01 Df =1634.2 -293.6 ps S = 47.3 ps Cin = 4.6 ff Cout = 9.0 ff Cmax = 510.0 ff G = 182 ABC: Path 9 -- 186 : 3 1 sky130_fd_sc_hd__nor3_4 A = 16.27 Df =1663.8 -205.4 ps S = 106.7 ps Cin = 8.7 ff Cout = 2.5 ff Cmax = 153.8 ff G = 27 ABC: Path 10 -- 189 : 2 10 sky130_fd_sc_hd__or2_4 A = 8.76 Df =1987.6 -274.2 ps S = 202.1 ps Cin = 2.4 ff Cout = 64.6 ff Cmax = 514.5 ff G = 2551 ABC: Path 11 -- 207 : 3 3 sky130_fd_sc_hd__o21ai_4 A = 16.27 Df =2390.9 -7.7 ps S = 170.3 ps Cin = 8.8 ff Cout = 16.1 ff Cmax = 224.3 ff G = 175 ABC: Path 12 -- 215 : 5 3 sky130_fd_sc_hd__a32o_4 A = 21.27 Df =2729.1 -98.3 ps S = 79.2 ps Cin = 4.3 ff Cout = 16.1 ff Cmax = 536.5 ff G = 355 ABC: Path 13 -- 219 : 5 2 sky130_fd_sc_hd__a32o_4 A = 21.27 Df =3056.4 -210.9 ps S = 66.1 ps Cin = 4.3 ff Cout = 11.3 ff Cmax = 536.5 ff G = 252 ABC: Path 14 -- 221 : 2 1 sky130_fd_sc_hd__or2_4 A = 8.76 Df =3301.2 -342.4 ps S = 46.3 ps Cin = 2.4 ff Cout = 4.7 ff Cmax = 514.5 ff G = 186 ABC: Path 15 -- 223 : 5 1 sky130_fd_sc_hd__a32o_4 A = 21.27 Df =3638.6 -310.4 ps S = 83.1 ps Cin = 4.3 ff Cout = 17.6 ff Cmax = 536.5 ff G = 407 ABC: Start-point = pi6 (\pll_control.count0 [1]). End-point = po16 ($auto$rtlil.cc:2290:MuxGate$2331). ABC: + print_stats -m ABC: netlist : i/o = 56/ 70 lat = 0 nd = 270 edge = 709 area =3324.55 delay =20.00 lev = 20 ABC: + write_blif /tmp/yosys-abc-LXniTP/output.blif 11.1.2. Re-integrating ABC results. ABC RESULTS: sky130_fd_sc_hd__a211o_4 cells: 4 ABC RESULTS: sky130_fd_sc_hd__a21bo_4 cells: 21 ABC RESULTS: sky130_fd_sc_hd__a21o_4 cells: 4 ABC RESULTS: sky130_fd_sc_hd__a21oi_4 cells: 2 ABC RESULTS: sky130_fd_sc_hd__a2bb2o_4 cells: 13 ABC RESULTS: sky130_fd_sc_hd__a32o_4 cells: 10 ABC RESULTS: sky130_fd_sc_hd__and2_4 cells: 11 ABC RESULTS: sky130_fd_sc_hd__and3_4 cells: 3 ABC RESULTS: sky130_fd_sc_hd__and4_4 cells: 21 ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 22 ABC RESULTS: sky130_fd_sc_hd__inv_8 cells: 34 ABC RESULTS: sky130_fd_sc_hd__nand2_4 cells: 8 ABC RESULTS: sky130_fd_sc_hd__nand4_4 cells: 1 ABC RESULTS: sky130_fd_sc_hd__nor2_4 cells: 5 ABC RESULTS: sky130_fd_sc_hd__nor3_4 cells: 6 ABC RESULTS: sky130_fd_sc_hd__nor4_4 cells: 3 ABC RESULTS: sky130_fd_sc_hd__o21a_4 cells: 7 ABC RESULTS: sky130_fd_sc_hd__o21ai_4 cells: 5 ABC RESULTS: sky130_fd_sc_hd__o22a_4 cells: 11 ABC RESULTS: sky130_fd_sc_hd__o32a_4 cells: 2 ABC RESULTS: sky130_fd_sc_hd__or2_4 cells: 55 ABC RESULTS: sky130_fd_sc_hd__or3_4 cells: 5 ABC RESULTS: sky130_fd_sc_hd__or4_4 cells: 15 ABC RESULTS: sky130_fd_sc_hd__xnor2_4 cells: 1 ABC RESULTS: sky130_fd_sc_hd__xor2_4 cells: 1 ABC RESULTS: internal signals: 500 ABC RESULTS: input signals: 56 ABC RESULTS: output signals: 70 Removing temp directory. 12. Executing SETUNDEF pass (replace undef values with defined constants). 13. Executing HILOMAP pass (mapping to constant drivers). 14. Executing SPLITNETS pass (splitting up multi-bit signals). 15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \digital_pll.. Removed 0 unused cells and 637 unused wires. 16. Executing INSBUF pass (insert buffer cells for connected wires). Added digital_pll.$auto$insbuf.cc:79:execute$2637: \pll_control.clock -> \clockp [0] 17. Executing CHECK pass (checking for obvious problems). checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:
port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:
port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8) port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:
port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:
port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:
port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:
port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:
port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:
port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:
port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:
port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:
port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:
port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:
port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:
port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:
port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:
port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:
port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:
port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:
port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:
port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:
port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:
port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:
port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:
port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:
port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:
port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2) port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8) found and reported 26 problems. 18. Printing statistics. === digital_pll === Number of wires: 369 Number of wire bits: 399 Number of public wires: 126 Number of public wire bits: 156 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 391 sky130_fd_sc_hd__a211o_4 4 sky130_fd_sc_hd__a21bo_4 21 sky130_fd_sc_hd__a21o_4 4 sky130_fd_sc_hd__a21oi_4 2 sky130_fd_sc_hd__a2bb2o_4 13 sky130_fd_sc_hd__a32o_4 10 sky130_fd_sc_hd__and2_4 11 sky130_fd_sc_hd__and3_4 3 sky130_fd_sc_hd__and4_4 21 sky130_fd_sc_hd__buf_1 22 sky130_fd_sc_hd__buf_2 1 sky130_fd_sc_hd__clkbuf_1 13 sky130_fd_sc_hd__clkbuf_2 12 sky130_fd_sc_hd__clkinv_1 13 sky130_fd_sc_hd__clkinv_2 2 sky130_fd_sc_hd__clkinv_8 2 sky130_fd_sc_hd__conb_1 1 sky130_fd_sc_hd__dfrtp_4 23 sky130_fd_sc_hd__einvn_4 13 sky130_fd_sc_hd__einvn_8 13 sky130_fd_sc_hd__einvp_1 1 sky130_fd_sc_hd__einvp_2 26 sky130_fd_sc_hd__inv_8 34 sky130_fd_sc_hd__nand2_4 8 sky130_fd_sc_hd__nand4_4 1 sky130_fd_sc_hd__nor2_4 5 sky130_fd_sc_hd__nor3_4 6 sky130_fd_sc_hd__nor4_4 3 sky130_fd_sc_hd__o21a_4 7 sky130_fd_sc_hd__o21ai_4 5 sky130_fd_sc_hd__o22a_4 11 sky130_fd_sc_hd__o32a_4 2 sky130_fd_sc_hd__or2_2 1 sky130_fd_sc_hd__or2_4 55 sky130_fd_sc_hd__or3_4 5 sky130_fd_sc_hd__or4_4 15 sky130_fd_sc_hd__xnor2_4 1 sky130_fd_sc_hd__xor2_4 1 Area for cell type \sky130_fd_sc_hd__buf_2 is unknown! Area for cell type \sky130_fd_sc_hd__clkbuf_1 is unknown! Area for cell type \sky130_fd_sc_hd__clkbuf_2 is unknown! Area for cell type \sky130_fd_sc_hd__clkinv_1 is unknown! Area for cell type \sky130_fd_sc_hd__clkinv_2 is unknown! Area for cell type \sky130_fd_sc_hd__clkinv_8 is unknown! Area for cell type \sky130_fd_sc_hd__einvn_4 is unknown! Area for cell type \sky130_fd_sc_hd__einvn_8 is unknown! Area for cell type \sky130_fd_sc_hd__einvp_1 is unknown! Area for cell type \sky130_fd_sc_hd__einvp_2 is unknown! Area for cell type \sky130_fd_sc_hd__or2_2 is unknown! Chip area for module '\digital_pll': 3990.076800 19. Executing Verilog backend. Dumping module `\digital_pll'.
Warnings: 26 unique messages, 78 total
End of script. Logfile hash: 835af948d2, CPU: user 3.12s system 0.08s, MEM: 43.74 MB peak Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) Time spent: 45% 2x abc (2 sec), 10% 2x read_liberty (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc. License GPLv3: GNU GPL version 3 This is free software, and you are free to change and redistribute it under certain conditions; type `show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
tns 0.00 wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Info: Added 43 rows of 254 sites. [INFO] Extracting DIE_AREA and CORE_AREA from the floorplan [INFO] Floorplanned on a die area of 0.0 0.0 128.205 138.925 (microns). Saving to /project/openlane/digital_pll/runs/digital_pll/reports/floorplan/verilog2def.die_area.rpt. [INFO] Floorplanned on a core area of 5.52 10.88 122.36 127.84 (microns). Saving to /project/openlane/digital_pll/runs/digital_pll/reports/floorplan/verilog2def.core_area.rpt.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 116.84
[INFO]: Core area height: 116.96000000000001
[INFO]: Changing layout from 0 to /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def
[INFO]: Running IO Placement...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
Notice 0: Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def Notice 0: Design: digital_pll Notice 0: Created 37 pins. Notice 0: Created 391 components and 2103 component-terminals. Notice 0: Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def
#Macro blocks found: 0
Warning: using the default boundaries offset (5 microns)
Warning: using the default min distance between IO pins (2 tracks)
WARNING: force pin spread option has no effect when using random pin placement
> Running IO placement * Num of slots 458 * Num of I/O 37 * Num of I/O w/sink 37 * Num of I/O w/o sink 0 * Slots Per Section 200 * Slots Increase Factor 0.01 * Usage Per Section 0.8 * Usage Increase Factor 0.01 * Force Pin Spread 1
WARNING: running random pin placement
RandomMode Even > IO placement done.
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def to /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def Notice 0: Design: digital_pll Notice 0: Created 37 pins. Notice 0: Created 391 components and 2103 component-terminals. Notice 0: Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def
Running tapcell... Step 1: Cut rows... [INFO] Macro blocks found: 0 [INFO] #Original rows: 43 [INFO] #Cut rows: 0 Step 2: Insert endcaps... [INFO] #Endcaps inserted: 86 Step 3: Insert tapcells... [INFO] #Tapcells inserted: 180 Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def to /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def
[INFO]: Running Placement...
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def Notice 0: Design: digital_pll Notice 0: Created 37 pins. Notice 0: Created 657 components and 2635 component-terminals. Notice 0: Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def
[INFO] DBU = 1000 [INFO] SiteSize = (460, 2720) [INFO] CoreAreaLxLy = (5520, 10880) [INFO] CoreAreaUxUy = (122360, 127840) [INFO] NumInstances = 657 [INFO] NumPlaceInstances = 391 [INFO] NumFixedInstances = 266 [INFO] NumDummyInstances = 0 [INFO] NumNets = 399 [INFO] NumPins = 1357 [INFO] DieAreaLxLy = (0, 0) [INFO] DieAreaUxUy = (128205, 138925) [INFO] CoreAreaLxLy = (5520, 10880) [INFO] CoreAreaUxUy = (122360, 127840) [INFO] CoreArea = 13665606400 [INFO] NonPlaceInstsArea = 548025600 [INFO] PlaceInstsArea = 4907206400 [INFO] Util(%) = 37.409386 [INFO] StdInstsArea = 4907206400 [INFO] MacroInstsArea = 0
[InitialPlace] Iter: 1 CG Error: 9.07291e-08 HPWL: 8510935
[InitialPlace] Iter: 2 CG Error: 1.08554e-07 HPWL: 7551106
[InitialPlace] Iter: 3 CG Error: 3.58893e-08 HPWL: 7577907
[InitialPlace] Iter: 4 CG Error: 7.62758e-08 HPWL: 7586893
[InitialPlace] Iter: 5 CG Error: 9.26014e-08 HPWL: 7594502
[INFO] FillerInit: NumGCells = 581 [INFO] FillerInit: NumGNets = 399 [INFO] FillerInit: NumGPins = 1357 [INFO] TargetDensity = 0.550000 [INFO] AveragePlaceInstArea = 12550400 [INFO] IdealBinArea = 22818908 [INFO] IdealBinCnt = 598 [INFO] TotalBinArea = 13665606400 [INFO] BinCnt = (16, 16) [INFO] BinSize = (7303, 7310) [INFO] NumBins = 256 [NesterovSolve] Iter: 1 overflow: 0.829049 HPWL: 5120479 [NesterovSolve] Iter: 10 overflow: 0.659243 HPWL: 6422500 [NesterovSolve] Iter: 20 overflow: 0.645066 HPWL: 6376095 [NesterovSolve] Iter: 30 overflow: 0.639655 HPWL: 6359602 [NesterovSolve] Iter: 40 overflow: 0.639009 HPWL: 6355749 [NesterovSolve] Iter: 50 overflow: 0.639255 HPWL: 6356390 [NesterovSolve] Iter: 60 overflow: 0.639833 HPWL: 6356298 [NesterovSolve] Iter: 70 overflow: 0.639345 HPWL: 6354037 [NesterovSolve] Iter: 80 overflow: 0.638459 HPWL: 6354082 [NesterovSolve] Iter: 90 overflow: 0.63835 HPWL: 6354720 [NesterovSolve] Iter: 100 overflow: 0.638407 HPWL: 6354278 [NesterovSolve] Iter: 110 overflow: 0.638583 HPWL: 6354843 [NesterovSolve] Iter: 120 overflow: 0.63842 HPWL: 6355911 [NesterovSolve] Iter: 130 overflow: 0.637903 HPWL: 6357122 [NesterovSolve] Iter: 140 overflow: 0.637205 HPWL: 6360954 [NesterovSolve] Iter: 150 overflow: 0.636317 HPWL: 6366812 [NesterovSolve] Iter: 160 overflow: 0.63491 HPWL: 6375721 [NesterovSolve] Iter: 170 overflow: 0.632598 HPWL: 6386753 [NesterovSolve] Iter: 180 overflow: 0.628515 HPWL: 6399743 [NesterovSolve] Iter: 190 overflow: 0.618267 HPWL: 6418631 [NesterovSolve] Iter: 200 overflow: 0.607508 HPWL: 6453097 [NesterovSolve] Iter: 210 overflow: 0.59483 HPWL: 6507751 [NesterovSolve] Iter: 220 overflow: 0.57804 HPWL: 6568625 [NesterovSolve] Iter: 230 overflow: 0.55541 HPWL: 6671420 [NesterovSolve] Iter: 240 overflow: 0.527597 HPWL: 6779189 [NesterovSolve] Iter: 250 overflow: 0.488521 HPWL: 6864908 [NesterovSolve] Iter: 260 overflow: 0.448009 HPWL: 6870369 [NesterovSolve] Iter: 270 overflow: 0.411036 HPWL: 6921435 [NesterovSolve] Iter: 280 overflow: 0.371938 HPWL: 7007490 [NesterovSolve] Iter: 290 overflow: 0.333982 HPWL: 7099616 [NesterovSolve] Iter: 300 overflow: 0.298876 HPWL: 7183504 [NesterovSolve] Iter: 310 overflow: 0.259567 HPWL: 7236857 [NesterovSolve] Iter: 320 overflow: 0.228557 HPWL: 7325040 [NesterovSolve] Iter: 330 overflow: 0.201717 HPWL: 7429722 [NesterovSolve] Iter: 340 overflow: 0.168847 HPWL: 7491825 [NesterovSolve] Iter: 350 overflow: 0.143018 HPWL: 7541160 [NesterovSolve] Iter: 360 overflow: 0.123883 HPWL: 7593098 [NesterovSolve] Iter: 370 overflow: 0.0987641 HPWL: 7634093
[NesterovSolve] Finished with Overflow: 0.0987641
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def to /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def
[INFO]: Running OpenPhySyn Timing Optimization...
[INFO]: Trimming Liberty...
[OpenPhySyn] [2020-11-20 15:12:40.015] [info] Loaded 6 transforms. [OpenPhySyn] [2020-11-20 15:12:42.302] [info] OpenPhySyn: 1.8.1
Warning: /project/openlane/digital_pll/runs/digital_pll/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Notice 0: Reading LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def Notice 0: Design: digital_pll Notice 0: Created 37 pins. Notice 0: Created 657 components and 2635 component-terminals. Notice 0: Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
=============== Initial Reports ============= No paths found. Capacitance violations: 0 Transition violations: 0 wns 0.00 tns 0.00 Initial area: 54552 um2 OpenPhySyn timing repair: [OpenPhySyn] [2020-11-20 15:13:42.186] [info] Invoking repair_timing transform [OpenPhySyn] [2020-11-20 15:13:42.205] [info] Buffer library: sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_1 [OpenPhySyn] [2020-11-20 15:13:42.205] [info] Inverter library: None [OpenPhySyn] [2020-11-20 15:13:42.205] [info] Buffering: enabled [OpenPhySyn] [2020-11-20 15:13:42.205] [info] Driver sizing: enabled [OpenPhySyn] [2020-11-20 15:13:42.205] [info] Pin-swapping: enabled [OpenPhySyn] [2020-11-20 15:13:42.205] [info] Mode: Timing-Driven [OpenPhySyn] [2020-11-20 15:13:42.205] [info] Iteration 1 [OpenPhySyn] [2020-11-20 15:13:42.424] [info] No more violations or cannot find more optimal buffer [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Runtime: 0s [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Buffers: 0 [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Resize up: 0 [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Resize down: 0 [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Pin Swap: 0 [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Buffered nets: 0 [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Fanout violations: 0 [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Transition violations: 0 [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Capacitance violations: 0 [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Slack gain: 0.0 [OpenPhySyn] [2020-11-20 15:13:42.425] [info] Initial area: 5455 [OpenPhySyn] [2020-11-20 15:13:42.425] [info] New area: 5455
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Finished repair_timing transform (0)
Added/updated 0 cells =============== Final Reports ============= No paths found. Capacitance violations: 0 Transition violations: 0 wns 0.00 tns 0.00 Final area: 54552 um2 Export optimized design
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def to /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def Notice 0: Design: digital_pll Notice 0: Created 37 pins. Notice 0: Created 657 components and 2635 component-terminals. Notice 0: Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def
[INFO]: Changing netlist from /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis.v to /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis_optimized.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc. License GPLv3: GNU GPL version 3 This is free software, and you are free to change and redistribute it under certain conditions; type `show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis_optimized.v, line 1422 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for PHY_86.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
tns 0.00 wns 0.00
[INFO]: Running Detailed Placement...
=========================================================================== Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 > Developers : SangGi Do, Mingyu Woo =========================================================================== Parsed 10000 number of lines!! Parsed 20000 number of lines!! Parsed 30000 number of lines!! Parsed 40000 number of lines!! Parsed 50000 number of lines!! Parsed 60000 number of lines!! Reading /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef is Done -------------------- INPUT FILES ---------------------------------- benchmark name : placement directory : /project/openlane/digital_pll/runs/digital_pll/tmp lef : /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef def : /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def ------------------------------------------------------------------- CoreArea: 5520.000000 : 10880.000000 - 122360.000000 : 127840.000000 DieArea: 0.000000 : 0.000000 - 116840.000000 : 116960.000000 Reading /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def is Done -------------------- DESIGN ANALYSIS ------------------------------ total cells : 657 multi cells : 0 fixed cells : 266 total nets : 399 design area : 1.36656e+10 total f_area : 5.48026e+08 total m_area : 6.86408e+09 design util : 52.3274 num rows : 43 row height : 2720 ------------------------------------------------------------------- non_group_cell_region_assign done .. - - - - - - - - - - - - - - - - - - - - - - - - non_group_cell_placement done .. - - - - - - - - - - - - - - - - - - - - - - - - Reading /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def is Done
DEF file write success !!
location : /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def ------------------------------------------------------------------- tasks Wtime Ctime Parser 0.198 0.180 resgin assign 0.198 0.180 pre-placement 0.198 0.180 non Group cell placement 0.200 0.190 All 0.200 0.190 - - - - - EVALUATION - - - - - AVG_displacement : 2566.91 SUM_displacement : 1.68646e+06 MAX_displacement : 34227 - - - - - - - - - - - - - - - - GP HPWL : 7781.67 HPWL : 9750.33 avg_Disp_site : 5.58023 avg_Disp_row : 0.943716 delta_HPWL : 25.2987 ==== CHECK LEGALITY ==== row_check ==>> PASS site_check ==>> PASS power_check ==>> PASS edge_check ==>> PASS placed_check ==>> PASS overlap_check ==>> PASS - - - - - < Program END > - - - - -
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def to /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def
[INFO]: ::env(CLOCK_PORT) is not set
[WARNING]: Skipping CTS...
[INFO]: Generating PDN...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def Notice 0: Design: digital_pll Notice 0: Created 37 pins. Notice 0: Created 657 components and 2635 component-terminals. Notice 0: Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN [INFO] [PDNG-0016] config: /project/openlane/digital_pll/pdn.tcl
Error: pdn.tcl, 20 can't read "::env(FP_PDN_CORE_RING_HWIDTH)": no such variable
[INFO] [PDNG-0008] Design Name is digital_pll [INFO] [PDNG-0009] Reading technology data [CRIT] [PDNG-0017] No stdcell grid specification found - no rails can be inserted Execution stopped
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/new_pdn.tcl |& tee >&@stdout /project/openlane/digital_pll/runs/digital_pll/logs/floorplan/pdn.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
[ERROR]: Please check openroad log file
[ERROR]: Dumping to /project/openlane/digital_pll/runs/digital_pll/error.log
while executing "try_catch openroad -exit $::env(SCRIPTS_DIR)/new_pdn.tcl |& tee $::env(TERMINAL_OUTPUT) $::env(pdn_log_file_tag).log" (procedure "gen_pdn" line 8) invoked from within "gen_pdn" (procedure "run_non_interactive_mode" line 15) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { puts_info "Running interactively" if { [info exists arg_values(-file)..." (file "/openLANE_flow/flow.tcl" line 164) make: *** [Makefile:26: digital_pll] Fehler 1

Submodule: gpio_control_block

###############################################
/bin/sh: 1: [[: not found
[INFO]: ___ ____ ___ ____ _ ____ ____ ___ / \ | \ / _]| \ | | / || \ / _] | || o ) [_ | _ || | | o || _ | / [_ | O || _/ _]| | || |___ | || | || _] | || | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____|
[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/gpio_control_block/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/gpio_control_block/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/gpio_control_block/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/gpio_control_block/runs/gpio_control_block
[WARNING]: Removing exisiting run /project/openlane/gpio_control_block/runs/gpio_control_block
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs sky130_fd_sc_hd.lef: SITEs matched found: 0 sky130_fd_sc_hd.lef: MACROs matched found: 437 mergeLef.py : Merging LEFs complete padLefMacro.py : Padding technology lef file Derived SITE width (microns): 0.46 Derived SITE height (microns): 5.44 Right cell padding (microns): 3.68 Left cell padding (microns): 0.0 Top cell padding (microns): 0.0 Bottom cell padding (microns): 0.0 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd2_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_12 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_3 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_6 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_2 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvpwrvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...
/----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. 1. Executing Liberty frontend. Imported 428 cell types from liberty file. 2. Executing Verilog-2005 frontend: /project/openlane/gpio_control_block/../../verilog/rtl/defines.v Parsing Verilog input from `/project/openlane/gpio_control_block/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: /project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v Parsing Verilog input from `/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:200)
Generating RTLIL representation for module `\gpio_control_block'.
Successfully finished Verilog frontend.
4. Executing HIERARCHY pass (managing design hierarchy). 4.1. Analyzing design hierarchy.. Top module: \gpio_control_block 4.2. Analyzing design hierarchy.. Top module: \gpio_control_block Removed 0 unused modules. 5. Executing SYNTH pass. 5.1. Executing HIERARCHY pass (managing design hierarchy). 5.1.1. Analyzing design hierarchy.. Top module: \gpio_control_block 5.1.2. Analyzing design hierarchy.. Top module: \gpio_control_block Removed 0 unused modules. 5.2. Executing PROC pass (convert processes to netlists). 5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8 in module gpio_control_block. Marked 1 switch rules as full_case in process $proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:142$6 in module gpio_control_block. Removed a total of 0 dead cases. 5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 12 redundant assignments. Promoted 0 assignments to connections. 5.2.4. Executing PROC_INIT pass (extract init attributes). 5.2.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \int_reset in `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. Found async reset \int_reset in `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:142$6'. 5.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. 1/11: $0\gpio_dm[2:0] 2/11: $0\gpio_vtrip_sel[0:0] 3/11: $0\gpio_slow_sel[0:0] 4/11: $0\gpio_ana_pol[0:0] 5/11: $0\gpio_ana_sel[0:0] 6/11: $0\gpio_ana_en[0:0] 7/11: $0\gpio_ib_mode_sel[0:0] 8/11: $0\gpio_inenb[0:0] 9/11: $0\gpio_holdover[0:0] 10/11: $0\gpio_outenb[0:0] 11/11: $0\mgmt_ena[0:0] Creating decoders for process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:142$6'. 1/1: $0\shift_register[12:0] 5.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). 5.2.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\gpio_control_block.\mgmt_ena' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$24' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\gpio_holdover' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$25' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\gpio_slow_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$26' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\gpio_vtrip_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$27' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\gpio_inenb' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$28' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\gpio_ib_mode_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$29' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\gpio_outenb' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$30' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\gpio_dm' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$31' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\gpio_ana_en' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$32' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\gpio_ana_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$33' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\gpio_ana_pol' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. created $adff cell `$procdff$34' with positive edge clock and positive level reset. Creating register for signal `\gpio_control_block.\shift_register' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:142$6'. created $adff cell `$procdff$35' with positive edge clock and positive level reset. 5.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'. Removing empty process `gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:142$6'. Cleaned up 0 empty switches. 5.3. Executing FLATTEN pass (flatten design). 5.4. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block. 5.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. Removed 1 unused cells and 23 unused wires. 5.6. Executing CHECK pass (checking for obvious problems). checking module gpio_control_block.. found and reported 0 problems. 5.7. Executing OPT pass (performing simple optimizations). 5.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block. 5.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 1 cells. 5.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \gpio_control_block.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \gpio_control_block. Performed a total of 0 changes. 5.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.7.6. Executing OPT_DFF pass (perform DFF optimizations). 5.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. Removed 0 unused cells and 1 unused wires. 5.7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block. 5.7.9. Rerunning OPT passes. (Maybe there is more to do..) 5.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \gpio_control_block.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \gpio_control_block. Performed a total of 0 changes. 5.7.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.7.13. Executing OPT_DFF pass (perform DFF optimizations). 5.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. 5.7.15. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block.
5.7.16. Finished OPT passes. (There is nothing left to do.)
5.8. Executing FSM pass (extract and optimize FSM). 5.8.1. Executing FSM_DETECT pass (finding FSMs in design). 5.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). 5.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). 5.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. 5.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). 5.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 5.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 5.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 5.9. Executing OPT pass (performing simple optimizations). 5.9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block. 5.9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \gpio_control_block.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \gpio_control_block. Performed a total of 0 changes. 5.9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.9.6. Executing OPT_DFF pass (perform DFF optimizations). 5.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. 5.9.8. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block.
5.9.9. Finished OPT passes. (There is nothing left to do.)
5.10. Executing WREDUCE pass (reducing word size of cells). Removed top 1 bits (of 2) from port B of cell gpio_control_block.$eq$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:206$18 ($eq). 5.11. Executing PEEPOPT pass (run peephole optimizers). 5.12. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. 5.13. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module gpio_control_block: created 0 $alu and 0 $macc cells. 5.14. Executing SHARE pass (SAT-based resource sharing). 5.15. Executing OPT pass (performing simple optimizations). 5.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block. 5.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \gpio_control_block.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \gpio_control_block. Performed a total of 0 changes. 5.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.15.6. Executing OPT_DFF pass (perform DFF optimizations). 5.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. 5.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block.
5.15.9. Finished OPT passes. (There is nothing left to do.)
5.16. Executing MEMORY pass. 5.16.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 5.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 5.16.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. 5.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 5.16.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. 5.16.6. Executing MEMORY_COLLECT pass (generating $mem cells). 5.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. 5.18. Executing OPT pass (performing simple optimizations). 5.18.1. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block. 5.18.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.18.3. Executing OPT_DFF pass (perform DFF optimizations). 5.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. Removed 0 unused cells and 1 unused wires.
5.18.5. Finished fast OPT passes.
5.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 5.20. Executing OPT pass (performing simple optimizations). 5.20.1. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block. 5.20.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \gpio_control_block.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \gpio_control_block. Performed a total of 0 changes. 5.20.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.20.6. Executing OPT_SHARE pass. 5.20.7. Executing OPT_DFF pass (perform DFF optimizations). 5.20.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. 5.20.9. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block.
5.20.10. Finished OPT passes. (There is nothing left to do.)
5.21. Executing TECHMAP pass (map to technology primitives). 5.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
5.21.2. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $adff. No more expansions possible. 5.22. Executing OPT pass (performing simple optimizations). 5.22.1. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block. 5.22.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.22.3. Executing OPT_DFF pass (perform DFF optimizations). 5.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. Removed 1 unused cells and 3 unused wires.
5.22.5. Finished fast OPT passes.
5.23. Executing ABC pass (technology mapping using ABC). 5.23.1. Extracting gate netlist of module `\gpio_control_block' to `/input.blif'.. Extracted 15 gates and 28 wires to a netlist network with 12 inputs and 6 outputs. 5.23.1.1. Executing ABC. Running ABC command: /yosys-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: Entered genlib library with 13 gates from file "/stdcells.genlib". ABC: + strash ABC: + dretime ABC: + map ABC: + write_blif /output.blif 5.23.1.2. Re-integrating ABC results. ABC RESULTS: AND cells: 2 ABC RESULTS: ANDNOT cells: 1 ABC RESULTS: MUX cells: 4 ABC RESULTS: NOR cells: 1 ABC RESULTS: NOT cells: 2 ABC RESULTS: ORNOT cells: 2 ABC RESULTS: internal signals: 10 ABC RESULTS: input signals: 12 ABC RESULTS: output signals: 6 Removing temp directory. 5.24. Executing OPT pass (performing simple optimizations). 5.24.1. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block. 5.24.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 5.24.3. Executing OPT_DFF pass (perform DFF optimizations). 5.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. Removed 1 unused cells and 28 unused wires.
5.24.5. Finished fast OPT passes.
5.25. Executing HIERARCHY pass (managing design hierarchy). 5.25.1. Analyzing design hierarchy.. Top module: \gpio_control_block 5.25.2. Analyzing design hierarchy.. Top module: \gpio_control_block Removed 0 unused modules. 5.26. Printing statistics. === gpio_control_block === Number of wires: 43 Number of wire bits: 59 Number of public wires: 37 Number of public wire bits: 53 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 39 $_ANDNOT_ 1 $_AND_ 2 $_DFF_PP0_ 23 $_DFF_PP1_ 3 $_MUX_ 4 $_NOR_ 1 $_NOT_ 1 $_ORNOT_ 2 sky130_fd_sc_hd__conb_1 1 sky130_fd_sc_hd__einvp_8 1 5.27. Executing CHECK pass (checking for obvious problems). checking module gpio_control_block.. found and reported 0 problems. 6. Executing SHARE pass (SAT-based resource sharing). 7. Executing OPT pass (performing simple optimizations). 7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block. 7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \gpio_control_block.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \gpio_control_block. Performed a total of 0 changes. 7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\gpio_control_block'. Removed a total of 0 cells. 7.6. Executing OPT_DFF pass (perform DFF optimizations). 7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. 7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module gpio_control_block.
7.9. Finished OPT passes. (There is nothing left to do.)
8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. Removed 0 unused cells and 9 unused wires. 9. Printing statistics. === gpio_control_block === Number of wires: 34 Number of wire bits: 48 Number of public wires: 28 Number of public wire bits: 42 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 39 $_ANDNOT_ 1 $_AND_ 2 $_DFF_PP0_ 23 $_DFF_PP1_ 3 $_MUX_ 4 $_NOR_ 1 $_NOT_ 1 $_ORNOT_ 2 sky130_fd_sc_hd__conb_1 1 sky130_fd_sc_hd__einvp_8 1 10. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_. cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_. cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_. cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_. final dff cell mappings: unmapped dff cell: $_DFF_N_ \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q)); unmapped dff cell: $_DFF_NN0_ unmapped dff cell: $_DFF_NN1_ unmapped dff cell: $_DFF_NP0_ unmapped dff cell: $_DFF_NP1_ \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R)); \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R)); unmapped dff cell: $_DFF_PP0_ unmapped dff cell: $_DFF_PP1_ \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); unmapped dff cell: $_DFFSR_NNP_ unmapped dff cell: $_DFFSR_NPN_ unmapped dff cell: $_DFFSR_NPP_ unmapped dff cell: $_DFFSR_PNN_ unmapped dff cell: $_DFFSR_PNP_ unmapped dff cell: $_DFFSR_PPN_ unmapped dff cell: $_DFFSR_PPP_ 10.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Mapping DFF cells in module `\gpio_control_block': mapped 23 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells. mapped 3 $_DFF_PN1_ cells to \sky130_fd_sc_hd__dfstp_4 cells. 11. Printing statistics. [INFO]: ABC: WireLoad : S_2 === gpio_control_block === Number of wires: 60 Number of wire bits: 74 Number of public wires: 28 Number of public wire bits: 42 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 65 $_ANDNOT_ 1 $_AND_ 2 $_MUX_ 4 $_NOR_ 1 $_NOT_ 27 $_ORNOT_ 2 sky130_fd_sc_hd__conb_1 1 sky130_fd_sc_hd__dfrtp_4 23 sky130_fd_sc_hd__dfstp_4 3 sky130_fd_sc_hd__einvp_8 1 12. Executing ABC pass (technology mapping using ABC). 12.1. Extracting gate netlist of module `\gpio_control_block' to `/tmp/yosys-abc-Hcq5yP/input.blif'.. Extracted 37 gates and 49 wires to a netlist network with 12 inputs and 31 outputs. 12.1.1. Executing ABC. Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-Hcq5yP/abc.script 2>&1 ABC: ABC command line: "source /tmp/yosys-abc-Hcq5yP/abc.script". ABC: ABC: + read_blif /tmp/yosys-abc-Hcq5yP/input.blif ABC: + read_lib -w /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/trimmed.lib
ABC: Parsing finished successfully. Parsing time = 0.06 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/gpio_control_block/runs/gpio_control_block/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.08 sec ABC: Memory = 1.92 MB. Time = 0.08 sec ABC: + read_constr -v /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/synthesis/yosys.sdc ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8". ABC: Setting output load to be 17.650000. ABC: + read_constr /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/synthesis/yosys.sdc ABC: + fx ABC: The network is unchanged by fast extract. ABC: + mfs ABC: + strash ABC: + refactor ABC: + balance ABC: + rewrite ABC: + refactor ABC: + balance ABC: + rewrite ABC: + rewrite -z ABC: + balance ABC: + refactor -z ABC: + rewrite -z ABC: + balance ABC: + retime -D -D 10000 -M 5 ABC: + scleanup
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 ABC: + retime -D -D 10000 ABC: + buffer -N 5 -S 1000.0 ABC: + upsize -D 10000 ABC: Current delay (745.80 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed. ABC: + dnsize -D 10000 ABC: + stime -p ABC: WireLoad = "none" Gates = 43 ( 79.1 %) Cap = 14.0 ff ( 0.0 %) Area = 261.50 (100.0 %) Delay = 745.80 ps ( 9.3 %) ABC: Path 0 -- 6 : 0 1 pi A = 0.00 Df = 21.9 -14.3 ps S = 37.7 ps Cin = 0.0 ff Cout = 18.5 ff Cmax = 0.0 ff G = 0 ABC: Path 1 -- 77 : 1 1 sky130_fd_sc_hd__inv_8 A = 11.26 Df = 41.3 -9.1 ps S = 14.8 ps Cin = 17.7 ff Cout = 2.5 ff Cmax =1035.5 ff G = 13 ABC: Path 2 -- 78 : 3 2 sky130_fd_sc_hd__and3_4 A = 11.26 Df = 213.4 -12.7 ps S = 64.9 ps Cin = 2.4 ff Cout = 11.8 ff Cmax = 532.8 ff G = 462 ABC: Path 3 -- 79 : 2 1 sky130_fd_sc_hd__or2_4 A = 8.76 Df = 421.3 -99.2 ps S = 46.2 ps Cin = 2.4 ff Cout = 4.5 ff Cmax = 514.5 ff G = 179 ABC: Path 4 -- 81 : 5 1 sky130_fd_sc_hd__a32o_4 A = 21.27 Df = 745.8 -205.1 ps S = 83.1 ps Cin = 4.3 ff Cout = 17.6 ff Cmax = 536.5 ff G = 407 ABC: Start-point = pi5 (\pad_gpio_dm [2]). End-point = po26 (\pad_gpio_out). ABC: + print_stats -m ABC: netlist : i/o = 12/ 31 lat = 0 nd = 43 edge = 59 area =261.39 delay = 4.00 lev = 4 ABC: + write_blif /tmp/yosys-abc-Hcq5yP/output.blif 12.1.2. Re-integrating ABC results. ABC RESULTS: sky130_fd_sc_hd__a32o_4 cells: 2 ABC RESULTS: sky130_fd_sc_hd__and2_4 cells: 2 ABC RESULTS: sky130_fd_sc_hd__and3_4 cells: 1 ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 31 ABC RESULTS: sky130_fd_sc_hd__inv_8 cells: 3 ABC RESULTS: sky130_fd_sc_hd__nand2_4 cells: 2 ABC RESULTS: sky130_fd_sc_hd__or2_4 cells: 2 ABC RESULTS: internal signals: 6 ABC RESULTS: input signals: 12 ABC RESULTS: output signals: 31 Removing temp directory. 13. Executing SETUNDEF pass (replace undef values with defined constants). 14. Executing HILOMAP pass (mapping to constant drivers). 15. Executing SPLITNETS pass (splitting up multi-bit signals). 16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \gpio_control_block.. Removed 0 unused cells and 50 unused wires. 17. Executing INSBUF pass (insert buffer cells for connected wires). 18. Executing CHECK pass (checking for obvious problems). checking module gpio_control_block.. found and reported 0 problems. 19. Printing statistics. === gpio_control_block === Number of wires: 77 Number of wire bits: 79 Number of public wires: 38 Number of public wire bits: 40 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 71 sky130_fd_sc_hd__a32o_4 2 sky130_fd_sc_hd__and2_4 2 sky130_fd_sc_hd__and3_4 1 sky130_fd_sc_hd__buf_1 31 sky130_fd_sc_hd__conb_1 1 sky130_fd_sc_hd__dfrtp_4 23 sky130_fd_sc_hd__dfstp_4 3 sky130_fd_sc_hd__einvp_8 1 sky130_fd_sc_hd__inv_8 3 sky130_fd_sc_hd__nand2_4 2 sky130_fd_sc_hd__or2_4 2 Area for cell type \sky130_fd_sc_hd__einvp_8 is unknown! Chip area for module '\gpio_control_block': 1017.225600 20. Executing Verilog backend. Dumping module `\gpio_control_block'.
Warnings: 1 unique messages, 1 total
End of script. Logfile hash: bd299fc028, CPU: user 1.61s system 0.11s, MEM: 43.61 MB peak Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) Time spent: 31% 2x abc (0 sec), 31% 2x read_liberty (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc. License GPLv3: GNU GPL version 3 This is free software, and you are free to change and redistribute it under certain conditions; type `show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) set IO_PCT 0.2 set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] puts "\[INFO\]: Setting output delay to: $output_delay_value" [INFO]: Setting output delay to: 2.0 puts "\[INFO\]: Setting input delay to: $input_delay_value" [INFO]: Setting input delay to: 2.0 set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] #set rst_indx [lsearch [all_inputs] [get_port resetn]] set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] set all_inputs_wo_clk_rst $all_inputs_wo_clk # correct resetn set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] # TODO set this as parameter set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "\[INFO\]: Setting load to: $cap_load" [INFO]: Setting load to: 0.01765 set_load $cap_load [all_outputs] tns 0.00 wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Info: Added 37 rows of 84 sites.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 38.959999999999994
[INFO]: Core area height: 103.24000000000001
[WARNING]: Current core area is too small for a power grid
[WARNING]: Minimizing the power grid!!!!
[INFO]: Changing layout from 0 to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/verilog2def_openroad.def
Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/verilog2def_openroad.def Notice 0: Design: gpio_control_block Notice 0: Created 24 pins. Notice 0: Created 71 components and 353 component-terminals. Notice 0: Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/verilog2def_openroad.def
Top-level design name: gpio_control_block Block boundaries: 0 0 50000 125000 Writing /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/verilog2def_openroad.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def Notice 0: Design: gpio_control_block Notice 0: Created 24 pins. Notice 0: Created 71 components and 353 component-terminals. Notice 0: Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def
Running tapcell... Step 1: Cut rows... [INFO] Macro blocks found: 0 [INFO] #Original rows: 37 [INFO] #Cut rows: 0 Step 2: Insert endcaps... [INFO] #Endcaps inserted: 74 Step 3: Insert tapcells... [INFO] #Tapcells inserted: 39 Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def to /project/openlane/gpio_control_block/runs/gpio_control_block/results/floorplan/gpio_control_block.floorplan.def
[INFO]: Running Placement...
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/floorplan/gpio_control_block.floorplan.def Notice 0: Design: gpio_control_block Notice 0: Created 24 pins. Notice 0: Created 184 components and 579 component-terminals. Notice 0: Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/floorplan/gpio_control_block.floorplan.def
[INFO] DBU = 1000 [INFO] SiteSize = (460, 2720) [INFO] CoreAreaLxLy = (5520, 10880) [INFO] CoreAreaUxUy = (44160, 111520) [INFO] NumInstances = 184 [INFO] NumPlaceInstances = 71 [INFO] NumFixedInstances = 113 [INFO] NumDummyInstances = 0 [INFO] NumNets = 79 [INFO] NumPins = 234 [INFO] DieAreaLxLy = (0, 0) [INFO] DieAreaUxUy = (50000, 125000) [INFO] CoreAreaLxLy = (5520, 10880) [INFO] CoreAreaUxUy = (44160, 111520) [INFO] CoreArea = 3888729600 [INFO] NonPlaceInstsArea = 326563200 [INFO] PlaceInstsArea = 1039747200 [INFO] Util(%) = 29.188622 [INFO] StdInstsArea = 1039747200 [INFO] MacroInstsArea = 0
[InitialPlace] Iter: 1 CG Error: 1.05906e-07 HPWL: 2753880
[InitialPlace] Iter: 2 CG Error: 1.14847e-07 HPWL: 2110888
[InitialPlace] Iter: 3 CG Error: 7.01776e-08 HPWL: 2085756
[InitialPlace] Iter: 4 CG Error: 7.54675e-08 HPWL: 2078520
[InitialPlace] Iter: 5 CG Error: 1.13936e-07 HPWL: 2092488
[INFO] FillerInit: NumGCells = 98 [INFO] FillerInit: NumGNets = 79 [INFO] FillerInit: NumGPins = 234 [INFO] TargetDensity = 0.400000 [INFO] AveragePlaceInstArea = 14644326 [INFO] IdealBinArea = 36610816 [INFO] IdealBinCnt = 106 [INFO] TotalBinArea = 3888729600 [INFO] BinCnt = (8, 8) [INFO] BinSize = (4830, 12580) [INFO] NumBins = 64 [NesterovSolve] Iter: 1 overflow: 0.709908 HPWL: 1638919 [NesterovSolve] Iter: 10 overflow: 0.497771 HPWL: 1673566 [NesterovSolve] Iter: 20 overflow: 0.50846 HPWL: 1660355 [NesterovSolve] Iter: 30 overflow: 0.505602 HPWL: 1661709 [NesterovSolve] Iter: 40 overflow: 0.506297 HPWL: 1661040 [NesterovSolve] Iter: 50 overflow: 0.50615 HPWL: 1661104 [NesterovSolve] Iter: 60 overflow: 0.506139 HPWL: 1661139 [NesterovSolve] Iter: 70 overflow: 0.506105 HPWL: 1661132 [NesterovSolve] Iter: 80 overflow: 0.506055 HPWL: 1661240 [NesterovSolve] Iter: 90 overflow: 0.505971 HPWL: 1661372 [NesterovSolve] Iter: 100 overflow: 0.505825 HPWL: 1661625 [NesterovSolve] Iter: 110 overflow: 0.505622 HPWL: 1661980 [NesterovSolve] Iter: 120 overflow: 0.505302 HPWL: 1662532 [NesterovSolve] Iter: 130 overflow: 0.504843 HPWL: 1663209 [NesterovSolve] Iter: 140 overflow: 0.504151 HPWL: 1663829 [NesterovSolve] Iter: 150 overflow: 0.503008 HPWL: 1664271 [NesterovSolve] Iter: 160 overflow: 0.501058 HPWL: 1665596 [NesterovSolve] Iter: 170 overflow: 0.497836 HPWL: 1667853 [NesterovSolve] Iter: 180 overflow: 0.492678 HPWL: 1671171 [NesterovSolve] Iter: 190 overflow: 0.484747 HPWL: 1676460 [NesterovSolve] Iter: 200 overflow: 0.472351 HPWL: 1683923 [NesterovSolve] Iter: 210 overflow: 0.460509 HPWL: 1694566 [NesterovSolve] Iter: 220 overflow: 0.446098 HPWL: 1706868 [NesterovSolve] Iter: 230 overflow: 0.429146 HPWL: 1722786 [NesterovSolve] Iter: 240 overflow: 0.407395 HPWL: 1738513 [NesterovSolve] Iter: 250 overflow: 0.373378 HPWL: 1751118 [NesterovSolve] Iter: 260 overflow: 0.327698 HPWL: 1761013 [NesterovSolve] Iter: 270 overflow: 0.269933 HPWL: 1773879 [NesterovSolve] Iter: 280 overflow: 0.228274 HPWL: 1787323 [NesterovSolve] Iter: 290 overflow: 0.203813 HPWL: 1796742 [NesterovSolve] Iter: 300 overflow: 0.178708 HPWL: 1809979 [NesterovSolve] Iter: 310 overflow: 0.159275 HPWL: 1816347 [NesterovSolve] Iter: 320 overflow: 0.141698 HPWL: 1821180 [NesterovSolve] Iter: 330 overflow: 0.123013 HPWL: 1827543 [NesterovSolve] Iter: 340 overflow: 0.104345 HPWL: 1833584
[NesterovSolve] Finished with Overflow: 0.0990607
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) set IO_PCT 0.2 set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] puts "\[INFO\]: Setting output delay to: $output_delay_value" [INFO]: Setting output delay to: 2.0 puts "\[INFO\]: Setting input delay to: $input_delay_value" [INFO]: Setting input delay to: 2.0 set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] #set rst_indx [lsearch [all_inputs] [get_port resetn]] set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] set all_inputs_wo_clk_rst $all_inputs_wo_clk # correct resetn set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] # TODO set this as parameter set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "\[INFO\]: Setting load to: $cap_load" [INFO]: Setting load to: 0.01765 set_load $cap_load [all_outputs]
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/results/floorplan/gpio_control_block.floorplan.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/replace.def
[INFO]: Running OpenPhySyn Timing Optimization...
[INFO]: Trimming Liberty...
[OpenPhySyn] [2020-11-20 15:15:47.938] [info] Loaded 6 transforms. [OpenPhySyn] [2020-11-20 15:15:50.436] [info] OpenPhySyn: 1.8.1
Warning: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/replace.def Notice 0: Design: gpio_control_block Notice 0: Created 24 pins. Notice 0: Created 184 components and 579 component-terminals. Notice 0: Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/replace.def
[INFO]: Setting output delay to: 2.0 [INFO]: Setting input delay to: 2.0 [INFO]: Setting load to: 0.01765 =============== Initial Reports ============= Startpoint: resetn (input port clocked by serial_clock) Endpoint: _082_ (recovery check against rising-edge clock serial_clock) Path Group: **async_default** Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock serial_clock (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 ^ input external delay 0.04 2.04 ^ resetn (in) 0.19 2.23 ^ _039_/X (sky130_fd_sc_hd__or2_4) 0.25 2.48 ^ _045_/X (sky130_fd_sc_hd__buf_1) 0.33 2.80 ^ _064_/X (sky130_fd_sc_hd__buf_1) 0.23 3.03 ^ _069_/X (sky130_fd_sc_hd__buf_1) 0.00 3.03 ^ _082_/SET_B (sky130_fd_sc_hd__dfstp_4) 3.03 data arrival time 10.00 10.00 clock serial_clock (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ _082_/CLK (sky130_fd_sc_hd__dfstp_4) 0.25 10.25 library recovery time 10.25 data required time --------------------------------------------------------- 10.25 data required time -3.03 data arrival time --------------------------------------------------------- 7.21 slack (MET) Startpoint: resetn (input port clocked by serial_clock) Endpoint: _079_ (rising clock gating-check end-point clocked by serial_clock) Path Group: **clock_gating_default** Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock serial_clock (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 ^ input external delay 0.04 2.04 ^ resetn (in) 0.04 2.08 v _078_/Y (sky130_fd_sc_hd__inv_8) 0.00 2.08 v _079_/B (sky130_fd_sc_hd__and2_4) 2.08 data arrival time 10.00 10.00 clock serial_clock (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ _079_/A (sky130_fd_sc_hd__and2_4) 0.00 10.00 clock gating setup time 10.00 data required time --------------------------------------------------------- 10.00 data required time -2.08 data arrival time --------------------------------------------------------- 7.92 slack (MET) Startpoint: mgmt_gpio_oeb (input port clocked by serial_clock) Endpoint: pad_gpio_out (output port clocked by serial_clock) Path Group: serial_clock Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock serial_clock (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.01 2.01 v mgmt_gpio_oeb (in) 0.26 2.26 v _073_/X (sky130_fd_sc_hd__and3_4) 0.43 2.69 v _074_/X (sky130_fd_sc_hd__or2_4) 0.57 3.26 v _076_/X (sky130_fd_sc_hd__a32o_4) 0.00 3.26 v pad_gpio_out (out) 3.26 data arrival time 10.00 10.00 clock serial_clock (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -3.26 data arrival time --------------------------------------------------------- 4.74 slack (MET) Capacitance violations: 0 Transition violations: 0 wns 0.00 tns 0.00 Initial area: 13663 um2 OpenPhySyn timing repair: [OpenPhySyn] [2020-11-20 15:17:00.923] [info] Invoking repair_timing transform [OpenPhySyn] [2020-11-20 15:17:00.943] [info] Buffer library: sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_1 [OpenPhySyn] [2020-11-20 15:17:00.943] [info] Inverter library: None [OpenPhySyn] [2020-11-20 15:17:00.943] [info] Buffering: enabled [OpenPhySyn] [2020-11-20 15:17:00.943] [info] Driver sizing: enabled [OpenPhySyn] [2020-11-20 15:17:00.943] [info] Pin-swapping: enabled [OpenPhySyn] [2020-11-20 15:17:00.943] [info] Mode: Timing-Driven [OpenPhySyn] [2020-11-20 15:17:00.943] [info] Iteration 1 [OpenPhySyn] [2020-11-20 15:17:00.991] [info] No more violations or cannot find more optimal buffer [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Runtime: 0s [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Buffers: 0 [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Resize up: 0 [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Resize down: 0 [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Pin Swap: 0 [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Buffered nets: 0 [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Fanout violations: 0 [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Transition violations: 0 [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Capacitance violations: 0 [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Slack gain: 0.0 [OpenPhySyn] [2020-11-20 15:17:00.992] [info] Initial area: 1366 [OpenPhySyn] [2020-11-20 15:17:00.992] [info] New area: 1366
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Finished repair_timing transform (0)
Added/updated 0 cells =============== Final Reports ============= Startpoint: resetn (input port clocked by serial_clock) Endpoint: _082_ (recovery check against rising-edge clock serial_clock) Path Group: **async_default** Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock serial_clock (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 ^ input external delay 0.04 2.04 ^ resetn (in) 0.19 2.23 ^ _039_/X (sky130_fd_sc_hd__or2_4) 0.25 2.47 ^ _045_/X (sky130_fd_sc_hd__buf_1) 0.31 2.79 ^ _064_/X (sky130_fd_sc_hd__buf_1) 0.22 3.00 ^ _069_/X (sky130_fd_sc_hd__buf_1) 0.00 3.00 ^ _082_/SET_B (sky130_fd_sc_hd__dfstp_4) 3.00 data arrival time 10.00 10.00 clock serial_clock (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ _082_/CLK (sky130_fd_sc_hd__dfstp_4) 0.25 10.25 library recovery time 10.25 data required time --------------------------------------------------------- 10.25 data required time -3.00 data arrival time --------------------------------------------------------- 7.24 slack (MET) Startpoint: resetn (input port clocked by serial_clock) Endpoint: _079_ (rising clock gating-check end-point clocked by serial_clock) Path Group: **clock_gating_default** Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock serial_clock (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 ^ input external delay 0.04 2.04 ^ resetn (in) 0.04 2.08 v _078_/Y (sky130_fd_sc_hd__inv_8) 0.00 2.08 v _079_/B (sky130_fd_sc_hd__and2_4) 2.08 data arrival time 10.00 10.00 clock serial_clock (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ _079_/A (sky130_fd_sc_hd__and2_4) 0.00 10.00 clock gating setup time 10.00 data required time --------------------------------------------------------- 10.00 data required time -2.08 data arrival time --------------------------------------------------------- 7.92 slack (MET) Startpoint: mgmt_gpio_oeb (input port clocked by serial_clock) Endpoint: pad_gpio_out (output port clocked by serial_clock) Path Group: serial_clock Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock serial_clock (rise edge) 0.00 0.00 clock network delay (ideal) 2.00 2.00 v input external delay 0.01 2.01 v mgmt_gpio_oeb (in) 0.26 2.26 v _073_/X (sky130_fd_sc_hd__and3_4) 0.43 2.69 v _074_/X (sky130_fd_sc_hd__or2_4) 0.57 3.26 v _076_/X (sky130_fd_sc_hd__a32o_4) 0.00 3.26 v pad_gpio_out (out) 3.26 data arrival time 10.00 10.00 clock serial_clock (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -3.26 data arrival time --------------------------------------------------------- 4.74 slack (MET) Capacitance violations: 0 Transition violations: 0 wns 0.00 tns 0.00 Final area: 13663 um2 Export optimized design
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/replace.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def Notice 0: Design: gpio_control_block Notice 0: Created 24 pins. Notice 0: Created 184 components and 579 component-terminals. Notice 0: Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def
[INFO]: Changing netlist from /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis.v to /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_optimized.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc. License GPLv3: GNU GPL version 3 This is free software, and you are free to change and redistribute it under certain conditions; type `show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_optimized.v, line 330 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for PHY_74.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) set IO_PCT 0.2 set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] puts "\[INFO\]: Setting output delay to: $output_delay_value" [INFO]: Setting output delay to: 2.0 puts "\[INFO\]: Setting input delay to: $input_delay_value" [INFO]: Setting input delay to: 2.0 set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] #set rst_indx [lsearch [all_inputs] [get_port resetn]] set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] set all_inputs_wo_clk_rst $all_inputs_wo_clk # correct resetn set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] # TODO set this as parameter set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "\[INFO\]: Setting load to: $cap_load" [INFO]: Setting load to: 0.01765 set_load $cap_load [all_outputs] tns 0.00 wns 0.00
[INFO]: Running Detailed Placement...
=========================================================================== Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 > Developers : SangGi Do, Mingyu Woo =========================================================================== Parsed 10000 number of lines!! Parsed 20000 number of lines!! Parsed 30000 number of lines!! Parsed 40000 number of lines!! Parsed 50000 number of lines!! Parsed 60000 number of lines!! Reading /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef is Done -------------------- INPUT FILES ---------------------------------- benchmark name : placement directory : /project/openlane/gpio_control_block/runs/gpio_control_block/tmp lef : /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef def : /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def ------------------------------------------------------------------- CoreArea: 5520.000000 : 10880.000000 - 44160.000000 : 111520.000000 DieArea: 0.000000 : 0.000000 - 38640.000000 : 100640.000000 Reading /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def is Done -------------------- DESIGN ANALYSIS ------------------------------ total cells : 184 multi cells : 0 fixed cells : 113 total nets : 79 design area : 3.88873e+09 total f_area : 3.26563e+08 total m_area : 1.75043e+09 design util : 49.1394 num rows : 37 row height : 2720 ------------------------------------------------------------------- non_group_cell_region_assign done .. - - - - - - - - - - - - - - - - - - - - - - - - non_group_cell_placement done .. - - - - - - - - - - - - - - - - - - - - - - - - Reading /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def is Done
DEF file write success !!
location : /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def ------------------------------------------------------------------- tasks Wtime Ctime Parser 0.175 0.160 resgin assign 0.175 0.160 pre-placement 0.175 0.160 non Group cell placement 0.175 0.170 All 0.176 0.170 - - - - - EVALUATION - - - - - AVG_displacement : 1900.9 SUM_displacement : 349766 MAX_displacement : 18870 - - - - - - - - - - - - - - - - GP HPWL : 1849.19 HPWL : 2153.75 avg_Disp_site : 4.1324 avg_Disp_row : 0.698861 delta_HPWL : 16.4702 ==== CHECK LEGALITY ==== row_check ==>> PASS site_check ==>> PASS power_check ==>> PASS edge_check ==>> PASS placed_check ==>> PASS overlap_check ==>> PASS - - - - - < Program END > - - - - -
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def to /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def
[INFO]: Running TritonCTS...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def Notice 0: Design: gpio_control_block Notice 0: Created 24 pins. Notice 0: Created 184 components and 579 component-terminals. Notice 0: Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def
[INFO]: Setting output delay to: 2.0 [INFO]: Setting input delay to: 2.0 [INFO]: Setting load to: 0.01765 [INFO]: Configuring cts characterization... [INFO]: Performing clock tree synthesis... [INFO]: Looking for the following net(s): serial_clock ***************** * TritonCTS 2.0 * ***************** ***************************** * Create characterization * ***************************** Number of created patterns = 50000. Number of created patterns = 100000. Number of created patterns = 150000. Number of created patterns = 200000. Number of created patterns = 250000. Number of created patterns = 300000. Number of created patterns = 313632. Compiling LUT Min. len Max. len Min. cap Max. cap Min. slew Max. slew 2 8 1 39 1 199
[WARNING] 6336 wires are pure wire and no slew degration.
TritonCTS forced slew degradation on these wires. Num wire segments: 216048 Num keys in characterization LUT: 1887 Actual min input cap: 2 ********************** * Find clock roots * ********************** Running TritonCTS with user-specified clock roots: serial_clock ************************ * Populate TritonCTS * ************************ Initializing clock nets Looking for clock nets in the design Net "serial_clock" found Initializing clock net for : "serial_clock" Clock net "serial_clock" has 15 sinks TritonCTS found 1 clock nets. **************************** * Check characterization * **************************** The chacterization used 4 buffer(s) types. All of them are in the loaded DB. *********************** * Build clock trees * *********************** Generating H-Tree topology for net serial_clock... Tot. number of sinks: 15 Number of static layers: 0 Wire segment unit: 13000 dbu (13 um) Original sink region: [(7165, 23175), (24972, 99340)] Normalized sink region: [(0.551154, 1.78269), (1.92092, 7.64154)] Width: 1.36977 Height: 5.85885
[WARNING] Creating fake entries in the LUT.
Level 1 Direction: Vertical # sinks per sub-region: 8 Sub-region size: 1.36977 X 2.92942 Segment length (rounded): 1 Key: 216280 outSlew: 11 load: 1 length: 1 isBuffered: 1 Stop criterion found. Max number of sinks is (15) Building clock sub nets... Number of sinks covered: 15 Clock topology of net "serial_clock" done. **************** * Post CTS opt * **************** Avg. source sink dist: 18924.3 dbu. Num outlier sinks: 0 ******************** * Write data to DB * ******************** Writing clock net "serial_clock" to DB Created 3 clock buffers. Minimum number of buffers in the clock path: 2. Maximum number of buffers in the clock path: 2. Created 3 clock nets. Fanout distribution for the current clock = 6:1, 9:1. Max level of the clock tree: 1. ... End of TritonCTS execution. [INFO]: Legalizing...
Warning: could not find power special net
Design Stats -------------------------------- total instances 187 multi row instances 0 fixed instances 113 nets 82 design area 3888.7 u^2 fixed area 326.6 u^2 movable area 1072.3 u^2 utilization 30 % utilization padded 31 % rows 37 row height 2.7 u Placement Analysis -------------------------------- total displacement 17.8 u average displacement 0.1 u max displacement 9.3 u original HPWL 2268.7 u legalized HPWL 2276.0 u delta HPWL 0 %
[INFO]: Clock Tree Synthesis was successful
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def to /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def Notice 0: Design: gpio_control_block Notice 0: Created 24 pins. Notice 0: Created 187 components and 591 component-terminals. Notice 0: Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def
[INFO]: Changing netlist from /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_optimized.v to /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_cts.v
[INFO]: Generating PDN...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def Notice 0: Design: gpio_control_block Notice 0: Created 24 pins. Notice 0: Created 187 components and 591 component-terminals. Notice 0: Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN [INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/openlane/common_pdn.tcl [INFO] [PDNG-0008] Design Name is gpio_control_block [INFO] [PDNG-0009] Reading technology data [INFO] [PDNG-0011] ****** INFO ****** Type: stdcell, grid Stdcell Rails Layer: met1 - width: 0.480 pitch: 2.720 offset: 0.000 Straps Layer: met4 - width: 1.600 pitch: 12.987 offset: 6.493 Layer: met5 - width: 1.600 pitch: 34.413 offset: 17.207 Connect: {met1 met4} {met4 met5} Type: macro, macro_1 Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90 Straps Connect: [INFO] [PDNG-0012] **** END INFO **** [INFO] [PDNG-0013] Inserting stdcell grid - grid [INFO] [PDNG-0015] Writing to database
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/pdn.def
[INFO]: Routing...
[INFO]: Running Global Routing...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/pdn.def Notice 0: Design: gpio_control_block Notice 0: Created 26 pins. Notice 0: Created 187 components and 591 component-terminals. Notice 0: Created 2 special nets and 0 connections. Notice 0: Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/pdn.def
[PARAMS] Min routing layer: 2 [PARAMS] Max routing layer: 6 [PARAMS] Global adjustment: 0 [PARAMS] Unidirectional routing: 1 [PARAMS] Grid origin: (-1, -1) [INFO] #DB Obstructions: 0 [INFO] #DB Obstacles: 5881 [INFO] #DB Macros: 0 [INFO] Found 0 clock nets [INFO] Minimum degree: 2 [INFO] Maximum degree: 14 [INFO] Processing 3763 obstacles in layer 1 [INFO] Processing 935 obstacles in layer 2 [INFO] Processing 5 obstacles in layer 5 [INFO] Processing 5 obstacles in layer 6 [INFO] Reducing resources of layer 1 by 99% [INFO] WIRELEN : 287, WIRELEN1 : 0 [INFO] NumSeg : 161 [INFO] NumShift: 0 First L Route [INFO] WIRELEN : 287, WIRELEN1 : 287 [INFO] NumSeg : 157 [INFO] NumShift: 4 [Overflow Report] Total hCap : 3060 [Overflow Report] Total vCap : 2594 [Overflow Report] Total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 Second L Route [Overflow Report] Total hCap : 3060 [Overflow Report] Total vCap : 2594 [Overflow Report] Total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 First Z Route [Overflow Report] Total hCap : 3060 [Overflow Report] Total vCap : 2594 [Overflow Report] Total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 [INFO] LV routing round 0, enlarge 10 [INFO] 10 threshold, 10 expand [Overflow Report] total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 [INFO] LV routing round 1, enlarge 15 [INFO] 5 threshold, 15 expand [Overflow Report] total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 [INFO] LV routing round 2, enlarge 20 [INFO] 1 threshold, 20 expand [Overflow Report] total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 Usage checked
Maze routing finished
[INFO] P3 runtime: 0.000000 sec [INFO] Final 2D results: [Overflow Report] total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 60.540001 sec Post Processing Begins
Post Processsing finished
Starting via filling [INFO] Via related to pin nodes 327 [INFO] Via related stiner nodes 20
Via filling finished
Final usage/overflow report: [INFO] Usage per layer: Layer 1 usage: 0 Layer 2 usage: 110 Layer 3 usage: 179 Layer 4 usage: 0 Layer 5 usage: 0 Layer 6 usage: 0 [INFO] Capacity per layer: Layer 1 capacity: 0 Layer 2 capacity: 1770 Layer 3 capacity: 1819 Layer 4 capacity: 1080 Layer 5 capacity: 775 Layer 6 capacity: 210 [INFO] Use percentage per layer: Layer 1 use percentage: 0.0% Layer 2 use percentage: 6.21% Layer 3 use percentage: 9.84% Layer 4 use percentage: 0.00% Layer 5 use percentage: 0.00% Layer 6 use percentage: 0.00% [INFO] Overflow per layer: Layer 1 overflow: 0 Layer 2 overflow: 0 Layer 3 overflow: 0 Layer 4 overflow: 0 Layer 5 overflow: 0 Layer 6 overflow: 0 [Overflow Report] Total Usage : 289 [Overflow Report] Total Capacity: 5654 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 [INFO] Final usage : 289 [INFO] Final number of vias : 384 [INFO] Final usage 3D : 1441 [INFO] Total wirelength: 3850 um Notice 0: Split top of 1 T shapes. Notice 0: Split top of 1 T shapes. Notice 0: Split top of 1 T shapes. Repairing antennas...
[WARNING]No OR_DEFAULT vias defined
[INFO] #Antenna violations: 0 [INFO] Num routed nets: 82
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/pdn.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def Notice 0: Design: gpio_control_block Notice 0: Created 26 pins. Notice 0: Created 187 components and 591 component-terminals. Notice 0: Created 2 special nets and 0 connections. Notice 0: Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
[PARAMS] Min routing layer: 2 [PARAMS] Max routing layer: 6 [PARAMS] Global adjustment: 0 [PARAMS] Unidirectional routing: 1 [PARAMS] Grid origin: (-1, -1) [INFO] #DB Obstructions: 0 [INFO] #DB Obstacles: 5881 [INFO] #DB Macros: 0 [INFO] Found 0 clock nets [INFO] Minimum degree: 2 [INFO] Maximum degree: 14 [INFO] Processing 3763 obstacles in layer 1 [INFO] Processing 935 obstacles in layer 2 [INFO] Processing 5 obstacles in layer 5 [INFO] Processing 5 obstacles in layer 6 [INFO] Reducing resources of layer 1 by 99% [INFO] WIRELEN : 287, WIRELEN1 : 0 [INFO] NumSeg : 161 [INFO] NumShift: 0 First L Route [INFO] WIRELEN : 287, WIRELEN1 : 287 [INFO] NumSeg : 157 [INFO] NumShift: 4 [Overflow Report] Total hCap : 3060 [Overflow Report] Total vCap : 2594 [Overflow Report] Total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 Second L Route [Overflow Report] Total hCap : 3060 [Overflow Report] Total vCap : 2594 [Overflow Report] Total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 First Z Route [Overflow Report] Total hCap : 3060 [Overflow Report] Total vCap : 2594 [Overflow Report] Total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 [INFO] LV routing round 0, enlarge 10 [INFO] 10 threshold, 10 expand [Overflow Report] total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 [INFO] LV routing round 1, enlarge 15 [INFO] 5 threshold, 15 expand [Overflow Report] total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 [INFO] LV routing round 2, enlarge 20 [INFO] 1 threshold, 20 expand [Overflow Report] total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 Usage checked
Maze routing finished
[INFO] P3 runtime: 0.000000 sec [INFO] Final 2D results: [Overflow Report] total Usage : 287 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] Num Overflow e: 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 65.010002 sec Post Processing Begins
Post Processsing finished
Starting via filling [INFO] Via related to pin nodes 327 [INFO] Via related stiner nodes 20
Via filling finished
Final usage/overflow report: [INFO] Usage per layer: Layer 1 usage: 0 Layer 2 usage: 110 Layer 3 usage: 179 Layer 4 usage: 0 Layer 5 usage: 0 Layer 6 usage: 0 [INFO] Capacity per layer: Layer 1 capacity: 0 Layer 2 capacity: 1770 Layer 3 capacity: 1819 Layer 4 capacity: 1080 Layer 5 capacity: 775 Layer 6 capacity: 210 [INFO] Use percentage per layer: Layer 1 use percentage: 0.0% Layer 2 use percentage: 6.21% Layer 3 use percentage: 9.84% Layer 4 use percentage: 0.00% Layer 5 use percentage: 0.00% Layer 6 use percentage: 0.00% [INFO] Overflow per layer: Layer 1 overflow: 0 Layer 2 overflow: 0 Layer 3 overflow: 0 Layer 4 overflow: 0 Layer 5 overflow: 0 Layer 6 overflow: 0 [Overflow Report] Total Usage : 289 [Overflow Report] Total Capacity: 5654 [Overflow Report] Max H Overflow: 0 [Overflow Report] Max V Overflow: 0 [Overflow Report] Max Overflow : 0 [Overflow Report] H Overflow : 0 [Overflow Report] V Overflow : 0 [Overflow Report] Final Overflow: 0 [INFO] Final usage : 289 [INFO] Final number of vias : 384 [INFO] Final usage 3D : 1441 [INFO] Total wirelength: 3850 um [INFO] Num routed nets: 82
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) set IO_PCT 0.2 set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] puts "\[INFO\]: Setting output delay to: $output_delay_value" [INFO]: Setting output delay to: 2.0 puts "\[INFO\]: Setting input delay to: $input_delay_value" [INFO]: Setting input delay to: 2.0 set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] #set rst_indx [lsearch [all_inputs] [get_port resetn]] set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] set all_inputs_wo_clk_rst $all_inputs_wo_clk # correct resetn set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] # TODO set this as parameter set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "\[INFO\]: Setting load to: $cap_load" [INFO]: Setting load to: 0.01765 set_load $cap_load [all_outputs]
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
[INFO]: Current Def is /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
[INFO]: Running Fill Insertion...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def Notice 0: Design: gpio_control_block Notice 0: Created 26 pins. Notice 0: Created 187 components and 591 component-terminals. Notice 0: Created 2 special nets and 0 connections. Notice 0: Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
Placed 276 filler instances.
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/addspacers.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/addspacers.def Notice 0: Design: gpio_control_block Notice 0: Created 26 pins. Notice 0: Created 463 components and 1143 component-terminals. Notice 0: Created 2 special nets and 0 connections. Notice 0: Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/addspacers.def
[INFO]: Changing netlist from /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_cts.v to /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_preroute.v
[INFO]: Running Detailed Routing...
reading lef ... units: 1000 #layers: 13 #macros: 437 #vias: 25 #viarulegen: 25 reading def ... design: gpio_control_block die area: ( 0 0 ) ( 50000 125000 ) trackPts: 12 defvias: 4 #components: 463 #terminals: 26 #snets: 2 #nets: 82 reading guide ... #guides: 578
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx List of default vias: Layer mcon default via: L1M1_PR_MR Layer via default via: M1M2_PR Layer via2 default via: via2_FR Layer via3 default via: M3M4_PR_M Layer via4 default via: via4_FR Writing reference output def... libcell analysis ... instance analysis ... #unique instances = 37 init region query ... complete FR_MASTERSLICE complete FR_VIA complete li1 complete mcon complete met1 complete via complete met2 complete via2 complete met3 complete via3 complete met4 complete via4 complete met5 FR_MASTERSLICE shape region query size = 0 FR_VIA shape region query size = 0 li1 shape region query size = 5159 mcon shape region query size = 6447 met1 shape region query size = 1582 via shape region query size = 380 met2 shape region query size = 190 via2 shape region query size = 380 met3 shape region query size = 214 via3 shape region query size = 380 met4 shape region query size = 113 via4 shape region query size = 13 met5 shape region query size = 20 start pin access
Error: no ap for PIN/VGND
Error: no ap for PIN/VPWR
complete 56 pins complete 31 unique inst patterns complete 73 groups Expt1 runtime (pin-level access point gen): 1.33315 Expt2 runtime (design-level access pattern gen): 0.131903 #scanned instances = 463 #unique instances = 37 #stdCellGenAp = 600 #stdCellValidPlanarAp = 28 #stdCellValidViaAp = 283 #stdCellPinNoAp = 0 #stdCellPinCnt = 216 #instTermValidViaApCnt = 0 #macroGenAp = 0 #macroValidPlanarAp = 0 #macroValidViaAp = 0 #macroNoAp = 0 complete pin access cpu time = 00:00:01, elapsed time = 00:00:01, memory = 13.24 (MB), peak = 13.57 (MB) post process guides ... GCELLGRID X -1 DO 18 STEP 6900 ; GCELLGRID Y -1 DO 7 STEP 6900 ; complete FR_MASTERSLICE complete FR_VIA complete li1 complete mcon complete met1 complete via complete met2 complete via2 complete met3 complete via3 complete met4 complete via4 complete met5 building cmap ... init guide query ... complete FR_MASTERSLICE (guide) complete FR_VIA (guide) complete li1 (guide) complete mcon (guide) complete met1 (guide) complete via (guide) complete met2 (guide) complete via2 (guide) complete met3 (guide) complete via3 (guide) complete met4 (guide) complete via4 (guide) complete met5 (guide) FR_MASTERSLICE guide region query size = 0 FR_VIA guide region query size = 0 li1 guide region query size = 179 mcon guide region query size = 0 met1 guide region query size = 169 via guide region query size = 0 met2 guide region query size = 112 via2 guide region query size = 0 met3 guide region query size = 24 via3 guide region query size = 0 met4 guide region query size = 0 via4 guide region query size = 0 met5 guide region query size = 0 init gr pin query ... start track assignment Done with 291 vertical wires in 1 frboxes and 193 horizontal wires in 1 frboxes. Done with 33 vertical wires in 1 frboxes and 48 horizontal wires in 1 frboxes. complete track assignment cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.35 (MB), peak = 15.82 (MB) post processing ... start routing data preparation initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370) initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460) initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630) initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680) initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020) initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0) initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370) initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1) initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460) initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1) initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630) initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1) initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680) initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1) initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020) initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1) initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0) initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1) initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370) initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460) initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630) initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630) initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020) initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0) initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370) initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460) initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630) initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630) initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020) initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0) initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370) initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460) initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630) initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630) initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020) initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0) cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.49 (MB), peak = 15.82 (MB) start detail routing ... start 0th optimization iteration ... completing 10% with 0 violations elapsed time = 00:00:00, memory = 28.19 (MB) completing 20% with 0 violations elapsed time = 00:00:00, memory = 25.18 (MB) completing 30% with 29 violations elapsed time = 00:00:01, memory = 30.17 (MB) number of violations = 8 cpu time = 00:00:02, elapsed time = 00:00:02, memory = 20.77 (MB), peak = 381.67 (MB) total wire length = 2421 um total wire length on LAYER li1 = 3 um total wire length on LAYER met1 = 820 um total wire length on LAYER met2 = 1244 um total wire length on LAYER met3 = 352 um total wire length on LAYER met4 = 0 um total wire length on LAYER met5 = 0 um total number of vias = 449 up-via summary (total 449): ---------------------- FR_MASTERSLICE 0 li1 194 met1 231 met2 24 met3 0 met4 0 ---------------------- 449 start 1st optimization iteration ... completing 10% with 8 violations elapsed time = 00:00:00, memory = 31.38 (MB) completing 20% with 8 violations elapsed time = 00:00:00, memory = 31.52 (MB) completing 30% with 3 violations elapsed time = 00:00:00, memory = 37.67 (MB) completing 40% with 3 violations elapsed time = 00:00:01, memory = 22.01 (MB) completing 50% with 3 violations elapsed time = 00:00:01, memory = 22.07 (MB) completing 60% with 3 violations elapsed time = 00:00:01, memory = 23.10 (MB) number of violations = 3 cpu time = 00:00:02, elapsed time = 00:00:02, memory = 22.07 (MB), peak = 383.02 (MB) total wire length = 2427 um total wire length on LAYER li1 = 0 um total wire length on LAYER met1 = 818 um total wire length on LAYER met2 = 1249 um total wire length on LAYER met3 = 359 um total wire length on LAYER met4 = 0 um total wire length on LAYER met5 = 0 um total number of vias = 449 up-via summary (total 449): ---------------------- FR_MASTERSLICE 0 li1 190 met1 235 met2 24 met3 0 met4 0 ---------------------- 449 start 2nd optimization iteration ... completing 10% with 3 violations elapsed time = 00:00:00, memory = 22.07 (MB) completing 20% with 3 violations elapsed time = 00:00:00, memory = 24.18 (MB) completing 30% with 3 violations elapsed time = 00:00:00, memory = 22.73 (MB) completing 40% with 3 violations elapsed time = 00:00:00, memory = 24.60 (MB) completing 50% with 3 violations elapsed time = 00:00:00, memory = 26.66 (MB) completing 60% with 3 violations elapsed time = 00:00:00, memory = 34.65 (MB) completing 70% with 0 violations elapsed time = 00:00:00, memory = 21.05 (MB) completing 80% with 0 violations elapsed time = 00:00:00, memory = 26.71 (MB) number of violations = 0 cpu time = 00:00:01, elapsed time = 00:00:01, memory = 26.71 (MB), peak = 387.64 (MB) total wire length = 2415 um total wire length on LAYER li1 = 0 um total wire length on LAYER met1 = 816 um total wire length on LAYER met2 = 1236 um total wire length on LAYER met3 = 363 um total wire length on LAYER met4 = 0 um total wire length on LAYER met5 = 0 um total number of vias = 450 up-via summary (total 450): ---------------------- FR_MASTERSLICE 0 li1 190 met1 236 met2 24 met3 0 met4 0 ---------------------- 450 start 17th optimization iteration ... completing 10% with 0 violations elapsed time = 00:00:00, memory = 28.61 (MB) completing 20% with 0 violations elapsed time = 00:00:00, memory = 29.49 (MB) completing 30% with 0 violations elapsed time = 00:00:00, memory = 28.38 (MB) completing 40% with 0 violations elapsed time = 00:00:00, memory = 26.71 (MB) completing 50% with 0 violations elapsed time = 00:00:00, memory = 26.72 (MB) completing 60% with 0 violations elapsed time = 00:00:00, memory = 27.75 (MB) number of violations = 0 cpu time = 00:00:00, elapsed time = 00:00:00, memory = 27.94 (MB), peak = 387.64 (MB) total wire length = 2415 um total wire length on LAYER li1 = 0 um total wire length on LAYER met1 = 816 um total wire length on LAYER met2 = 1236 um total wire length on LAYER met3 = 363 um total wire length on LAYER met4 = 0 um total wire length on LAYER met5 = 0 um total number of vias = 450 up-via summary (total 450): ---------------------- FR_MASTERSLICE 0 li1 190 met1 236 met2 24 met3 0 met4 0 ---------------------- 450 start 25th optimization iteration ... completing 10% with 0 violations elapsed time = 00:00:00, memory = 24.71 (MB) completing 20% with 0 violations elapsed time = 00:00:00, memory = 25.09 (MB) completing 30% with 0 violations elapsed time = 00:00:00, memory = 25.81 (MB) completing 40% with 0 violations elapsed time = 00:00:00, memory = 26.14 (MB) completing 50% with 0 violations elapsed time = 00:00:00, memory = 24.75 (MB) completing 60% with 0 violations elapsed time = 00:00:00, memory = 27.33 (MB) completing 70% with 0 violations elapsed time = 00:00:00, memory = 29.05 (MB) completing 80% with 0 violations elapsed time = 00:00:00, memory = 29.26 (MB) number of violations = 0 cpu time = 00:00:00, elapsed time = 00:00:00, memory = 29.26 (MB), peak = 387.64 (MB) total wire length = 2415 um total wire length on LAYER li1 = 0 um total wire length on LAYER met1 = 816 um total wire length on LAYER met2 = 1236 um total wire length on LAYER met3 = 363 um total wire length on LAYER met4 = 0 um total wire length on LAYER met5 = 0 um total number of vias = 450 up-via summary (total 450): ---------------------- FR_MASTERSLICE 0 li1 190 met1 236 met2 24 met3 0 met4 0 ---------------------- 450 start 33rd optimization iteration ... completing 10% with 0 violations elapsed time = 00:00:00, memory = 29.26 (MB) completing 20% with 0 violations elapsed time = 00:00:00, memory = 22.60 (MB) completing 30% with 0 violations elapsed time = 00:00:00, memory = 23.66 (MB) completing 40% with 0 violations elapsed time = 00:00:00, memory = 23.13 (MB) completing 50% with 0 violations elapsed time = 00:00:00, memory = 22.60 (MB) completing 60% with 0 violations elapsed time = 00:00:00, memory = 23.48 (MB) completing 70% with 0 violations elapsed time = 00:00:00, memory = 22.96 (MB) completing 80% with 0 violations elapsed time = 00:00:00, memory = 23.48 (MB) completing 90% with 0 violations elapsed time = 00:00:00, memory = 27.14 (MB) completing 100% with 0 violations elapsed time = 00:00:00, memory = 26.83 (MB) number of violations = 0 cpu time = 00:00:00, elapsed time = 00:00:00, memory = 26.83 (MB), peak = 387.64 (MB) total wire length = 2415 um total wire length on LAYER li1 = 0 um total wire length on LAYER met1 = 816 um total wire length on LAYER met2 = 1236 um total wire length on LAYER met3 = 363 um total wire length on LAYER met4 = 0 um total wire length on LAYER met5 = 0 um total number of vias = 450 up-via summary (total 450): ---------------------- FR_MASTERSLICE 0 li1 190 met1 236 met2 24 met3 0 met4 0 ---------------------- 450 start 41st optimization iteration ... completing 10% with 0 violations elapsed time = 00:00:00, memory = 24.35 (MB) completing 20% with 0 violations elapsed time = 00:00:00, memory = 24.36 (MB) completing 30% with 0 violations elapsed time = 00:00:00, memory = 26.17 (MB) completing 40% with 0 violations elapsed time = 00:00:00, memory = 23.38 (MB) completing 50% with 0 violations elapsed time = 00:00:00, memory = 21.80 (MB) completing 60% with 0 violations elapsed time = 00:00:00, memory = 22.68 (MB) completing 70% with 0 violations elapsed time = 00:00:00, memory = 22.68 (MB) completing 80% with 0 violations elapsed time = 00:00:00, memory = 24.04 (MB) completing 90% with 0 violations elapsed time = 00:00:00, memory = 25.95 (MB) completing 100% with 0 violations elapsed time = 00:00:00, memory = 26.21 (MB) number of violations = 0 cpu time = 00:00:00, elapsed time = 00:00:00, memory = 26.21 (MB), peak = 387.64 (MB) total wire length = 2415 um total wire length on LAYER li1 = 0 um total wire length on LAYER met1 = 816 um total wire length on LAYER met2 = 1236 um total wire length on LAYER met3 = 363 um total wire length on LAYER met4 = 0 um total wire length on LAYER met5 = 0 um total number of vias = 450 up-via summary (total 450): ---------------------- FR_MASTERSLICE 0 li1 190 met1 236 met2 24 met3 0 met4 0 ---------------------- 450 start 49th optimization iteration ... completing 10% with 0 violations elapsed time = 00:00:00, memory = 21.83 (MB) completing 20% with 0 violations elapsed time = 00:00:00, memory = 22.61 (MB) completing 30% with 0 violations elapsed time = 00:00:00, memory = 23.58 (MB) completing 40% with 0 violations elapsed time = 00:00:00, memory = 24.81 (MB) completing 50% with 0 violations elapsed time = 00:00:00, memory = 24.81 (MB) completing 60% with 0 violations elapsed time = 00:00:00, memory = 25.06 (MB) completing 70% with 0 violations elapsed time = 00:00:00, memory = 24.36 (MB) completing 80% with 0 violations elapsed time = 00:00:00, memory = 24.36 (MB) completing 90% with 0 violations elapsed time = 00:00:00, memory = 26.39 (MB) completing 100% with 0 violations elapsed time = 00:00:00, memory = 26.39 (MB) number of violations = 0 cpu time = 00:00:00, elapsed time = 00:00:00, memory = 26.39 (MB), peak = 387.64 (MB) total wire length = 2415 um total wire length on LAYER li1 = 0 um total wire length on LAYER met1 = 816 um total wire length on LAYER met2 = 1236 um total wire length on LAYER met3 = 363 um total wire length on LAYER met4 = 0 um total wire length on LAYER met5 = 0 um total number of vias = 450 up-via summary (total 450): ---------------------- FR_MASTERSLICE 0 li1 190 met1 236 met2 24 met3 0 met4 0 ---------------------- 450 start 57th optimization iteration ... completing 10% with 0 violations elapsed time = 00:00:00, memory = 26.39 (MB) completing 20% with 0 violations elapsed time = 00:00:00, memory = 23.55 (MB) completing 30% with 0 violations elapsed time = 00:00:00, memory = 23.65 (MB) completing 40% with 0 violations elapsed time = 00:00:00, memory = 23.57 (MB) completing 50% with 0 violations elapsed time = 00:00:00, memory = 23.57 (MB) completing 60% with 0 violations elapsed time = 00:00:00, memory = 23.57 (MB) completing 70% with 0 violations elapsed time = 00:00:00, memory = 22.76 (MB) completing 80% with 0 violations elapsed time = 00:00:00, memory = 24.78 (MB) completing 90% with 0 violations elapsed time = 00:00:00, memory = 27.16 (MB) completing 100% with 0 violations elapsed time = 00:00:00, memory = 26.90 (MB) number of violations = 0 cpu time = 00:00:00, elapsed time = 00:00:00, memory = 26.90 (MB), peak = 387.64 (MB) total wire length = 2415 um total wire length on LAYER li1 = 0 um total wire length on LAYER met1 = 816 um total wire length on LAYER met2 = 1236 um total wire length on LAYER met3 = 363 um total wire length on LAYER met4 = 0 um total wire length on LAYER met5 = 0 um total number of vias = 450 up-via summary (total 450): ---------------------- FR_MASTERSLICE 0 li1 190 met1 236 met2 24 met3 0 met4 0 ---------------------- 450 complete detail routing total wire length = 2415 um total wire length on LAYER li1 = 0 um total wire length on LAYER met1 = 816 um total wire length on LAYER met2 = 1236 um total wire length on LAYER met3 = 363 um total wire length on LAYER met4 = 0 um total wire length on LAYER met5 = 0 um total number of vias = 450 up-via summary (total 450): ---------------------- FR_MASTERSLICE 0 li1 190 met1 236 met2 24 met3 0 met4 0 ---------------------- 450 cpu time = 00:00:07, elapsed time = 00:00:08, memory = 26.90 (MB), peak = 387.64 (MB) post processing ... Runtime taken (hrt): 11.8858
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/addspacers.def to /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def
[INFO]: Running SPEF Extraction...
Start parsing LEF file... Parsing LEF file done. Start parsing DEF file... Parsing DEF file done. Parameters Used: Edge Capacitance Factor: 1.0 Wire model: L RC Extraction is done Start writing SPEF file Writing SPEF is done
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc. License GPLv3: GNU GPL version 3 This is free software, and you are free to change and redistribute it under certain conditions; type `show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_preroute.v, line 334 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for PHY_74.
Warning: /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_preroute.v, line 389 module sky130_fd_sc_hd__fill_1 not found. Creating black box for FILLER_1_21.
Warning: /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_preroute.v, line 402 module sky130_fd_sc_hd__fill_2 not found. Creating black box for FILLER_2_79.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) set IO_PCT 0.2 set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] puts "\[INFO\]: Setting output delay to: $output_delay_value" [INFO]: Setting output delay to: 2.0 puts "\[INFO\]: Setting input delay to: $input_delay_value" [INFO]: Setting input delay to: 2.0 set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] #set rst_indx [lsearch [all_inputs] [get_port resetn]] set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] set all_inputs_wo_clk_rst $all_inputs_wo_clk # correct resetn set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] # TODO set this as parameter set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "\[INFO\]: Setting load to: $cap_load" [INFO]: Setting load to: 0.01765 set_load $cap_load [all_outputs] tns 0.00 wns 0.00
[INFO]: Routing completed for gpio_control_block/20-11_15-13 in 0h9m55s
[INFO]: Writing Powered Verilog...
Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def Notice 0: Design: gpio_control_block Notice 0: Created 26 pins. Notice 0: Created 463 components and 1143 component-terminals. Notice 0: Created 2 special nets and 0 connections. Notice 0: Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def
Top-level design name: gpio_control_block Found port VPWR of type SIGNAL Found port VGND of type SIGNAL Power net: VPWR Ground net: VGND Modified power connections of 463 cells (Remaining: 0 ).
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/gpio_control_block.powered.def Notice 0: Design: gpio_control_block Notice 0: Created 26 pins. Notice 0: Created 463 components and 1143 component-terminals. Notice 0: Created 2 special nets and 0 connections. Notice 0: Created 84 nets and 1142 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/gpio_control_block.powered.def
[INFO]: Rewriting /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.powered.v into /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.powered.v
[INFO]: Changing netlist from /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_preroute.v to /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.powered.v
[INFO]: Running Magic...
[INFO]: Streaming out GDS II...
Magic 8.3 revision 64 - Compiled on Fri Oct 9 12:13:18 UTC 2020. Starting magic under Tcl interpreter Using the terminal as the console. Using NULL graphics device. Processing system .magicrc file Sourcing design .magicrc for technology sky130A ... 2 Magic internal units = 1 Lambda Input style sky130: scaleFactor=2, multiplier=2 Scaled tech values by 2 / 1 to match internal grid scaling Loading sky130A Device Generator Menu ... Loading "/openLANE_flow/scripts/magic.tcl" from command line. Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef. This action cannot be undone. LEF read, Line 61 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 62 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 95 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 96 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 102 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 103 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 104 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 142 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 143 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 145 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 146 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 147 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 183 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 184 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 186 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 187 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 188 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 224 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 225 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 227 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 228 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 229 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 265 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 266 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read: Processed 772 lines. Reading DEF data from file /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def. This action cannot be undone. Processed 6 vias total. Processed 463 subcell instances total. Processed 26 pins total. Processed 2 special nets total. Processed 82 nets total. DEF read: Processed 2147 lines. [INFO]: Zeroizing Origin [INFO]: Current Box Values: 0 0 10000 23376 [INFO]: Saving .mag view With BBox Values: 0 0 10000 23376 [INFO]: GDS Write Complete Generating LEF output /project/openlane/gpio_control_block/runs/gpio_control_block/results/magic/gpio_control_block.lef for cell gpio_control_block: Diagnostic: Write LEF header for cell gpio_control_block Diagnostic: Writing LEF output for cell gpio_control_block Diagnostic: Scale value is 0.005000 [INFO]: LEF Write Complete [INFO]: MAGIC TAPEOUT STEP DONE
[INFO]: Running Magic Spice Export...
Magic 8.3 revision 64 - Compiled on Fri Oct 9 12:13:18 UTC 2020. Starting magic under Tcl interpreter Using the terminal as the console. Using NULL graphics device. Processing system .magicrc file Sourcing design .magicrc for technology sky130A ... 2 Magic internal units = 1 Lambda Input style sky130: scaleFactor=2, multiplier=2 Scaled tech values by 2 / 1 to match internal grid scaling Loading sky130A Device Generator Menu ... Loading "/project/openlane/gpio_control_block/runs/gpio_control_block/tmp/magic_spice.tcl" from command line. Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef. This action cannot be undone. LEF read, Line 61 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 62 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 95 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 96 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 102 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 103 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 104 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 142 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 143 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 145 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 146 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 147 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 183 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 184 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 186 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 187 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 188 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 224 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 225 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 227 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 228 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 229 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 265 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 266 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read: Processed 772 lines. Reading DEF data from file /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def. This action cannot be undone. Processed 6 vias total. Processed 463 subcell instances total. Processed 26 pins total. Processed 2 special nets total. Processed 82 nets total. DEF read: Processed 2147 lines. Extracting sky130_fd_sc_hd__and3_4 into sky130_fd_sc_hd__and3_4.ext: Extracting sky130_fd_sc_hd__or2_4 into sky130_fd_sc_hd__or2_4.ext: Extracting sky130_fd_sc_hd__a32o_4 into sky130_fd_sc_hd__a32o_4.ext: Extracting sky130_fd_sc_hd__nand2_4 into sky130_fd_sc_hd__nand2_4.ext: Extracting sky130_fd_sc_hd__inv_8 into sky130_fd_sc_hd__inv_8.ext: Extracting sky130_fd_sc_hd__and2_4 into sky130_fd_sc_hd__and2_4.ext: Extracting sky130_fd_sc_hd__buf_1 into sky130_fd_sc_hd__buf_1.ext: Extracting sky130_fd_sc_hd__dfstp_4 into sky130_fd_sc_hd__dfstp_4.ext: Extracting sky130_fd_sc_hd__dfrtp_4 into sky130_fd_sc_hd__dfrtp_4.ext: Extracting sky130_fd_sc_hd__einvp_8 into sky130_fd_sc_hd__einvp_8.ext: Extracting sky130_fd_sc_hd__conb_1 into sky130_fd_sc_hd__conb_1.ext: Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext: Extracting sky130_fd_sc_hd__clkbuf_16 into sky130_fd_sc_hd__clkbuf_16.ext: Extracting sky130_fd_sc_hd__clkbuf_1 into sky130_fd_sc_hd__clkbuf_1.ext: Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext: Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext: Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext: Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext: Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext: Extracting sky130_fd_sc_hd__decap_12 into sky130_fd_sc_hd__decap_12.ext: Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext: Extracting gpio_control_block into gpio_control_block.ext:
exttospice finished.
Using technology "sky130A", version 20200508
[INFO]: Saving Magic Views in /project
[INFO]: Running Magic DRC...
Magic 8.3 revision 64 - Compiled on Fri Oct 9 12:13:18 UTC 2020. Starting magic under Tcl interpreter Using the terminal as the console. Using NULL graphics device. Processing system .magicrc file Sourcing design .magicrc for technology sky130A ... 2 Magic internal units = 1 Lambda Input style sky130: scaleFactor=2, multiplier=2 Scaled tech values by 2 / 1 to match internal grid scaling Loading sky130A Device Generator Menu ... Loading "/openLANE_flow/scripts/magic_drc.tcl" from command line. Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef. This action cannot be undone. LEF read, Line 61 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 62 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 95 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 96 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 102 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 103 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 104 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 142 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 143 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 145 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 146 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 147 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 183 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 184 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 186 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 187 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 188 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 224 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 225 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read, Line 227 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring. LEF read, Line 228 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring. LEF read, Line 229 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring. LEF read, Line 265 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring. LEF read, Line 266 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring. LEF read: Processed 772 lines. Reading DEF data from file /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def. This action cannot be undone. Processed 6 vias total. Processed 463 subcell instances total. Processed 26 pins total. Processed 2 special nets total. Processed 82 nets total. DEF read: Processed 2147 lines. [INFO]: Loading gpio_control_block DRC style is now "drc(full)" Loading DRC CIF style.
No errors found.
[INFO]: COUNT: 0 [INFO]: Should be divided by 3 or 4 [INFO]: DRC Checking DONE (/project/openlane/gpio_control_block/runs/gpio_control_block/logs/magic/magic.drc)
[INFO]: Saving mag view with DRC errors(/project/openlane/gpio_control_block/runs/gpio_control_block/results/magic/gpio_control_block.drc.mag)
[INFO]: Saved
[INFO]: Running LVS...
[INFO]: /project/openlane/gpio_control_block/runs/gpio_control_block/results/magic/gpio_control_block.spice against /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.powered.v
Netgen 1.5.157 compiled on Fri Oct 9 13:50:13 UTC 2020
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Generating JSON file result Reading netlist file /project/openlane/gpio_control_block/runs/gpio_control_block/results/magic/gpio_control_block.spice Reading netlist file /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.powered.v
Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_12. Creating placeholder cell definition for module sky130_fd_sc_hd__decap_4. Creating placeholder cell definition for module sky130_fd_sc_hd__decap_6. Creating placeholder cell definition for module sky130_fd_sc_hd__fill_1. Creating placeholder cell definition for module sky130_fd_sc_hd__decap_8. Creating placeholder cell definition for module sky130_fd_sc_hd__fill_2. Creating placeholder cell definition for module sky130_fd_sc_hd__decap_3. Creating placeholder cell definition for module sky130_fd_sc_hd__tapvpwrvgnd_1. Creating placeholder cell definition for module sky130_fd_sc_hd__or2_4. Creating placeholder cell definition for module sky130_fd_sc_hd__buf_1. Creating placeholder cell definition for module sky130_fd_sc_hd__inv_8. Creating placeholder cell definition for module sky130_fd_sc_hd__a32o_4. Creating placeholder cell definition for module sky130_fd_sc_hd__and3_4. Creating placeholder cell definition for module sky130_fd_sc_hd__nand2_4. Creating placeholder cell definition for module sky130_fd_sc_hd__and2_4. Creating placeholder cell definition for module sky130_fd_sc_hd__dfstp_4. Creating placeholder cell definition for module sky130_fd_sc_hd__dfrtp_4. Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_16. Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_1. Creating placeholder cell definition for module sky130_fd_sc_hd__einvp_8. Creating placeholder cell definition for module sky130_fd_sc_hd__conb_1. Reading setup file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/netgen/sky130A_setup.tcl Comparison output logged to file /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.log Logging to file "/project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.log" enabled Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__buf_1' Circuit sky130_fd_sc_hd__buf_1 contains 0 device instances. Circuit contains 0 nets, and 4 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_1' Circuit sky130_fd_sc_hd__buf_1 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__buf_1 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__dfrtp_4' Circuit sky130_fd_sc_hd__dfrtp_4 contains 0 device instances. Circuit contains 0 nets, and 6 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfrtp_4' Circuit sky130_fd_sc_hd__dfrtp_4 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__dfrtp_4 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1' Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances. Circuit contains 0 nets, and 2 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1' Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__and2_4' Circuit sky130_fd_sc_hd__and2_4 contains 0 device instances. Circuit contains 0 nets, and 5 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_4' Circuit sky130_fd_sc_hd__and2_4 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__and2_4 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__inv_8' Circuit sky130_fd_sc_hd__inv_8 contains 0 device instances. Circuit contains 0 nets, and 4 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__inv_8' Circuit sky130_fd_sc_hd__inv_8 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__inv_8 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__nand2_4' Circuit sky130_fd_sc_hd__nand2_4 contains 0 device instances. Circuit contains 0 nets, and 5 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_4' Circuit sky130_fd_sc_hd__nand2_4 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__nand2_4 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__a32o_4' Circuit sky130_fd_sc_hd__a32o_4 contains 0 device instances. Circuit contains 0 nets, and 8 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a32o_4' Circuit sky130_fd_sc_hd__a32o_4 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__a32o_4 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__einvp_8' Circuit sky130_fd_sc_hd__einvp_8 contains 0 device instances. Circuit contains 0 nets, and 5 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__einvp_8' Circuit sky130_fd_sc_hd__einvp_8 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__einvp_8 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__or2_4' Circuit sky130_fd_sc_hd__or2_4 contains 0 device instances. Circuit contains 0 nets, and 5 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or2_4' Circuit sky130_fd_sc_hd__or2_4 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__or2_4 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__and3_4' Circuit sky130_fd_sc_hd__and3_4 contains 0 device instances. Circuit contains 0 nets, and 6 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and3_4' Circuit sky130_fd_sc_hd__and3_4 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__and3_4 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__clkbuf_1' Circuit sky130_fd_sc_hd__clkbuf_1 contains 0 device instances. Circuit contains 0 nets, and 4 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_1' Circuit sky130_fd_sc_hd__clkbuf_1 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__clkbuf_1 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__conb_1' Circuit sky130_fd_sc_hd__conb_1 contains 0 device instances. Circuit contains 0 nets, and 4 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__conb_1' Circuit sky130_fd_sc_hd__conb_1 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__conb_1 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__dfstp_4' Circuit sky130_fd_sc_hd__dfstp_4 contains 0 device instances. Circuit contains 0 nets, and 6 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfstp_4' Circuit sky130_fd_sc_hd__dfstp_4 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__dfstp_4 contains no devices. Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__clkbuf_16' Circuit sky130_fd_sc_hd__clkbuf_16 contains 0 device instances. Circuit contains 0 nets, and 4 disconnected pins. Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_16' Circuit sky130_fd_sc_hd__clkbuf_16 contains 0 device instances. Circuit contains 0 nets. Circuit sky130_fd_sc_hd__clkbuf_16 contains no devices. Contents of circuit 1: Circuit: 'gpio_control_block' Circuit gpio_control_block contains 113 device instances. Class: sky130_fd_sc_hd__clkbuf_16 instances: 1 Class: sky130_fd_sc_hd__buf_1 instances: 31 Class: sky130_fd_sc_hd__dfstp_4 instances: 3 Class: sky130_fd_sc_hd__dfrtp_4 instances: 23 Class: sky130_fd_sc_hd__inv_8 instances: 3 Class: sky130_fd_sc_hd__clkbuf_1 instances: 2 Class: sky130_fd_sc_hd__conb_1 instances: 1 Class: sky130_fd_sc_hd__and3_4 instances: 1 Class: sky130_fd_sc_hd__or2_4 instances: 2 Class: sky130_fd_sc_hd__einvp_8 instances: 1 Class: sky130_fd_sc_hd__nand2_4 instances: 2 Class: sky130_fd_sc_hd__and2_4 instances: 2 Class: sky130_fd_sc_hd__a32o_4 instances: 2 Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 39 Circuit contains 85 nets. Contents of circuit 2: Circuit: 'gpio_control_block' Circuit gpio_control_block contains 113 device instances. Class: sky130_fd_sc_hd__clkbuf_16 instances: 1 Class: sky130_fd_sc_hd__buf_1 instances: 31 Class: sky130_fd_sc_hd__dfstp_4 instances: 3 Class: sky130_fd_sc_hd__dfrtp_4 instances: 23 Class: sky130_fd_sc_hd__inv_8 instances: 3 Class: sky130_fd_sc_hd__clkbuf_1 instances: 2 Class: sky130_fd_sc_hd__conb_1 instances: 1 Class: sky130_fd_sc_hd__and3_4 instances: 1 Class: sky130_fd_sc_hd__or2_4 instances: 2 Class: sky130_fd_sc_hd__einvp_8 instances: 1 Class: sky130_fd_sc_hd__nand2_4 instances: 2 Class: sky130_fd_sc_hd__and2_4 instances: 2 Class: sky130_fd_sc_hd__a32o_4 instances: 2 Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 39 Circuit contains 84 nets. Circuit 1 contains 113 devices, Circuit 2 contains 113 devices. Circuit 1 contains 84 nets, Circuit 2 contains 84 nets. Circuits match with 1 symmetry. Resolving automorphisms by property value. Resolving automorphisms by pin name. Netlists match with 1 symmetry. Circuits match correctly. Result: Circuits match uniquely. Logging to file "/project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.log" disabled LVS Done. LVS reports no net, device, pin, or property mismatches.
Total errors = 0
[INFO]: Running Antenna Checks...
[INFO]: Running OpenROAD Antenna Rule Checker...
OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 437 library cells
Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def Notice 0: Design: gpio_control_block Notice 0: Created 26 pins. Notice 0: Created 463 components and 1143 component-terminals. Notice 0: Created 2 special nets and 0 connections. Notice 0: Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def
Notice 0: Split top of 24 T shapes. Number of pins violated: 0 Number of nets violated: 0 Total number of nets: 82
[INFO]: Generating Final Summary Report...
[SUCCESS]: Flow Completed Without Fatal Errors.

Submodule: mgmt_core

###############################################
/bin/sh: 1: [[: not found
[INFO]: ___ ____ ___ ____ _ ____ ____ ___ / \ | \ / _]| \ | | / || \ / _] | || o ) [_ | _ || | | o || _ | / [_ | O || _/ _]| | || |___ | || | || _] | || | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____|
[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/mgmt_core/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/mgmt_core/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/mgmt_core/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/mgmt_core/runs/mgmt_core
[WARNING]: Removing exisiting run /project/openlane/mgmt_core/runs/mgmt_core
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs sky130_fd_sc_hd.lef: SITEs matched found: 0 sky130_fd_sc_hd.lef: MACROs matched found: 437 mergeLef.py : Merging LEFs complete mergeLef.py : Merging LEFs DFFRAM.lef: SITEs matched found: 0 DFFRAM.lef: MACROs matched found: 1 digital_pll.lef: SITEs matched found: 0 digital_pll.lef: MACROs matched found: 1 mergeLef.py : Merging LEFs complete
[INFO]: Merging the following extra LEFs: /project/openlane/mgmt_core/../../lef/DFFRAM.lef /project/openlane/mgmt_core/../../lef/digital_pll.lef
padLefMacro.py : Padding technology lef file Derived SITE width (microns): 0.46 Derived SITE height (microns): 5.44 Right cell padding (microns): 3.68 Left cell padding (microns): 0.0 Top cell padding (microns): 0.0 Bottom cell padding (microns): 0.0 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd2_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_12 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_3 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_6 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_2 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvpwrvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...
/----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. 1. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/defines.v Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/DFFRAM.v Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/DFFRAM.v' to AST representation. Generating RTLIL representation for module `\DFFRAM'.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/digital_pll.v Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/digital_pll.v' to AST representation. Generating RTLIL representation for module `\digital_pll_controller'. Generating RTLIL representation for module `\delay_stage'. Generating RTLIL representation for module `\start_stage'. Generating RTLIL representation for module `\ring_osc2x13'. Generating RTLIL representation for module `\digital_pll'.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/defines.v Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
5. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v' to AST representation. Generating RTLIL representation for module `\storage_bridge_wb'.
Successfully finished Verilog frontend.
6. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/clock_div.v Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v' to AST representation. Generating RTLIL representation for module `\clock_div'. Generating RTLIL representation for module `\odd'. Generating RTLIL representation for module `\even'.
Successfully finished Verilog frontend.
7. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v' to AST representation. Generating RTLIL representation for module `\caravel_clocking'.
Successfully finished Verilog frontend.
8. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v' to AST representation. Generating RTLIL representation for module `\mgmt_core'.
Successfully finished Verilog frontend.
9. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:192)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:193)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:198)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:162)
Generating RTLIL representation for module `\picorv32'. Generating RTLIL representation for module `\picorv32_regs'. Generating RTLIL representation for module `\picorv32_pcpi_mul'. Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'. Generating RTLIL representation for module `\picorv32_pcpi_div'. Generating RTLIL representation for module `\picorv32_axi'. Generating RTLIL representation for module `\picorv32_axi_adapter'. Generating RTLIL representation for module `\picorv32_wb'. Generating RTLIL representation for module `\spimemio_wb'. Generating RTLIL representation for module `\spimemio'. Generating RTLIL representation for module `\spimemio_xfer'. Generating RTLIL representation for module `\simpleuart_wb'. Generating RTLIL representation for module `\simpleuart'. Generating RTLIL representation for module `\simple_spi_master_wb'. Generating RTLIL representation for module `\simple_spi_master'. Generating RTLIL representation for module `\counter_timer_high_wb'. Generating RTLIL representation for module `\counter_timer_high'. Generating RTLIL representation for module `\counter_timer_low_wb'. Generating RTLIL representation for module `\counter_timer_low'. Generating RTLIL representation for module `\wb_intercon'. Generating RTLIL representation for module `\mem_wb'. Generating RTLIL representation for module `\soc_mem'. Generating RTLIL representation for module `\gpio_wb'. Generating RTLIL representation for module `\gpio'. Generating RTLIL representation for module `\sysctrl_wb'. Generating RTLIL representation for module `\sysctrl'. Generating RTLIL representation for module `\la_wb'. Generating RTLIL representation for module `\la'. Generating RTLIL representation for module `\mprj_ctrl_wb'. Generating RTLIL representation for module `\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270
Generating RTLIL representation for module `\convert_gpio_sigs'. Generating RTLIL representation for module `\mgmt_soc'. Generating RTLIL representation for module `\mgmt_soc_regs'.
Successfully finished Verilog frontend.
10. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:129)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:130)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:131)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:133)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:134)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:135)
Generating RTLIL representation for module `\housekeeping_spi'. Generating RTLIL representation for module `\housekeeping_spi_slave'.
Successfully finished Verilog frontend.
11. Executing HIERARCHY pass (managing design hierarchy). 11.1. Analyzing design hierarchy.. Top module: \mgmt_core Used module: \housekeeping_spi Used module: \housekeeping_spi_slave Used module: \mgmt_soc Used module: \wb_intercon Used module: \storage_bridge_wb Used module: \mem_wb Used module: \soc_mem Used module: \mprj_ctrl_wb Used module: \mprj_ctrl Used module: \la_wb Used module: \la Used module: \sysctrl_wb Used module: \sysctrl Used module: \gpio_wb Used module: \gpio Used module: \counter_timer_high_wb Used module: \counter_timer_high Used module: \counter_timer_low_wb Used module: \counter_timer_low Used module: \simple_spi_master_wb Used module: \simple_spi_master Used module: \simpleuart_wb Used module: \simpleuart Used module: \spimemio_wb Used module: \spimemio Used module: \spimemio_xfer Used module: \picorv32_wb Used module: \picorv32 Used module: \mgmt_soc_regs Used module: \convert_gpio_sigs Used module: \caravel_clocking Used module: \clock_div Used module: \odd Used module: \even Parameter \SIZE = 3 11.2. Executing AST frontend in derive mode using pre-parsed AST for module `\clock_div'. Parameter \SIZE = 3 Generating RTLIL representation for module `$paramod\clock_div\SIZE=3'. Parameter \SIZE = 3 Found cached RTLIL representation for module `$paramod\clock_div\SIZE=3'. Parameter \DW = 32 Parameter \AW = 32 Parameter \NS = 14 Parameter \ADR_MASK = 448'1111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000 Parameter \SLAVE_ADR = 448'0010111100000000000000000000000000101101000000000000000000000000001100000000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 11.3. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_intercon'. Parameter \DW = 32 Parameter \AW = 32 Parameter \NS = 14 Parameter \ADR_MASK = 448'1111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000 Parameter \SLAVE_ADR = 448'0010111100000000000000000000000000101101000000000000000000000000001100000000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 Generating RTLIL representation for module `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon'. Parameter \RW_BLOCKS_ADR = 48'000100000000000000000000000000000000000000000000 Parameter \RO_BLOCKS_ADR = 24'000000000000000000000000 11.4. Executing AST frontend in derive mode using pre-parsed AST for module `\storage_bridge_wb'. Parameter \RW_BLOCKS_ADR = 48'000100000000000000000000000000000000000000000000 Parameter \RO_BLOCKS_ADR = 24'000000000000000000000000 Generating RTLIL representation for module `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb'. Parameter \BASE_ADR = 637534208 11.5. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl_wb'. Parameter \BASE_ADR = 637534208 Generating RTLIL representation for module `$paramod\mprj_ctrl_wb\BASE_ADR=637534208'. Parameter \BASE_ADR = 620756992 Parameter \LA_DATA_0 = 8'00000000 Parameter \LA_DATA_1 = 8'00000100 Parameter \LA_DATA_3 = 8'00001100 Parameter \LA_ENA_0 = 8'00010000 Parameter \LA_ENA_1 = 8'00010100 Parameter \LA_ENA_2 = 8'00011000 Parameter \LA_ENA_3 = 8'00011100 11.6. Executing AST frontend in derive mode using pre-parsed AST for module `\la_wb'. Parameter \BASE_ADR = 620756992 Parameter \LA_DATA_0 = 8'00000000 Parameter \LA_DATA_1 = 8'00000100 Parameter \LA_DATA_3 = 8'00001100 Parameter \LA_ENA_0 = 8'00010000 Parameter \LA_ENA_1 = 8'00010100 Parameter \LA_ENA_2 = 8'00011000 Parameter \LA_ENA_3 = 8'00011100 Generating RTLIL representation for module `$paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb'. Parameter \BASE_ADR = 788529152 Parameter \PWRGOOD = 8'00000000 Parameter \CLK_OUT = 8'00000100 Parameter \TRAP_OUT = 8'00001000 Parameter \IRQ_SRC = 8'00001100 11.7. Executing AST frontend in derive mode using pre-parsed AST for module `\sysctrl_wb'. Parameter \BASE_ADR = 788529152 Parameter \PWRGOOD = 8'00000000 Parameter \CLK_OUT = 8'00000100 Parameter \TRAP_OUT = 8'00001000 Parameter \IRQ_SRC = 8'00001100 Generating RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb'. Parameter \BASE_ADR = 553648128 Parameter \GPIO_DATA = 8'00000000 Parameter \GPIO_ENA = 8'00000100 Parameter \GPIO_PU = 8'00001000 Parameter \GPIO_PD = 8'00001100 11.8. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio_wb'. Parameter \BASE_ADR = 553648128 Parameter \GPIO_DATA = 8'00000000 Parameter \GPIO_ENA = 8'00000100 Parameter \GPIO_PU = 8'00001000 Parameter \GPIO_PD = 8'00001100 Generating RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb'. Parameter \BASE_ADR = 587202560 Parameter \CONFIG = 8'00000000 Parameter \VALUE = 8'00000100 Parameter \DATA = 8'00001000 11.9. Executing AST frontend in derive mode using pre-parsed AST for module `\counter_timer_high_wb'. Parameter \BASE_ADR = 587202560 Parameter \CONFIG = 8'00000000 Parameter \VALUE = 8'00000100 Parameter \DATA = 8'00001000 Generating RTLIL representation for module `$paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb'. Parameter \BASE_ADR = 570425344 Parameter \CONFIG = 8'00000000 Parameter \VALUE = 8'00000100 Parameter \DATA = 8'00001000 11.10. Executing AST frontend in derive mode using pre-parsed AST for module `\counter_timer_low_wb'. Parameter \BASE_ADR = 570425344 Parameter \CONFIG = 8'00000000 Parameter \VALUE = 8'00000100 Parameter \DATA = 8'00001000 Generating RTLIL representation for module `$paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb'. Parameter \BASE_ADR = 603979776 Parameter \CONFIG = 8'00000000 Parameter \DATA = 8'00000100 11.11. Executing AST frontend in derive mode using pre-parsed AST for module `\simple_spi_master_wb'. Parameter \BASE_ADR = 603979776 Parameter \CONFIG = 8'00000000 Parameter \DATA = 8'00000100 Generating RTLIL representation for module `$paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100'. Parameter \BASE_ADR = 536870912 Parameter \CLK_DIV = 8'00000000 Parameter \DATA = 8'00000100 11.12. Executing AST frontend in derive mode using pre-parsed AST for module `\simpleuart_wb'. Parameter \BASE_ADR = 536870912 Parameter \CLK_DIV = 8'00000000 Parameter \DATA = 8'00000100 Generating RTLIL representation for module `$paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100'. Parameter \BARREL_SHIFTER = 1 Parameter \COMPRESSED_ISA = 1 Parameter \ENABLE_MUL = 1 Parameter \ENABLE_DIV = 1 Parameter \ENABLE_IRQ = 1 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 268435456 Parameter \PROGADDR_IRQ = 0 Parameter \STACKADDR = 1024 11.13. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32_wb'. Parameter \BARREL_SHIFTER = 1 Parameter \COMPRESSED_ISA = 1 Parameter \ENABLE_MUL = 1 Parameter \ENABLE_DIV = 1 Parameter \ENABLE_IRQ = 1 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 268435456 Parameter \PROGADDR_IRQ = 0 Parameter \STACKADDR = 1024 Generating RTLIL representation for module `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb'. Parameter \ENABLE_COUNTERS = 1'1 Parameter \ENABLE_COUNTERS64 = 1'1 Parameter \ENABLE_REGS_16_31 = 1'1 Parameter \ENABLE_REGS_DUALPORT = 1'1 Parameter \TWO_STAGE_SHIFT = 1'1 Parameter \BARREL_SHIFTER = 1'0 Parameter \TWO_CYCLE_COMPARE = 1'0 Parameter \TWO_CYCLE_ALU = 1'0 Parameter \COMPRESSED_ISA = 1'0 Parameter \CATCH_MISALIGN = 1'1 Parameter \CATCH_ILLINSN = 1'1 Parameter \ENABLE_PCPI = 1'0 Parameter \ENABLE_MUL = 1'0 Parameter \ENABLE_FAST_MUL = 1'0 Parameter \ENABLE_DIV = 1'0 Parameter \ENABLE_IRQ = 1'0 Parameter \ENABLE_IRQ_QREGS = 1'1 Parameter \ENABLE_IRQ_TIMER = 1'1 Parameter \ENABLE_TRACE = 1'0 Parameter \REGS_INIT_ZERO = 1'0 Parameter \MASKED_IRQ = 0 Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111 Parameter \PROGADDR_RESET = 0 Parameter \PROGADDR_IRQ = 16 Parameter \STACKADDR = 32'11111111111111111111111111111111 11.14. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'. Parameter \ENABLE_COUNTERS = 1'1 Parameter \ENABLE_COUNTERS64 = 1'1 Parameter \ENABLE_REGS_16_31 = 1'1 Parameter \ENABLE_REGS_DUALPORT = 1'1 Parameter \TWO_STAGE_SHIFT = 1'1 Parameter \BARREL_SHIFTER = 1'0 Parameter \TWO_CYCLE_COMPARE = 1'0 Parameter \TWO_CYCLE_ALU = 1'0 Parameter \COMPRESSED_ISA = 1'0 Parameter \CATCH_MISALIGN = 1'1 Parameter \CATCH_ILLINSN = 1'1 Parameter \ENABLE_PCPI = 1'0 Parameter \ENABLE_MUL = 1'0 Parameter \ENABLE_FAST_MUL = 1'0 Parameter \ENABLE_DIV = 1'0 Parameter \ENABLE_IRQ = 1'0 Parameter \ENABLE_IRQ_QREGS = 1'1 Parameter \ENABLE_IRQ_TIMER = 1'1 Parameter \ENABLE_TRACE = 1'0 Parameter \REGS_INIT_ZERO = 1'0 Parameter \MASKED_IRQ = 0 Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111 Parameter \PROGADDR_RESET = 0 Parameter \PROGADDR_IRQ = 16 Parameter \STACKADDR = 32'11111111111111111111111111111111 Generating RTLIL representation for module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'. Parameter \WORDS = 256 Parameter \ADR_WIDTH = 8 11.15. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_mem'. Parameter \WORDS = 256 Parameter \ADR_WIDTH = 8 Generating RTLIL representation for module `$paramod\soc_mem\WORDS=256\ADR_WIDTH=8'. Parameter \BASE_ADR = 553648128 Parameter \GPIO_DATA = 8'00000000 Parameter \GPIO_ENA = 8'00000100 Parameter \GPIO_PU = 8'00001000 Parameter \GPIO_PD = 8'00001100 11.16. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio'. Parameter \BASE_ADR = 553648128 Parameter \GPIO_DATA = 8'00000000 Parameter \GPIO_ENA = 8'00000100 Parameter \GPIO_PU = 8'00001000 Parameter \GPIO_PD = 8'00001100 Generating RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio'. Parameter \BASE_ADR = 788529152 Parameter \PWRGOOD = 8'00000000 Parameter \CLK_OUT = 8'00000100 Parameter \TRAP_OUT = 8'00001000 Parameter \IRQ_SRC = 8'00001100 11.17. Executing AST frontend in derive mode using pre-parsed AST for module `\sysctrl'. Parameter \BASE_ADR = 788529152 Parameter \PWRGOOD = 8'00000000 Parameter \CLK_OUT = 8'00000100 Parameter \TRAP_OUT = 8'00001000 Parameter \IRQ_SRC = 8'00001100 Generating RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl'. Parameter \BASE_ADR = 570425344 Parameter \LA_DATA_0 = 8'00000000 Parameter \LA_DATA_1 = 8'00000100 Parameter \LA_DATA_2 = 8'00001000 Parameter \LA_DATA_3 = 8'00001100 Parameter \LA_ENA_0 = 8'00010000 Parameter \LA_ENA_1 = 8'00010100 Parameter \LA_ENA_2 = 8'00011000 Parameter \LA_ENA_3 = 8'00011100 11.18. Executing AST frontend in derive mode using pre-parsed AST for module `\la'. Parameter \BASE_ADR = 570425344 Parameter \LA_DATA_0 = 8'00000000 Parameter \LA_DATA_1 = 8'00000100 Parameter \LA_DATA_2 = 8'00001000 Parameter \LA_DATA_3 = 8'00001100 Parameter \LA_ENA_0 = 8'00010000 Parameter \LA_ENA_1 = 8'00010100 Parameter \LA_ENA_2 = 8'00011000 Parameter \LA_ENA_3 = 8'00011100 Generating RTLIL representation for module `$paramod$499b0a1c054fbe1b70d6dc28b15376e5cd987bff\la'. Parameter \BASE_ADR = 587202560 Parameter \XFER = 8'00000000 Parameter \PWRDATA = 8'00000100 Parameter \IODATA = 8'00001000 Parameter \IOCONFIG = 8'00100000 11.19. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl'. Parameter \BASE_ADR = 587202560 Parameter \XFER = 8'00000000 Parameter \PWRDATA = 8'00000100 Parameter \IODATA = 8'00001000 Parameter \IOCONFIG = 8'00100000 Generating RTLIL representation for module `$paramod$ed88d8bd975b89882ecfbd510fe3c5e6ac127a6b\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270
11.20. Analyzing design hierarchy.. Top module: \mgmt_core Used module: \housekeeping_spi Used module: \housekeeping_spi_slave Used module: \mgmt_soc Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon Used module: $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb Used module: \mem_wb Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8 Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208 Used module: \mprj_ctrl Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb Used module: \la Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb Used module: \sysctrl Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb Used module: \gpio Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb Used module: \counter_timer_high Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb Used module: \counter_timer_low Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100 Used module: \simple_spi_master Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100 Used module: \simpleuart Used module: \spimemio_wb Used module: \spimemio Used module: \spimemio_xfer Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb Used module: \picorv32 Used module: \mgmt_soc_regs Used module: \convert_gpio_sigs Used module: \caravel_clocking Used module: $paramod\clock_div\SIZE=3 Used module: \odd Used module: \even Parameter \BASE_ADR = 637534208 Parameter \XFER = 8'00000000 Parameter \PWRDATA = 8'00000100 Parameter \IODATA = 8'00001000 Parameter \IOCONFIG = 8'00100000 11.21. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl'. Parameter \BASE_ADR = 637534208 Parameter \XFER = 8'00000000 Parameter \PWRDATA = 8'00000100 Parameter \IODATA = 8'00001000 Parameter \IOCONFIG = 8'00100000 Generating RTLIL representation for module `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270
Parameter \BASE_ADR = 620756992 Parameter \LA_DATA_0 = 8'00000000 Parameter \LA_DATA_1 = 8'00000100 Parameter \LA_DATA_2 = 8'00001000 Parameter \LA_DATA_3 = 8'00001100 Parameter \LA_ENA_0 = 8'00010000 Parameter \LA_ENA_1 = 8'00010100 Parameter \LA_ENA_2 = 8'00011000 Parameter \LA_ENA_3 = 8'00011100 11.22. Executing AST frontend in derive mode using pre-parsed AST for module `\la'. Parameter \BASE_ADR = 620756992 Parameter \LA_DATA_0 = 8'00000000 Parameter \LA_DATA_1 = 8'00000100 Parameter \LA_DATA_2 = 8'00001000 Parameter \LA_DATA_3 = 8'00001100 Parameter \LA_ENA_0 = 8'00010000 Parameter \LA_ENA_1 = 8'00010100 Parameter \LA_ENA_2 = 8'00011000 Parameter \LA_ENA_3 = 8'00011100 Generating RTLIL representation for module `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la'. Parameter \BASE_ADR = 788529152 Parameter \PWRGOOD = 8'00000000 Parameter \CLK_OUT = 8'00000100 Parameter \TRAP_OUT = 8'00001000 Parameter \IRQ_SRC = 8'00001100 Found cached RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl'. Parameter \BASE_ADR = 553648128 Parameter \GPIO_DATA = 8'00000000 Parameter \GPIO_ENA = 8'00000100 Parameter \GPIO_PU = 8'00001000 Parameter \GPIO_PD = 8'00001100 Found cached RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio'. Parameter \ENABLE_COUNTERS = 1'1 Parameter \ENABLE_COUNTERS64 = 1'1 Parameter \ENABLE_REGS_16_31 = 1'1 Parameter \ENABLE_REGS_DUALPORT = 1'1 Parameter \TWO_STAGE_SHIFT = 1'1 Parameter \BARREL_SHIFTER = 1'1 Parameter \TWO_CYCLE_COMPARE = 1'0 Parameter \TWO_CYCLE_ALU = 1'0 Parameter \COMPRESSED_ISA = 1'1 Parameter \CATCH_MISALIGN = 1'1 Parameter \CATCH_ILLINSN = 1'1 Parameter \ENABLE_PCPI = 1'0 Parameter \ENABLE_MUL = 1'1 Parameter \ENABLE_FAST_MUL = 1'0 Parameter \ENABLE_DIV = 1'1 Parameter \ENABLE_IRQ = 1'1 Parameter \ENABLE_IRQ_QREGS = 1'0 Parameter \ENABLE_IRQ_TIMER = 1'1 Parameter \ENABLE_TRACE = 1'0 Parameter \REGS_INIT_ZERO = 1'0 Parameter \MASKED_IRQ = 0 Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111 Parameter \PROGADDR_RESET = 268435456 Parameter \PROGADDR_IRQ = 0 Parameter \STACKADDR = 1024 11.23. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'. Parameter \ENABLE_COUNTERS = 1'1 Parameter \ENABLE_COUNTERS64 = 1'1 Parameter \ENABLE_REGS_16_31 = 1'1 Parameter \ENABLE_REGS_DUALPORT = 1'1 Parameter \TWO_STAGE_SHIFT = 1'1 Parameter \BARREL_SHIFTER = 1'1 Parameter \TWO_CYCLE_COMPARE = 1'0 Parameter \TWO_CYCLE_ALU = 1'0 Parameter \COMPRESSED_ISA = 1'1 Parameter \CATCH_MISALIGN = 1'1 Parameter \CATCH_ILLINSN = 1'1 Parameter \ENABLE_PCPI = 1'0 Parameter \ENABLE_MUL = 1'1 Parameter \ENABLE_FAST_MUL = 1'0 Parameter \ENABLE_DIV = 1'1 Parameter \ENABLE_IRQ = 1'1 Parameter \ENABLE_IRQ_QREGS = 1'0 Parameter \ENABLE_IRQ_TIMER = 1'1 Parameter \ENABLE_TRACE = 1'0 Parameter \REGS_INIT_ZERO = 1'0 Parameter \MASKED_IRQ = 0 Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111 Parameter \PROGADDR_RESET = 268435456 Parameter \PROGADDR_IRQ = 0 Parameter \STACKADDR = 1024 Generating RTLIL representation for module `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32'. 11.24. Analyzing design hierarchy.. Top module: \mgmt_core Used module: \housekeeping_spi Used module: \housekeeping_spi_slave Used module: \mgmt_soc Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon Used module: $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb Used module: \mem_wb Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8 Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208 Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb Used module: \counter_timer_high Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb Used module: \counter_timer_low Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100 Used module: \simple_spi_master Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100 Used module: \simpleuart Used module: \spimemio_wb Used module: \spimemio Used module: \spimemio_xfer Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32 Used module: \picorv32_pcpi_div Used module: \picorv32_pcpi_mul Used module: \mgmt_soc_regs Used module: \convert_gpio_sigs Used module: \caravel_clocking Used module: $paramod\clock_div\SIZE=3 Used module: \odd Used module: \even 11.25. Analyzing design hierarchy.. Top module: \mgmt_core Used module: \housekeeping_spi Used module: \housekeeping_spi_slave Used module: \mgmt_soc Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon Used module: $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb Used module: \mem_wb Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8 Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208 Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb Used module: \counter_timer_high Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb Used module: \counter_timer_low Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100 Used module: \simple_spi_master Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100 Used module: \simpleuart Used module: \spimemio_wb Used module: \spimemio Used module: \spimemio_xfer Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32 Used module: \picorv32_pcpi_div Used module: \picorv32_pcpi_mul Used module: \mgmt_soc_regs Used module: \convert_gpio_sigs Used module: \caravel_clocking Used module: $paramod\clock_div\SIZE=3 Used module: \odd Used module: \even Removing unused module `$paramod$ed88d8bd975b89882ecfbd510fe3c5e6ac127a6b\mprj_ctrl'. Removing unused module `$paramod$499b0a1c054fbe1b70d6dc28b15376e5cd987bff\la'. Removing unused module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'. Removing unused module `\mprj_ctrl'. Removing unused module `\mprj_ctrl_wb'. Removing unused module `\la'. Removing unused module `\la_wb'. Removing unused module `\sysctrl'. Removing unused module `\sysctrl_wb'. Removing unused module `\gpio'. Removing unused module `\gpio_wb'. Removing unused module `\soc_mem'. Removing unused module `\wb_intercon'. Removing unused module `\counter_timer_low_wb'. Removing unused module `\counter_timer_high_wb'. Removing unused module `\simple_spi_master_wb'. Removing unused module `\simpleuart_wb'. Removing unused module `\picorv32_wb'. Removing unused module `\picorv32_axi_adapter'. Removing unused module `\picorv32_axi'. Removing unused module `\picorv32_pcpi_fast_mul'. Removing unused module `\picorv32_regs'. Removing unused module `\picorv32'. Removing unused module `\clock_div'. Removing unused module `\storage_bridge_wb'. Removed 25 unused modules. Mapping positional arguments of cell $paramod\clock_div\SIZE=3.odd_0 (odd). Mapping positional arguments of cell $paramod\clock_div\SIZE=3.even_0 (even). 12. Executing SYNTH pass. 12.1. Executing HIERARCHY pass (managing design hierarchy). 12.1.1. Analyzing design hierarchy.. Top module: \mgmt_core Used module: \housekeeping_spi Used module: \housekeeping_spi_slave Used module: \mgmt_soc Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon Used module: $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb Used module: \mem_wb Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8 Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208 Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb Used module: \counter_timer_high Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb Used module: \counter_timer_low Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100 Used module: \simple_spi_master Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100 Used module: \simpleuart Used module: \spimemio_wb Used module: \spimemio Used module: \spimemio_xfer Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32 Used module: \picorv32_pcpi_div Used module: \picorv32_pcpi_mul Used module: \mgmt_soc_regs Used module: \convert_gpio_sigs Used module: \caravel_clocking Used module: $paramod\clock_div\SIZE=3 Used module: \odd Used module: \even 12.1.2. Analyzing design hierarchy.. Top module: \mgmt_core Used module: \housekeeping_spi Used module: \housekeeping_spi_slave Used module: \mgmt_soc Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon Used module: $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb Used module: \mem_wb Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8 Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208 Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb Used module: \counter_timer_high Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb Used module: \counter_timer_low Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100 Used module: \simple_spi_master Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100 Used module: \simpleuart Used module: \spimemio_wb Used module: \spimemio Used module: \spimemio_xfer Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32 Used module: \picorv32_pcpi_div Used module: \picorv32_pcpi_mul Used module: \mgmt_soc_regs Used module: \convert_gpio_sigs Used module: \caravel_clocking Used module: $paramod\clock_div\SIZE=3 Used module: \odd Used module: \even Removed 0 unused modules. 12.2. Executing PROC pass (convert processes to netlists). 12.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 16 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. Found and cleaned up 1 empty switch in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'. Found and cleaned up 6 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:546$6993'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:546$6993'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'. Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'. Found and cleaned up 1 empty switch in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. Cleaned up 62 empty switches. 12.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 41 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 8 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 47 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Removed 2 dead cases from process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Marked 8 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855 in module $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la. Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443 in module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl. Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433 in module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 11 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 43 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757 in module $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156 in module mem_wb. Marked 22 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519 in module counter_timer_low. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509 in module counter_timer_low. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507 in module counter_timer_low. Marked 17 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458 in module counter_timer_high. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450 in module counter_timer_high. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448 in module counter_timer_high. Marked 5 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413 in module simple_spi_master. Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407 in module simple_spi_master. Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401 in module simple_spi_master. Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390 in module simple_spi_master. Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373 in module simple_spi_master. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371 in module simple_spi_master. Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326 in module simpleuart. Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316 in module simpleuart. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314 in module simpleuart. Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268 in module spimemio_xfer. Marked 5 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244 in module spimemio_xfer. Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214 in module spimemio. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146 in module spimemio. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506 in module $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb. Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066 in module picorv32_pcpi_div. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045 in module $paramod\clock_div\SIZE=3. Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023 in module picorv32_pcpi_mul. Marked 16 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011 in module housekeeping_spi_slave. Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001 in module housekeeping_spi_slave. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994 in module housekeeping_spi. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263 in module caravel_clocking. Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258 in module caravel_clocking. Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252 in module even. Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244 in module odd. Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236 in module odd. Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230 in module odd. Removed a total of 2 dead cases. 12.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 24 redundant assignments. Promoted 263 assignments to connections. 12.2.4. Executing PROC_INIT pass (extract init attributes). 12.2.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \resetn in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'. Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'. Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'. Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'. Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'. Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'. Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'. Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'. Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'. Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'. Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'. Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. Found async reset \resetb in `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'. Found async reset \csb_reset in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. Found async reset \csb_reset in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'. Found async reset \RSTB in `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. Found async reset \resetb in `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'. Found async reset \resetb in `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'. Found async reset \resetb in `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'. Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'. Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'. Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'. 12.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. 1/86: $23\next_irq_pending[2:2] 2/86: $22\next_irq_pending[2:2] 3/86: $21\next_irq_pending[2:2] 4/86: $20\next_irq_pending[2:2] 5/86: $19\next_irq_pending[2:2] 6/86: $18\next_irq_pending[2:2] 7/86: $17\next_irq_pending[2:2] 8/86: $16\next_irq_pending[0:0] 9/86: $15\next_irq_pending[0:0] 10/86: $14\next_irq_pending[31:0] [0] 11/86: $14\next_irq_pending[31:0] [31:1] 12/86: $2\next_irq_pending[31:0] [31:2] 13/86: $3\set_mem_do_rdata[0:0] 14/86: $2\next_irq_pending[31:0] [1] 15/86: $3\set_mem_do_wdata[0:0] 16/86: $2\next_irq_pending[31:0] [0] 17/86: $4\set_mem_do_rinst[0:0] 18/86: $3\set_mem_do_rinst[0:0] 19/86: $4\set_mem_do_wdata[0:0] 20/86: $12\next_irq_pending[1:1] 21/86: $11\next_irq_pending[1:1] 22/86: $10\next_irq_pending[1:1] 23/86: $4\set_mem_do_rdata[0:0] 24/86: $8\next_irq_pending[1:1] 25/86: $7\next_irq_pending[1:1] 26/86: $6\next_irq_pending[1:1] 27/86: $5\next_irq_pending[1:1] 28/86: $4\next_irq_pending[1:1] 29/86: $13\next_irq_pending[1:1] 30/86: $5\set_mem_do_rinst[0:0] 31/86: $9\next_irq_pending[1:1] 32/86: $3\next_irq_pending[31:0] 33/86: $3\current_pc[31:0] 34/86: $2\current_pc[31:0] 35/86: $2\set_mem_do_wdata[0:0] 36/86: $2\set_mem_do_rdata[0:0] 37/86: $2\set_mem_do_rinst[0:0] 38/86: $1\next_irq_pending[31:0] 39/86: $1\current_pc[31:0] 40/86: $1\set_mem_do_wdata[0:0] 41/86: $1\set_mem_do_rdata[0:0] 42/86: $1\set_mem_do_rinst[0:0] 43/86: $0\trace_data[35:0] 44/86: $0\count_cycle[63:0] 45/86: $0\pcpi_timeout[0:0] 46/86: $0\trace_valid[0:0] 47/86: $0\do_waitirq[0:0] 48/86: $0\decoder_pseudo_trigger[0:0] 49/86: $0\decoder_trigger[0:0] 50/86: $0\alu_wait_2[0:0] 51/86: $0\alu_wait[0:0] 52/86: $0\reg_out[31:0] 53/86: $0\reg_sh[4:0] 54/86: $0\trap[0:0] 55/86: $0\pcpi_timeout_counter[3:0] 56/86: $0\latched_rd[4:0] 57/86: $0\latched_is_lb[0:0] 58/86: $0\latched_is_lh[0:0] 59/86: $0\latched_is_lu[0:0] 60/86: $0\latched_trace[0:0] 61/86: $0\latched_compr[0:0] 62/86: $0\latched_branch[0:0] 63/86: $0\latched_stalu[0:0] 64/86: $0\latched_store[0:0] 65/86: $0\irq_state[1:0] 66/86: $0\cpu_state[7:0] 67/86: $0\dbg_rs2val_valid[0:0] 68/86: $0\dbg_rs1val_valid[0:0] 69/86: $0\dbg_rs2val[31:0] 70/86: $0\dbg_rs1val[31:0] 71/86: $0\mem_do_wdata[0:0] 72/86: $0\mem_do_rdata[0:0] 73/86: $0\mem_do_rinst[0:0] 74/86: $0\mem_do_prefetch[0:0] 75/86: $0\mem_wordsize[1:0] 76/86: $0\timer[31:0] 77/86: $0\irq_mask[31:0] 78/86: $0\irq_active[0:0] 79/86: $0\irq_delay[0:0] 80/86: $0\reg_op2[31:0] 81/86: $0\reg_op1[31:0] 82/86: $0\reg_next_pc[31:0] 83/86: $0\reg_pc[31:0] 84/86: $0\count_instr[63:0] 85/86: $0\eoi[31:0] 86/86: $0\pcpi_valid[0:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'. Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'. 1/4: $2\cpuregs_write[0:0] 2/4: $2\cpuregs_wrdata[31:0] 3/4: $1\cpuregs_wrdata[31:0] 4/4: $1\cpuregs_write[0:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'. 1/2: $2\clear_prefetched_high_word[0:0] 2/2: $1\clear_prefetched_high_word[0:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'. Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'. 1/2: $1\alu_out[31:0] 2/2: $1\alu_out_0[0:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'. 1/8: $8\dbg_ascii_state[127:0] 2/8: $7\dbg_ascii_state[127:0] 3/8: $6\dbg_ascii_state[127:0] 4/8: $5\dbg_ascii_state[127:0] 5/8: $4\dbg_ascii_state[127:0] 6/8: $3\dbg_ascii_state[127:0] 7/8: $2\dbg_ascii_state[127:0] 8/8: $1\dbg_ascii_state[127:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. 1/76: $0\decoded_rs1[4:0] [4] 2/76: $0\decoded_imm_j[31:0] [10] 3/76: $0\decoded_imm_j[31:0] [7] 4/76: $0\decoded_imm_j[31:0] [6] 5/76: $0\decoded_imm_j[31:0] [3:1] 6/76: $0\decoded_imm_j[31:0] [5] 7/76: $0\decoded_imm_j[31:0] [9:8] 8/76: $0\decoded_imm_j[31:0] [31:20] 9/76: $0\decoded_imm_j[31:0] [4] 10/76: $0\decoded_imm_j[31:0] [11] 11/76: $0\decoded_imm_j[31:0] [0] 12/76: $0\decoded_rs1[4:0] [3:0] 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0] 14/76: $0\is_alu_reg_reg[0:0] 15/76: $0\is_alu_reg_imm[0:0] 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0] 17/76: $0\is_sll_srl_sra[0:0] 18/76: $0\is_sb_sh_sw[0:0] 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0] 20/76: $0\is_slli_srli_srai[0:0] 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0] 22/76: $0\compressed_instr[0:0] 23/76: $0\is_compare[0:0] 24/76: $0\decoded_imm[31:0] 25/76: $0\decoded_rs2[4:0] 26/76: $0\decoded_imm_j[31:0] [19:12] 27/76: $0\decoded_rd[4:0] 28/76: $0\instr_timer[0:0] 29/76: $0\instr_waitirq[0:0] 30/76: $0\instr_maskirq[0:0] 31/76: $0\instr_retirq[0:0] 32/76: $0\instr_setq[0:0] 33/76: $0\instr_getq[0:0] 34/76: $0\instr_ecall_ebreak[0:0] 35/76: $0\instr_rdinstrh[0:0] 36/76: $0\instr_rdinstr[0:0] 37/76: $0\instr_rdcycleh[0:0] 38/76: $0\instr_rdcycle[0:0] 39/76: $0\instr_and[0:0] 40/76: $0\instr_or[0:0] 41/76: $0\instr_sra[0:0] 42/76: $0\instr_srl[0:0] 43/76: $0\instr_xor[0:0] 44/76: $0\instr_sltu[0:0] 45/76: $0\instr_slt[0:0] 46/76: $0\instr_sll[0:0] 47/76: $0\instr_sub[0:0] 48/76: $0\instr_add[0:0] 49/76: $0\instr_srai[0:0] 50/76: $0\instr_srli[0:0] 51/76: $0\instr_slli[0:0] 52/76: $0\instr_andi[0:0] 53/76: $0\instr_ori[0:0] 54/76: $0\instr_xori[0:0] 55/76: $0\instr_sltiu[0:0] 56/76: $0\instr_slti[0:0] 57/76: $0\instr_addi[0:0] 58/76: $0\instr_sw[0:0] 59/76: $0\instr_sh[0:0] 60/76: $0\instr_sb[0:0] 61/76: $0\instr_lhu[0:0] 62/76: $0\instr_lbu[0:0] 63/76: $0\instr_lw[0:0] 64/76: $0\instr_lh[0:0] 65/76: $0\instr_lb[0:0] 66/76: $0\instr_bgeu[0:0] 67/76: $0\instr_bltu[0:0] 68/76: $0\instr_bge[0:0] 69/76: $0\instr_blt[0:0] 70/76: $0\instr_bne[0:0] 71/76: $0\instr_beq[0:0] 72/76: $0\instr_jalr[0:0] 73/76: $0\instr_jal[0:0] 74/76: $0\instr_auipc[0:0] 75/76: $0\instr_lui[0:0] 76/76: $0\pcpi_insn[31:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'. 1/13: $3\dbg_insn_opcode[31:0] 2/13: $2\dbg_insn_rd[4:0] 3/13: $2\dbg_insn_rs2[4:0] 4/13: $2\dbg_insn_rs1[4:0] 5/13: $2\dbg_insn_opcode[31:0] 6/13: $2\dbg_insn_imm[31:0] 7/13: $2\dbg_ascii_instr[63:0] 8/13: $1\dbg_insn_rd[4:0] 9/13: $1\dbg_insn_rs2[4:0] 10/13: $1\dbg_insn_rs1[4:0] 11/13: $1\dbg_insn_imm[31:0] 12/13: $1\dbg_ascii_instr[63:0] 13/13: $1\dbg_insn_opcode[31:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. 1/8: $0\cached_insn_rd[4:0] 2/8: $0\cached_insn_rs2[4:0] 3/8: $0\cached_insn_rs1[4:0] 4/8: $0\cached_insn_opcode[31:0] 5/8: $0\cached_insn_imm[31:0] 6/8: $0\cached_ascii_instr[63:0] 7/8: $0\dbg_valid_insn[0:0] 8/8: $0\dbg_insn_addr[31:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'. 1/47: $47\new_ascii_instr[63:0] 2/47: $46\new_ascii_instr[63:0] 3/47: $45\new_ascii_instr[63:0] 4/47: $44\new_ascii_instr[63:0] 5/47: $43\new_ascii_instr[63:0] 6/47: $42\new_ascii_instr[63:0] 7/47: $41\new_ascii_instr[63:0] 8/47: $40\new_ascii_instr[63:0] 9/47: $39\new_ascii_instr[63:0] 10/47: $38\new_ascii_instr[63:0] 11/47: $37\new_ascii_instr[63:0] 12/47: $36\new_ascii_instr[63:0] 13/47: $35\new_ascii_instr[63:0] 14/47: $34\new_ascii_instr[63:0] 15/47: $33\new_ascii_instr[63:0] 16/47: $32\new_ascii_instr[63:0] 17/47: $31\new_ascii_instr[63:0] 18/47: $30\new_ascii_instr[63:0] 19/47: $29\new_ascii_instr[63:0] 20/47: $28\new_ascii_instr[63:0] 21/47: $27\new_ascii_instr[63:0] 22/47: $26\new_ascii_instr[63:0] 23/47: $25\new_ascii_instr[63:0] 24/47: $24\new_ascii_instr[63:0] 25/47: $23\new_ascii_instr[63:0] 26/47: $22\new_ascii_instr[63:0] 27/47: $21\new_ascii_instr[63:0] 28/47: $20\new_ascii_instr[63:0] 29/47: $19\new_ascii_instr[63:0] 30/47: $18\new_ascii_instr[63:0] 31/47: $17\new_ascii_instr[63:0] 32/47: $16\new_ascii_instr[63:0] 33/47: $15\new_ascii_instr[63:0] 34/47: $14\new_ascii_instr[63:0] 35/47: $13\new_ascii_instr[63:0] 36/47: $12\new_ascii_instr[63:0] 37/47: $11\new_ascii_instr[63:0] 38/47: $10\new_ascii_instr[63:0] 39/47: $9\new_ascii_instr[63:0] 40/47: $8\new_ascii_instr[63:0] 41/47: $7\new_ascii_instr[63:0] 42/47: $6\new_ascii_instr[63:0] 43/47: $5\new_ascii_instr[63:0] 44/47: $4\new_ascii_instr[63:0] 45/47: $3\new_ascii_instr[63:0] 46/47: $2\new_ascii_instr[63:0] 47/47: $1\new_ascii_instr[63:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. 1/9: $0\mem_16bit_buffer[15:0] 2/9: $0\prefetched_high_word[0:0] 3/9: $0\mem_la_secondword[0:0] 4/9: $0\mem_state[1:0] 5/9: $0\mem_wstrb[3:0] 6/9: $0\mem_wdata[31:0] 7/9: $0\mem_addr[31:0] 8/9: $0\mem_instr[0:0] 9/9: $0\mem_valid[0:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'. Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'. 1/9: $0\mem_rdata_q[31:0] [31] 2/9: $0\mem_rdata_q[31:0] [7] 3/9: $0\mem_rdata_q[31:0] [24:20] 4/9: $0\mem_rdata_q[31:0] [19:15] 5/9: $0\mem_rdata_q[31:0] [6:0] 6/9: $0\mem_rdata_q[31:0] [14:12] 7/9: $0\mem_rdata_q[31:0] [11:8] 8/9: $0\mem_rdata_q[31:0] [30:25] 9/9: $0\next_insn_opcode[31:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'. 1/5: $3\mem_rdata_word[31:0] 2/5: $2\mem_rdata_word[31:0] 3/5: $1\mem_rdata_word[31:0] 4/5: $1\mem_la_wstrb[3:0] 5/5: $1\mem_la_wdata[31:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'. 1/2: $0\last_mem_valid[0:0] 2/2: $0\mem_la_firstword_reg[0:0] Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'. 1/2: $1\pcpi_int_rd[31:0] 2/2: $1\pcpi_int_wr[0:0] Creating decoders for process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. 1/34: $0\la_ena_3[31:0] [31:24] 2/34: $0\la_ena_3[31:0] [23:16] 3/34: $0\la_ena_3[31:0] [15:8] 4/34: $0\la_ena_3[31:0] [7:0] 5/34: $0\la_ena_2[31:0] [23:16] 6/34: $0\la_ena_2[31:0] [15:8] 7/34: $0\la_ena_2[31:0] [7:0] 8/34: $0\la_ena_1[31:0] [23:16] 9/34: $0\la_ena_1[31:0] [15:8] 10/34: $0\la_ena_1[31:0] [7:0] 11/34: $0\la_ena_0[31:0] [23:16] 12/34: $0\la_ena_0[31:0] [15:8] 13/34: $0\la_ena_0[31:0] [7:0] 14/34: $0\la_data_3[31:0] [23:16] 15/34: $0\la_data_3[31:0] [15:8] 16/34: $0\la_data_3[31:0] [7:0] 17/34: $0\la_data_2[31:0] [23:16] 18/34: $0\la_data_2[31:0] [15:8] 19/34: $0\la_data_2[31:0] [7:0] 20/34: $0\la_data_1[31:0] [23:16] 21/34: $0\la_data_1[31:0] [15:8] 22/34: $0\la_data_1[31:0] [7:0] 23/34: $0\la_data_0[31:0] [23:16] 24/34: $0\la_data_0[31:0] [15:8] 25/34: $0\la_data_0[31:0] [7:0] 26/34: $0\la_ena_1[31:0] [31:24] 27/34: $0\la_ena_0[31:0] [31:24] 28/34: $0\la_data_3[31:0] [31:24] 29/34: $0\la_data_2[31:0] [31:24] 30/34: $0\la_data_1[31:0] [31:24] 31/34: $0\la_data_0[31:0] [31:24] 32/34: $0\la_ena_2[31:0] [31:24] 33/34: $0\iomem_ready[0:0] 34/34: $0\iomem_rdata[31:0] Creating decoders for process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'. 1/7: $0\irq_8_inputsrc[0:0] 2/7: $0\irq_7_inputsrc[0:0] 3/7: $0\trap_output_dest[0:0] 4/7: $0\clk2_output_dest[0:0] 5/7: $0\clk1_output_dest[0:0] 6/7: $0\iomem_ready[0:0] 7/7: $0\iomem_rdata[31:0] Creating decoders for process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'. 1/6: $0\iomem_ready[0:0] 2/6: $0\iomem_rdata[31:0] 3/6: $0\gpio_pd[0:0] 4/6: $0\gpio_pu[0:0] 5/6: $0\gpio_oeb[0:0] 6/6: $0\gpio[0:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'. 1/1: $0\io_ctrl[37][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'. 1/1: $0\io_ctrl[36][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'. 1/1: $0\io_ctrl[35][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'. 1/1: $0\io_ctrl[34][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'. 1/1: $0\io_ctrl[33][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'. 1/1: $0\io_ctrl[32][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'. 1/1: $0\io_ctrl[31][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'. 1/1: $0\io_ctrl[30][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'. 1/1: $0\io_ctrl[29][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'. 1/1: $0\io_ctrl[28][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'. 1/1: $0\io_ctrl[27][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'. 1/1: $0\io_ctrl[26][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'. 1/1: $0\io_ctrl[25][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'. 1/1: $0\io_ctrl[24][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'. 1/1: $0\io_ctrl[23][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'. 1/1: $0\io_ctrl[22][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'. 1/1: $0\io_ctrl[21][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'. 1/1: $0\io_ctrl[20][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'. 1/1: $0\io_ctrl[19][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'. 1/1: $0\io_ctrl[18][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'. 1/1: $0\io_ctrl[17][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'. 1/1: $0\io_ctrl[16][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'. 1/1: $0\io_ctrl[15][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'. 1/1: $0\io_ctrl[14][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'. 1/1: $0\io_ctrl[13][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'. 1/1: $0\io_ctrl[12][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'. 1/1: $0\io_ctrl[11][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'. 1/1: $0\io_ctrl[10][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'. 1/1: $0\io_ctrl[9][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'. 1/1: $0\io_ctrl[8][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'. 1/1: $0\io_ctrl[7][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'. 1/1: $0\io_ctrl[6][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'. 1/1: $0\io_ctrl[5][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'. 1/1: $0\io_ctrl[4][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'. 1/1: $0\io_ctrl[3][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'. 1/1: $0\io_ctrl[2][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'. 1/1: $0\io_ctrl[1][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'. 1/1: $0\io_ctrl[0][12:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'. 1/1: $0\mgmt_gpio_outr[37:32] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'. 1/1: $0\mgmt_gpio_outr[31:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'. Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. 1/13: $4$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6397 2/13: $3$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6394 3/13: $3$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6393 4/13: $2$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6390 5/13: $2$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6389 6/13: $1$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6387 7/13: $1$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6386 8/13: $0\serial_data_staging[12:0] 9/13: $0\xfer_state[1:0] 10/13: $0\pad_count[5:0] 11/13: $0\xfer_count[3:0] 12/13: $0\serial_resetn[0:0] 13/13: $0\serial_clock[0:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'. 1/2: $0\xfer_ctrl[0:0] 2/2: $0\pwr_ctrl_out[3:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'. 1/2: $0\iomem_ready[0:0] 2/2: $0\iomem_rdata[31:0] Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'. 1/46: $43\iomem_rdata_pre[31:0] 2/46: $42\iomem_rdata_pre[31:0] 3/46: $41\iomem_rdata_pre[31:0] 4/46: $40\iomem_rdata_pre[31:0] 5/46: $39\iomem_rdata_pre[31:0] 6/46: $38\iomem_rdata_pre[31:0] 7/46: $37\iomem_rdata_pre[31:0] 8/46: $36\iomem_rdata_pre[31:0] 9/46: $35\iomem_rdata_pre[31:0] 10/46: $34\iomem_rdata_pre[31:0] 11/46: $33\iomem_rdata_pre[31:0] 12/46: $32\iomem_rdata_pre[31:0] 13/46: $31\iomem_rdata_pre[31:0] 14/46: $30\iomem_rdata_pre[31:0] 15/46: $29\iomem_rdata_pre[31:0] 16/46: $28\iomem_rdata_pre[31:0] 17/46: $27\iomem_rdata_pre[31:0] 18/46: $26\iomem_rdata_pre[31:0] 19/46: $25\iomem_rdata_pre[31:0] 20/46: $24\iomem_rdata_pre[31:0] 21/46: $23\iomem_rdata_pre[31:0] 22/46: $22\iomem_rdata_pre[31:0] 23/46: $21\iomem_rdata_pre[31:0] 24/46: $20\iomem_rdata_pre[31:0] 25/46: $19\iomem_rdata_pre[31:0] 26/46: $18\iomem_rdata_pre[31:0] 27/46: $17\iomem_rdata_pre[31:0] 28/46: $16\iomem_rdata_pre[31:0] 29/46: $15\iomem_rdata_pre[31:0] 30/46: $14\iomem_rdata_pre[31:0] 31/46: $13\iomem_rdata_pre[31:0] 32/46: $12\iomem_rdata_pre[31:0] 33/46: $11\iomem_rdata_pre[31:0] 34/46: $10\iomem_rdata_pre[31:0] 35/46: $9\iomem_rdata_pre[31:0] 36/46: $8\iomem_rdata_pre[31:0] 37/46: $7\iomem_rdata_pre[31:0] 38/46: $6\iomem_rdata_pre[31:0] 39/46: $5\iomem_rdata_pre[31:0] 40/46: $4\iomem_rdata_pre[31:0] 41/46: $3\j[31:0] 42/46: $3\iomem_rdata_pre[31:0] 43/46: $2\iomem_rdata_pre[31:0] 44/46: $2\j[31:0] 45/46: $1\iomem_rdata_pre[31:0] 46/46: $1\j[31:0] Creating decoders for process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. 1/9: $0\state[1:0] 2/9: $0\wbm_cyc_o[0:0] 3/9: $0\wbm_stb_o[0:0] 4/9: $0\wbm_sel_o[3:0] 5/9: $0\wbm_we_o[0:0] 6/9: $0\wbm_dat_o[31:0] 7/9: $0\wbm_adr_o[31:0] 8/9: $0\mem_rdata[31:0] 9/9: $0\mem_ready[0:0] Creating decoders for process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'. 1/2: $0\wb_ack_o[0:0] 2/2: $0\wb_ack_read[0:0] Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'. 1/8: $0\value_cur[31:0] [31:24] 2/8: $0\value_cur[31:0] [7:0] 3/8: $0\value_cur[31:0] [15:8] 4/8: $0\value_cur[31:0] [23:16] 5/8: $0\lastenable[0:0] 6/8: $0\stop_out[0:0] 7/8: $0\strobe[0:0] 8/8: $0\irq_out[0:0] Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'. 1/4: $0\value_reset[31:0] [15:8] 2/4: $0\value_reset[31:0] [7:0] 3/4: $0\value_reset[31:0] [23:16] 4/4: $0\value_reset[31:0] [31:24] Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'. 1/5: $0\chain[0:0] 2/5: $0\irq_ena[0:0] 3/5: $0\updown[0:0] 4/5: $0\oneshot[0:0] 5/5: $0\enable[0:0] Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'. 1/7: $0\value_cur[31:0] [31:24] 2/7: $0\value_cur[31:0] [23:16] 3/7: $0\value_cur[31:0] [7:0] 4/7: $0\value_cur[31:0] [15:8] 5/7: $0\lastenable[0:0] 6/7: $0\stop_out[0:0] 7/7: $0\irq_out[0:0] Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'. 1/4: $0\value_reset[31:0] [15:8] 2/4: $0\value_reset[31:0] [7:0] 3/4: $0\value_reset[31:0] [23:16] 4/4: $0\value_reset[31:0] [31:24] Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'. 1/5: $0\chain[0:0] 2/5: $0\irq_ena[0:0] 3/5: $0\updown[0:0] 4/5: $0\oneshot[0:0] 5/5: $0\enable[0:0] Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'. 1/3: $0\rreg[7:0] 2/3: $0\treg[7:0] 3/3: $0\isdo[0:0] Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'. 1/1: $0\isck[0:0] Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'. 1/2: $0\count[7:0] 2/2: $0\hsck[0:0] Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'. 1/4: $0\nbit[2:0] 2/4: $0\icsb[0:0] 3/4: $0\done[0:0] 4/4: $0\state[1:0] Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'. 1/4: $0\r_latched[0:0] 2/4: $0\w_latched[0:0] 3/4: $0\d_latched[7:0] 4/4: $0\err_out[0:0] Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. 1/9: $0\hkconn[0:0] 2/9: $0\mode[0:0] 3/9: $0\stream[0:0] 4/9: $0\irqena[0:0] 5/9: $0\mlb[0:0] 6/9: $0\invcsb[0:0] 7/9: $0\invsck[0:0] 8/9: $0\prescaler[7:0] 9/9: $0\enable[0:0] Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'. 1/4: $0\send_divcnt[31:0] 2/4: $0\send_dummy[0:0] 3/4: $0\send_bitcnt[3:0] 4/4: $0\send_pattern[9:0] Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'. 1/5: $0\recv_divcnt[31:0] 2/5: $0\recv_buf_valid[0:0] 3/5: $0\recv_buf_data[7:0] 4/5: $0\recv_pattern[7:0] 5/5: $0\recv_state[3:0] Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'. 1/5: $0\cfg_divider[31:0] [31:24] 2/5: $0\cfg_divider[31:0] [23:16] 3/5: $0\cfg_divider[31:0] [15:8] 4/5: $0\cfg_divider[31:0] [7:0] 5/5: $0\enabled[0:0] Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. 1/14: $0\last_fetch[0:0] 2/14: $0\fetch[0:0] 3/14: $0\xfer_tag[3:0] 4/14: $0\xfer_rd[0:0] 5/14: $0\xfer_qspi[0:0] 6/14: $0\xfer_cont[0:0] 7/14: $0\dummy_count[3:0] 8/14: $0\count[3:0] 9/14: $0\ibuffer[7:0] 10/14: $0\obuffer[7:0] 11/14: $0\xfer_ddr[0:0] 12/14: $0\xfer_dspi[0:0] 13/14: $0\flash_clk[0:0] 14/14: $0\flash_csb[0:0] Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. 1/33: $5\next_count[3:0] 2/33: $5\next_obuffer[7:0] 3/33: $5\next_ibuffer[7:0] 4/33: $4\next_count[3:0] 5/33: $4\next_obuffer[7:0] 6/33: $4\next_ibuffer[7:0] 7/33: $3\next_count[3:0] 8/33: $3\next_obuffer[7:0] 9/33: $3\next_ibuffer[7:0] 10/33: $2\next_fetch[0:0] 11/33: $2\next_count[3:0] 12/33: $2\next_ibuffer[7:0] 13/33: $2\next_obuffer[7:0] 14/33: $2\flash_io0_do[0:0] 15/33: $2\flash_io0_oe[0:0] 16/33: $2\flash_io3_oe[0:0] 17/33: $2\flash_io2_oe[0:0] 18/33: $2\flash_io1_oe[0:0] 19/33: $2\flash_io3_do[0:0] 20/33: $2\flash_io2_do[0:0] 21/33: $2\flash_io1_do[0:0] 22/33: $1\next_fetch[0:0] 23/33: $1\next_count[3:0] 24/33: $1\next_ibuffer[7:0] 25/33: $1\next_obuffer[7:0] 26/33: $1\flash_io3_oe[0:0] 27/33: $1\flash_io2_oe[0:0] 28/33: $1\flash_io1_oe[0:0] 29/33: $1\flash_io0_oe[0:0] 30/33: $1\flash_io3_do[0:0] 31/33: $1\flash_io2_do[0:0] 32/33: $1\flash_io1_do[0:0] 33/33: $1\flash_io0_do[0:0] Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'. Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. 1/17: $0\buffer[23:0] [23:16] 2/17: $0\buffer[23:0] [15:8] 3/17: $0\buffer[23:0] [7:0] 4/17: $0\xfer_resetn[0:0] 5/17: $0\rd_inc[0:0] 6/17: $0\rd_wait[0:0] 7/17: $0\rd_valid[0:0] 8/17: $0\rd_addr[23:0] 9/17: $0\din_valid[0:0] 10/17: $0\din_rd[0:0] 11/17: $0\din_ddr[0:0] 12/17: $0\din_qspi[0:0] 13/17: $0\din_cont[0:0] 14/17: $0\din_tag[3:0] 15/17: $0\din_data[7:0] 16/17: $0\rdata[31:0] 17/17: $0\state[3:0] Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'. Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. 1/10: $0\softreset[0:0] 2/10: $0\config_do[3:0] 3/10: $0\config_clk[0:0] 4/10: $0\config_csb[0:0] 5/10: $0\config_oe[3:0] 6/10: $0\config_dummy[3:0] 7/10: $0\config_cont[0:0] 8/10: $0\config_qspi[0:0] 9/10: $0\config_ddr[0:0] 10/10: $0\config_en[0:0] Creating decoders for process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'. Creating decoders for process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'. 1/2: $0\wb_ack_o[1:0] 2/2: $0\wb_ack_read[1:0] Creating decoders for process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'. Creating decoders for process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. 1/9: $0\pcpi_rd[31:0] 2/9: $0\pcpi_wr[0:0] 3/9: $0\pcpi_ready[0:0] 4/9: $0\outsign[0:0] 5/9: $0\running[0:0] 6/9: $0\quotient_msk[31:0] 7/9: $0\quotient[31:0] 8/9: $0\divisor[62:0] 9/9: $0\dividend[31:0] Creating decoders for process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'. 1/4: $0\instr_remu[0:0] 2/4: $0\instr_rem[0:0] 3/4: $0\instr_divu[0:0] 4/4: $0\instr_div[0:0] Creating decoders for process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'. 1/2: $0\syncN[2:0] 2/2: $0\syncNp[2:0] Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'. 1/3: $0\pcpi_ready[0:0] 2/3: $0\pcpi_wr[0:0] 3/3: $0\pcpi_rd[31:0] Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
1/7: $0\mul_finish[0:0]
2/7: $0\mul_waiting[0:0] 3/7: $0\mul_counter[6:0] 4/7: $0\rdx[63:0] 5/7: $0\rd[63:0] 6/7: $0\rs2[63:0] 7/7: $0\rs1[63:0] Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'. 1/4: $0\instr_mulhu[0:0] 2/4: $0\instr_mulhsu[0:0] 3/4: $0\instr_mulh[0:0] 4/4: $0\instr_mul[0:0] Creating decoders for process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. 1/14: $1\pass_thru_user[0:0] 2/14: $0\pre_pass_thru_user[0:0] 3/14: $0\pre_pass_thru_mgmt[0:0] 4/14: $0\predata[6:0] 5/14: $0\fixed[2:0] 6/14: $0\readmode[0:0] 7/14: $0\writemode[0:0] 8/14: $0\pass_thru_user_delay[0:0] 9/14: $0\pass_thru_mgmt_delay[0:0] 10/14: $0\rdstb[0:0] 11/14: $0\count[2:0] 12/14: $0\addr[7:0] 13/14: $0\state[2:0] 14/14: $0\pass_thru_mgmt[0:0] Creating decoders for process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'. 1/3: $0\sdoenb[0:0] 2/3: $0\ldata[7:0] 3/3: $0\wrstb[0:0] Creating decoders for process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. 1/12: $0\pll_trim[25:0] [25:24] 2/12: $0\pll_trim[25:0] [23:16] 3/12: $0\pll_trim[25:0] [15:8] 4/12: $0\pll_trim[25:0] [7:0] 5/12: $0\irq[0:0] 6/12: $0\pll_bypass[0:0] 7/12: $0\reset_reg[0:0] 8/12: $0\pll_ena[0:0] 9/12: $0\pll_div[4:0] 10/12: $0\pll90_sel[2:0] 11/12: $0\pll_sel[2:0] 12/12: $0\pll_dco_ena[0:0] Creating decoders for process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'. 1/1: $0\reset_delay[2:0] Creating decoders for process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'. 1/4: $0\ext_clk_syncd[0:0] 2/4: $0\use_pll_second[0:0] 3/4: $0\use_pll_first[0:0] 4/4: $0\ext_clk_syncd_pre[0:0] Creating decoders for process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'. 1/2: $0\out_counter[0:0] 2/2: $0\counter[2:0] Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'. Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'. 1/1: $0\rst_pulse[0:0] Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'. 1/3: $0\initial_begin[2:0] 2/3: $0\out_counter2[0:0] 3/3: $0\counter2[2:0] Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'. 1/2: $0\out_counter[0:0] 2/2: $0\counter[2:0] Creating decoders for process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'. 1/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 2/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_DATA[31:0]$2935 3/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_ADDR[4:0]$2934 Creating decoders for process `\mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'. 12.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_rs1' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_rs2' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_write' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_wrdata' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\clear_prefetched_high_word' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_0' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_ascii_state' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_opcode' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_ascii_instr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_imm' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rs1' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rs2' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rd' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\new_ascii_instr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_add_sub' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_shl' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_shr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_eq' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_ltu' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_lts' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_wdata' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_wstrb' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_rdata_word' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_wr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_rd' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_wait' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'. No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_ready' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_data_arr[0]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_data_arr[1]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[0]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[1]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[2]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[3]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[4]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[5]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[6]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[7]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[8]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[9]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[10]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[11]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[12]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[13]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[14]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[15]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[16]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[17]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[18]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[19]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[20]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[21]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[22]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[23]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[24]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[25]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[26]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[27]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[28]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[29]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[30]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[31]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[32]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[33]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[34]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[35]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[36]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[37]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6238' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6236' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6234' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6232' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6230' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6228' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6226' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6224' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6222' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6220' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6218' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6216' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6214' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6212' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6210' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6208' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6206' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6204' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6202' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6200' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6198' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6196' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6194' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6192' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6190' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6188' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6186' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6184' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6182' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6180' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6178' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6176' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6174' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6172' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6170' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6168' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6166' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6164' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:141$6160' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:140$6159' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'. No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_rdata_pre' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'. Latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\j' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367': $auto$proc_dlatch.cc:430:proc_dlatch$14650 No latch inferred for signal `\spimemio_xfer.\flash_io0_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\flash_io1_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\flash_io2_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\flash_io3_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\flash_io0_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\flash_io1_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\flash_io2_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\flash_io3_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\next_obuffer' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\next_ibuffer' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\next_count' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `\spimemio_xfer.\next_fetch' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. No latch inferred for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_rw_dat_o' from process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'. No latch inferred for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\i' from process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'. No latch inferred for signal `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.\i' from process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'. No latch inferred for signal `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.\wbm_dat_o' from process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'. No latch inferred for signal `\picorv32_pcpi_mul.\i' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. No latch inferred for signal `\picorv32_pcpi_mul.\next_rs1' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. No latch inferred for signal `\picorv32_pcpi_mul.\next_rs2' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. No latch inferred for signal `\picorv32_pcpi_mul.\this_rs2' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. No latch inferred for signal `\picorv32_pcpi_mul.\next_rd' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. No latch inferred for signal `\picorv32_pcpi_mul.\next_rdx' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. No latch inferred for signal `\picorv32_pcpi_mul.\next_rdt' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. No latch inferred for signal `\picorv32_pcpi_mul.\j' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. No latch inferred for signal `\mgmt_soc.\irq' from process `\mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'. 12.2.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trap' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14651' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14652' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\eoi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14653' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trace_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14654' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trace_data' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14655' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\count_cycle' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14656' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\count_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14657' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14658' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_next_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14659' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_op1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14660' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_op2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14661' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_out' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14662' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_sh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14663' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_delay' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14664' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_active' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14665' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_mask' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14666' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_pending' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14667' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\timer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14668' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wordsize' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14669' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_prefetch' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14670' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_rinst' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14671' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_rdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14672' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14673' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_trigger' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14674' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_trigger_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14675' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_pseudo_trigger' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14676' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14677' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs1val' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14678' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs2val' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14679' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs1val_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14680' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs2val_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14681' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpu_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14682' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14683' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_rinst' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14684' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_rdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14685' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14686' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_store' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14687' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_stalu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14688' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_branch' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14689' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_compr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14690' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_trace' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14691' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14692' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14693' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14694' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14695' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\current_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14696' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_timeout_counter' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14697' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_timeout' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14698' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\next_irq_pending' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14699' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\do_waitirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14700' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14701' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_0_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14702' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_wait' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14703' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_wait_2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. created $dff cell `$procdff$14704' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\clear_prefetched_high_word_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'. created $dff cell `$procdff$14705' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_insn' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14706' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lui' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14707' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_auipc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14708' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_jal' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14709' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_jalr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14710' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_beq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14711' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bne' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14712' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_blt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14713' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bge' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14714' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14715' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bgeu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14716' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14717' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14718' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14719' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lbu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14720' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lhu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14721' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14722' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14723' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14724' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_addi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14725' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slti' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14726' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sltiu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14727' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_xori' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14728' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_ori' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14729' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_andi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14730' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slli' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14731' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srli' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14732' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srai' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14733' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_add' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14734' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sub' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14735' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sll' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14736' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14737' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14738' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_xor' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14739' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srl' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14740' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sra' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14741' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_or' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14742' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_and' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14743' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdcycle' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14744' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdcycleh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14745' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdinstr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14746' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdinstrh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14747' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_ecall_ebreak' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14748' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_getq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14749' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_setq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14750' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_retirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14751' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_maskirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14752' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_waitirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14753' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_timer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14754' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14755' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14756' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14757' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14758' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_imm_j' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14759' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\compressed_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14760' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lui_auipc_jal' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14761' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14762' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_slli_srli_srai' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14763' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14764' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sb_sh_sw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14765' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sll_srl_sra' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14766' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14767' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_slti_blt_slt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14768' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14769' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14770' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lbu_lhu_lw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14771' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_alu_reg_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14772' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_alu_reg_reg' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14773' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_compare' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. created $dff cell `$procdff$14774' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_addr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14775' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_ascii_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14776' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14777' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14778' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14779' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14780' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14781' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_next' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14782' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_valid_insn' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14783' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_ascii_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14784' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14785' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14786' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14787' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14788' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. created $dff cell `$procdff$14789' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. created $dff cell `$procdff$14790' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. created $dff cell `$procdff$14791' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_addr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. created $dff cell `$procdff$14792' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. created $dff cell `$procdff$14793' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wstrb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. created $dff cell `$procdff$14794' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. created $dff cell `$procdff$14795' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_secondword' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. created $dff cell `$procdff$14796' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\prefetched_high_word' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. created $dff cell `$procdff$14797' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_16bit_buffer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. created $dff cell `$procdff$14798' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\next_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'. created $dff cell `$procdff$14799' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_rdata_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'. created $dff cell `$procdff$14800' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_firstword_reg' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'. created $dff cell `$procdff$14801' with positive edge clock. Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\last_mem_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'. created $dff cell `$procdff$14802' with positive edge clock. Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\iomem_rdata' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. created $dff cell `$procdff$14803' with positive edge clock. Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\iomem_ready' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. created $dff cell `$procdff$14804' with positive edge clock. Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_0' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. created $dff cell `$procdff$14805' with positive edge clock. Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_1' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. created $dff cell `$procdff$14806' with positive edge clock. Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_2' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. created $dff cell `$procdff$14807' with positive edge clock. Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_3' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. created $dff cell `$procdff$14808' with positive edge clock. Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_0' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. created $dff cell `$procdff$14809' with positive edge clock. Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_1' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. created $dff cell `$procdff$14810' with positive edge clock. Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_2' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. created $dff cell `$procdff$14811' with positive edge clock. Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_3' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. created $dff cell `$procdff$14812' with positive edge clock. Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\iomem_rdata' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'. created $dff cell `$procdff$14813' with positive edge clock. Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\iomem_ready' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'. created $dff cell `$procdff$14814' with positive edge clock. Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\clk1_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'. created $dff cell `$procdff$14815' with positive edge clock. Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\clk2_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'. created $dff cell `$procdff$14816' with positive edge clock. Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\trap_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'. created $dff cell `$procdff$14817' with positive edge clock. Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\irq_7_inputsrc' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'. created $dff cell `$procdff$14818' with positive edge clock. Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\irq_8_inputsrc' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'. created $dff cell `$procdff$14819' with positive edge clock. Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'. created $dff cell `$procdff$14820' with positive edge clock. Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_oeb' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'. created $dff cell `$procdff$14821' with positive edge clock. Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_pu' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'. created $dff cell `$procdff$14822' with positive edge clock. Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_pd' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'. created $dff cell `$procdff$14823' with positive edge clock. Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\iomem_rdata' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'. created $dff cell `$procdff$14824' with positive edge clock. Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\iomem_ready' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'. created $dff cell `$procdff$14825' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[37]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'. created $dff cell `$procdff$14826' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[36]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'. created $dff cell `$procdff$14827' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[35]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'. created $dff cell `$procdff$14828' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[34]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'. created $dff cell `$procdff$14829' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[33]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'. created $dff cell `$procdff$14830' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[32]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'. created $dff cell `$procdff$14831' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[31]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'. created $dff cell `$procdff$14832' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[30]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'. created $dff cell `$procdff$14833' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[29]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'. created $dff cell `$procdff$14834' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[28]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'. created $dff cell `$procdff$14835' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[27]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'. created $dff cell `$procdff$14836' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[26]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'. created $dff cell `$procdff$14837' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[25]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'. created $dff cell `$procdff$14838' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[24]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'. created $dff cell `$procdff$14839' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[23]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'. created $dff cell `$procdff$14840' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[22]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'. created $dff cell `$procdff$14841' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[21]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'. created $dff cell `$procdff$14842' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[20]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'. created $dff cell `$procdff$14843' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[19]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'. created $dff cell `$procdff$14844' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[18]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'. created $dff cell `$procdff$14845' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[17]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'. created $dff cell `$procdff$14846' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[16]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'. created $dff cell `$procdff$14847' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[15]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'. created $dff cell `$procdff$14848' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[14]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'. created $dff cell `$procdff$14849' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[13]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'. created $dff cell `$procdff$14850' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[12]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'. created $dff cell `$procdff$14851' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[11]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'. created $dff cell `$procdff$14852' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[10]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'. created $dff cell `$procdff$14853' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[9]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'. created $dff cell `$procdff$14854' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[8]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'. created $dff cell `$procdff$14855' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[7]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'. created $dff cell `$procdff$14856' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[6]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'. created $dff cell `$procdff$14857' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[5]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'. created $dff cell `$procdff$14858' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[4]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'. created $dff cell `$procdff$14859' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[3]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'. created $dff cell `$procdff$14860' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[2]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'. created $dff cell `$procdff$14861' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[1]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'. created $dff cell `$procdff$14862' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[0]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'. created $dff cell `$procdff$14863' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\mgmt_gpio_outr [37:32]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'. created $dff cell `$procdff$14864' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\mgmt_gpio_outr [31:0]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'. created $dff cell `$procdff$14865' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_clock' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. created $adff cell `$procdff$14866' with positive edge clock and negative level reset. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_resetn' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. created $adff cell `$procdff$14867' with positive edge clock and negative level reset. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_count' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. created $adff cell `$procdff$14868' with positive edge clock and negative level reset. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\pad_count' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. created $adff cell `$procdff$14869' with positive edge clock and negative level reset. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_state' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. created $adff cell `$procdff$14870' with positive edge clock and negative level reset. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_data_staging' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. created $dff cell `$procdff$14871' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. created $adff cell `$procdff$14872' with positive edge clock and negative level reset. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. created $adff cell `$procdff$14873' with positive edge clock and negative level reset. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\pwr_ctrl_out' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'. created $dff cell `$procdff$14874' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_ctrl' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'. created $dff cell `$procdff$14875' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_rdata' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'. created $dff cell `$procdff$14876' with positive edge clock. Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_ready' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'. created $dff cell `$procdff$14877' with positive edge clock. Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\mem_ready' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. created $dff cell `$procdff$14878' with positive edge clock. Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\mem_rdata' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. created $dff cell `$procdff$14879' with positive edge clock. Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_adr_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. created $dff cell `$procdff$14880' with positive edge clock. Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_dat_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. created $dff cell `$procdff$14881' with positive edge clock. Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_we_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. created $dff cell `$procdff$14882' with positive edge clock. Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_sel_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. created $dff cell `$procdff$14883' with positive edge clock. Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_stb_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. created $dff cell `$procdff$14884' with positive edge clock. Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_cyc_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. created $dff cell `$procdff$14885' with positive edge clock. Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\state' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. created $dff cell `$procdff$14886' with positive edge clock. Creating register for signal `\mem_wb.\wb_ack_o' using process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'. created $dff cell `$procdff$14887' with positive edge clock. Creating register for signal `\mem_wb.\wb_ack_read' using process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'. created $dff cell `$procdff$14888' with positive edge clock. Creating register for signal `\counter_timer_low.\irq_out' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'. created $adff cell `$procdff$14889' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_low.\strobe' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'. created $adff cell `$procdff$14890' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_low.\stop_out' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'. created $adff cell `$procdff$14891' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_low.\value_cur' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'. created $adff cell `$procdff$14892' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_low.\lastenable' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'. created $adff cell `$procdff$14893' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_low.\value_reset' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'. created $adff cell `$procdff$14894' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_low.\enable' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'. created $adff cell `$procdff$14895' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_low.\oneshot' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'. created $adff cell `$procdff$14896' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_low.\updown' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'. created $adff cell `$procdff$14897' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_low.\irq_ena' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'. created $adff cell `$procdff$14898' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_low.\chain' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'. created $adff cell `$procdff$14899' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_high.\irq_out' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'. created $adff cell `$procdff$14900' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_high.\stop_out' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'. created $adff cell `$procdff$14901' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_high.\value_cur' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'. created $adff cell `$procdff$14902' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_high.\lastenable' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'. created $adff cell `$procdff$14903' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_high.\value_reset' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'. created $adff cell `$procdff$14904' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_high.\enable' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'. created $adff cell `$procdff$14905' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_high.\oneshot' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'. created $adff cell `$procdff$14906' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_high.\updown' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'. created $adff cell `$procdff$14907' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_high.\irq_ena' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'. created $adff cell `$procdff$14908' with positive edge clock and negative level reset. Creating register for signal `\counter_timer_high.\chain' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'. created $adff cell `$procdff$14909' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\isdo' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'. created $adff cell `$procdff$14910' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\treg' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'. created $adff cell `$procdff$14911' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\rreg' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'. created $adff cell `$procdff$14912' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\isck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'. created $adff cell `$procdff$14913' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\count' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'. created $adff cell `$procdff$14914' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\hsck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'. created $adff cell `$procdff$14915' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\state' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'. created $adff cell `$procdff$14916' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\done' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'. created $adff cell `$procdff$14917' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\icsb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'. created $adff cell `$procdff$14918' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\nbit' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'. created $adff cell `$procdff$14919' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\err_out' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'. created $adff cell `$procdff$14920' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\d_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'. created $adff cell `$procdff$14921' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\w_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'. created $adff cell `$procdff$14922' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\r_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'. created $adff cell `$procdff$14923' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\enable' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. created $adff cell `$procdff$14924' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\prescaler' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. created $adff cell `$procdff$14925' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\invsck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. created $adff cell `$procdff$14926' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\invcsb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. created $adff cell `$procdff$14927' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\mlb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. created $adff cell `$procdff$14928' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\irqena' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. created $adff cell `$procdff$14929' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\stream' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. created $adff cell `$procdff$14930' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\mode' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. created $adff cell `$procdff$14931' with positive edge clock and negative level reset. Creating register for signal `\simple_spi_master.\hkconn' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. created $adff cell `$procdff$14932' with positive edge clock and negative level reset. Creating register for signal `\simpleuart.\send_pattern' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'. created $dff cell `$procdff$14933' with positive edge clock. Creating register for signal `\simpleuart.\send_bitcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'. created $dff cell `$procdff$14934' with positive edge clock. Creating register for signal `\simpleuart.\send_divcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'. created $dff cell `$procdff$14935' with positive edge clock. Creating register for signal `\simpleuart.\send_dummy' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'. created $dff cell `$procdff$14936' with positive edge clock. Creating register for signal `\simpleuart.\recv_state' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'. created $dff cell `$procdff$14937' with positive edge clock. Creating register for signal `\simpleuart.\recv_divcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'. created $dff cell `$procdff$14938' with positive edge clock. Creating register for signal `\simpleuart.\recv_pattern' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'. created $dff cell `$procdff$14939' with positive edge clock. Creating register for signal `\simpleuart.\recv_buf_data' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'. created $dff cell `$procdff$14940' with positive edge clock. Creating register for signal `\simpleuart.\recv_buf_valid' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'. created $dff cell `$procdff$14941' with positive edge clock. Creating register for signal `\simpleuart.\enabled' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'. created $dff cell `$procdff$14942' with positive edge clock. Creating register for signal `\simpleuart.\cfg_divider' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'. created $dff cell `$procdff$14943' with positive edge clock. Creating register for signal `\spimemio_xfer.\flash_csb' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14944' with positive edge clock. Creating register for signal `\spimemio_xfer.\flash_clk' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14945' with positive edge clock. Creating register for signal `\spimemio_xfer.\xfer_dspi' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14946' with positive edge clock. Creating register for signal `\spimemio_xfer.\xfer_ddr' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14947' with positive edge clock. Creating register for signal `\spimemio_xfer.\obuffer' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14948' with positive edge clock. Creating register for signal `\spimemio_xfer.\ibuffer' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14949' with positive edge clock. Creating register for signal `\spimemio_xfer.\count' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14950' with positive edge clock. Creating register for signal `\spimemio_xfer.\dummy_count' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14951' with positive edge clock. Creating register for signal `\spimemio_xfer.\xfer_cont' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14952' with positive edge clock. Creating register for signal `\spimemio_xfer.\xfer_qspi' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14953' with positive edge clock. Creating register for signal `\spimemio_xfer.\xfer_rd' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14954' with positive edge clock. Creating register for signal `\spimemio_xfer.\xfer_tag' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14955' with positive edge clock. Creating register for signal `\spimemio_xfer.\fetch' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14956' with positive edge clock. Creating register for signal `\spimemio_xfer.\last_fetch' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. created $dff cell `$procdff$14957' with positive edge clock. Creating register for signal `\spimemio_xfer.\xfer_ddr_q' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'. created $dff cell `$procdff$14958' with positive edge clock. Creating register for signal `\spimemio_xfer.\xfer_tag_q' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'. created $dff cell `$procdff$14959' with positive edge clock. Creating register for signal `\spimemio.\state' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14960' with positive edge clock. Creating register for signal `\spimemio.\rdata' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14961' with positive edge clock. Creating register for signal `\spimemio.\xfer_resetn' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14962' with positive edge clock. Creating register for signal `\spimemio.\din_valid' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14963' with positive edge clock. Creating register for signal `\spimemio.\din_data' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14964' with positive edge clock. Creating register for signal `\spimemio.\din_tag' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14965' with positive edge clock. Creating register for signal `\spimemio.\din_cont' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14966' with positive edge clock. Creating register for signal `\spimemio.\din_qspi' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14967' with positive edge clock. Creating register for signal `\spimemio.\din_ddr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14968' with positive edge clock. Creating register for signal `\spimemio.\din_rd' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14969' with positive edge clock. Creating register for signal `\spimemio.\buffer' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14970' with positive edge clock. Creating register for signal `\spimemio.\rd_addr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14971' with positive edge clock. Creating register for signal `\spimemio.\rd_valid' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14972' with positive edge clock. Creating register for signal `\spimemio.\rd_wait' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14973' with positive edge clock. Creating register for signal `\spimemio.\rd_inc' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. created $dff cell `$procdff$14974' with positive edge clock. Creating register for signal `\spimemio.\xfer_io0_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'. created $dff cell `$procdff$14975' with negative edge clock. Creating register for signal `\spimemio.\xfer_io1_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'. created $dff cell `$procdff$14976' with negative edge clock. Creating register for signal `\spimemio.\xfer_io2_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'. created $dff cell `$procdff$14977' with negative edge clock. Creating register for signal `\spimemio.\xfer_io3_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'. created $dff cell `$procdff$14978' with negative edge clock. Creating register for signal `\spimemio.\softreset' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. created $dff cell `$procdff$14979' with positive edge clock. Creating register for signal `\spimemio.\config_en' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. created $dff cell `$procdff$14980' with positive edge clock. Creating register for signal `\spimemio.\config_ddr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. created $dff cell `$procdff$14981' with positive edge clock. Creating register for signal `\spimemio.\config_qspi' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. created $dff cell `$procdff$14982' with positive edge clock. Creating register for signal `\spimemio.\config_cont' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. created $dff cell `$procdff$14983' with positive edge clock. Creating register for signal `\spimemio.\config_dummy' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. created $dff cell `$procdff$14984' with positive edge clock. Creating register for signal `\spimemio.\config_oe' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. created $dff cell `$procdff$14985' with positive edge clock. Creating register for signal `\spimemio.\config_csb' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. created $dff cell `$procdff$14986' with positive edge clock. Creating register for signal `\spimemio.\config_clk' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. created $dff cell `$procdff$14987' with positive edge clock. Creating register for signal `\spimemio.\config_do' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. created $dff cell `$procdff$14988' with positive edge clock. Creating register for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_ack_o' using process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'. created $dff cell `$procdff$14989' with positive edge clock. Creating register for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_ack_read' using process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'. created $dff cell `$procdff$14990' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\pcpi_wr' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. created $dff cell `$procdff$14991' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\pcpi_rd' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. created $dff cell `$procdff$14992' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\pcpi_ready' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. created $dff cell `$procdff$14993' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\dividend' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. created $dff cell `$procdff$14994' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\divisor' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. created $dff cell `$procdff$14995' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\quotient' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. created $dff cell `$procdff$14996' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\quotient_msk' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. created $dff cell `$procdff$14997' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\running' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. created $dff cell `$procdff$14998' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\outsign' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. created $dff cell `$procdff$14999' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\pcpi_wait' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'. created $dff cell `$procdff$15000' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\pcpi_wait_q' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'. created $dff cell `$procdff$15001' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\instr_div' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'. created $dff cell `$procdff$15002' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\instr_divu' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'. created $dff cell `$procdff$15003' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\instr_rem' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'. created $dff cell `$procdff$15004' with positive edge clock. Creating register for signal `\picorv32_pcpi_div.\instr_remu' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'. created $dff cell `$procdff$15005' with positive edge clock. Creating register for signal `$paramod\clock_div\SIZE=3.\syncN' using process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'. created $adff cell `$procdff$15006' with positive edge clock and negative level reset. Creating register for signal `$paramod\clock_div\SIZE=3.\syncNp' using process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'. created $adff cell `$procdff$15007' with positive edge clock and negative level reset. Creating register for signal `\picorv32_pcpi_mul.\pcpi_wr' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'. created $dff cell `$procdff$15008' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\pcpi_rd' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'. created $dff cell `$procdff$15009' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\pcpi_ready' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'. created $dff cell `$procdff$15010' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\rs1' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'. created $dff cell `$procdff$15011' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\rs2' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'. created $dff cell `$procdff$15012' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\rd' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'. created $dff cell `$procdff$15013' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\rdx' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'. created $dff cell `$procdff$15014' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\mul_counter' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'. created $dff cell `$procdff$15015' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\mul_waiting' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'. created $dff cell `$procdff$15016' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\mul_finish' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
created $dff cell `$procdff$15017' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\pcpi_wait' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'. created $dff cell `$procdff$15018' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\instr_mul' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'. created $dff cell `$procdff$15019' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\instr_mulh' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'. created $dff cell `$procdff$15020' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\instr_mulhsu' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'. created $dff cell `$procdff$15021' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\instr_mulhu' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'. created $dff cell `$procdff$15022' with positive edge clock. Creating register for signal `\picorv32_pcpi_mul.\pcpi_wait_q' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'. created $dff cell `$procdff$15023' with positive edge clock. Creating register for signal `\housekeeping_spi_slave.\pass_thru_mgmt' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15024' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\state' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15025' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\addr' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15026' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\count' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15027' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\rdstb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15028' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\pass_thru_mgmt_delay' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15029' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\pass_thru_user' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15030' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\pass_thru_user_delay' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15031' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\writemode' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15032' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\readmode' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15033' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\fixed' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15034' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\predata' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15035' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\pre_pass_thru_mgmt' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15036' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\pre_pass_thru_user' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. created $adff cell `$procdff$15037' with positive edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\sdoenb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'. created $adff cell `$procdff$15038' with negative edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\wrstb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'. created $adff cell `$procdff$15039' with negative edge clock and positive level reset. Creating register for signal `\housekeeping_spi_slave.\ldata' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'. created $adff cell `$procdff$15040' with negative edge clock and positive level reset. Creating register for signal `\housekeeping_spi.\pll_dco_ena' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. created $adff cell `$procdff$15041' with positive edge clock and negative level reset. Creating register for signal `\housekeeping_spi.\pll_sel' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. created $adff cell `$procdff$15042' with positive edge clock and negative level reset. Creating register for signal `\housekeeping_spi.\pll90_sel' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. created $adff cell `$procdff$15043' with positive edge clock and negative level reset. Creating register for signal `\housekeeping_spi.\pll_div' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. created $adff cell `$procdff$15044' with positive edge clock and negative level reset. Creating register for signal `\housekeeping_spi.\pll_ena' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. created $adff cell `$procdff$15045' with positive edge clock and negative level reset. Creating register for signal `\housekeeping_spi.\pll_trim' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. created $adff cell `$procdff$15046' with positive edge clock and negative level reset. Creating register for signal `\housekeeping_spi.\pll_bypass' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. created $adff cell `$procdff$15047' with positive edge clock and negative level reset. Creating register for signal `\housekeeping_spi.\irq' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. created $adff cell `$procdff$15048' with positive edge clock and negative level reset. Creating register for signal `\housekeeping_spi.\reset_reg' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. created $adff cell `$procdff$15049' with positive edge clock and negative level reset. Creating register for signal `\caravel_clocking.\reset_delay' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'. created $adff cell `$procdff$15050' with positive edge clock and negative level reset. Creating register for signal `\caravel_clocking.\use_pll_first' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'. created $adff cell `$procdff$15051' with positive edge clock and negative level reset. Creating register for signal `\caravel_clocking.\use_pll_second' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'. created $adff cell `$procdff$15052' with positive edge clock and negative level reset. Creating register for signal `\caravel_clocking.\ext_clk_syncd_pre' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'. created $dff cell `$procdff$15053' with positive edge clock. Creating register for signal `\caravel_clocking.\ext_clk_syncd' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'. created $adff cell `$procdff$15054' with positive edge clock and negative level reset. Creating register for signal `\even.\counter' using process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'. created $adff cell `$procdff$15055' with positive edge clock and negative level reset. Creating register for signal `\even.\out_counter' using process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'. created $adff cell `$procdff$15056' with positive edge clock and negative level reset. Creating register for signal `\odd.\old_N' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'. created $dff cell `$procdff$15057' with positive edge clock. Creating register for signal `\odd.\rst_pulse' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'. created $adff cell `$procdff$15058' with positive edge clock and negative level reset. Creating register for signal `\odd.\counter2' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Warning: Async reset value `\N' is not constant!
created $dffsr cell `$procdff$15059' with negative edge clock and negative level non-const reset. Creating register for signal `\odd.\out_counter2' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'. created $adff cell `$procdff$15066' with negative edge clock and negative level reset. Creating register for signal `\odd.\initial_begin' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Warning: Async reset value `$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235_Y [3:1]' is not constant!
created $dffsr cell `$procdff$15067' with negative edge clock and negative level non-const reset. Creating register for signal `\odd.\counter' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
Warning: Async reset value `\N' is not constant!
created $dffsr cell `$procdff$15074' with positive edge clock and negative level non-const reset. Creating register for signal `\odd.\out_counter' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'. created $adff cell `$procdff$15081' with positive edge clock and negative level reset. Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_ADDR' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'. created $dff cell `$procdff$15082' with positive edge clock. Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_DATA' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'. created $dff cell `$procdff$15083' with positive edge clock. Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'. created $dff cell `$procdff$15084' with positive edge clock. 12.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 61 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'. Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'. Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'. Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'. Found and cleaned up 8 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'. Found and cleaned up 22 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'. Found and cleaned up 3 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'. Found and cleaned up 5 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'. Found and cleaned up 47 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'. Found and cleaned up 16 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'. Found and cleaned up 19 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'. Found and cleaned up 3 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'. Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'. Found and cleaned up 1 empty switch in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'. Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'. Found and cleaned up 42 empty switches in `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. Removing empty process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'. Found and cleaned up 9 empty switches in `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'. Removing empty process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'. Found and cleaned up 10 empty switches in `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'. Removing empty process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'. Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'. Found and cleaned up 13 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'. Found and cleaned up 6 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'. Found and cleaned up 3 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'. Found and cleaned up 43 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'. Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'. Found and cleaned up 4 empty switches in `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. Removing empty process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'. Found and cleaned up 1 empty switch in `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'. Removing empty process `mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'. Found and cleaned up 25 empty switches in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'. Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'. Found and cleaned up 4 empty switches in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'. Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'. Found and cleaned up 1 empty switch in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'. Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'. Found and cleaned up 26 empty switches in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'. Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'. Found and cleaned up 4 empty switches in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'. Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'. Found and cleaned up 1 empty switch in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'. Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'. Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'. Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'. Found and cleaned up 1 empty switch in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'. Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'. Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'. Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'. Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'. Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'. Found and cleaned up 9 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'. Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'. Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'. Found and cleaned up 5 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'. Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'. Found and cleaned up 7 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'. Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'. Found and cleaned up 6 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'. Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'. Found and cleaned up 4 empty switches in `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'. Found and cleaned up 5 empty switches in `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'. Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'. Found and cleaned up 25 empty switches in `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'. Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'. Found and cleaned up 5 empty switches in `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'. Removing empty process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'. Found and cleaned up 1 empty switch in `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'. Removing empty process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'. Removing empty process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'. Found and cleaned up 5 empty switches in `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. Removing empty process `picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'. Found and cleaned up 2 empty switches in `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'. Removing empty process `picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'. Removing empty process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'. Found and cleaned up 1 empty switch in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'. Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'. Found and cleaned up 5 empty switches in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'. Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'. Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'. Found and cleaned up 2 empty switches in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'. Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'. Found and cleaned up 18 empty switches in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. Removing empty process `housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'. Found and cleaned up 6 empty switches in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'. Removing empty process `housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'. Found and cleaned up 2 empty switches in `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. Removing empty process `housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'. Removing empty process `caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'. Removing empty process `caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'. Found and cleaned up 2 empty switches in `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'. Removing empty process `even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'. Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'. Found and cleaned up 2 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'. Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'. Found and cleaned up 4 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'. Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'. Found and cleaned up 3 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'. Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'. Found and cleaned up 1 empty switch in `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'. Removing empty process `mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'. Removing empty process `mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'. Cleaned up 682 empty switches. 12.3. Executing FLATTEN pass (flatten design). Deleting now unused module convert_gpio_sigs. Deleting now unused module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. Deleting now unused module $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la. Deleting now unused module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl. Deleting now unused module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio. Deleting now unused module $paramod\soc_mem\WORDS=256\ADR_WIDTH=8. Deleting now unused module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. Deleting now unused module $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb. Deleting now unused module $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100. Deleting now unused module $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100. Deleting now unused module mem_wb. Deleting now unused module $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb. Deleting now unused module counter_timer_low. Deleting now unused module $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb. Deleting now unused module counter_timer_high. Deleting now unused module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb. Deleting now unused module simple_spi_master. Deleting now unused module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb. Deleting now unused module simpleuart. Deleting now unused module $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb. Deleting now unused module spimemio_xfer. Deleting now unused module spimemio. Deleting now unused module spimemio_wb. Deleting now unused module $paramod\mprj_ctrl_wb\BASE_ADR=637534208. Deleting now unused module $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb. Deleting now unused module $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon. Deleting now unused module picorv32_pcpi_div. Deleting now unused module $paramod\clock_div\SIZE=3. Deleting now unused module picorv32_pcpi_mul. Deleting now unused module housekeeping_spi_slave. Deleting now unused module housekeeping_spi. Deleting now unused module caravel_clocking. Deleting now unused module even. Deleting now unused module odd. Deleting now unused module mgmt_soc_regs. Deleting now unused module mgmt_soc. 12.4. Executing OPT_EXPR pass (perform const folding). Optimizing module mgmt_core. 12.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \mgmt_core.. Removed 395 unused cells and 4411 unused wires. 12.6. Executing CHECK pass (checking for obvious problems). checking module mgmt_core..
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.sck:
port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6440 ($mux) port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:193$1362 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.csb:
port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6435 ($mux) port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:192$1358 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.sdo:
port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6430 ($mux) port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:198$1364 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_sdi:
port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:135$2951 ($mux) port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6470 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_sck:
port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:134$2949 ($mux) port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6465 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_csb:
port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:133$2947 ($mux) port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6460 ($mux)
Warning: Wire mgmt_core.\pwr_ctrl_out [3] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [2] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [1] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [0] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [31] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [30] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [29] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [28] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [27] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [26] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [25] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [24] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [23] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [22] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [21] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [20] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [19] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [18] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [17] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [16] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [15] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [14] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [13] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [12] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [11] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [10] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [9] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [8] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [7] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [6] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [5] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [4] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [3] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [2] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [1] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [0] is used but has no driver.
Warning: Wire mgmt_core.\soc.intercon.wbs_dat_i [387] is used but has no driver.
Warning: Wire mgmt_core.\soc.intercon.wbs_dat_i [386] is used but has no driver.
Warning: Wire mgmt_core.\soc.cpu.picorv32_core.irq [4] is used but has no driver.
found and reported 45 problems. 12.7. Executing OPT pass (performing simple optimizations). 12.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module mgmt_core. 12.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\mgmt_core'. Removed a total of 805 cells. 12.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \mgmt_core.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $flatten\housekeeping.\U1.$procmux$14195: \housekeeping.U1.pre_pass_thru_user -> 1'0 Replacing known input bits on port A of cell $flatten\housekeeping.\U1.$procmux$14221: \housekeeping.U1.pre_pass_thru_mgmt -> 1'0 Replacing known input bits on port A of cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14113: \soc.cpu.picorv32_core.pcpi_mul.mul_waiting -> 1'0 Analyzing evaluation results. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10354. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10361. dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10387. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7556. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7566. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7568. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7574. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7581. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7583. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7589. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7598. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7618. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7624. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7627. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7640. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7647. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7650. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7663. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7675. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7678. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7687. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7690. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7698. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7700. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7703. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7717. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7719. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7721. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7724. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7737. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7739. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7742. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7754. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7757. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7764. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7766. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7769. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7792. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7794. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7796. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7799. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7821. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7823. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7826. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7845. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7847. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7850. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7869. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7871. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7874. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7895. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7898. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7912. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7915. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7917. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7919. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7922. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7932. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7937. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7940. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7963. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7966. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7968. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7970. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7973. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7985. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7988. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8031. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8044. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8057. dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8287. dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8287. dead port 2/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8330. dead port 7/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8330. dead port 8/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8330. dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8537. dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8537. dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8605. dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8620. dead port 2/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8624. dead port 7/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8624. dead port 8/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8624. dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808. dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8820. dead port 2/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8824. dead port 7/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8824. dead port 8/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8824. dead port 2/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9008. dead port 7/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9008. dead port 8/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9008. dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9058. dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9058. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9199. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9208. dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11658. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11661. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11833. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11836. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11839. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11845. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11848. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11851. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11857. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11860. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11863. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11869. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11872. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11875. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11881. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11884. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11887. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11893. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11896. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11899. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11905. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11908. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11911. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11917. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11920. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11923. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11929. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11932. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11935. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11941. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11944. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11947. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11953. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11956. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11959. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11965. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11968. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11971. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11977. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11980. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11983. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11989. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11992. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11995. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12001. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12004. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12007. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12013. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12016. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12019. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12025. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12028. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12031. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12037. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12040. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12043. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12049. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12052. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12055. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12061. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12064. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12067. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12073. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12076. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12079. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12085. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12088. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12091. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12097. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12100. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12103. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12109. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12112. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12115. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12121. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12124. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12127. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12133. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12136. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12139. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12145. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12148. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12151. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12157. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12160. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12163. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12169. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12172. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12175. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12181. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12184. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12187. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12193. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12196. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12199. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12205. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12208. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12211. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12217. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12220. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12223. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12229. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12232. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12235. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12241. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12244. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12247. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12253. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12256. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12259. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12265. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12268. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12271. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12277. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12280. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12283. dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12289. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12292. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12295. dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12301. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12304. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12307. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12322. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12325. dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12331. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13432. dead port 1/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13434. dead port 2/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13434. dead port 3/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13434. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13438. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13445. dead port 1/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13447. dead port 2/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13447. dead port 3/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13447. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13451. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13471. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13473. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13482. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13484. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13506. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13508. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13518. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13520. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13530. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13540. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13550. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13560. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13570. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13580. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13588. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13596. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13606. dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13632. Removed 247 multiplexer ports. 12.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \mgmt_core. New input vector for $reduce_or cell $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:329$6890: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_ready \soc.cpu.picorv32_core.pcpi_div.pcpi_ready } New input vector for $reduce_or cell $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:328$6886: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_wait \soc.cpu.picorv32_core.pcpi_div.pcpi_wait } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10133: { $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15086 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10148: { $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15088 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10166: $auto$opt_reduce.cc:134:opt_mux$15090 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10179: $auto$opt_reduce.cc:134:opt_mux$15092 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10204: { $auto$opt_reduce.cc:134:opt_mux$15094 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10239: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15096 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10254: { $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15098 $flatten\soc.\cpu.\picorv32_core.$procmux$10149_CMP } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10281: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $auto$opt_reduce.cc:134:opt_mux$15100 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10294: $auto$opt_reduce.cc:134:opt_mux$15102 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10320: { $auto$opt_reduce.cc:134:opt_mux$15106 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15104 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10339: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $auto$opt_reduce.cc:134:opt_mux$15108 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7608: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $auto$opt_reduce.cc:134:opt_mux$15110 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7630: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $auto$opt_reduce.cc:134:opt_mux$15112 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7653: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $auto$opt_reduce.cc:134:opt_mux$15114 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8021: { $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP $auto$opt_reduce.cc:134:opt_mux$15116 } New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$14195: { } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8034: { $auto$opt_reduce.cc:134:opt_mux$15118 $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP } New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$14221: { } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8047: { $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $auto$opt_reduce.cc:134:opt_mux$15120 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8330: $auto$opt_reduce.cc:134:opt_mux$15122 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8374: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8514: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $auto$opt_reduce.cc:134:opt_mux$15124 } New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$14360: { } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8537: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$15126 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8624: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$15130 $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y $auto$opt_reduce.cc:134:opt_mux$15128 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8798: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8824: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$15134 $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y $auto$opt_reduce.cc:134:opt_mux$15132 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9008: { \soc.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$15136 $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9058: { \soc.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$15138 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9194: $auto$opt_reduce.cc:134:opt_mux$15140 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9284: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15142 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9302: $auto$opt_reduce.cc:134:opt_mux$15144 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9370: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15146 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9388: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $auto$opt_reduce.cc:134:opt_mux$15148 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9436: { $auto$opt_reduce.cc:134:opt_mux$15150 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9457: $auto$opt_reduce.cc:134:opt_mux$15152 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9578: { $flatten\soc.\cpu.\picorv32_core.$procmux$9586_CMP $auto$opt_reduce.cc:134:opt_mux$15154 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9590: $auto$opt_reduce.cc:134:opt_mux$15156 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9746: $auto$opt_reduce.cc:134:opt_mux$15158 Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\cpuregs.$procmux$14616: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 New ports: A=1'0, B=1'1, Y=$flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] New connections: $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [31:1] = { $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] } New ctrl vector for $pmux cell $flatten\soc.\simpleuart.\simpleuart.$procmux$13279: $auto$opt_reduce.cc:134:opt_mux$15160 New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13839: { $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP $auto$opt_reduce.cc:134:opt_mux$15162 $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP } New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13421: $auto$opt_reduce.cc:134:opt_mux$15164 New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13566: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15166 } New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13576: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15168 } New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13585: $auto$opt_reduce.cc:134:opt_mux$15170 New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13593: $auto$opt_reduce.cc:134:opt_mux$15172 New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13602: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15174 } New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13628: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15176 } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15121: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15125: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15127: { \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15129: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15131: { \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15133: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15135: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15137: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer } Optimizing cells in module \mgmt_core. Performed a total of 59 changes. 12.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\mgmt_core'. Removed a total of 104 cells. 12.7.6. Executing OPT_DFF pass (perform DFF optimizations). 12.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \mgmt_core.. Removed 0 unused cells and 1142 unused wires. 12.7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module mgmt_core. 12.7.9. Rerunning OPT passes. (Maybe there is more to do..) 12.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \mgmt_core.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $flatten\soc.\cpu.\picorv32_core.$procmux$10392: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_wr \soc.cpu.picorv32_core.pcpi_div.pcpi_wr } -> 2'11 Analyzing evaluation results. Removed 0 multiplexer ports. 12.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \mgmt_core. New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10177: { $flatten\soc.\cpu.\picorv32_core.$procmux$10165_CMP $auto$opt_reduce.cc:134:opt_mux$15178 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10392: $auto$opt_reduce.cc:134:opt_mux$15180 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7630: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $auto$opt_reduce.cc:134:opt_mux$15182 $auto$opt_reduce.cc:134:opt_mux$15112 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8138: $auto$opt_reduce.cc:134:opt_mux$15184 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8155: { $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $auto$opt_reduce.cc:134:opt_mux$15186 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8583: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP $auto$opt_reduce.cc:134:opt_mux$15188 } New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9167: $auto$opt_reduce.cc:134:opt_mux$15190 New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9472: $auto$opt_reduce.cc:134:opt_mux$15192 New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13696: $auto$opt_reduce.cc:134:opt_mux$15194 New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13746: { $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP $auto$opt_reduce.cc:134:opt_mux$15196 $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP } Optimizing cells in module \mgmt_core. Performed a total of 10 changes. 12.7.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\mgmt_core'. Removed a total of 5 cells. 12.7.13. Executing OPT_DFF pass (perform DFF optimizations). 12.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \mgmt_core.. Removed 0 unused cells and 5 unused wires. 12.7.15. Executing OPT_EXPR pass (perform const folding). Optimizing module mgmt_core. 12.7.16. Rerunning OPT passes. (Maybe there is more to do..) 12.7.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \mgmt_core.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10392. Removed 1 multiplexer ports. 12.7.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \mgmt_core. Performed a total of 0 changes. 12.7.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\mgmt_core'. Removed a total of 0 cells. 12.7.20. Executing OPT_DFF pass (perform DFF optimizations). 12.7.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \mgmt_core.. 12.7.22. Executing OPT_EXPR pass (perform const folding). Optimizing module mgmt_core. 12.7.23. Rerunning OPT passes. (Maybe there is more to do..) 12.7.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \mgmt_core.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 12.7.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \mgmt_core. Performed a total of 0 changes. 12.7.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\mgmt_core'. Removed a total of 0 cells. 12.7.27. Executing OPT_DFF pass (perform DFF optimizations). 12.7.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \mgmt_core.. 12.7.29. Executing OPT_EXPR pass (perform const folding). Optimizing module mgmt_core.
12.7.30. Finished OPT passes. (There is nothing left to do.)
12.8. Executing FSM pass (extract and optimize FSM). 12.8.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register mgmt_core.housekeeping.U1.state. Found FSM state register mgmt_core.soc.cpu.picorv32_core.cpu_state. Not marking mgmt_core.soc.cpu.picorv32_core.irq_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking mgmt_core.soc.cpu.picorv32_core.mem_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register mgmt_core.soc.cpu.picorv32_core.mem_wordsize. Found FSM state register mgmt_core.soc.cpu.state. Not marking mgmt_core.soc.mprj_ctrl.mprj_ctrl.xfer_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register mgmt_core.soc.simple_spi_master_inst.spi_master.state. Not marking mgmt_core.soc.spimemio.spimemio.din_tag as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register mgmt_core.soc.spimemio.spimemio.state. 12.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\housekeeping.U1.state' from module `\mgmt_core'. found $adff cell for state register: $flatten\housekeeping.\U1.$procdff$15025 root of input selection tree: $flatten\housekeeping.\U1.$0\state[2:0] found reset state: 3'000 (from async reset) found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:382$3006_Y found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030_Y found state code: 3'010 found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:369$3005_Y found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016_Y found ctrl input: $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017_Y found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018_Y found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:429$3019_Y found ctrl input: \housekeeping.U1.pre_pass_thru_mgmt found ctrl input: \housekeeping.U1.pre_pass_thru_user found state code: 3'001 found state code: 3'100 found state code: 3'101 found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3008_Y found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3009_Y found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y ctrl inputs: { $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030_Y \housekeeping.U1.pre_pass_thru_mgmt \housekeeping.U1.pre_pass_thru_user $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:369$3005_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:382$3006_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016_Y $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:429$3019_Y } ctrl outputs: { $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3008_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3009_Y $flatten\housekeeping.\U1.$0\state[2:0] $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y } transition: 3'000 9'---000000 -> 3'000 8'00000001 transition: 3'000 9'-00010000 -> 3'001 8'00000011 transition: 3'000 9'-01010000 -> 3'100 8'00001001 transition: 3'000 9'-1-010000 -> 3'101 8'00001011 transition: 3'000 9'---0-0001 -> 3'000 8'00000001 transition: 3'000 9'---0-001- -> 3'000 8'00000001 transition: 3'000 9'---0-01-- -> 3'000 8'00000001 transition: 3'000 9'---0-1--- -> 3'000 8'00000001 transition: 3'000 9'---1----- -> 3'000 8'00000001 transition: 3'100 9'--------- -> 3'100 8'00011000 transition: 3'010 9'----0---- -> 3'010 8'01000100 transition: 3'010 9'0---1---- -> 3'010 8'01000100 transition: 3'010 9'1---1---- -> 3'000 8'01000000 transition: 3'001 9'----0---- -> 3'001 8'10000010 transition: 3'001 9'----1---- -> 3'010 8'10000100 transition: 3'101 9'--------- -> 3'101 8'00101010 Extracting FSM `\soc.cpu.picorv32_core.cpu_state' from module `\mgmt_core'. found $dff cell for state register: $flatten\soc.\cpu.\picorv32_core.$procdff$14682 root of input selection tree: $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$7529_Y found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$7512_Y found ctrl input: \soc.cpu.wb_rst_i found ctrl input: $auto$opt_reduce.cc:134:opt_mux$15184 found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$7497_Y found state code: 8'01000000 found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$7475_Y found ctrl input: \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu found ctrl input: \soc.cpu.picorv32_core.mem_done found ctrl input: \soc.cpu.picorv32_core.is_sb_sh_sw found ctrl input: \soc.cpu.picorv32_core.instr_trap found state code: 8'00001000 found state code: 8'00000010 found ctrl input: \soc.cpu.picorv32_core.pcpi_int_ready found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$7429_Y found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$7433_Y found state code: 8'10000000 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$15128 found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y found ctrl input: $auto$opt_reduce.cc:134:opt_mux$15126 found state code: 8'00000001 found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$7408_Y found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$7416_Y found ctrl input: \soc.cpu.picorv32_core.decoder_trigger found ctrl input: \soc.cpu.picorv32_core.instr_jal found state code: 8'00100000 found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7522_Y found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7515_Y found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$7519_Y found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7616_CMP found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$15128 $auto$opt_reduce.cc:134:opt_mux$15126 $auto$opt_reduce.cc:134:opt_mux$15184 \soc.cpu.picorv32_core.pcpi_int_ready \soc.cpu.picorv32_core.mem_done \soc.cpu.picorv32_core.instr_jal \soc.cpu.picorv32_core.instr_trap \soc.cpu.picorv32_core.decoder_trigger \soc.cpu.picorv32_core.is_sb_sh_sw \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$7408_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$7416_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$7429_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$7433_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$7475_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$7497_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$7512_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7515_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$7519_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7522_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$7529_Y \soc.cpu.wb_rst_i } ctrl outputs: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7616_CMP } transition: 8'10000000 24'------------------0---00 -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------0---01 -> 8'01000000 16'0010000000000001 transition: 8'10000000 24'------------------10-000 -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------10-001 -> 8'01000000 16'0010000000000001 transition: 8'10000000 24'------------------11000- -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------111000 -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------111001 -> 8'01000000 16'0010000000000001 transition: 8'10000000 24'------------------1-010- -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------101100 -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------101101 -> 8'01000000 16'0010000000000001 transition: 8'10000000 24'------------------111100 -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------111101 -> 8'01000000 16'0010000000000001 transition: 8'10000000 24'--------------------0-1- -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------0-1-10 -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------0-1-11 -> 8'01000000 16'0010000000000001 transition: 8'10000000 24'------------------101010 -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------101011 -> 8'01000000 16'0010000000000001 transition: 8'10000000 24'------------------111010 -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------111011 -> 8'01000000 16'0010000000000001 transition: 8'10000000 24'------------------101110 -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------101111 -> 8'01000000 16'0010000000000001 transition: 8'10000000 24'------------------111110 -> 8'10000000 16'0100000000000001 transition: 8'10000000 24'------------------111111 -> 8'01000000 16'0010000000000001 transition: 8'01000000 24'-------0--00------0---00 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-----0-1--00------0---00 -> 8'00100000 16'1001000000000000 transition: 8'01000000 24'-----1-1--00------0---00 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------01------0---00 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------1-------0---00 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------0---01 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-------0--00------10-000 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-----0-1--00------10-000 -> 8'00100000 16'1001000000000000 transition: 8'01000000 24'-----1-1--00------10-000 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------01------10-000 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------1-------10-000 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------10-001 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------11000- -> 8'10000000 16'1100000000000000 transition: 8'01000000 24'-------0--00------111000 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-----0-1--00------111000 -> 8'00100000 16'1001000000000000 transition: 8'01000000 24'-----1-1--00------111000 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------01------111000 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------1-------111000 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------111001 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------1-010- -> 8'10000000 16'1100000000000000 transition: 8'01000000 24'-------0--00------101100 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-----0-1--00------101100 -> 8'00100000 16'1001000000000000 transition: 8'01000000 24'-----1-1--00------101100 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------01------101100 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------1-------101100 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------101101 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-------0--00------111100 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-----0-1--00------111100 -> 8'00100000 16'1001000000000000 transition: 8'01000000 24'-----1-1--00------111100 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------01------111100 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------1-------111100 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------111101 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'--------------------0-1- -> 8'10000000 16'1100000000000000 transition: 8'01000000 24'-------0--00------0-1-10 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-----0-1--00------0-1-10 -> 8'00100000 16'1001000000000000 transition: 8'01000000 24'-----1-1--00------0-1-10 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------01------0-1-10 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------1-------0-1-10 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------0-1-11 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-------0--00------101010 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-----0-1--00------101010 -> 8'00100000 16'1001000000000000 transition: 8'01000000 24'-----1-1--00------101010 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------01------101010 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------1-------101010 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------101011 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-------0--00------111010 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-----0-1--00------111010 -> 8'00100000 16'1001000000000000 transition: 8'01000000 24'-----1-1--00------111010 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------01------111010 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------1-------111010 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------111011 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-------0--00------101110 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-----0-1--00------101110 -> 8'00100000 16'1001000000000000 transition: 8'01000000 24'-----1-1--00------101110 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------01------101110 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------1-------101110 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------101111 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-------0--00------111110 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'-----0-1--00------111110 -> 8'00100000 16'1001000000000000 transition: 8'01000000 24'-----1-1--00------111110 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------01------111110 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'----------1-------111110 -> 8'01000000 16'1010000000000000 transition: 8'01000000 24'------------------111111 -> 8'01000000 16'1010000000000000 transition: 8'00100000 24'00----0-0-----0---0---00 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'00------1-----0---0---00 -> 8'00000010 16'0000000100000010 transition: 8'00100000 24'---0--1-----0-----0---00 -> 8'00100000 16'0001000000000010 transition: 8'00100000 24'---0--1-----10----0---00 -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'---0--1-----11----0---00 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'---1--1-----------0---00 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'-1----------------0---00 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------1---0---00 -> 8'00000001 16'0000000010000010 transition: 8'00100000 24'1-----------------0---00 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'------------------0---01 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'00----0-0-----0---10-000 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'00------1-----0---10-000 -> 8'00000010 16'0000000100000010 transition: 8'00100000 24'---0--1-----0-----10-000 -> 8'00100000 16'0001000000000010 transition: 8'00100000 24'---0--1-----10----10-000 -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'---0--1-----11----10-000 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'---1--1-----------10-000 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'-1----------------10-000 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------1---10-000 -> 8'00000001 16'0000000010000010 transition: 8'00100000 24'1-----------------10-000 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'------------------10-001 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'------------------11000- -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'00----0-0-----0---111000 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'00------1-----0---111000 -> 8'00000010 16'0000000100000010 transition: 8'00100000 24'---0--1-----0-----111000 -> 8'00100000 16'0001000000000010 transition: 8'00100000 24'---0--1-----10----111000 -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'---0--1-----11----111000 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'---1--1-----------111000 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'-1----------------111000 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------1---111000 -> 8'00000001 16'0000000010000010 transition: 8'00100000 24'1-----------------111000 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'------------------111001 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'------------------1-010- -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'00----0-0-----0---101100 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'00------1-----0---101100 -> 8'00000010 16'0000000100000010 transition: 8'00100000 24'---0--1-----0-----101100 -> 8'00100000 16'0001000000000010 transition: 8'00100000 24'---0--1-----10----101100 -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'---0--1-----11----101100 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'---1--1-----------101100 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'-1----------------101100 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------1---101100 -> 8'00000001 16'0000000010000010 transition: 8'00100000 24'1-----------------101100 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'------------------101101 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'00----0-0-----0---111100 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'00------1-----0---111100 -> 8'00000010 16'0000000100000010 transition: 8'00100000 24'---0--1-----0-----111100 -> 8'00100000 16'0001000000000010 transition: 8'00100000 24'---0--1-----10----111100 -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'---0--1-----11----111100 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'---1--1-----------111100 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'-1----------------111100 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------1---111100 -> 8'00000001 16'0000000010000010 transition: 8'00100000 24'1-----------------111100 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'------------------111101 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------------0-1- -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'00----0-0-----0---0-1-10 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'00------1-----0---0-1-10 -> 8'00000010 16'0000000100000010 transition: 8'00100000 24'---0--1-----0-----0-1-10 -> 8'00100000 16'0001000000000010 transition: 8'00100000 24'---0--1-----10----0-1-10 -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'---0--1-----11----0-1-10 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'---1--1-----------0-1-10 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'-1----------------0-1-10 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------1---0-1-10 -> 8'00000001 16'0000000010000010 transition: 8'00100000 24'1-----------------0-1-10 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'------------------0-1-11 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'00----0-0-----0---101010 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'00------1-----0---101010 -> 8'00000010 16'0000000100000010 transition: 8'00100000 24'---0--1-----0-----101010 -> 8'00100000 16'0001000000000010 transition: 8'00100000 24'---0--1-----10----101010 -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'---0--1-----11----101010 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'---1--1-----------101010 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'-1----------------101010 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------1---101010 -> 8'00000001 16'0000000010000010 transition: 8'00100000 24'1-----------------101010 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'------------------101011 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'00----0-0-----0---111010 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'00------1-----0---111010 -> 8'00000010 16'0000000100000010 transition: 8'00100000 24'---0--1-----0-----111010 -> 8'00100000 16'0001000000000010 transition: 8'00100000 24'---0--1-----10----111010 -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'---0--1-----11----111010 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'---1--1-----------111010 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'-1----------------111010 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------1---111010 -> 8'00000001 16'0000000010000010 transition: 8'00100000 24'1-----------------111010 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'------------------111011 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'00----0-0-----0---101110 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'00------1-----0---101110 -> 8'00000010 16'0000000100000010 transition: 8'00100000 24'---0--1-----0-----101110 -> 8'00100000 16'0001000000000010 transition: 8'00100000 24'---0--1-----10----101110 -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'---0--1-----11----101110 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'---1--1-----------101110 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'-1----------------101110 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------1---101110 -> 8'00000001 16'0000000010000010 transition: 8'00100000 24'1-----------------101110 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'------------------101111 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'00----0-0-----0---111110 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'00------1-----0---111110 -> 8'00000010 16'0000000100000010 transition: 8'00100000 24'---0--1-----0-----111110 -> 8'00100000 16'0001000000000010 transition: 8'00100000 24'---0--1-----10----111110 -> 8'10000000 16'0100000000000010 transition: 8'00100000 24'---0--1-----11----111110 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'---1--1-----------111110 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'-1----------------111110 -> 8'01000000 16'0010000000000010 transition: 8'00100000 24'--------------1---111110 -> 8'00000001 16'0000000010000010 transition: 8'00100000 24'1-----------------111110 -> 8'00001000 16'0000010000000010 transition: 8'00100000 24'------------------111111 -> 8'01000000 16'0010000000000010 transition: 8'00001000 24'---------0--------0---00 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'----0----1--------0---00 -> 8'00001000 16'0000010000001000 transition: 8'00001000 24'----1----1--------0---00 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------0---01 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'---------0--------10-000 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'----0----1--------10-000 -> 8'00001000 16'0000010000001000 transition: 8'00001000 24'----1----1--------10-000 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------10-001 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------11000- -> 8'10000000 16'0100000000001000 transition: 8'00001000 24'---------0--------111000 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'----0----1--------111000 -> 8'00001000 16'0000010000001000 transition: 8'00001000 24'----1----1--------111000 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------111001 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------1-010- -> 8'10000000 16'0100000000001000 transition: 8'00001000 24'---------0--------101100 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'----0----1--------101100 -> 8'00001000 16'0000010000001000 transition: 8'00001000 24'----1----1--------101100 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------101101 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'---------0--------111100 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'----0----1--------111100 -> 8'00001000 16'0000010000001000 transition: 8'00001000 24'----1----1--------111100 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------111101 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'--------------------0-1- -> 8'10000000 16'0100000000001000 transition: 8'00001000 24'---------0--------0-1-10 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'----0----1--------0-1-10 -> 8'00001000 16'0000010000001000 transition: 8'00001000 24'----1----1--------0-1-10 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------0-1-11 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'---------0--------101010 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'----0----1--------101010 -> 8'00001000 16'0000010000001000 transition: 8'00001000 24'----1----1--------101010 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------101011 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'---------0--------111010 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'----0----1--------111010 -> 8'00001000 16'0000010000001000 transition: 8'00001000 24'----1----1--------111010 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------111011 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'---------0--------101110 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'----0----1--------101110 -> 8'00001000 16'0000010000001000 transition: 8'00001000 24'----1----1--------101110 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------101111 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'---------0--------111110 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'----0----1--------111110 -> 8'00001000 16'0000010000001000 transition: 8'00001000 24'----1----1--------111110 -> 8'01000000 16'0010000000001000 transition: 8'00001000 24'------------------111111 -> 8'01000000 16'0010000000001000 transition: 8'00000010 24'----------------0-0---00 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------100---00 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------110---00 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------0---01 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'----------------0-10-000 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------1010-000 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------1110-000 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------10-001 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------11000- -> 8'10000000 16'0100000000100000 transition: 8'00000010 24'----------------0-111000 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------10111000 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------11111000 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------111001 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------1-010- -> 8'10000000 16'0100000000100000 transition: 8'00000010 24'----------------0-101100 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------10101100 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------11101100 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------101101 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'----------------0-111100 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------10111100 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------11111100 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------111101 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'--------------------0-1- -> 8'10000000 16'0100000000100000 transition: 8'00000010 24'----------------0-0-1-10 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------100-1-10 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------110-1-10 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------0-1-11 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'----------------0-101010 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------10101010 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------11101010 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------101011 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'----------------0-111010 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------10111010 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------11111010 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------111011 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'----------------0-101110 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------10101110 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------11101110 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------101111 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'----------------0-111110 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------10111110 -> 8'00000010 16'0000000100100000 transition: 8'00000010 24'----------------11111110 -> 8'01000000 16'0010000000100000 transition: 8'00000010 24'------------------111111 -> 8'01000000 16'0010000000100000 transition: 8'00000001 24'----------------0-0---00 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------100---00 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------110---00 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------0---01 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'----------------0-10-000 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------1010-000 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------1110-000 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------10-001 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------11000- -> 8'10000000 16'0100000001000000 transition: 8'00000001 24'----------------0-111000 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------10111000 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------11111000 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------111001 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------1-010- -> 8'10000000 16'0100000001000000 transition: 8'00000001 24'----------------0-101100 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------10101100 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------11101100 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------101101 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'----------------0-111100 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------10111100 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------11111100 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------111101 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'--------------------0-1- -> 8'10000000 16'0100000001000000 transition: 8'00000001 24'----------------0-0-1-10 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------100-1-10 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------110-1-10 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------0-1-11 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'----------------0-101010 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------10101010 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------11101010 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------101011 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'----------------0-111010 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------10111010 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------11111010 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------111011 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'----------------0-101110 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------10101110 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------11101110 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------101111 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'----------------0-111110 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------10111110 -> 8'00000001 16'0000000011000000 transition: 8'00000001 24'----------------11111110 -> 8'01000000 16'0010000001000000 transition: 8'00000001 24'------------------111111 -> 8'01000000 16'0010000001000000 Extracting FSM `\soc.cpu.picorv32_core.mem_wordsize' from module `\mgmt_core'. found $dff cell for state register: $flatten\soc.\cpu.\picorv32_core.$procdff$14669 root of input selection tree: $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] found ctrl input: \soc.cpu.wb_rst_i found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y found ctrl input: \soc.cpu.picorv32_core.mem_do_rdata found ctrl input: \soc.cpu.picorv32_core.instr_lw found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$7502_Y found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$7501_Y found state code: 2'00 found state code: 2'01 found state code: 2'10 found ctrl input: \soc.cpu.picorv32_core.mem_do_wdata found ctrl input: \soc.cpu.picorv32_core.instr_sw found ctrl input: \soc.cpu.picorv32_core.instr_sh found ctrl input: \soc.cpu.picorv32_core.instr_sb found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$10355_CMP found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7520_Y found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7513_Y ctrl inputs: { \soc.cpu.picorv32_core.mem_do_rdata \soc.cpu.picorv32_core.mem_do_wdata \soc.cpu.picorv32_core.instr_lw \soc.cpu.picorv32_core.instr_sb \soc.cpu.picorv32_core.instr_sh \soc.cpu.picorv32_core.instr_sw $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$7501_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$7502_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP \soc.cpu.wb_rst_i } ctrl outputs: { $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7513_Y $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7520_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10355_CMP } transition: 2'00 13'------0---000 -> 2'00 5'00100 transition: 2'00 13'------1-----0 -> 2'00 5'00100 transition: 2'00 13'-------0---10 -> 2'00 5'00100 transition: 2'00 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx100 transition: 2'00 13'-0-1---1---10 -> 2'10 5'10100 transition: 2'00 13'-0--1--1---10 -> 2'01 5'01100 transition: 2'00 13'-0---1-1---10 -> 2'00 5'00100 transition: 2'00 13'-1-----1---10 -> 2'00 5'00100 transition: 2'00 13'-------0--1-0 -> 2'00 5'00100 transition: 2'00 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx100 transition: 2'00 13'0------11-1-0 -> 2'10 5'10100 transition: 2'00 13'0------1-11-0 -> 2'01 5'01100 transition: 2'00 13'0-1----1--1-0 -> 2'00 5'00100 transition: 2'00 13'1------1--1-0 -> 2'00 5'00100 transition: 2'00 13'------------1 -> 2'00 5'00100 transition: 2'10 13'------0---000 -> 2'10 5'10001 transition: 2'10 13'------1-----0 -> 2'00 5'00001 transition: 2'10 13'-------0---10 -> 2'10 5'10001 transition: 2'10 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx001 transition: 2'10 13'-0-1---1---10 -> 2'10 5'10001 transition: 2'10 13'-0--1--1---10 -> 2'01 5'01001 transition: 2'10 13'-0---1-1---10 -> 2'00 5'00001 transition: 2'10 13'-1-----1---10 -> 2'10 5'10001 transition: 2'10 13'-------0--1-0 -> 2'10 5'10001 transition: 2'10 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx001 transition: 2'10 13'0------11-1-0 -> 2'10 5'10001 transition: 2'10 13'0------1-11-0 -> 2'01 5'01001 transition: 2'10 13'0-1----1--1-0 -> 2'00 5'00001 transition: 2'10 13'1------1--1-0 -> 2'10 5'10001 transition: 2'10 13'------------1 -> 2'10 5'10001 transition: 2'01 13'------0---000 -> 2'01 5'01010 transition: 2'01 13'------1-----0 -> 2'00 5'00010 transition: 2'01 13'-------0---10 -> 2'01 5'01010 transition: 2'01 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx010 transition: 2'01 13'-0-1---1---10 -> 2'10 5'10010 transition: 2'01 13'-0--1--1---10 -> 2'01 5'01010 transition: 2'01 13'-0---1-1---10 -> 2'00 5'00010 transition: 2'01 13'-1-----1---10 -> 2'01 5'01010 transition: 2'01 13'-------0--1-0 -> 2'01 5'01010 transition: 2'01 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx010 transition: 2'01 13'0------11-1-0 -> 2'10 5'10010 transition: 2'01 13'0------1-11-0 -> 2'01 5'01010 transition: 2'01 13'0-1----1--1-0 -> 2'00 5'00010 transition: 2'01 13'1------1--1-0 -> 2'01 5'01010 transition: 2'01 13'------------1 -> 2'01 5'01010 Extracting FSM `\soc.cpu.state' from module `\mgmt_core'. found $dff cell for state register: $flatten\soc.\cpu.$procdff$14886 root of input selection tree: $flatten\soc.\cpu.$0\state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \soc.cpu.wb_rst_i found ctrl input: $flatten\soc.\cpu.$procmux$12350_CMP found ctrl input: $flatten\soc.\cpu.$procmux$12354_CMP found state code: 2'00 found ctrl input: \soc.cpu.wbm_ack_i found state code: 2'10 found ctrl input: \soc.cpu.picorv32_core.mem_valid found state code: 2'01 found ctrl output: $flatten\soc.\cpu.$procmux$12350_CMP found ctrl output: $flatten\soc.\cpu.$procmux$12354_CMP found ctrl output: $flatten\soc.\cpu.$procmux$12441_CMP ctrl inputs: { \soc.cpu.picorv32_core.mem_valid \soc.cpu.wbm_ack_i \soc.cpu.wb_rst_i } ctrl outputs: { $flatten\soc.\cpu.$procmux$12441_CMP $flatten\soc.\cpu.$procmux$12354_CMP $flatten\soc.\cpu.$procmux$12350_CMP $flatten\soc.\cpu.$0\state[1:0] } transition: 2'00 3'0-0 -> 2'00 5'01000 transition: 2'00 3'1-0 -> 2'01 5'01001 transition: 2'00 3'--1 -> 2'00 5'01000 transition: 2'10 3'--0 -> 2'00 5'10000 transition: 2'10 3'--1 -> 2'00 5'10000 transition: 2'01 3'-00 -> 2'01 5'00101 transition: 2'01 3'-10 -> 2'10 5'00110 transition: 2'01 3'--1 -> 2'00 5'00100 Extracting FSM `\soc.simple_spi_master_inst.spi_master.state' from module `\mgmt_core'. found $adff cell for state register: $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14916 root of input selection tree: $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] found reset state: 2'00 (from async reset) found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:305$1398_Y found state code: 2'01 found state code: 2'11 found state code: 2'10 found ctrl input: \soc.simple_spi_master_inst.spi_master.w_latched found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y ctrl inputs: { \soc.simple_spi_master_inst.spi_master.w_latched $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:305$1398_Y } ctrl outputs: { $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y } transition: 2'00 2'0- -> 2'00 6'000010 transition: 2'00 2'1- -> 2'01 6'000110 transition: 2'10 2'-0 -> 2'01 6'010100 transition: 2'10 2'-1 -> 2'11 6'011100 transition: 2'01 2'-- -> 2'10 6'101000 transition: 2'11 2'-- -> 2'00 6'000001 Extracting FSM `\soc.spimemio.spimemio.state' from module `\mgmt_core'. found $dff cell for state register: $flatten\soc.\spimemio.\spimemio.$procdff$14960 root of input selection tree: $flatten\soc.\spimemio.\spimemio.$0\state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:373$1216_Y found ctrl input: \soc.spimemio.spimemio.jump found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:512$1234_Y found ctrl input: \soc.spimemio.spimemio.xfer.din_ready found state code: 4'1001 found state code: 4'1100 found state code: 4'1011 found state code: 4'1010 found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:472$1230_Y found state code: 4'1000 found state code: 4'0111 found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1137_Y found state code: 4'0110 found state code: 4'0101 found ctrl input: \soc.spimemio.spimemio.dout_valid found state code: 4'0100 found state code: 4'0011 found state code: 4'0010 found state code: 4'0001 found ctrl input: \soc.spimemio.spimemio.config_cont found state code: 4'0000 found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP ctrl inputs: { \soc.spimemio.spimemio.dout_valid \soc.spimemio.spimemio.jump \soc.spimemio.spimemio.config_cont $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1137_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:373$1216_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:472$1230_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:512$1234_Y \soc.spimemio.spimemio.xfer.din_ready } ctrl outputs: { $flatten\soc.\spimemio.\spimemio.$0\state[3:0] $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP } transition: 4'0000 8'-0--0--0 -> 4'0000 17'00000000000000001 transition: 4'0000 8'-0--0--1 -> 4'0001 17'00010000000000001 transition: 4'0000 8'-10-0--- -> 4'0100 17'01000000000000001 transition: 4'0000 8'-11-0--- -> 4'0101 17'01010000000000001 transition: 4'0000 8'----1--- -> 4'0000 17'00000000000000001 transition: 4'1000 8'-0--0--0 -> 4'1000 17'10000000000100000 transition: 4'1000 8'-0--0--1 -> 4'1001 17'10010000000100000 transition: 4'1000 8'-10-0--- -> 4'0100 17'01000000000100000 transition: 4'1000 8'-11-0--- -> 4'0101 17'01010000000100000 transition: 4'1000 8'----1--- -> 4'0000 17'00000000000100000 transition: 4'0100 8'-0--0--0 -> 4'0100 17'01000010000000000 transition: 4'0100 8'-0--0--1 -> 4'0101 17'01010010000000000 transition: 4'0100 8'-10-0--- -> 4'0100 17'01000010000000000 transition: 4'0100 8'-11-0--- -> 4'0101 17'01010010000000000 transition: 4'0100 8'----1--- -> 4'0000 17'00000010000000000 transition: 4'1100 8'-0--0-0- -> 4'1100 17'11000001000000000 transition: 4'1100 8'-0--0-10 -> 4'1100 17'11000001000000000 transition: 4'1100 8'-0--0-11 -> 4'1001 17'10010001000000000 transition: 4'1100 8'-10-0--- -> 4'0100 17'01000001000000000 transition: 4'1100 8'-11-0--- -> 4'0101 17'01010001000000000 transition: 4'1100 8'----1--- -> 4'0000 17'00000001000000000 transition: 4'0010 8'-0--0--0 -> 4'0010 17'00100000000000010 transition: 4'0010 8'-0--0--1 -> 4'0011 17'00110000000000010 transition: 4'0010 8'-10-0--- -> 4'0100 17'01000000000000010 transition: 4'0010 8'-11-0--- -> 4'0101 17'01010000000000010 transition: 4'0010 8'----1--- -> 4'0000 17'00000000000000010 transition: 4'1010 8'-0--0--0 -> 4'1010 17'10100000010000000 transition: 4'1010 8'-0--0--1 -> 4'1011 17'10110000010000000 transition: 4'1010 8'-10-0--- -> 4'0100 17'01000000010000000 transition: 4'1010 8'-11-0--- -> 4'0101 17'01010000010000000 transition: 4'1010 8'----1--- -> 4'0000 17'00000000010000000 transition: 4'0110 8'-0--0--0 -> 4'0110 17'01100000000001000 transition: 4'0110 8'-0--0--1 -> 4'0111 17'01110000000001000 transition: 4'0110 8'-10-0--- -> 4'0100 17'01000000000001000 transition: 4'0110 8'-11-0--- -> 4'0101 17'01010000000001000 transition: 4'0110 8'----1--- -> 4'0000 17'00000000000001000 transition: 4'0001 8'00--0--- -> 4'0001 17'00010100000000000 transition: 4'0001 8'10--0--- -> 4'0010 17'00100100000000000 transition: 4'0001 8'-10-0--- -> 4'0100 17'01000100000000000 transition: 4'0001 8'-11-0--- -> 4'0101 17'01010100000000000 transition: 4'0001 8'----1--- -> 4'0000 17'00000100000000000 transition: 4'1001 8'-0--0--0 -> 4'1001 17'10010000001000000 transition: 4'1001 8'-0--0--1 -> 4'1010 17'10100000001000000 transition: 4'1001 8'-10-0--- -> 4'0100 17'01000000001000000 transition: 4'1001 8'-11-0--- -> 4'0101 17'01010000001000000 transition: 4'1001 8'----1--- -> 4'0000 17'00000000001000000 transition: 4'0101 8'-0-00--- -> 4'0101 17'01010000000000100 transition: 4'0101 8'-0-10--0 -> 4'0101 17'01010000000000100 transition: 4'0101 8'-0-10--1 -> 4'0110 17'01100000000000100 transition: 4'0101 8'-10-0--- -> 4'0100 17'01000000000000100 transition: 4'0101 8'-11-0--- -> 4'0101 17'01010000000000100 transition: 4'0101 8'----1--- -> 4'0000 17'00000000000000100 transition: 4'0011 8'00--0--- -> 4'0011 17'00111000000000000 transition: 4'0011 8'10--0--- -> 4'0100 17'01001000000000000 transition: 4'0011 8'-10-0--- -> 4'0100 17'01001000000000000 transition: 4'0011 8'-11-0--- -> 4'0101 17'01011000000000000 transition: 4'0011 8'----1--- -> 4'0000 17'00001000000000000 transition: 4'1011 8'-0--0--0 -> 4'1011 17'10110000100000000 transition: 4'1011 8'-0--0--1 -> 4'1100 17'11000000100000000 transition: 4'1011 8'-10-0--- -> 4'0100 17'01000000100000000 transition: 4'1011 8'-11-0--- -> 4'0101 17'01010000100000000 transition: 4'1011 8'----1--- -> 4'0000 17'00000000100000000 transition: 4'0111 8'-0--0--0 -> 4'0111 17'01110000000010000 transition: 4'0111 8'-0--00-1 -> 4'1001 17'10010000000010000 transition: 4'0111 8'-0--01-1 -> 4'1000 17'10000000000010000 transition: 4'0111 8'-10-0--- -> 4'0100 17'01000000000010000 transition: 4'0111 8'-11-0--- -> 4'0101 17'01010000000010000 transition: 4'0111 8'----1--- -> 4'0000 17'00000000000010000 12.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core'. Optimizing FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core'. Optimizing FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core'. Merging pattern 3'--0 and 3'--1 from group (1 0 5'10000). Merging pattern 3'--1 and 3'--0 from group (1 0 5'10000). Optimizing FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core'. Optimizing FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core'. Merging pattern 24'------------------111000 and 24'------------------111010 from group (0 0 16'0100000000000001). Merging pattern 24'------------------101100 and 24'------------------101110 from group (0 0 16'0100000000000001). Merging pattern 24'------------------111100 and 24'------------------111110 from group (0 0 16'0100000000000001). Merging pattern 24'------------------111010 and 24'------------------111000 from group (0 0 16'0100000000000001). Merging pattern 24'------------------101110 and 24'------------------101100 from group (0 0 16'0100000000000001). Merging pattern 24'------------------111110 and 24'------------------111100 from group (0 0 16'0100000000000001). Merging pattern 24'------------------1110-0 and 24'------------------1111-0 from group (0 0 16'0100000000000001). Merging pattern 24'------------------1111-0 and 24'------------------1110-0 from group (0 0 16'0100000000000001). Merging pattern 24'------------------111001 and 24'------------------111011 from group (0 1 16'0010000000000001). Merging pattern 24'------------------101101 and 24'------------------101111 from group (0 1 16'0010000000000001). Merging pattern 24'------------------111101 and 24'------------------111111 from group (0 1 16'0010000000000001). Merging pattern 24'------------------111011 and 24'------------------111001 from group (0 1 16'0010000000000001). Merging pattern 24'------------------101111 and 24'------------------101101 from group (0 1 16'0010000000000001). Merging pattern 24'------------------111111 and 24'------------------111101 from group (0 1 16'0010000000000001). Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (0 1 16'0010000000000001). Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (0 1 16'0010000000000001). Merging pattern 24'-------0--00------111000 and 24'-------0--00------111010 from group (1 1 16'1010000000000000). Merging pattern 24'-----1-1--00------111000 and 24'-----1-1--00------111010 from group (1 1 16'1010000000000000). Merging pattern 24'----------01------111000 and 24'----------01------111010 from group (1 1 16'1010000000000000). Merging pattern 24'----------1-------111000 and 24'----------1-------111010 from group (1 1 16'1010000000000000). Merging pattern 24'-------0--00------101100 and 24'-------0--00------101110 from group (1 1 16'1010000000000000). Merging pattern 24'-----1-1--00------101100 and 24'-----1-1--00------101110 from group (1 1 16'1010000000000000). Merging pattern 24'----------01------101100 and 24'----------01------101110 from group (1 1 16'1010000000000000). Merging pattern 24'----------1-------101100 and 24'----------1-------101110 from group (1 1 16'1010000000000000). Merging pattern 24'-------0--00------111100 and 24'-------0--00------111110 from group (1 1 16'1010000000000000). Merging pattern 24'-----1-1--00------111100 and 24'-----1-1--00------111110 from group (1 1 16'1010000000000000). Merging pattern 24'----------01------111100 and 24'----------01------111110 from group (1 1 16'1010000000000000). Merging pattern 24'----------1-------111100 and 24'----------1-------111110 from group (1 1 16'1010000000000000). Merging pattern 24'-------0--00------111010 and 24'-------0--00------111000 from group (1 1 16'1010000000000000). Merging pattern 24'-----1-1--00------111010 and 24'-----1-1--00------111000 from group (1 1 16'1010000000000000). Merging pattern 24'----------01------111010 and 24'----------01------111000 from group (1 1 16'1010000000000000). Merging pattern 24'----------1-------111010 and 24'----------1-------111000 from group (1 1 16'1010000000000000). Merging pattern 24'-------0--00------101110 and 24'-------0--00------101100 from group (1 1 16'1010000000000000). Merging pattern 24'-----1-1--00------101110 and 24'-----1-1--00------101100 from group (1 1 16'1010000000000000). Merging pattern 24'----------01------101110 and 24'----------01------101100 from group (1 1 16'1010000000000000). Merging pattern 24'----------1-------101110 and 24'----------1-------101100 from group (1 1 16'1010000000000000). Merging pattern 24'-------0--00------111110 and 24'-------0--00------111100 from group (1 1 16'1010000000000000). Merging pattern 24'-----1-1--00------111110 and 24'-----1-1--00------111100 from group (1 1 16'1010000000000000). Merging pattern 24'----------01------111110 and 24'----------01------111100 from group (1 1 16'1010000000000000). Merging pattern 24'----------1-------111110 and 24'----------1-------111100 from group (1 1 16'1010000000000000). Merging pattern 24'------------------111001 and 24'------------------111011 from group (1 1 16'1010000000000000). Merging pattern 24'------------------101101 and 24'------------------101111 from group (1 1 16'1010000000000000). Merging pattern 24'------------------111101 and 24'------------------111111 from group (1 1 16'1010000000000000). Merging pattern 24'------------------111011 and 24'------------------111001 from group (1 1 16'1010000000000000). Merging pattern 24'------------------101111 and 24'------------------101101 from group (1 1 16'1010000000000000). Merging pattern 24'------------------111111 and 24'------------------111101 from group (1 1 16'1010000000000000). Merging pattern 24'-------0--00------1110-0 and 24'-------0--00------1111-0 from group (1 1 16'1010000000000000). Merging pattern 24'-----1-1--00------1110-0 and 24'-----1-1--00------1111-0 from group (1 1 16'1010000000000000). Merging pattern 24'----------01------1110-0 and 24'----------01------1111-0 from group (1 1 16'1010000000000000). Merging pattern 24'----------1-------1110-0 and 24'----------1-------1111-0 from group (1 1 16'1010000000000000). Merging pattern 24'-------0--00------1111-0 and 24'-------0--00------1110-0 from group (1 1 16'1010000000000000). Merging pattern 24'-----1-1--00------1111-0 and 24'-----1-1--00------1110-0 from group (1 1 16'1010000000000000). Merging pattern 24'----------01------1111-0 and 24'----------01------1110-0 from group (1 1 16'1010000000000000). Merging pattern 24'----------1-------1111-0 and 24'----------1-------1110-0 from group (1 1 16'1010000000000000). Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (1 1 16'1010000000000000). Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (1 1 16'1010000000000000). Merging pattern 24'-----0-1--00------111000 and 24'-----0-1--00------111010 from group (1 2 16'1001000000000000). Merging pattern 24'-----0-1--00------101100 and 24'-----0-1--00------101110 from group (1 2 16'1001000000000000). Merging pattern 24'-----0-1--00------111100 and 24'-----0-1--00------111110 from group (1 2 16'1001000000000000). Merging pattern 24'-----0-1--00------111010 and 24'-----0-1--00------111000 from group (1 2 16'1001000000000000). Merging pattern 24'-----0-1--00------101110 and 24'-----0-1--00------101100 from group (1 2 16'1001000000000000). Merging pattern 24'-----0-1--00------111110 and 24'-----0-1--00------111100 from group (1 2 16'1001000000000000). Merging pattern 24'-----0-1--00------1110-0 and 24'-----0-1--00------1111-0 from group (1 2 16'1001000000000000). Merging pattern 24'-----0-1--00------1111-0 and 24'-----0-1--00------1110-0 from group (1 2 16'1001000000000000). Merging pattern 24'---0--1-----10----111000 and 24'---0--1-----10----111010 from group (2 0 16'0100000000000010). Merging pattern 24'---0--1-----10----101100 and 24'---0--1-----10----101110 from group (2 0 16'0100000000000010). Merging pattern 24'---0--1-----10----111100 and 24'---0--1-----10----111110 from group (2 0 16'0100000000000010). Merging pattern 24'---0--1-----10----111010 and 24'---0--1-----10----111000 from group (2 0 16'0100000000000010). Merging pattern 24'---0--1-----10----101110 and 24'---0--1-----10----101100 from group (2 0 16'0100000000000010). Merging pattern 24'---0--1-----10----111110 and 24'---0--1-----10----111100 from group (2 0 16'0100000000000010). Merging pattern 24'---0--1-----10----1110-0 and 24'---0--1-----10----1111-0 from group (2 0 16'0100000000000010). Merging pattern 24'---0--1-----10----1111-0 and 24'---0--1-----10----1110-0 from group (2 0 16'0100000000000010). Merging pattern 24'---0--1-----11----111000 and 24'---0--1-----11----111010 from group (2 1 16'0010000000000010). Merging pattern 24'---1--1-----------111000 and 24'---1--1-----------111010 from group (2 1 16'0010000000000010). Merging pattern 24'-1----------------111000 and 24'-1----------------111010 from group (2 1 16'0010000000000010). Merging pattern 24'---0--1-----11----101100 and 24'---0--1-----11----101110 from group (2 1 16'0010000000000010). Merging pattern 24'---1--1-----------101100 and 24'---1--1-----------101110 from group (2 1 16'0010000000000010). Merging pattern 24'-1----------------101100 and 24'-1----------------101110 from group (2 1 16'0010000000000010). Merging pattern 24'---0--1-----11----111100 and 24'---0--1-----11----111110 from group (2 1 16'0010000000000010). Merging pattern 24'---1--1-----------111100 and 24'---1--1-----------111110 from group (2 1 16'0010000000000010). Merging pattern 24'-1----------------111100 and 24'-1----------------111110 from group (2 1 16'0010000000000010). Merging pattern 24'---0--1-----11----111010 and 24'---0--1-----11----111000 from group (2 1 16'0010000000000010). Merging pattern 24'---1--1-----------111010 and 24'---1--1-----------111000 from group (2 1 16'0010000000000010). Merging pattern 24'-1----------------111010 and 24'-1----------------111000 from group (2 1 16'0010000000000010). Merging pattern 24'---0--1-----11----101110 and 24'---0--1-----11----101100 from group (2 1 16'0010000000000010). Merging pattern 24'---1--1-----------101110 and 24'---1--1-----------101100 from group (2 1 16'0010000000000010). Merging pattern 24'-1----------------101110 and 24'-1----------------101100 from group (2 1 16'0010000000000010). Merging pattern 24'---0--1-----11----111110 and 24'---0--1-----11----111100 from group (2 1 16'0010000000000010). Merging pattern 24'---1--1-----------111110 and 24'---1--1-----------111100 from group (2 1 16'0010000000000010). Merging pattern 24'-1----------------111110 and 24'-1----------------111100 from group (2 1 16'0010000000000010). Merging pattern 24'------------------111001 and 24'------------------111011 from group (2 1 16'0010000000000010). Merging pattern 24'------------------101101 and 24'------------------101111 from group (2 1 16'0010000000000010). Merging pattern 24'------------------111101 and 24'------------------111111 from group (2 1 16'0010000000000010). Merging pattern 24'------------------111011 and 24'------------------111001 from group (2 1 16'0010000000000010). Merging pattern 24'------------------101111 and 24'------------------101101 from group (2 1 16'0010000000000010). Merging pattern 24'------------------111111 and 24'------------------111101 from group (2 1 16'0010000000000010). Merging pattern 24'---0--1-----11----1110-0 and 24'---0--1-----11----1111-0 from group (2 1 16'0010000000000010). Merging pattern 24'---1--1-----------1110-0 and 24'---1--1-----------1111-0 from group (2 1 16'0010000000000010). Merging pattern 24'-1----------------1110-0 and 24'-1----------------1111-0 from group (2 1 16'0010000000000010). Merging pattern 24'---0--1-----11----1111-0 and 24'---0--1-----11----1110-0 from group (2 1 16'0010000000000010). Merging pattern 24'---1--1-----------1111-0 and 24'---1--1-----------1110-0 from group (2 1 16'0010000000000010). Merging pattern 24'-1----------------1111-0 and 24'-1----------------1110-0 from group (2 1 16'0010000000000010). Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (2 1 16'0010000000000010). Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (2 1 16'0010000000000010). Merging pattern 24'---0--1-----0-----111000 and 24'---0--1-----0-----111010 from group (2 2 16'0001000000000010). Merging pattern 24'---0--1-----0-----101100 and 24'---0--1-----0-----101110 from group (2 2 16'0001000000000010). Merging pattern 24'---0--1-----0-----111100 and 24'---0--1-----0-----111110 from group (2 2 16'0001000000000010). Merging pattern 24'---0--1-----0-----111010 and 24'---0--1-----0-----111000 from group (2 2 16'0001000000000010). Merging pattern 24'---0--1-----0-----101110 and 24'---0--1-----0-----101100 from group (2 2 16'0001000000000010). Merging pattern 24'---0--1-----0-----111110 and 24'---0--1-----0-----111100 from group (2 2 16'0001000000000010). Merging pattern 24'---0--1-----0-----1110-0 and 24'---0--1-----0-----1111-0 from group (2 2 16'0001000000000010). Merging pattern 24'---0--1-----0-----1111-0 and 24'---0--1-----0-----1110-0 from group (2 2 16'0001000000000010). Merging pattern 24'00----0-0-----0---111000 and 24'00----0-0-----0---111010 from group (2 3 16'0000010000000010). Merging pattern 24'1-----------------111000 and 24'1-----------------111010 from group (2 3 16'0000010000000010). Merging pattern 24'00----0-0-----0---101100 and 24'00----0-0-----0---101110 from group (2 3 16'0000010000000010). Merging pattern 24'1-----------------101100 and 24'1-----------------101110 from group (2 3 16'0000010000000010). Merging pattern 24'00----0-0-----0---111100 and 24'00----0-0-----0---111110 from group (2 3 16'0000010000000010). Merging pattern 24'1-----------------111100 and 24'1-----------------111110 from group (2 3 16'0000010000000010). Merging pattern 24'00----0-0-----0---111010 and 24'00----0-0-----0---111000 from group (2 3 16'0000010000000010). Merging pattern 24'1-----------------111010 and 24'1-----------------111000 from group (2 3 16'0000010000000010). Merging pattern 24'00----0-0-----0---101110 and 24'00----0-0-----0---101100 from group (2 3 16'0000010000000010). Merging pattern 24'1-----------------101110 and 24'1-----------------101100 from group (2 3 16'0000010000000010). Merging pattern 24'00----0-0-----0---111110 and 24'00----0-0-----0---111100 from group (2 3 16'0000010000000010). Merging pattern 24'1-----------------111110 and 24'1-----------------111100 from group (2 3 16'0000010000000010). Merging pattern 24'00----0-0-----0---1110-0 and 24'00----0-0-----0---1111-0 from group (2 3 16'0000010000000010). Merging pattern 24'1-----------------1110-0 and 24'1-----------------1111-0 from group (2 3 16'0000010000000010). Merging pattern 24'00----0-0-----0---1111-0 and 24'00----0-0-----0---1110-0 from group (2 3 16'0000010000000010). Merging pattern 24'1-----------------1111-0 and 24'1-----------------1110-0 from group (2 3 16'0000010000000010). Merging pattern 24'00------1-----0---111000 and 24'00------1-----0---111010 from group (2 4 16'0000000100000010). Merging pattern 24'00------1-----0---101100 and 24'00------1-----0---101110 from group (2 4 16'0000000100000010). Merging pattern 24'00------1-----0---111100 and 24'00------1-----0---111110 from group (2 4 16'0000000100000010). Merging pattern 24'00------1-----0---111010 and 24'00------1-----0---111000 from group (2 4 16'0000000100000010). Merging pattern 24'00------1-----0---101110 and 24'00------1-----0---101100 from group (2 4 16'0000000100000010). Merging pattern 24'00------1-----0---111110 and 24'00------1-----0---111100 from group (2 4 16'0000000100000010). Merging pattern 24'00------1-----0---1110-0 and 24'00------1-----0---1111-0 from group (2 4 16'0000000100000010). Merging pattern 24'00------1-----0---1111-0 and 24'00------1-----0---1110-0 from group (2 4 16'0000000100000010). Merging pattern 24'--------------1---111000 and 24'--------------1---111010 from group (2 5 16'0000000010000010). Merging pattern 24'--------------1---101100 and 24'--------------1---101110 from group (2 5 16'0000000010000010). Merging pattern 24'--------------1---111100 and 24'--------------1---111110 from group (2 5 16'0000000010000010). Merging pattern 24'--------------1---111010 and 24'--------------1---111000 from group (2 5 16'0000000010000010). Merging pattern 24'--------------1---101110 and 24'--------------1---101100 from group (2 5 16'0000000010000010). Merging pattern 24'--------------1---111110 and 24'--------------1---111100 from group (2 5 16'0000000010000010). Merging pattern 24'--------------1---1110-0 and 24'--------------1---1111-0 from group (2 5 16'0000000010000010). Merging pattern 24'--------------1---1111-0 and 24'--------------1---1110-0 from group (2 5 16'0000000010000010). Merging pattern 24'---------0--------111000 and 24'---------0--------111010 from group (3 1 16'0010000000001000). Merging pattern 24'----1----1--------111000 and 24'----1----1--------111010 from group (3 1 16'0010000000001000). Merging pattern 24'---------0--------101100 and 24'---------0--------101110 from group (3 1 16'0010000000001000). Merging pattern 24'----1----1--------101100 and 24'----1----1--------101110 from group (3 1 16'0010000000001000). Merging pattern 24'---------0--------111100 and 24'---------0--------111110 from group (3 1 16'0010000000001000). Merging pattern 24'----1----1--------111100 and 24'----1----1--------111110 from group (3 1 16'0010000000001000). Merging pattern 24'---------0--------111010 and 24'---------0--------111000 from group (3 1 16'0010000000001000). Merging pattern 24'----1----1--------111010 and 24'----1----1--------111000 from group (3 1 16'0010000000001000). Merging pattern 24'---------0--------101110 and 24'---------0--------101100 from group (3 1 16'0010000000001000). Merging pattern 24'----1----1--------101110 and 24'----1----1--------101100 from group (3 1 16'0010000000001000). Merging pattern 24'---------0--------111110 and 24'---------0--------111100 from group (3 1 16'0010000000001000). Merging pattern 24'----1----1--------111110 and 24'----1----1--------111100 from group (3 1 16'0010000000001000). Merging pattern 24'------------------111001 and 24'------------------111011 from group (3 1 16'0010000000001000). Merging pattern 24'------------------101101 and 24'------------------101111 from group (3 1 16'0010000000001000). Merging pattern 24'------------------111101 and 24'------------------111111 from group (3 1 16'0010000000001000). Merging pattern 24'------------------111011 and 24'------------------111001 from group (3 1 16'0010000000001000). Merging pattern 24'------------------101111 and 24'------------------101101 from group (3 1 16'0010000000001000). Merging pattern 24'------------------111111 and 24'------------------111101 from group (3 1 16'0010000000001000). Merging pattern 24'---------0--------1110-0 and 24'---------0--------1111-0 from group (3 1 16'0010000000001000). Merging pattern 24'----1----1--------1110-0 and 24'----1----1--------1111-0 from group (3 1 16'0010000000001000). Merging pattern 24'---------0--------1111-0 and 24'---------0--------1110-0 from group (3 1 16'0010000000001000). Merging pattern 24'----1----1--------1111-0 and 24'----1----1--------1110-0 from group (3 1 16'0010000000001000). Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (3 1 16'0010000000001000). Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (3 1 16'0010000000001000). Merging pattern 24'----0----1--------111000 and 24'----0----1--------111010 from group (3 3 16'0000010000001000). Merging pattern 24'----0----1--------101100 and 24'----0----1--------101110 from group (3 3 16'0000010000001000). Merging pattern 24'----0----1--------111100 and 24'----0----1--------111110 from group (3 3 16'0000010000001000). Merging pattern 24'----0----1--------111010 and 24'----0----1--------111000 from group (3 3 16'0000010000001000). Merging pattern 24'----0----1--------101110 and 24'----0----1--------101100 from group (3 3 16'0000010000001000). Merging pattern 24'----0----1--------111110 and 24'----0----1--------111100 from group (3 3 16'0000010000001000). Merging pattern 24'----0----1--------1110-0 and 24'----0----1--------1111-0 from group (3 3 16'0000010000001000). Merging pattern 24'----0----1--------1111-0 and 24'----0----1--------1110-0 from group (3 3 16'0000010000001000). Merging pattern 24'----------------11111000 and 24'----------------11111010 from group (4 1 16'0010000000100000). Merging pattern 24'----------------11101100 and 24'----------------11101110 from group (4 1 16'0010000000100000). Merging pattern 24'----------------11111100 and 24'----------------11111110 from group (4 1 16'0010000000100000). Merging pattern 24'----------------11111010 and 24'----------------11111000 from group (4 1 16'0010000000100000). Merging pattern 24'----------------11101110 and 24'----------------11101100 from group (4 1 16'0010000000100000). Merging pattern 24'----------------11111110 and 24'----------------11111100 from group (4 1 16'0010000000100000). Merging pattern 24'------------------111001 and 24'------------------111011 from group (4 1 16'0010000000100000). Merging pattern 24'------------------101101 and 24'------------------101111 from group (4 1 16'0010000000100000). Merging pattern 24'------------------111101 and 24'------------------111111 from group (4 1 16'0010000000100000). Merging pattern 24'------------------111011 and 24'------------------111001 from group (4 1 16'0010000000100000). Merging pattern 24'------------------101111 and 24'------------------101101 from group (4 1 16'0010000000100000). Merging pattern 24'------------------111111 and 24'------------------111101 from group (4 1 16'0010000000100000). Merging pattern 24'----------------111110-0 and 24'----------------111111-0 from group (4 1 16'0010000000100000). Merging pattern 24'----------------111111-0 and 24'----------------111110-0 from group (4 1 16'0010000000100000). Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (4 1 16'0010000000100000). Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (4 1 16'0010000000100000). Merging pattern 24'----------------10111000 and 24'----------------10111010 from group (4 4 16'0000000100100000). Merging pattern 24'----------------0-111000 and 24'----------------0-111010 from group (4 4 16'0000000100100000). Merging pattern 24'----------------10101100 and 24'----------------10101110 from group (4 4 16'0000000100100000). Merging pattern 24'----------------0-101100 and 24'----------------0-101110 from group (4 4 16'0000000100100000). Merging pattern 24'----------------10111100 and 24'----------------10111110 from group (4 4 16'0000000100100000). Merging pattern 24'----------------0-111100 and 24'----------------0-111110 from group (4 4 16'0000000100100000). Merging pattern 24'----------------10111010 and 24'----------------10111000 from group (4 4 16'0000000100100000). Merging pattern 24'----------------0-111010 and 24'----------------0-111000 from group (4 4 16'0000000100100000). Merging pattern 24'----------------10101110 and 24'----------------10101100 from group (4 4 16'0000000100100000). Merging pattern 24'----------------0-101110 and 24'----------------0-101100 from group (4 4 16'0000000100100000). Merging pattern 24'----------------10111110 and 24'----------------10111100 from group (4 4 16'0000000100100000). Merging pattern 24'----------------0-111110 and 24'----------------0-111100 from group (4 4 16'0000000100100000). Merging pattern 24'----------------101110-0 and 24'----------------101111-0 from group (4 4 16'0000000100100000). Merging pattern 24'----------------0-1110-0 and 24'----------------0-1111-0 from group (4 4 16'0000000100100000). Merging pattern 24'----------------101111-0 and 24'----------------101110-0 from group (4 4 16'0000000100100000). Merging pattern 24'----------------0-1111-0 and 24'----------------0-1110-0 from group (4 4 16'0000000100100000). Merging pattern 24'----------------11111000 and 24'----------------11111010 from group (5 1 16'0010000001000000). Merging pattern 24'----------------11101100 and 24'----------------11101110 from group (5 1 16'0010000001000000). Merging pattern 24'----------------11111100 and 24'----------------11111110 from group (5 1 16'0010000001000000). Merging pattern 24'----------------11111010 and 24'----------------11111000 from group (5 1 16'0010000001000000). Merging pattern 24'----------------11101110 and 24'----------------11101100 from group (5 1 16'0010000001000000). Merging pattern 24'----------------11111110 and 24'----------------11111100 from group (5 1 16'0010000001000000). Merging pattern 24'------------------111001 and 24'------------------111011 from group (5 1 16'0010000001000000). Merging pattern 24'------------------101101 and 24'------------------101111 from group (5 1 16'0010000001000000). Merging pattern 24'------------------111101 and 24'------------------111111 from group (5 1 16'0010000001000000). Merging pattern 24'------------------111011 and 24'------------------111001 from group (5 1 16'0010000001000000). Merging pattern 24'------------------101111 and 24'------------------101101 from group (5 1 16'0010000001000000). Merging pattern 24'------------------111111 and 24'------------------111101 from group (5 1 16'0010000001000000). Merging pattern 24'----------------111110-0 and 24'----------------111111-0 from group (5 1 16'0010000001000000). Merging pattern 24'----------------111111-0 and 24'----------------111110-0 from group (5 1 16'0010000001000000). Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (5 1 16'0010000001000000). Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (5 1 16'0010000001000000). Merging pattern 24'----------------10111000 and 24'----------------10111010 from group (5 5 16'0000000011000000). Merging pattern 24'----------------0-111000 and 24'----------------0-111010 from group (5 5 16'0000000011000000). Merging pattern 24'----------------10101100 and 24'----------------10101110 from group (5 5 16'0000000011000000). Merging pattern 24'----------------0-101100 and 24'----------------0-101110 from group (5 5 16'0000000011000000). Merging pattern 24'----------------10111100 and 24'----------------10111110 from group (5 5 16'0000000011000000). Merging pattern 24'----------------0-111100 and 24'----------------0-111110 from group (5 5 16'0000000011000000). Merging pattern 24'----------------10111010 and 24'----------------10111000 from group (5 5 16'0000000011000000). Merging pattern 24'----------------0-111010 and 24'----------------0-111000 from group (5 5 16'0000000011000000). Merging pattern 24'----------------10101110 and 24'----------------10101100 from group (5 5 16'0000000011000000). Merging pattern 24'----------------0-101110 and 24'----------------0-101100 from group (5 5 16'0000000011000000). Merging pattern 24'----------------10111110 and 24'----------------10111100 from group (5 5 16'0000000011000000). Merging pattern 24'----------------0-111110 and 24'----------------0-111100 from group (5 5 16'0000000011000000). Merging pattern 24'----------------101110-0 and 24'----------------101111-0 from group (5 5 16'0000000011000000). Merging pattern 24'----------------0-1110-0 and 24'----------------0-1111-0 from group (5 5 16'0000000011000000). Merging pattern 24'----------------101111-0 and 24'----------------101110-0 from group (5 5 16'0000000011000000). Merging pattern 24'----------------0-1111-0 and 24'----------------0-1110-0 from group (5 5 16'0000000011000000). Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$15184. Removing unused input signal $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$7475_Y. Optimizing FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core'. 12.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \mgmt_core.. Removed 117 unused cells and 117 unused wires. 12.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core'. Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [0]. Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [1]. Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [2]. Optimizing FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core'. Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [0]. Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [1]. Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [2]. Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [3]. Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [4]. Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [5]. Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [6]. Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [7]. Optimizing FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core'. Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [0]. Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [1]. Optimizing FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core'. Removing unused output signal $flatten\soc.\cpu.$0\state[1:0] [0]. Removing unused output signal $flatten\soc.\cpu.$0\state[1:0] [1]. Optimizing FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core'. Removing unused output signal $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] [0]. Removing unused output signal $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] [1]. Optimizing FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core'. Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [0]. Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [1]. Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [2]. Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [3]. 12.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 101 -> 1---- Recoding FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 10000000 -> -----1 01000000 -> ----1- 00100000 -> ---1-- 00001000 -> --1--- 00000010 -> -1---- 00000001 -> 1----- Recoding FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- Recoding FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> ------------1 1000 -> -----------1- 0100 -> ----------1-- 1100 -> ---------1--- 0010 -> --------1---- 1010 -> -------1----- 0110 -> ------1------ 0001 -> -----1------- 1001 -> ----1-------- 0101 -> ---1--------- 0011 -> --1---------- 1011 -> -1----------- 0111 -> 1------------ 12.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\housekeeping.U1.state$15197' from module `mgmt_core': ------------------------------------- Information on FSM $fsm$\housekeeping.U1.state$15197 (\housekeeping.U1.state): Number of input signals: 9 Number of output signals: 5 Number of state bits: 5 Input signals: 0: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:429$3019_Y 1: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018_Y 2: $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017_Y 3: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016_Y 4: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:382$3006_Y 5: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:369$3005_Y 6: \housekeeping.U1.pre_pass_thru_user 7: \housekeeping.U1.pre_pass_thru_mgmt 8: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030_Y Output signals: 0: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y 1: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3009_Y 2: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3008_Y 3: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y 4: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y State encoding: 0: 5'----1 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 9'---000000 -> 0 5'00001 1: 0 9'---0-0001 -> 0 5'00001 2: 0 9'---0-001- -> 0 5'00001 3: 0 9'---0-01-- -> 0 5'00001 4: 0 9'---0-1--- -> 0 5'00001 5: 0 9'---1----- -> 0 5'00001 6: 0 9'-01010000 -> 1 5'00001 7: 0 9'-00010000 -> 3 5'00001 8: 0 9'-1-010000 -> 4 5'00001 9: 1 9'--------- -> 1 5'00010 10: 2 9'1---1---- -> 0 5'01000 11: 2 9'----0---- -> 2 5'01000 12: 2 9'0---1---- -> 2 5'01000 13: 3 9'----1---- -> 2 5'10000 14: 3 9'----0---- -> 3 5'10000 15: 4 9'--------- -> 4 5'00100 ------------------------------------- FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `mgmt_core': ------------------------------------- Information on FSM $fsm$\soc.cpu.picorv32_core.cpu_state$15204 (\soc.cpu.picorv32_core.cpu_state): Number of input signals: 22 Number of output signals: 8 Number of state bits: 6 Input signals: 0: \soc.cpu.wb_rst_i 1: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$7529_Y 2: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7522_Y 3: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$7519_Y 4: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7515_Y 5: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$7512_Y 6: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$7497_Y 7: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y 8: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y 9: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$7433_Y 10: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$7429_Y 11: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$7416_Y 12: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$7408_Y 13: \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu 14: \soc.cpu.picorv32_core.is_sb_sh_sw 15: \soc.cpu.picorv32_core.decoder_trigger 16: \soc.cpu.picorv32_core.instr_trap 17: \soc.cpu.picorv32_core.instr_jal 18: \soc.cpu.picorv32_core.mem_done 19: \soc.cpu.picorv32_core.pcpi_int_ready 20: $auto$opt_reduce.cc:134:opt_mux$15126 21: $auto$opt_reduce.cc:134:opt_mux$15128 Output signals: 0: $flatten\soc.\cpu.\picorv32_core.$procmux$7616_CMP 1: $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP 2: $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP 3: $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP 4: $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP 5: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP 6: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP 7: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y State encoding: 0: 6'-----1 1: 6'----1- 2: 6'---1-- 3: 6'--1--- 4: 6'-1---- 5: 6'1----- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 22'----------------10-000 -> 0 8'00000001 1: 0 22'----------------0---00 -> 0 8'00000001 2: 0 22'----------------101010 -> 0 8'00000001 3: 0 22'----------------0-1-10 -> 0 8'00000001 4: 0 22'----------------1011-0 -> 0 8'00000001 5: 0 22'----------------111--0 -> 0 8'00000001 6: 0 22'----------------11000- -> 0 8'00000001 7: 0 22'----------------1-010- -> 0 8'00000001 8: 0 22'------------------0-1- -> 0 8'00000001 9: 0 22'----------------10-001 -> 1 8'00000001 10: 0 22'----------------0---01 -> 1 8'00000001 11: 0 22'----------------101011 -> 1 8'00000001 12: 0 22'----------------0-1-11 -> 1 8'00000001 13: 0 22'----------------1011-1 -> 1 8'00000001 14: 0 22'----------------111--1 -> 1 8'00000001 15: 1 22'----------------11000- -> 0 8'10000000 16: 1 22'----------------1-010- -> 0 8'10000000 17: 1 22'------------------0-1- -> 0 8'10000000 18: 1 22'------0--00-----10-000 -> 1 8'10000000 19: 1 22'----1-1--00-----10-000 -> 1 8'10000000 20: 1 22'---------01-----10-000 -> 1 8'10000000 21: 1 22'---------1------10-000 -> 1 8'10000000 22: 1 22'------0--00-----0---00 -> 1 8'10000000 23: 1 22'----1-1--00-----0---00 -> 1 8'10000000 24: 1 22'---------01-----0---00 -> 1 8'10000000 25: 1 22'---------1------0---00 -> 1 8'10000000 26: 1 22'------0--00-----101010 -> 1 8'10000000 27: 1 22'----1-1--00-----101010 -> 1 8'10000000 28: 1 22'---------01-----101010 -> 1 8'10000000 29: 1 22'---------1------101010 -> 1 8'10000000 30: 1 22'------0--00-----0-1-10 -> 1 8'10000000 31: 1 22'----1-1--00-----0-1-10 -> 1 8'10000000 32: 1 22'---------01-----0-1-10 -> 1 8'10000000 33: 1 22'---------1------0-1-10 -> 1 8'10000000 34: 1 22'------0--00-----1011-0 -> 1 8'10000000 35: 1 22'----1-1--00-----1011-0 -> 1 8'10000000 36: 1 22'---------01-----1011-0 -> 1 8'10000000 37: 1 22'---------1------1011-0 -> 1 8'10000000 38: 1 22'------0--00-----111--0 -> 1 8'10000000 39: 1 22'----1-1--00-----111--0 -> 1 8'10000000 40: 1 22'---------01-----111--0 -> 1 8'10000000 41: 1 22'---------1------111--0 -> 1 8'10000000 42: 1 22'----------------10-001 -> 1 8'10000000 43: 1 22'----------------0---01 -> 1 8'10000000 44: 1 22'----------------101011 -> 1 8'10000000 45: 1 22'----------------0-1-11 -> 1 8'10000000 46: 1 22'----------------1011-1 -> 1 8'10000000 47: 1 22'----------------111--1 -> 1 8'10000000 48: 1 22'----0-1--00-----10-000 -> 2 8'10000000 49: 1 22'----0-1--00-----0---00 -> 2 8'10000000 50: 1 22'----0-1--00-----101010 -> 2 8'10000000 51: 1 22'----0-1--00-----0-1-10 -> 2 8'10000000 52: 1 22'----0-1--00-----1011-0 -> 2 8'10000000 53: 1 22'----0-1--00-----111--0 -> 2 8'10000000 54: 2 22'--0--1-----10---10-000 -> 0 8'00000010 55: 2 22'--0--1-----10---0---00 -> 0 8'00000010 56: 2 22'--0--1-----10---101010 -> 0 8'00000010 57: 2 22'--0--1-----10---0-1-10 -> 0 8'00000010 58: 2 22'--0--1-----10---1011-0 -> 0 8'00000010 59: 2 22'--0--1-----10---111--0 -> 0 8'00000010 60: 2 22'----------------11000- -> 0 8'00000010 61: 2 22'----------------1-010- -> 0 8'00000010 62: 2 22'------------------0-1- -> 0 8'00000010 63: 2 22'--0--1-----11---10-000 -> 1 8'00000010 64: 2 22'--1--1----------10-000 -> 1 8'00000010 65: 2 22'-1--------------10-000 -> 1 8'00000010 66: 2 22'--0--1-----11---0---00 -> 1 8'00000010 67: 2 22'--1--1----------0---00 -> 1 8'00000010 68: 2 22'-1--------------0---00 -> 1 8'00000010 69: 2 22'--0--1-----11---101010 -> 1 8'00000010 70: 2 22'--1--1----------101010 -> 1 8'00000010 71: 2 22'-1--------------101010 -> 1 8'00000010 72: 2 22'--0--1-----11---0-1-10 -> 1 8'00000010 73: 2 22'--1--1----------0-1-10 -> 1 8'00000010 74: 2 22'-1--------------0-1-10 -> 1 8'00000010 75: 2 22'--0--1-----11---1011-0 -> 1 8'00000010 76: 2 22'--1--1----------1011-0 -> 1 8'00000010 77: 2 22'-1--------------1011-0 -> 1 8'00000010 78: 2 22'--0--1-----11---111--0 -> 1 8'00000010 79: 2 22'--1--1----------111--0 -> 1 8'00000010 80: 2 22'-1--------------111--0 -> 1 8'00000010 81: 2 22'----------------10-001 -> 1 8'00000010 82: 2 22'----------------0---01 -> 1 8'00000010 83: 2 22'----------------101011 -> 1 8'00000010 84: 2 22'----------------0-1-11 -> 1 8'00000010 85: 2 22'----------------1011-1 -> 1 8'00000010 86: 2 22'----------------111--1 -> 1 8'00000010 87: 2 22'--0--1-----0----10-000 -> 2 8'00000010 88: 2 22'--0--1-----0----0---00 -> 2 8'00000010 89: 2 22'--0--1-----0----101010 -> 2 8'00000010 90: 2 22'--0--1-----0----0-1-10 -> 2 8'00000010 91: 2 22'--0--1-----0----1011-0 -> 2 8'00000010 92: 2 22'--0--1-----0----111--0 -> 2 8'00000010 93: 2 22'00---0-0-----0--10-000 -> 3 8'00000010 94: 2 22'1---------------10-000 -> 3 8'00000010 95: 2 22'00---0-0-----0--0---00 -> 3 8'00000010 96: 2 22'1---------------0---00 -> 3 8'00000010 97: 2 22'00---0-0-----0--101010 -> 3 8'00000010 98: 2 22'1---------------101010 -> 3 8'00000010 99: 2 22'00---0-0-----0--0-1-10 -> 3 8'00000010 100: 2 22'1---------------0-1-10 -> 3 8'00000010 101: 2 22'00---0-0-----0--1011-0 -> 3 8'00000010 102: 2 22'1---------------1011-0 -> 3 8'00000010 103: 2 22'00---0-0-----0--111--0 -> 3 8'00000010 104: 2 22'1---------------111--0 -> 3 8'00000010 105: 2 22'00-----1-----0--10-000 -> 4 8'00000010 106: 2 22'00-----1-----0--0---00 -> 4 8'00000010 107: 2 22'00-----1-----0--101010 -> 4 8'00000010 108: 2 22'00-----1-----0--0-1-10 -> 4 8'00000010 109: 2 22'00-----1-----0--1011-0 -> 4 8'00000010 110: 2 22'00-----1-----0--111--0 -> 4 8'00000010 111: 2 22'-------------1--10-000 -> 5 8'00000010 112: 2 22'-------------1--0---00 -> 5 8'00000010 113: 2 22'-------------1--101010 -> 5 8'00000010 114: 2 22'-------------1--0-1-10 -> 5 8'00000010 115: 2 22'-------------1--1011-0 -> 5 8'00000010 116: 2 22'-------------1--111--0 -> 5 8'00000010 117: 3 22'----------------11000- -> 0 8'00001000 118: 3 22'----------------1-010- -> 0 8'00001000 119: 3 22'------------------0-1- -> 0 8'00001000 120: 3 22'--------0-------10-000 -> 1 8'00001000 121: 3 22'---1----1-------10-000 -> 1 8'00001000 122: 3 22'--------0-------0---00 -> 1 8'00001000 123: 3 22'---1----1-------0---00 -> 1 8'00001000 124: 3 22'--------0-------101010 -> 1 8'00001000 125: 3 22'---1----1-------101010 -> 1 8'00001000 126: 3 22'--------0-------0-1-10 -> 1 8'00001000 127: 3 22'---1----1-------0-1-10 -> 1 8'00001000 128: 3 22'--------0-------1011-0 -> 1 8'00001000 129: 3 22'---1----1-------1011-0 -> 1 8'00001000 130: 3 22'--------0-------111--0 -> 1 8'00001000 131: 3 22'---1----1-------111--0 -> 1 8'00001000 132: 3 22'----------------10-001 -> 1 8'00001000 133: 3 22'----------------0---01 -> 1 8'00001000 134: 3 22'----------------101011 -> 1 8'00001000 135: 3 22'----------------0-1-11 -> 1 8'00001000 136: 3 22'----------------1011-1 -> 1 8'00001000 137: 3 22'----------------111--1 -> 1 8'00001000 138: 3 22'---0----1-------10-000 -> 3 8'00001000 139: 3 22'---0----1-------0---00 -> 3 8'00001000 140: 3 22'---0----1-------101010 -> 3 8'00001000 141: 3 22'---0----1-------0-1-10 -> 3 8'00001000 142: 3 22'---0----1-------1011-0 -> 3 8'00001000 143: 3 22'---0----1-------111--0 -> 3 8'00001000 144: 4 22'----------------11000- -> 0 8'00100000 145: 4 22'----------------1-010- -> 0 8'00100000 146: 4 22'------------------0-1- -> 0 8'00100000 147: 4 22'--------------1110-000 -> 1 8'00100000 148: 4 22'--------------110---00 -> 1 8'00100000 149: 4 22'--------------11101010 -> 1 8'00100000 150: 4 22'--------------110-1-10 -> 1 8'00100000 151: 4 22'--------------111011-0 -> 1 8'00100000 152: 4 22'--------------11111--0 -> 1 8'00100000 153: 4 22'----------------10-001 -> 1 8'00100000 154: 4 22'----------------0---01 -> 1 8'00100000 155: 4 22'----------------101011 -> 1 8'00100000 156: 4 22'----------------0-1-11 -> 1 8'00100000 157: 4 22'----------------1011-1 -> 1 8'00100000 158: 4 22'----------------111--1 -> 1 8'00100000 159: 4 22'--------------1010-000 -> 4 8'00100000 160: 4 22'--------------0-10-000 -> 4 8'00100000 161: 4 22'--------------100---00 -> 4 8'00100000 162: 4 22'--------------0-0---00 -> 4 8'00100000 163: 4 22'--------------10101010 -> 4 8'00100000 164: 4 22'--------------0-101010 -> 4 8'00100000 165: 4 22'--------------100-1-10 -> 4 8'00100000 166: 4 22'--------------0-0-1-10 -> 4 8'00100000 167: 4 22'--------------101011-0 -> 4 8'00100000 168: 4 22'--------------0-1011-0 -> 4 8'00100000 169: 4 22'--------------10111--0 -> 4 8'00100000 170: 4 22'--------------0-111--0 -> 4 8'00100000 171: 5 22'----------------11000- -> 0 8'01000000 172: 5 22'----------------1-010- -> 0 8'01000000 173: 5 22'------------------0-1- -> 0 8'01000000 174: 5 22'--------------1110-000 -> 1 8'01000000 175: 5 22'--------------110---00 -> 1 8'01000000 176: 5 22'--------------11101010 -> 1 8'01000000 177: 5 22'--------------110-1-10 -> 1 8'01000000 178: 5 22'--------------111011-0 -> 1 8'01000000 179: 5 22'--------------11111--0 -> 1 8'01000000 180: 5 22'----------------10-001 -> 1 8'01000000 181: 5 22'----------------0---01 -> 1 8'01000000 182: 5 22'----------------101011 -> 1 8'01000000 183: 5 22'----------------0-1-11 -> 1 8'01000000 184: 5 22'----------------1011-1 -> 1 8'01000000 185: 5 22'----------------111--1 -> 1 8'01000000 186: 5 22'--------------1010-000 -> 5 8'01000000 187: 5 22'--------------0-10-000 -> 5 8'01000000 188: 5 22'--------------100---00 -> 5 8'01000000 189: 5 22'--------------0-0---00 -> 5 8'01000000 190: 5 22'--------------10101010 -> 5 8'01000000 191: 5 22'--------------0-101010 -> 5 8'01000000 192: 5 22'--------------100-1-10 -> 5 8'01000000 193: 5 22'--------------0-0-1-10 -> 5 8'01000000 194: 5 22'--------------101011-0 -> 5 8'01000000 195: 5 22'--------------0-1011-0 -> 5 8'01000000 196: 5 22'--------------10111--0 -> 5 8'01000000 197: 5 22'--------------0-111--0 -> 5 8'01000000 ------------------------------------- FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `mgmt_core': ------------------------------------- Information on FSM $fsm$\soc.cpu.picorv32_core.mem_wordsize$15214 (\soc.cpu.picorv32_core.mem_wordsize): Number of input signals: 13 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \soc.cpu.wb_rst_i 1: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP 2: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP 3: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$7502_Y 4: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$7501_Y 5: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y 6: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y 7: \soc.cpu.picorv32_core.instr_sw 8: \soc.cpu.picorv32_core.instr_sh 9: \soc.cpu.picorv32_core.instr_sb 10: \soc.cpu.picorv32_core.instr_lw 11: \soc.cpu.picorv32_core.mem_do_wdata 12: \soc.cpu.picorv32_core.mem_do_rdata Output signals: 0: $flatten\soc.\cpu.\picorv32_core.$procmux$10355_CMP 1: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7520_Y 2: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7513_Y State encoding: 0: 3'--1 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 13'------0---000 -> 0 3'100 1: 0 13'-------0---10 -> 0 3'100 2: 0 13'-0---1-1---10 -> 0 3'100 3: 0 13'-1-----1---10 -> 0 3'100 4: 0 13'-------0--1-0 -> 0 3'100 5: 0 13'0-1----1--1-0 -> 0 3'100 6: 0 13'1------1--1-0 -> 0 3'100 7: 0 13'------1-----0 -> 0 3'100 8: 0 13'------------1 -> 0 3'100 9: 0 13'-0-1---1---10 -> 1 3'100 10: 0 13'0------11-1-0 -> 1 3'100 11: 0 13'-0--1--1---10 -> 2 3'100 12: 0 13'0------1-11-0 -> 2 3'100 13: 1 13'-0---1-1---10 -> 0 3'001 14: 1 13'0-1----1--1-0 -> 0 3'001 15: 1 13'------1-----0 -> 0 3'001 16: 1 13'------0---000 -> 1 3'001 17: 1 13'-------0---10 -> 1 3'001 18: 1 13'-0-1---1---10 -> 1 3'001 19: 1 13'-1-----1---10 -> 1 3'001 20: 1 13'0------11-1-0 -> 1 3'001 21: 1 13'-------0--1-0 -> 1 3'001 22: 1 13'1------1--1-0 -> 1 3'001 23: 1 13'------------1 -> 1 3'001 24: 1 13'-0--1--1---10 -> 2 3'001 25: 1 13'0------1-11-0 -> 2 3'001 26: 2 13'-0---1-1---10 -> 0 3'010 27: 2 13'0-1----1--1-0 -> 0 3'010 28: 2 13'------1-----0 -> 0 3'010 29: 2 13'-0-1---1---10 -> 1 3'010 30: 2 13'0------11-1-0 -> 1 3'010 31: 2 13'------0---000 -> 2 3'010 32: 2 13'-------0---10 -> 2 3'010 33: 2 13'-0--1--1---10 -> 2 3'010 34: 2 13'-1-----1---10 -> 2 3'010 35: 2 13'0------1-11-0 -> 2 3'010 36: 2 13'-------0--1-0 -> 2 3'010 37: 2 13'1------1--1-0 -> 2 3'010 38: 2 13'------------1 -> 2 3'010 ------------------------------------- FSM `$fsm$\soc.cpu.state$15219' from module `mgmt_core': ------------------------------------- Information on FSM $fsm$\soc.cpu.state$15219 (\soc.cpu.state): Number of input signals: 3 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \soc.cpu.wb_rst_i 1: \soc.cpu.wbm_ack_i 2: \soc.cpu.picorv32_core.mem_valid Output signals: 0: $flatten\soc.\cpu.$procmux$12350_CMP 1: $flatten\soc.\cpu.$procmux$12354_CMP 2: $flatten\soc.\cpu.$procmux$12441_CMP State encoding: 0: 3'--1 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'0-0 -> 0 3'010 1: 0 3'--1 -> 0 3'010 2: 0 3'1-0 -> 2 3'010 3: 1 3'--- -> 0 3'100 4: 2 3'--1 -> 0 3'001 5: 2 3'-10 -> 1 3'001 6: 2 3'-00 -> 2 3'001 ------------------------------------- FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `mgmt_core': ------------------------------------- Information on FSM $fsm$\soc.simple_spi_master_inst.spi_master.state$15224 (\soc.simple_spi_master_inst.spi_master.state): Number of input signals: 2 Number of output signals: 4 Number of state bits: 4 Input signals: 0: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:305$1398_Y 1: \soc.simple_spi_master_inst.spi_master.w_latched Output signals: 0: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y 1: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y 2: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y 3: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y State encoding: 0: 4'---1 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 2'0- -> 0 4'0010 1: 0 2'1- -> 2 4'0010 2: 1 2'-0 -> 2 4'0100 3: 1 2'-1 -> 3 4'0100 4: 2 2'-- -> 1 4'1000 5: 3 2'-- -> 0 4'0001 ------------------------------------- FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `mgmt_core': ------------------------------------- Information on FSM $fsm$\soc.spimemio.spimemio.state$15230 (\soc.spimemio.spimemio.state): Number of input signals: 8 Number of output signals: 13 Number of state bits: 13 Input signals: 0: \soc.spimemio.spimemio.xfer.din_ready 1: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:512$1234_Y 2: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:472$1230_Y 3: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:373$1216_Y 4: $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1137_Y 5: \soc.spimemio.spimemio.config_cont 6: \soc.spimemio.spimemio.jump 7: \soc.spimemio.spimemio.dout_valid Output signals: 0: $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP 1: $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP 2: $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP 3: $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP 4: $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP 5: $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP 6: $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP 7: $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP 8: $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP 9: $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP 10: $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP 11: $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP 12: $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP State encoding: 0: 13'------------1 1: 13'-----------1- 2: 13'----------1-- 3: 13'---------1--- 4: 13'--------1---- 5: 13'-------1----- 6: 13'------1------ 7: 13'-----1------- 8: 13'----1-------- 9: 13'---1--------- 10: 13'--1---------- 11: 13'-1----------- 12: 13'1------------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 8'-0--0--0 -> 0 13'0000000000001 1: 0 8'----1--- -> 0 13'0000000000001 2: 0 8'-10-0--- -> 2 13'0000000000001 3: 0 8'-0--0--1 -> 7 13'0000000000001 4: 0 8'-11-0--- -> 9 13'0000000000001 5: 1 8'----1--- -> 0 13'0000000100000 6: 1 8'-0--0--0 -> 1 13'0000000100000 7: 1 8'-10-0--- -> 2 13'0000000100000 8: 1 8'-0--0--1 -> 8 13'0000000100000 9: 1 8'-11-0--- -> 9 13'0000000100000 10: 2 8'----1--- -> 0 13'0010000000000 11: 2 8'-0--0--0 -> 2 13'0010000000000 12: 2 8'-10-0--- -> 2 13'0010000000000 13: 2 8'-0--0--1 -> 9 13'0010000000000 14: 2 8'-11-0--- -> 9 13'0010000000000 15: 3 8'----1--- -> 0 13'0001000000000 16: 3 8'-10-0--- -> 2 13'0001000000000 17: 3 8'-0--0-10 -> 3 13'0001000000000 18: 3 8'-0--0-0- -> 3 13'0001000000000 19: 3 8'-0--0-11 -> 8 13'0001000000000 20: 3 8'-11-0--- -> 9 13'0001000000000 21: 4 8'----1--- -> 0 13'0000000000010 22: 4 8'-10-0--- -> 2 13'0000000000010 23: 4 8'-0--0--0 -> 4 13'0000000000010 24: 4 8'-11-0--- -> 9 13'0000000000010 25: 4 8'-0--0--1 -> 10 13'0000000000010 26: 5 8'----1--- -> 0 13'0000010000000 27: 5 8'-10-0--- -> 2 13'0000010000000 28: 5 8'-0--0--0 -> 5 13'0000010000000 29: 5 8'-11-0--- -> 9 13'0000010000000 30: 5 8'-0--0--1 -> 11 13'0000010000000 31: 6 8'----1--- -> 0 13'0000000001000 32: 6 8'-10-0--- -> 2 13'0000000001000 33: 6 8'-0--0--0 -> 6 13'0000000001000 34: 6 8'-11-0--- -> 9 13'0000000001000 35: 6 8'-0--0--1 -> 12 13'0000000001000 36: 7 8'----1--- -> 0 13'0100000000000 37: 7 8'-10-0--- -> 2 13'0100000000000 38: 7 8'10--0--- -> 4 13'0100000000000 39: 7 8'00--0--- -> 7 13'0100000000000 40: 7 8'-11-0--- -> 9 13'0100000000000 41: 8 8'----1--- -> 0 13'0000001000000 42: 8 8'-10-0--- -> 2 13'0000001000000 43: 8 8'-0--0--1 -> 5 13'0000001000000 44: 8 8'-0--0--0 -> 8 13'0000001000000 45: 8 8'-11-0--- -> 9 13'0000001000000 46: 9 8'----1--- -> 0 13'0000000000100 47: 9 8'-10-0--- -> 2 13'0000000000100 48: 9 8'-0-10--1 -> 6 13'0000000000100 49: 9 8'-0-10--0 -> 9 13'0000000000100 50: 9 8'-0-00--- -> 9 13'0000000000100 51: 9 8'-11-0--- -> 9 13'0000000000100 52: 10 8'----1--- -> 0 13'1000000000000 53: 10 8'-10-0--- -> 2 13'1000000000000 54: 10 8'10--0--- -> 2 13'1000000000000 55: 10 8'-11-0--- -> 9 13'1000000000000 56: 10 8'00--0--- -> 10 13'1000000000000 57: 11 8'----1--- -> 0 13'0000100000000 58: 11 8'-10-0--- -> 2 13'0000100000000 59: 11 8'-0--0--1 -> 3 13'0000100000000 60: 11 8'-11-0--- -> 9 13'0000100000000 61: 11 8'-0--0--0 -> 11 13'0000100000000 62: 12 8'----1--- -> 0 13'0000000010000 63: 12 8'-0--01-1 -> 1 13'0000000010000 64: 12 8'-10-0--- -> 2 13'0000000010000 65: 12 8'-0--00-1 -> 8 13'0000000010000 66: 12 8'-11-0--- -> 9 13'0000000010000 67: 12 8'-0--0--0 -> 12 13'0000000010000 ------------------------------------- 12.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core'. Mapping FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core'. Mapping FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core'. Mapping FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core'. Mapping FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core'. Mapping FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core'. 12.9. Executing OPT pass (performing simple optimizations). 12.9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module mgmt_core. 12.9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\mgmt_core'. Removed a total of 46 cells. 12.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \mgmt_core.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/7 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8267. dead port 4/7 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8267. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8270. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8270. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8280. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8280. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8321. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8321. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8324. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8324. dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8326. dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8326. dead port 3/6 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8514. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8530. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8530. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8796. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8796. dead port 1/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8798. dead port 2/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8798. dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808. dead port 2/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808. dead port 3/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808. dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9005. dead port 3/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9030. dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039. dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039. dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039. dead port 4/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039. dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044. dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044. dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044. dead port 4/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9048. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9048. dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9051. dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9051. Removed 36 multiplexer ports. 12.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \mgmt_core. New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15119: { \soc.cpu.picorv32_core.cpu_state [5:4] \soc.cpu.picorv32_core.cpu_state [2:0] } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15117: \soc.cpu.picorv32_core.cpu_state [4:0] New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15115: { \soc.cpu.picorv32_core.cpu_state [5] \soc.cpu.picorv32_core.cpu_state [3:0] } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15113: { \soc.cpu.picorv32_core.cpu_state [5:2] \soc.cpu.picorv32_core.cpu_state [0] } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15111: { \soc.cpu.picorv32_core.cpu_state [5:3] \soc.cpu.picorv32_core.cpu_state [0] } Optimizing cells in module \mgmt_core. Performed a total of 5 changes. 12.9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\mgmt_core'. Removed a total of 0 cells. 12.9.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\soc.\wb_bridge.$procdff$14990 ($dff) from module mgmt_core (D = $flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:60$4514_Y, Q = \soc.wb_bridge.wb_ack_read, rval = 2'00). Adding SRST signal on $flatten\soc.\wb_bridge.$procdff$14989 ($dff) from module mgmt_core (D = $flatten\soc.\wb_bridge.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:59$4510_Y, Q = \soc.wb_bridge.wb_ack_o, rval = 2'00). Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14819 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11093_Y, Q = \soc.sysctrl.sysctrl.irq_8_inputsrc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16182 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.sysctrl.sysctrl.irq_8_inputsrc). Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14818 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11111_Y, Q = \soc.sysctrl.sysctrl.irq_7_inputsrc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16192 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.irq_7_inputsrc). Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14817 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11127_Y, Q = \soc.sysctrl.sysctrl.trap_output_dest, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16202 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.trap_output_dest). Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14816 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11140_Y, Q = \soc.sysctrl.sysctrl.clk2_output_dest, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16210 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.sysctrl.sysctrl.clk2_output_dest). Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14815 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11153_Y, Q = \soc.sysctrl.sysctrl.clk1_output_dest, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16216 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.clk1_output_dest). Adding EN signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14814 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11158_Y, Q = \soc.sysctrl.sysctrl.iomem_ready). Adding EN signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14813 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11172_Y, Q = \soc.sysctrl.sysctrl.iomem_rdata). Adding SRST signal on $auto$opt_dff.cc:764:run$16229 ($dffe) from module mgmt_core (D = 28'xxxxxxxxxxxxxxxxxxxxxxxxxxxx, Q = \soc.sysctrl.sysctrl.iomem_rdata [31:4], rval = 28'0000000000000000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core. Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14957 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.fetch, Q = \soc.spimemio.spimemio.xfer.last_fetch, rval = 1'1). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14956 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.next_fetch, Q = \soc.spimemio.spimemio.xfer.fetch, rval = 1'1). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14955 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13333_Y, Q = \soc.spimemio.spimemio.xfer.xfer_tag, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$16239 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_tag, Q = \soc.spimemio.spimemio.xfer.xfer_tag). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14954 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13338_Y, Q = \soc.spimemio.spimemio.xfer.xfer_rd, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16241 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_rd, Q = \soc.spimemio.spimemio.xfer.xfer_rd). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14953 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13343_Y, Q = \soc.spimemio.spimemio.xfer.xfer_qspi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16243 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_qspi, Q = \soc.spimemio.spimemio.xfer.xfer_qspi). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14951 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13356_Y, Q = \soc.spimemio.spimemio.xfer.dummy_count, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$16245 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13356_Y, Q = \soc.spimemio.spimemio.xfer.dummy_count). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14950 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13366_Y [3], Q = \soc.spimemio.spimemio.xfer.count [3], rval = 1'0). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14950 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13364_Y [2:0], Q = \soc.spimemio.spimemio.xfer.count [2:0], rval = 3'000). Adding EN signal on $auto$opt_dff.cc:702:run$16252 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$2\next_count[3:0] [2:0], Q = \soc.spimemio.spimemio.xfer.count [2:0]). Adding EN signal on $auto$opt_dff.cc:702:run$16249 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13366_Y [3], Q = \soc.spimemio.spimemio.xfer.count [3]). Adding EN signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14949 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$2\next_ibuffer[7:0], Q = \soc.spimemio.spimemio.xfer.ibuffer). Adding EN signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14948 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13384_Y, Q = \soc.spimemio.spimemio.xfer.obuffer). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14947 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13389_Y, Q = \soc.spimemio.spimemio.xfer.xfer_ddr, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16305 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.din_ddr, Q = \soc.spimemio.spimemio.xfer.xfer_ddr). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14946 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13394_Y, Q = \soc.spimemio.spimemio.xfer.xfer_dspi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16307 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.din_dspi, Q = \soc.spimemio.spimemio.xfer.xfer_dspi). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14945 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13402_Y, Q = \soc.spimemio.spimemio.xfer.flash_clk, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16311 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13402_Y, Q = \soc.spimemio.spimemio.xfer.flash_clk). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14944 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13409_Y, Q = \soc.spimemio.spimemio.xfer.flash_csb, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$16315 ($sdff) from module mgmt_core (D = 1'0, Q = \soc.spimemio.spimemio.xfer.flash_csb). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14988 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13941_Y, Q = \soc.spimemio.spimemio.config_do, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$16317 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3:0], Q = \soc.spimemio.spimemio.config_do). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14987 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13946_Y, Q = \soc.spimemio.spimemio.config_clk, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16319 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [4], Q = \soc.spimemio.spimemio.config_clk). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14986 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13951_Y, Q = \soc.spimemio.spimemio.config_csb, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16321 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [5], Q = \soc.spimemio.spimemio.config_csb). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14985 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13956_Y, Q = \soc.spimemio.spimemio.config_oe, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$16323 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [11:8], Q = \soc.spimemio.spimemio.config_oe). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14984 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13961_Y, Q = \soc.spimemio.spimemio.config_dummy, rval = 4'1000). Adding EN signal on $auto$opt_dff.cc:702:run$16325 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [19:16], Q = \soc.spimemio.spimemio.config_dummy). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14983 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13966_Y, Q = \soc.spimemio.spimemio.config_cont, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16327 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [20], Q = \soc.spimemio.spimemio.config_cont). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14982 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13971_Y, Q = \soc.spimemio.spimemio.config_qspi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16329 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [21], Q = \soc.spimemio.spimemio.config_qspi). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14981 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13976_Y, Q = \soc.spimemio.spimemio.config_ddr, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16331 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [22], Q = \soc.spimemio.spimemio.config_ddr). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14980 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13981_Y, Q = \soc.spimemio.spimemio.config_en, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$16333 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31], Q = \soc.spimemio.spimemio.config_en). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14979 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:244$1148_Y, Q = \soc.spimemio.spimemio.softreset, rval = 1'1). Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14974 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13718_Y, Q = \soc.spimemio.spimemio.rd_inc). Adding SRST signal on $auto$opt_dff.cc:764:run$16342 ($dffe) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13706_Y, Q = \soc.spimemio.spimemio.rd_inc, rval = 1'0). Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14973 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13725_Y, Q = \soc.spimemio.spimemio.rd_wait). Adding SRST signal on $auto$opt_dff.cc:764:run$16352 ($dffe) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13723_Y, Q = \soc.spimemio.spimemio.rd_wait, rval = 1'0). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14972 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13730_Y, Q = \soc.spimemio.spimemio.rd_valid, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16356 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.spimemio.spimemio.rd_valid). Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14971 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:388$1227_Y [23:0], Q = \soc.spimemio.spimemio.rd_addr). Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14970 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [23:16]). Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14970 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [15:8]). Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14970 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [7:0]). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14969 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13789_Y, Q = \soc.spimemio.spimemio.din_rd, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16380 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.spimemio.spimemio.din_rd). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14968 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13810_Y, Q = \soc.spimemio.spimemio.din_ddr, rval = 1'0). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14967 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13829_Y, Q = \soc.spimemio.spimemio.din_qspi, rval = 1'0). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14965 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13839_Y, Q = \soc.spimemio.spimemio.din_tag, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$16386 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13839_Y, Q = \soc.spimemio.spimemio.din_tag). Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14964 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858_Y, Q = \soc.spimemio.spimemio.din_data). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14963 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13746_Y, Q = \soc.spimemio.spimemio.din_valid, rval = 1'0). Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14962 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13696_Y, Q = \soc.spimemio.spimemio.xfer_resetn, rval = 1'0). Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14961 ($dff) from module mgmt_core (D = { \soc.spimemio.spimemio.xfer.ibuffer \soc.spimemio.spimemio.buffer }, Q = \soc.spimemio.spimemio.rdata). Adding SRST signal on $flatten\soc.\soc_mem.$procdff$14888 ($dff) from module mgmt_core (D = $flatten\soc.\soc_mem.$and$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:49$2164_Y, Q = \soc.soc_mem.wb_ack_read, rval = 1'0). Adding SRST signal on $flatten\soc.\soc_mem.$procdff$14887 ($dff) from module mgmt_core (D = $flatten\soc.\soc_mem.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:48$2160_Y, Q = \soc.soc_mem.wb_ack_o, rval = 1'0). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14943 ($dff) from module mgmt_core (D = { $flatten\soc.\simpleuart.\simpleuart.$procmux$13302_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$13307_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$13312_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$13317_Y }, Q = \soc.simpleuart.simpleuart.cfg_divider, rval = 1). Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simpleuart.simpleuart.cfg_divider [7:0]). Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.simpleuart.simpleuart.cfg_divider [15:8]). Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.simpleuart.simpleuart.cfg_divider [23:16]). Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.simpleuart.simpleuart.cfg_divider [31:24]). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14942 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13322_Y, Q = \soc.simpleuart.simpleuart.enabled, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16421 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.simpleuart.simpleuart.enabled). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14941 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13263_Y, Q = \soc.simpleuart.simpleuart.recv_buf_valid, rval = 1'0). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14940 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13271_Y, Q = \soc.simpleuart.simpleuart.recv_buf_data, rval = 8'00000000). Adding EN signal on $auto$opt_dff.cc:702:run$16424 ($sdff) from module mgmt_core (D = \soc.simpleuart.simpleuart.recv_pattern, Q = \soc.simpleuart.simpleuart.recv_buf_data). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14939 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13279_Y, Q = \soc.simpleuart.simpleuart.recv_pattern, rval = 8'00000000). Adding EN signal on $auto$opt_dff.cc:702:run$16428 ($sdff) from module mgmt_core (D = { \mgmt_in_data [5] \soc.simpleuart.simpleuart.recv_pattern [7:1] }, Q = \soc.simpleuart.simpleuart.recv_pattern). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14938 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13249_Y, Q = \soc.simpleuart.simpleuart.recv_divcnt, rval = 0). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14937 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13291_Y, Q = \soc.simpleuart.simpleuart.recv_state, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$16435 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13291_Y, Q = \soc.simpleuart.simpleuart.recv_state). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14936 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13219_Y, Q = \soc.simpleuart.simpleuart.send_dummy, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$16447 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13219_Y, Q = \soc.simpleuart.simpleuart.send_dummy). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14935 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328_Y, Q = \soc.simpleuart.simpleuart.send_divcnt, rval = 0). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14934 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13230_Y, Q = \soc.simpleuart.simpleuart.send_bitcnt, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$16454 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13230_Y, Q = \soc.simpleuart.simpleuart.send_bitcnt). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14933 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13235_Y [9], Q = \soc.simpleuart.simpleuart.send_pattern [9], rval = 1'1). Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14933 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13238_Y [8:0], Q = \soc.simpleuart.simpleuart.send_pattern [8:0], rval = 9'111111111). Adding EN signal on $auto$opt_dff.cc:702:run$16463 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13238_Y [8:0], Q = \soc.simpleuart.simpleuart.send_pattern [8:0]). Adding EN signal on $auto$opt_dff.cc:702:run$16460 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.simpleuart.simpleuart.send_pattern [9]). Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$16467 ($sdffe) from module mgmt_core. Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14932 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15], Q = \soc.simple_spi_master_inst.spi_master.hkconn). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14931 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [11], Q = \soc.simple_spi_master_inst.spi_master.mode). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14930 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12], Q = \soc.simple_spi_master_inst.spi_master.stream). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14929 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [14], Q = \soc.simple_spi_master_inst.spi_master.irqena). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14928 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [8], Q = \soc.simple_spi_master_inst.spi_master.mlb). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14927 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [9], Q = \soc.simple_spi_master_inst.spi_master.invcsb). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14926 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [10], Q = \soc.simple_spi_master_inst.spi_master.invsck). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14925 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simple_spi_master_inst.spi_master.prescaler). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14924 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [13], Q = \soc.simple_spi_master_inst.spi_master.enable). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14922 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\w_latched[0:0], Q = \soc.simple_spi_master_inst.spi_master.w_latched). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14921 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simple_spi_master_inst.spi_master.d_latched). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14919 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\nbit[2:0], Q = \soc.simple_spi_master_inst.spi_master.nbit). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14918 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\icsb[0:0], Q = \soc.simple_spi_master_inst.spi_master.icsb). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14917 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\done[0:0], Q = \soc.simple_spi_master_inst.spi_master.done). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14915 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$not$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:331$1406_Y, Q = \soc.simple_spi_master_inst.spi_master.hsck). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14912 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13041_Y, Q = \soc.simple_spi_master_inst.spi_master.rreg). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14911 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\treg[7:0], Q = \soc.simple_spi_master_inst.spi_master.treg). Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14910 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\isdo[0:0], Q = \soc.simple_spi_master_inst.spi_master.isdo). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14877 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11817_Y, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_ready, rval = 1'0). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14876 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11824_Y, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata, rval = 0). Adding EN signal on $auto$opt_dff.cc:702:run$16533 ($sdff) from module mgmt_core (D = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata_pre, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14875 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11797_Y, Q = \soc.mprj_ctrl.mprj_ctrl.xfer_ctrl, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$16541 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.mprj_ctrl.mprj_ctrl.xfer_ctrl). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14874 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11812_Y, Q = \soc.mprj_ctrl.mprj_ctrl.pwr_ctrl_out, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$16545 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3:0], Q = \soc.mprj_ctrl.mprj_ctrl.pwr_ctrl_out). Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14871 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11688_Y, Q = \soc.mprj_ctrl.mprj_ctrl.serial_data_staging). Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14870 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\xfer_state[1:0], Q = \soc.mprj_ctrl.mprj_ctrl.xfer_state). Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14869 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\pad_count[5:0], Q = \soc.mprj_ctrl.mprj_ctrl.pad_count). Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14868 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11744_Y, Q = \soc.mprj_ctrl.mprj_ctrl.xfer_count). Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14867 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\serial_resetn[0:0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_resetn). Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14866 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\serial_clock[0:0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_clock). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14865 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11612_Y, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [31:0], rval = 0). Adding EN signal on $auto$opt_dff.cc:702:run$16607 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [31:0]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14864 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11603_Y, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [37:32], rval = 6'000000). Adding EN signal on $auto$opt_dff.cc:702:run$16611 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [5:0], Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [37:32]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14863 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11594_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[0], rval = 13'1100000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16615 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[0]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14862 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11585_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[1], rval = 13'1100000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16619 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[1]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14861 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11576_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[2], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16623 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[2]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14860 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11567_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[3], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16627 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[3]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14859 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11558_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[4], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16631 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[4]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14858 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11549_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[5], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16635 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[5]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14857 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11540_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[6], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16639 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[6]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14856 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11531_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[7], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16643 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[7]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14855 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11522_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[8], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16647 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[8]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14854 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11513_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[9], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16651 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[9]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14853 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11504_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[10], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16655 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[10]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14852 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11495_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[11], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16659 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[11]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14851 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11486_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[12], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16663 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[12]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14850 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11477_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[13], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16667 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[13]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14849 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11468_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[14], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16671 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[14]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14848 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11459_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[15], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16675 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[15]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14847 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11450_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[16], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16679 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[16]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14846 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11441_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[17], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16683 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[17]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14845 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11432_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[18], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16687 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[18]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14844 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11423_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[19], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16691 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[19]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14843 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11414_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[20], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16695 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[20]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14842 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11405_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[21], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16699 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[21]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14841 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11396_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[22], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16703 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[22]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14840 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11387_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[23], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16707 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[23]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14839 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11378_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[24], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16711 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[24]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14838 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11369_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[25], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16715 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[25]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14837 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11360_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[26], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16719 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[26]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14836 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11351_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[27], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16723 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[27]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14835 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11342_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[28], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16727 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[28]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14834 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11333_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[29], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16731 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[29]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14833 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11324_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[30], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16735 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[30]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14832 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11315_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[31], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16739 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[31]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14831 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11306_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[32], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16743 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[32]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14830 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11297_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[33], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16747 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[33]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14829 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11288_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[34], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16751 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[34]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14828 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11279_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[35], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16755 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[35]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14827 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11270_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[36], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16759 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[36]). Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14826 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11261_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[37], rval = 13'0010000000011). Adding EN signal on $auto$opt_dff.cc:702:run$16763 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[37]). Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14812 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10420_Y $flatten\soc.\la.\la_ctrl.$procmux$10450_Y $flatten\soc.\la.\la_ctrl.$procmux$10480_Y $flatten\soc.\la.\la_ctrl.$procmux$10510_Y }, Q = \soc.la.la_ctrl.la_ena_3, rval = 32'11111111111111111111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_3 [7:0]). Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_3 [15:8]). Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_3 [23:16]). Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_3 [31:24]). Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14811 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$11042_Y $flatten\soc.\la.\la_ctrl.$procmux$10538_Y $flatten\soc.\la.\la_ctrl.$procmux$10566_Y $flatten\soc.\la.\la_ctrl.$procmux$10594_Y }, Q = \soc.la.la_ctrl.la_ena_2, rval = 32'11111111111111111111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_2 [7:0]). Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_2 [15:8]). Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_2 [23:16]). Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_2 [31:24]). Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14810 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10934_Y $flatten\soc.\la.\la_ctrl.$procmux$10619_Y $flatten\soc.\la.\la_ctrl.$procmux$10644_Y $flatten\soc.\la.\la_ctrl.$procmux$10669_Y }, Q = \soc.la.la_ctrl.la_ena_1, rval = 32'11111111111111111111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_1 [7:0]). Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_1 [15:8]). Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_1 [23:16]). Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_1 [31:24]). Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14809 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10956_Y $flatten\soc.\la.\la_ctrl.$procmux$10691_Y $flatten\soc.\la.\la_ctrl.$procmux$10713_Y $flatten\soc.\la.\la_ctrl.$procmux$10735_Y }, Q = \soc.la.la_ctrl.la_ena_0, rval = 32'11111111111111111111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_0 [7:0]). Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_0 [15:8]). Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_0 [23:16]). Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_0 [31:24]). Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14808 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10975_Y $flatten\soc.\la.\la_ctrl.$procmux$10754_Y $flatten\soc.\la.\la_ctrl.$procmux$10773_Y $flatten\soc.\la.\la_ctrl.$procmux$10792_Y }, Q = \soc.la.la_ctrl.la_data_3, rval = 0). Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_3 [7:0]). Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_3 [15:8]). Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_3 [23:16]). Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_3 [31:24]). Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14807 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10991_Y $flatten\soc.\la.\la_ctrl.$procmux$10808_Y $flatten\soc.\la.\la_ctrl.$procmux$10824_Y $flatten\soc.\la.\la_ctrl.$procmux$10840_Y }, Q = \soc.la.la_ctrl.la_data_2, rval = 0). Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_2 [7:0]). Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_2 [15:8]). Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_2 [23:16]). Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_2 [31:24]). Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14806 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$11004_Y $flatten\soc.\la.\la_ctrl.$procmux$10853_Y $flatten\soc.\la.\la_ctrl.$procmux$10866_Y $flatten\soc.\la.\la_ctrl.$procmux$10879_Y }, Q = \soc.la.la_ctrl.la_data_1, rval = 0). Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_1 [7:0]). Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_1 [15:8]). Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_1 [23:16]). Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_1 [31:24]). Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14805 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$11014_Y $flatten\soc.\la.\la_ctrl.$procmux$10889_Y $flatten\soc.\la.\la_ctrl.$procmux$10899_Y $flatten\soc.\la.\la_ctrl.$procmux$10909_Y }, Q = \soc.la.la_ctrl.la_data_0, rval = 0). Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_0 [7:0]). Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_0 [15:8]). Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_0 [23:16]). Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_0 [31:24]). Adding EN signal on $flatten\soc.\la.\la_ctrl.$procdff$14804 ($dff) from module mgmt_core (D = $flatten\soc.\la.\la_ctrl.$procmux$11047_Y, Q = \soc.la.la_ctrl.iomem_ready). Adding EN signal on $flatten\soc.\la.\la_ctrl.$procdff$14803 ($dff) from module mgmt_core (D = $flatten\soc.\la.\la_ctrl.$procmux$11073_Y, Q = \soc.la.la_ctrl.iomem_rdata). Adding EN signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14825 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11179_Y, Q = \soc.gpio_wb.gpio_ctrl.iomem_ready). Adding EN signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14824 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11193_Y, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata). Adding SRST signal on $auto$opt_dff.cc:764:run$17110 ($dffe) from module mgmt_core (D = 30'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata [31:2], rval = 30'000000000000000000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 28 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Setting constant 0-bit at position 29 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core. Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14823 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11213_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_pd, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$17114 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_pd). Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14822 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11229_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_pu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$17124 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_pu). Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14821 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11242_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_oeb, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$17132 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_oeb). Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14820 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11252_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$17138 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15022 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14157_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulhu, rval = 1'0). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15021 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14162_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulhsu, rval = 1'0). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15020 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14168_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulh, rval = 1'0). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15019 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14175_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mul, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15017 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14105_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_finish, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15016 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14116_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_waiting, rval = 1'1). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15015 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14122_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_counter). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15014 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14128_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rdx). Adding SRST signal on $auto$opt_dff.cc:764:run$17151 ($dffe) from module mgmt_core (D = { \soc.cpu.picorv32_core.pcpi_mul.next_rdx [60] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [56] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [52] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [48] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [44] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [40] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [36] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [32] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [28] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [24] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [20] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [16] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [12] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [8] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [4] }, Q = { \soc.cpu.picorv32_core.pcpi_mul.rdx [60] \soc.cpu.picorv32_core.pcpi_mul.rdx [56] \soc.cpu.picorv32_core.pcpi_mul.rdx [52] \soc.cpu.picorv32_core.pcpi_mul.rdx [48] \soc.cpu.picorv32_core.pcpi_mul.rdx [44] \soc.cpu.picorv32_core.pcpi_mul.rdx [40] \soc.cpu.picorv32_core.pcpi_mul.rdx [36] \soc.cpu.picorv32_core.pcpi_mul.rdx [32] \soc.cpu.picorv32_core.pcpi_mul.rdx [28] \soc.cpu.picorv32_core.pcpi_mul.rdx [24] \soc.cpu.picorv32_core.pcpi_mul.rdx [20] \soc.cpu.picorv32_core.pcpi_mul.rdx [16] \soc.cpu.picorv32_core.pcpi_mul.rdx [12] \soc.cpu.picorv32_core.pcpi_mul.rdx [8] \soc.cpu.picorv32_core.pcpi_mul.rdx [4] }, rval = 15'000000000000000). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15013 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14134_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rd). Adding SRST signal on $auto$opt_dff.cc:764:run$17153 ($dffe) from module mgmt_core (D = \soc.cpu.picorv32_core.pcpi_mul.next_rd, Q = \soc.cpu.picorv32_core.pcpi_mul.rd, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15012 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14143_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rs2). Adding SRST signal on $auto$opt_dff.cc:764:run$17155 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [0], Q = \soc.cpu.picorv32_core.pcpi_mul.rs2 [0], rval = 1'0). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15011 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14152_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rs1). Adding SRST signal on $auto$opt_dff.cc:764:run$17157 ($dffe) from module mgmt_core (D = \soc.cpu.picorv32_core.reg_op1 [31], Q = \soc.cpu.picorv32_core.pcpi_mul.rs1 [63], rval = 1'0). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15009 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2308$1031_Y [31:0], Q = \soc.cpu.picorv32_core.pcpi_mul.pcpi_rd). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15005 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14077_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_remu, rval = 1'0). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15004 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14082_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_rem, rval = 1'0). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15003 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14088_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_divu, rval = 1'0). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15002 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14095_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_div, rval = 1'0). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14999 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2471$1084_Y, Q = \soc.cpu.picorv32_core.pcpi_div.outsign). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14998 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14032_Y, Q = \soc.cpu.picorv32_core.pcpi_div.running, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$17171 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14032_Y, Q = \soc.cpu.picorv32_core.pcpi_div.running). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14997 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14041_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient_msk). Adding SRST signal on $auto$opt_dff.cc:764:run$17181 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14038_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient_msk, rval = 32'10000000000000000000000000000000). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14996 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14052_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient). Adding SRST signal on $auto$opt_dff.cc:764:run$17191 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14049_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient, rval = 0). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14995 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14061_Y, Q = \soc.cpu.picorv32_core.pcpi_div.divisor). Adding SRST signal on $auto$opt_dff.cc:764:run$17199 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14058_Y [30:0], Q = \soc.cpu.picorv32_core.pcpi_div.divisor [30:0], rval = 31'0000000000000000000000000000000). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14994 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14072_Y, Q = \soc.cpu.picorv32_core.pcpi_div.dividend). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14991 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14005_Y, Q = \soc.cpu.picorv32_core.pcpi_div.pcpi_wr, rval = 1'0). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14802 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:397$6960_Y, Q = \soc.cpu.picorv32_core.last_mem_valid, rval = 1'0). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14801 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10381_Y, Q = \soc.cpu.picorv32_core.mem_la_firstword_reg, rval = 1'0). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14800 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_rdata_latched [6:0], Q = \soc.cpu.picorv32_core.mem_rdata_q [6:0]). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14798 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10013_Y, Q = \soc.cpu.picorv32_core.mem_16bit_buffer). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14797 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10034_Y, Q = \soc.cpu.picorv32_core.prefetched_high_word, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$17229 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10025_Y, Q = \soc.cpu.picorv32_core.prefetched_high_word). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14796 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10048_Y, Q = \soc.cpu.picorv32_core.mem_la_secondword, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$17237 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10044_Y, Q = \soc.cpu.picorv32_core.mem_la_secondword). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14795 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$0\mem_state[1:0], Q = \soc.cpu.picorv32_core.mem_state). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14794 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10083_Y, Q = \soc.cpu.picorv32_core.mem_wstrb). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14793 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_la_wdata, Q = \soc.cpu.picorv32_core.mem_wdata). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14792 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_la_addr, Q = \soc.cpu.picorv32_core.mem_addr). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14790 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$0\mem_valid[0:0], Q = \soc.cpu.picorv32_core.mem_valid). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14774 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:862$7039_Y, Q = \soc.cpu.picorv32_core.is_compare, rval = 1'0). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14773 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9416_Y, Q = \soc.cpu.picorv32_core.is_alu_reg_reg). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14772 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9452_Y, Q = \soc.cpu.picorv32_core.is_alu_reg_imm). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14770 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9464_Y, Q = \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$17287 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9462_Y, Q = \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14767 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:858$7035_Y, Q = \soc.cpu.picorv32_core.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14765 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9477_Y, Q = \soc.cpu.picorv32_core.is_sb_sh_sw). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14764 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1098$7277_Y, Q = \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14763 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1092$7268_Y, Q = \soc.cpu.picorv32_core.is_slli_srli_srai). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14762 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9497_Y, Q = \soc.cpu.picorv32_core.is_lb_lh_lw_lbu_lhu). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14760 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9501_Y, Q = \soc.cpu.picorv32_core.compressed_instr). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14759 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9547_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9342_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9310_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9330_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9314_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9318_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9326_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9338_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9322_Y 1'0 }, Q = \soc.cpu.picorv32_core.decoded_imm_j). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17295 ($dffe) from module mgmt_core. Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14758 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510_Y, Q = \soc.cpu.picorv32_core.decoded_imm). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14757 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9543_Y, Q = \soc.cpu.picorv32_core.decoded_rs2). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14756 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$procmux$9306_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9393_Y }, Q = \soc.cpu.picorv32_core.decoded_rs1). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14755 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9594_Y, Q = \soc.cpu.picorv32_core.decoded_rd). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14754 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1090$7255_Y, Q = \soc.cpu.picorv32_core.instr_timer). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14753 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:870$7053_Y, Q = \soc.cpu.picorv32_core.instr_waitirq). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14752 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1089$7251_Y, Q = \soc.cpu.picorv32_core.instr_maskirq). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14751 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:869$7049_Y, Q = \soc.cpu.picorv32_core.instr_retirq). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14750 ($dff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.instr_setq). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17304 ($dffe) from module mgmt_core. Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14749 ($dff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.instr_getq). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17305 ($dffe) from module mgmt_core. Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14748 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1084$7238_Y, Q = \soc.cpu.picorv32_core.instr_ecall_ebreak). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14747 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1082$7228_Y, Q = \soc.cpu.picorv32_core.instr_rdinstrh). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14746 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1081$7224_Y, Q = \soc.cpu.picorv32_core.instr_rdinstr). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14745 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1079$7220_Y, Q = \soc.cpu.picorv32_core.instr_rdcycleh). Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14744 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1077$7212_Y, Q = \soc.cpu.picorv32_core.instr_rdcycle). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14743 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9620_Y, Q = \soc.cpu.picorv32_core.instr_and, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$17311 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1075$7204_Y, Q = \soc.cpu.picorv32_core.instr_and). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14742 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9624_Y, Q = \soc.cpu.picorv32_core.instr_or, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$17313 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1074$7200_Y, Q = \soc.cpu.picorv32_core.instr_or). Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14741 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9628_Y, Q = \soc.cpu.picorv32_core.instr_sra, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$17315 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../ver