Reports:

Submodule: caravel

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/caravel/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/caravel/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hvl
no files matched glob pattern "/media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hvl/lef/*.lef"
    while executing
"glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef""
    invoked from within
"set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"]"
    (file "/media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/openlane/config.tcl" line 13)
    invoked from within
"source $pdk_config"
    (procedure "prep" line 124)
    invoked from within
"prep {*}$args"
    (procedure "run_non_interactive_mode" line 9)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: caravel] Fehler 1

Submodule: chip_io

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/chip_io/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/chip_io/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/chip_io/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/chip_io/runs/chip_io
[WARNING]: Removing exisiting run /project/openlane/chip_io/runs/chip_io
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 3.68
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Merging the following GPIO LEF views: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef
[INFO]: Trimming Liberty...
[WARNING]: GPIO_PADS_VERILOG is not set; cannot read as a blackbox
[INFO]: Preparation complete
[INFO]: Running Synthesis...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/stubs/sky130_fd_io__top_xres4v2.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/stubs/sky130_fd_io__top_xres4v2.v' to AST representation.
Generating RTLIL representation for module `\sky130_fd_io__top_xres4v2'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/pads.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/pads.v' to AST representation.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/mprj_io.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/mprj_io.v' to AST representation.
Generating RTLIL representation for module `\mprj_io'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/chip_io.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/chip_io.v' to AST representation.
Generating RTLIL representation for module `\chip_io'.
/project/openlane/chip_io/../../verilog/rtl/chip_io.v:173: Warning: Identifier `\loop_gpio' is implicitly declared.
/project/openlane/chip_io/../../verilog/rtl/chip_io.v:178: Warning: Identifier `\loop_flash_io0' is implicitly declared.
/project/openlane/chip_io/../../verilog/rtl/chip_io.v:181: Warning: Identifier `\loop_flash_io1' is implicitly declared.
/project/openlane/chip_io/../../verilog/rtl/chip_io.v:196: Warning: Identifier `\xresloop' is implicitly declared.
Successfully finished Verilog frontend.

6. Executing HIERARCHY pass (managing design hierarchy).

6.1. Analyzing design hierarchy..
ERROR: Module `\sky130_ef_io__gpiov2_pad' referenced in module `\mprj_io' in cell `\area2_io_pad[19]' is not part of the design.
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/chip_io/runs/chip_io/logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check yosys  log file
[ERROR]: Dumping to /project/openlane/chip_io/runs/chip_io/error.log

    while executing
"try_catch [get_yosys_bin]  -c $::env(SYNTH_SCRIPT)  -l $::env(yosys_log_file_tag).log  |& tee $::env(TERMINAL_OUTPUT)"
    (procedure "run_yosys" line 18)
    invoked from within
"run_yosys"
    (procedure "run_synthesis" line 4)
    invoked from within
"run_synthesis"
    (procedure "run_non_interactive_mode" line 11)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: chip_io] Fehler 1

Submodule: DFFRAM

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/DFFRAM/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/DFFRAM/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/DFFRAM/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/DFFRAM/runs/DFFRAM
[WARNING]: Removing exisiting run /project/openlane/DFFRAM/runs/DFFRAM
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 0.0
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/DFFRAM/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/DFFRAM/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/DFFRAM/../../verilog/rtl/DFFRAM.v
Parsing Verilog input from `/project/openlane/DFFRAM/../../verilog/rtl/DFFRAM.v' to AST representation.
Generating RTLIL representation for module `\DFFRAM'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/DFFRAM/../../verilog/rtl/DFFRAMBB.v
Parsing Verilog input from `/project/openlane/DFFRAM/../../verilog/rtl/DFFRAMBB.v' to AST representation.
Generating RTLIL representation for module `\BYTE'.
Generating RTLIL representation for module `\WORD32'.
Generating RTLIL representation for module `\DEC1x2'.
Generating RTLIL representation for module `\DEC2x4'.
Generating RTLIL representation for module `\DEC3x8'.
Generating RTLIL representation for module `\DEC6x64'.
Generating RTLIL representation for module `\MUX2x1_32'.
Generating RTLIL representation for module `\MUX4x1_32'.
Generating RTLIL representation for module `\PASS'.
Generating RTLIL representation for module `\SRAM64x32'.
Generating RTLIL representation for module `\DFFRAM_COL4'.
Successfully finished Verilog frontend.

5. Executing HIERARCHY pass (managing design hierarchy).

5.1. Analyzing design hierarchy..
Top module:  \DFFRAM
Used module:     \PASS
Used module:     \DFFRAM_COL4
Used module:         \MUX4x1_32
Used module:         \SRAM64x32
Used module:             \WORD32
Used module:                 \BYTE
Used module:             \DEC6x64
Used module:                 \DEC3x8
Used module:         \DEC2x4

5.2. Analyzing design hierarchy..
Top module:  \DFFRAM
Used module:     \PASS
Used module:     \DFFRAM_COL4
Used module:         \MUX4x1_32
Used module:         \SRAM64x32
Used module:             \WORD32
Used module:                 \BYTE
Used module:             \DEC6x64
Used module:                 \DEC3x8
Used module:         \DEC2x4
Removing unused module `\MUX2x1_32'.
Removing unused module `\DEC1x2'.
Removed 2 unused modules.

6. Printing statistics.

=== PASS ===

   Number of wires:                  2
   Number of wire bits:             64
   Number of public wires:           2
   Number of public wire bits:      64
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== MUX4x1_32 ===

   Number of wires:                  6
   Number of wire bits:            162
   Number of public wires:           6
   Number of public wire bits:     162
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     sky130_fd_sc_hd__mux4_1        32

=== DFFRAM_COL4 ===

   Number of wires:                 16
   Number of wire bits:            282
   Number of public wires:          16
   Number of public wire bits:     282
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 46
     DEC2x4                          1
     MUX4x1_32                       1
     SRAM64x32                       4
     sky130_fd_sc_hd__clkbuf_16      3
     sky130_fd_sc_hd__clkbuf_8      37

=== DEC6x64 ===

   Number of wires:                  5
   Number of wire bits:             82
   Number of public wires:           5
   Number of public wire bits:      82
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 12
     DEC3x8                          9
     sky130_fd_sc_hd__clkbuf_16      3

=== DEC3x8 ===

   Number of wires:                  3
   Number of wire bits:             12
   Number of public wires:           3
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  8
     sky130_fd_sc_hd__and4_2         1
     sky130_fd_sc_hd__and4b_2        3
     sky130_fd_sc_hd__and4bb_2       3
     sky130_fd_sc_hd__nor4b_2        1

=== DEC2x4 ===

   Number of wires:                  3
   Number of wire bits:              7
   Number of public wires:           3
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     sky130_fd_sc_hd__and3_4         1
     sky130_fd_sc_hd__and3b_4        2
     sky130_fd_sc_hd__nor3b_4        1

=== SRAM64x32 ===

   Number of wires:                 13
   Number of wire bits:            211
   Number of public wires:          13
   Number of public wire bits:     211
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                168
     DEC6x64                         1
     WORD32                         64
     sky130_fd_sc_hd__clkbuf_16     37
     sky130_fd_sc_hd__clkbuf_4       1
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfxtp_1       32
     sky130_fd_sc_hd__ebufn_4       32

=== WORD32 ===

   Number of wires:                  5
   Number of wire bits:             70
   Number of public wires:           5
   Number of public wire bits:      70
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     BYTE                            4

=== BYTE ===

   Number of wires:                  9
   Number of wire bits:             30
   Number of public wires:           9
   Number of public wire bits:      30
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     sky130_fd_sc_hd__and2_1         1
     sky130_fd_sc_hd__dfxtp_1        8
     sky130_fd_sc_hd__dlclkp_1       1
     sky130_fd_sc_hd__ebufn_2        8
     sky130_fd_sc_hd__inv_1          1

=== DFFRAM ===

   Number of wires:                  9
   Number of wire bits:            143
   Number of public wires:           9
   Number of public wire bits:     143
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 35
     DFFRAM_COL4                     1
     PASS                            1
     sky130_fd_sc_hd__clkbuf_4      33

=== design hierarchy ===

   DFFRAM                            1
     DFFRAM_COL4                     1
       DEC2x4                        1
       MUX4x1_32                     1
       SRAM64x32                     4
         DEC6x64                     1
           DEC3x8                    9
         WORD32                     64
           BYTE                      4
     PASS                            1

   Number of wires:              10712
   Number of wire bits:          50902
   Number of public wires:       10712
   Number of public wire bits:   50902
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              20277
     sky130_fd_sc_hd__and2_1      1024
     sky130_fd_sc_hd__and3_4         1
     sky130_fd_sc_hd__and3b_4        2
     sky130_fd_sc_hd__and4_2        36
     sky130_fd_sc_hd__and4b_2      108
     sky130_fd_sc_hd__and4bb_2     108
     sky130_fd_sc_hd__clkbuf_16    163
     sky130_fd_sc_hd__clkbuf_4      37
     sky130_fd_sc_hd__clkbuf_8      37
     sky130_fd_sc_hd__conb_1         4
     sky130_fd_sc_hd__dfxtp_1     8320
     sky130_fd_sc_hd__dlclkp_1    1024
     sky130_fd_sc_hd__ebufn_2     8192
     sky130_fd_sc_hd__ebufn_4      128
     sky130_fd_sc_hd__inv_1       1024
     sky130_fd_sc_hd__mux4_1        32
     sky130_fd_sc_hd__nor3b_4        1
     sky130_fd_sc_hd__nor4b_2       36

7. Executing SPLITNETS pass (splitting up multi-bit signals).

8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \PASS..
Finding unused cells or wires in module \MUX4x1_32..
Finding unused cells or wires in module \DFFRAM_COL4..
Finding unused cells or wires in module \DEC6x64..
Finding unused cells or wires in module \DEC3x8..
Finding unused cells or wires in module \DEC2x4..
Finding unused cells or wires in module \SRAM64x32..
Finding unused cells or wires in module \WORD32..
Finding unused cells or wires in module \BYTE..
Finding unused cells or wires in module \DFFRAM..

9. Executing CHECK pass (checking for obvious problems).
checking module BYTE..
checking module DEC2x4..
checking module DEC3x8..
checking module DEC6x64..
checking module DFFRAM..
checking module DFFRAM_COL4..
checking module MUX4x1_32..
checking module PASS..
checking module SRAM64x32..
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[9]:
    port Z[0] of cell FLOATBUF[9] (sky130_fd_sc_hd__ebufn_4)
    port Do[9] of cell WORD[0].W (WORD32)
    port Do[9] of cell WORD[10].W (WORD32)
    port Do[9] of cell WORD[11].W (WORD32)
    port Do[9] of cell WORD[12].W (WORD32)
    port Do[9] of cell WORD[13].W (WORD32)
    port Do[9] of cell WORD[14].W (WORD32)
    port Do[9] of cell WORD[15].W (WORD32)
    port Do[9] of cell WORD[16].W (WORD32)
    port Do[9] of cell WORD[17].W (WORD32)
    port Do[9] of cell WORD[18].W (WORD32)
    port Do[9] of cell WORD[19].W (WORD32)
    port Do[9] of cell WORD[1].W (WORD32)
    port Do[9] of cell WORD[20].W (WORD32)
    port Do[9] of cell WORD[21].W (WORD32)
    port Do[9] of cell WORD[22].W (WORD32)
    port Do[9] of cell WORD[23].W (WORD32)
    port Do[9] of cell WORD[24].W (WORD32)
    port Do[9] of cell WORD[25].W (WORD32)
    port Do[9] of cell WORD[26].W (WORD32)
    port Do[9] of cell WORD[27].W (WORD32)
    port Do[9] of cell WORD[28].W (WORD32)
    port Do[9] of cell WORD[29].W (WORD32)
    port Do[9] of cell WORD[2].W (WORD32)
    port Do[9] of cell WORD[30].W (WORD32)
    port Do[9] of cell WORD[31].W (WORD32)
    port Do[9] of cell WORD[32].W (WORD32)
    port Do[9] of cell WORD[33].W (WORD32)
    port Do[9] of cell WORD[34].W (WORD32)
    port Do[9] of cell WORD[35].W (WORD32)
    port Do[9] of cell WORD[36].W (WORD32)
    port Do[9] of cell WORD[37].W (WORD32)
    port Do[9] of cell WORD[38].W (WORD32)
    port Do[9] of cell WORD[39].W (WORD32)
    port Do[9] of cell WORD[3].W (WORD32)
    port Do[9] of cell WORD[40].W (WORD32)
    port Do[9] of cell WORD[41].W (WORD32)
    port Do[9] of cell WORD[42].W (WORD32)
    port Do[9] of cell WORD[43].W (WORD32)
    port Do[9] of cell WORD[44].W (WORD32)
    port Do[9] of cell WORD[45].W (WORD32)
    port Do[9] of cell WORD[46].W (WORD32)
    port Do[9] of cell WORD[47].W (WORD32)
    port Do[9] of cell WORD[48].W (WORD32)
    port Do[9] of cell WORD[49].W (WORD32)
    port Do[9] of cell WORD[4].W (WORD32)
    port Do[9] of cell WORD[50].W (WORD32)
    port Do[9] of cell WORD[51].W (WORD32)
    port Do[9] of cell WORD[52].W (WORD32)
    port Do[9] of cell WORD[53].W (WORD32)
    port Do[9] of cell WORD[54].W (WORD32)
    port Do[9] of cell WORD[55].W (WORD32)
    port Do[9] of cell WORD[56].W (WORD32)
    port Do[9] of cell WORD[57].W (WORD32)
    port Do[9] of cell WORD[58].W (WORD32)
    port Do[9] of cell WORD[59].W (WORD32)
    port Do[9] of cell WORD[5].W (WORD32)
    port Do[9] of cell WORD[60].W (WORD32)
    port Do[9] of cell WORD[61].W (WORD32)
    port Do[9] of cell WORD[62].W (WORD32)
    port Do[9] of cell WORD[63].W (WORD32)
    port Do[9] of cell WORD[6].W (WORD32)
    port Do[9] of cell WORD[7].W (WORD32)
    port Do[9] of cell WORD[8].W (WORD32)
    port Do[9] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[8]:
    port Z[0] of cell FLOATBUF[8] (sky130_fd_sc_hd__ebufn_4)
    port Do[8] of cell WORD[0].W (WORD32)
    port Do[8] of cell WORD[10].W (WORD32)
    port Do[8] of cell WORD[11].W (WORD32)
    port Do[8] of cell WORD[12].W (WORD32)
    port Do[8] of cell WORD[13].W (WORD32)
    port Do[8] of cell WORD[14].W (WORD32)
    port Do[8] of cell WORD[15].W (WORD32)
    port Do[8] of cell WORD[16].W (WORD32)
    port Do[8] of cell WORD[17].W (WORD32)
    port Do[8] of cell WORD[18].W (WORD32)
    port Do[8] of cell WORD[19].W (WORD32)
    port Do[8] of cell WORD[1].W (WORD32)
    port Do[8] of cell WORD[20].W (WORD32)
    port Do[8] of cell WORD[21].W (WORD32)
    port Do[8] of cell WORD[22].W (WORD32)
    port Do[8] of cell WORD[23].W (WORD32)
    port Do[8] of cell WORD[24].W (WORD32)
    port Do[8] of cell WORD[25].W (WORD32)
    port Do[8] of cell WORD[26].W (WORD32)
    port Do[8] of cell WORD[27].W (WORD32)
    port Do[8] of cell WORD[28].W (WORD32)
    port Do[8] of cell WORD[29].W (WORD32)
    port Do[8] of cell WORD[2].W (WORD32)
    port Do[8] of cell WORD[30].W (WORD32)
    port Do[8] of cell WORD[31].W (WORD32)
    port Do[8] of cell WORD[32].W (WORD32)
    port Do[8] of cell WORD[33].W (WORD32)
    port Do[8] of cell WORD[34].W (WORD32)
    port Do[8] of cell WORD[35].W (WORD32)
    port Do[8] of cell WORD[36].W (WORD32)
    port Do[8] of cell WORD[37].W (WORD32)
    port Do[8] of cell WORD[38].W (WORD32)
    port Do[8] of cell WORD[39].W (WORD32)
    port Do[8] of cell WORD[3].W (WORD32)
    port Do[8] of cell WORD[40].W (WORD32)
    port Do[8] of cell WORD[41].W (WORD32)
    port Do[8] of cell WORD[42].W (WORD32)
    port Do[8] of cell WORD[43].W (WORD32)
    port Do[8] of cell WORD[44].W (WORD32)
    port Do[8] of cell WORD[45].W (WORD32)
    port Do[8] of cell WORD[46].W (WORD32)
    port Do[8] of cell WORD[47].W (WORD32)
    port Do[8] of cell WORD[48].W (WORD32)
    port Do[8] of cell WORD[49].W (WORD32)
    port Do[8] of cell WORD[4].W (WORD32)
    port Do[8] of cell WORD[50].W (WORD32)
    port Do[8] of cell WORD[51].W (WORD32)
    port Do[8] of cell WORD[52].W (WORD32)
    port Do[8] of cell WORD[53].W (WORD32)
    port Do[8] of cell WORD[54].W (WORD32)
    port Do[8] of cell WORD[55].W (WORD32)
    port Do[8] of cell WORD[56].W (WORD32)
    port Do[8] of cell WORD[57].W (WORD32)
    port Do[8] of cell WORD[58].W (WORD32)
    port Do[8] of cell WORD[59].W (WORD32)
    port Do[8] of cell WORD[5].W (WORD32)
    port Do[8] of cell WORD[60].W (WORD32)
    port Do[8] of cell WORD[61].W (WORD32)
    port Do[8] of cell WORD[62].W (WORD32)
    port Do[8] of cell WORD[63].W (WORD32)
    port Do[8] of cell WORD[6].W (WORD32)
    port Do[8] of cell WORD[7].W (WORD32)
    port Do[8] of cell WORD[8].W (WORD32)
    port Do[8] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[7]:
    port Z[0] of cell FLOATBUF[7] (sky130_fd_sc_hd__ebufn_4)
    port Do[7] of cell WORD[0].W (WORD32)
    port Do[7] of cell WORD[10].W (WORD32)
    port Do[7] of cell WORD[11].W (WORD32)
    port Do[7] of cell WORD[12].W (WORD32)
    port Do[7] of cell WORD[13].W (WORD32)
    port Do[7] of cell WORD[14].W (WORD32)
    port Do[7] of cell WORD[15].W (WORD32)
    port Do[7] of cell WORD[16].W (WORD32)
    port Do[7] of cell WORD[17].W (WORD32)
    port Do[7] of cell WORD[18].W (WORD32)
    port Do[7] of cell WORD[19].W (WORD32)
    port Do[7] of cell WORD[1].W (WORD32)
    port Do[7] of cell WORD[20].W (WORD32)
    port Do[7] of cell WORD[21].W (WORD32)
    port Do[7] of cell WORD[22].W (WORD32)
    port Do[7] of cell WORD[23].W (WORD32)
    port Do[7] of cell WORD[24].W (WORD32)
    port Do[7] of cell WORD[25].W (WORD32)
    port Do[7] of cell WORD[26].W (WORD32)
    port Do[7] of cell WORD[27].W (WORD32)
    port Do[7] of cell WORD[28].W (WORD32)
    port Do[7] of cell WORD[29].W (WORD32)
    port Do[7] of cell WORD[2].W (WORD32)
    port Do[7] of cell WORD[30].W (WORD32)
    port Do[7] of cell WORD[31].W (WORD32)
    port Do[7] of cell WORD[32].W (WORD32)
    port Do[7] of cell WORD[33].W (WORD32)
    port Do[7] of cell WORD[34].W (WORD32)
    port Do[7] of cell WORD[35].W (WORD32)
    port Do[7] of cell WORD[36].W (WORD32)
    port Do[7] of cell WORD[37].W (WORD32)
    port Do[7] of cell WORD[38].W (WORD32)
    port Do[7] of cell WORD[39].W (WORD32)
    port Do[7] of cell WORD[3].W (WORD32)
    port Do[7] of cell WORD[40].W (WORD32)
    port Do[7] of cell WORD[41].W (WORD32)
    port Do[7] of cell WORD[42].W (WORD32)
    port Do[7] of cell WORD[43].W (WORD32)
    port Do[7] of cell WORD[44].W (WORD32)
    port Do[7] of cell WORD[45].W (WORD32)
    port Do[7] of cell WORD[46].W (WORD32)
    port Do[7] of cell WORD[47].W (WORD32)
    port Do[7] of cell WORD[48].W (WORD32)
    port Do[7] of cell WORD[49].W (WORD32)
    port Do[7] of cell WORD[4].W (WORD32)
    port Do[7] of cell WORD[50].W (WORD32)
    port Do[7] of cell WORD[51].W (WORD32)
    port Do[7] of cell WORD[52].W (WORD32)
    port Do[7] of cell WORD[53].W (WORD32)
    port Do[7] of cell WORD[54].W (WORD32)
    port Do[7] of cell WORD[55].W (WORD32)
    port Do[7] of cell WORD[56].W (WORD32)
    port Do[7] of cell WORD[57].W (WORD32)
    port Do[7] of cell WORD[58].W (WORD32)
    port Do[7] of cell WORD[59].W (WORD32)
    port Do[7] of cell WORD[5].W (WORD32)
    port Do[7] of cell WORD[60].W (WORD32)
    port Do[7] of cell WORD[61].W (WORD32)
    port Do[7] of cell WORD[62].W (WORD32)
    port Do[7] of cell WORD[63].W (WORD32)
    port Do[7] of cell WORD[6].W (WORD32)
    port Do[7] of cell WORD[7].W (WORD32)
    port Do[7] of cell WORD[8].W (WORD32)
    port Do[7] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[6]:
    port Z[0] of cell FLOATBUF[6] (sky130_fd_sc_hd__ebufn_4)
    port Do[6] of cell WORD[0].W (WORD32)
    port Do[6] of cell WORD[10].W (WORD32)
    port Do[6] of cell WORD[11].W (WORD32)
    port Do[6] of cell WORD[12].W (WORD32)
    port Do[6] of cell WORD[13].W (WORD32)
    port Do[6] of cell WORD[14].W (WORD32)
    port Do[6] of cell WORD[15].W (WORD32)
    port Do[6] of cell WORD[16].W (WORD32)
    port Do[6] of cell WORD[17].W (WORD32)
    port Do[6] of cell WORD[18].W (WORD32)
    port Do[6] of cell WORD[19].W (WORD32)
    port Do[6] of cell WORD[1].W (WORD32)
    port Do[6] of cell WORD[20].W (WORD32)
    port Do[6] of cell WORD[21].W (WORD32)
    port Do[6] of cell WORD[22].W (WORD32)
    port Do[6] of cell WORD[23].W (WORD32)
    port Do[6] of cell WORD[24].W (WORD32)
    port Do[6] of cell WORD[25].W (WORD32)
    port Do[6] of cell WORD[26].W (WORD32)
    port Do[6] of cell WORD[27].W (WORD32)
    port Do[6] of cell WORD[28].W (WORD32)
    port Do[6] of cell WORD[29].W (WORD32)
    port Do[6] of cell WORD[2].W (WORD32)
    port Do[6] of cell WORD[30].W (WORD32)
    port Do[6] of cell WORD[31].W (WORD32)
    port Do[6] of cell WORD[32].W (WORD32)
    port Do[6] of cell WORD[33].W (WORD32)
    port Do[6] of cell WORD[34].W (WORD32)
    port Do[6] of cell WORD[35].W (WORD32)
    port Do[6] of cell WORD[36].W (WORD32)
    port Do[6] of cell WORD[37].W (WORD32)
    port Do[6] of cell WORD[38].W (WORD32)
    port Do[6] of cell WORD[39].W (WORD32)
    port Do[6] of cell WORD[3].W (WORD32)
    port Do[6] of cell WORD[40].W (WORD32)
    port Do[6] of cell WORD[41].W (WORD32)
    port Do[6] of cell WORD[42].W (WORD32)
    port Do[6] of cell WORD[43].W (WORD32)
    port Do[6] of cell WORD[44].W (WORD32)
    port Do[6] of cell WORD[45].W (WORD32)
    port Do[6] of cell WORD[46].W (WORD32)
    port Do[6] of cell WORD[47].W (WORD32)
    port Do[6] of cell WORD[48].W (WORD32)
    port Do[6] of cell WORD[49].W (WORD32)
    port Do[6] of cell WORD[4].W (WORD32)
    port Do[6] of cell WORD[50].W (WORD32)
    port Do[6] of cell WORD[51].W (WORD32)
    port Do[6] of cell WORD[52].W (WORD32)
    port Do[6] of cell WORD[53].W (WORD32)
    port Do[6] of cell WORD[54].W (WORD32)
    port Do[6] of cell WORD[55].W (WORD32)
    port Do[6] of cell WORD[56].W (WORD32)
    port Do[6] of cell WORD[57].W (WORD32)
    port Do[6] of cell WORD[58].W (WORD32)
    port Do[6] of cell WORD[59].W (WORD32)
    port Do[6] of cell WORD[5].W (WORD32)
    port Do[6] of cell WORD[60].W (WORD32)
    port Do[6] of cell WORD[61].W (WORD32)
    port Do[6] of cell WORD[62].W (WORD32)
    port Do[6] of cell WORD[63].W (WORD32)
    port Do[6] of cell WORD[6].W (WORD32)
    port Do[6] of cell WORD[7].W (WORD32)
    port Do[6] of cell WORD[8].W (WORD32)
    port Do[6] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[5]:
    port Z[0] of cell FLOATBUF[5] (sky130_fd_sc_hd__ebufn_4)
    port Do[5] of cell WORD[0].W (WORD32)
    port Do[5] of cell WORD[10].W (WORD32)
    port Do[5] of cell WORD[11].W (WORD32)
    port Do[5] of cell WORD[12].W (WORD32)
    port Do[5] of cell WORD[13].W (WORD32)
    port Do[5] of cell WORD[14].W (WORD32)
    port Do[5] of cell WORD[15].W (WORD32)
    port Do[5] of cell WORD[16].W (WORD32)
    port Do[5] of cell WORD[17].W (WORD32)
    port Do[5] of cell WORD[18].W (WORD32)
    port Do[5] of cell WORD[19].W (WORD32)
    port Do[5] of cell WORD[1].W (WORD32)
    port Do[5] of cell WORD[20].W (WORD32)
    port Do[5] of cell WORD[21].W (WORD32)
    port Do[5] of cell WORD[22].W (WORD32)
    port Do[5] of cell WORD[23].W (WORD32)
    port Do[5] of cell WORD[24].W (WORD32)
    port Do[5] of cell WORD[25].W (WORD32)
    port Do[5] of cell WORD[26].W (WORD32)
    port Do[5] of cell WORD[27].W (WORD32)
    port Do[5] of cell WORD[28].W (WORD32)
    port Do[5] of cell WORD[29].W (WORD32)
    port Do[5] of cell WORD[2].W (WORD32)
    port Do[5] of cell WORD[30].W (WORD32)
    port Do[5] of cell WORD[31].W (WORD32)
    port Do[5] of cell WORD[32].W (WORD32)
    port Do[5] of cell WORD[33].W (WORD32)
    port Do[5] of cell WORD[34].W (WORD32)
    port Do[5] of cell WORD[35].W (WORD32)
    port Do[5] of cell WORD[36].W (WORD32)
    port Do[5] of cell WORD[37].W (WORD32)
    port Do[5] of cell WORD[38].W (WORD32)
    port Do[5] of cell WORD[39].W (WORD32)
    port Do[5] of cell WORD[3].W (WORD32)
    port Do[5] of cell WORD[40].W (WORD32)
    port Do[5] of cell WORD[41].W (WORD32)
    port Do[5] of cell WORD[42].W (WORD32)
    port Do[5] of cell WORD[43].W (WORD32)
    port Do[5] of cell WORD[44].W (WORD32)
    port Do[5] of cell WORD[45].W (WORD32)
    port Do[5] of cell WORD[46].W (WORD32)
    port Do[5] of cell WORD[47].W (WORD32)
    port Do[5] of cell WORD[48].W (WORD32)
    port Do[5] of cell WORD[49].W (WORD32)
    port Do[5] of cell WORD[4].W (WORD32)
    port Do[5] of cell WORD[50].W (WORD32)
    port Do[5] of cell WORD[51].W (WORD32)
    port Do[5] of cell WORD[52].W (WORD32)
    port Do[5] of cell WORD[53].W (WORD32)
    port Do[5] of cell WORD[54].W (WORD32)
    port Do[5] of cell WORD[55].W (WORD32)
    port Do[5] of cell WORD[56].W (WORD32)
    port Do[5] of cell WORD[57].W (WORD32)
    port Do[5] of cell WORD[58].W (WORD32)
    port Do[5] of cell WORD[59].W (WORD32)
    port Do[5] of cell WORD[5].W (WORD32)
    port Do[5] of cell WORD[60].W (WORD32)
    port Do[5] of cell WORD[61].W (WORD32)
    port Do[5] of cell WORD[62].W (WORD32)
    port Do[5] of cell WORD[63].W (WORD32)
    port Do[5] of cell WORD[6].W (WORD32)
    port Do[5] of cell WORD[7].W (WORD32)
    port Do[5] of cell WORD[8].W (WORD32)
    port Do[5] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[4]:
    port Z[0] of cell FLOATBUF[4] (sky130_fd_sc_hd__ebufn_4)
    port Do[4] of cell WORD[0].W (WORD32)
    port Do[4] of cell WORD[10].W (WORD32)
    port Do[4] of cell WORD[11].W (WORD32)
    port Do[4] of cell WORD[12].W (WORD32)
    port Do[4] of cell WORD[13].W (WORD32)
    port Do[4] of cell WORD[14].W (WORD32)
    port Do[4] of cell WORD[15].W (WORD32)
    port Do[4] of cell WORD[16].W (WORD32)
    port Do[4] of cell WORD[17].W (WORD32)
    port Do[4] of cell WORD[18].W (WORD32)
    port Do[4] of cell WORD[19].W (WORD32)
    port Do[4] of cell WORD[1].W (WORD32)
    port Do[4] of cell WORD[20].W (WORD32)
    port Do[4] of cell WORD[21].W (WORD32)
    port Do[4] of cell WORD[22].W (WORD32)
    port Do[4] of cell WORD[23].W (WORD32)
    port Do[4] of cell WORD[24].W (WORD32)
    port Do[4] of cell WORD[25].W (WORD32)
    port Do[4] of cell WORD[26].W (WORD32)
    port Do[4] of cell WORD[27].W (WORD32)
    port Do[4] of cell WORD[28].W (WORD32)
    port Do[4] of cell WORD[29].W (WORD32)
    port Do[4] of cell WORD[2].W (WORD32)
    port Do[4] of cell WORD[30].W (WORD32)
    port Do[4] of cell WORD[31].W (WORD32)
    port Do[4] of cell WORD[32].W (WORD32)
    port Do[4] of cell WORD[33].W (WORD32)
    port Do[4] of cell WORD[34].W (WORD32)
    port Do[4] of cell WORD[35].W (WORD32)
    port Do[4] of cell WORD[36].W (WORD32)
    port Do[4] of cell WORD[37].W (WORD32)
    port Do[4] of cell WORD[38].W (WORD32)
    port Do[4] of cell WORD[39].W (WORD32)
    port Do[4] of cell WORD[3].W (WORD32)
    port Do[4] of cell WORD[40].W (WORD32)
    port Do[4] of cell WORD[41].W (WORD32)
    port Do[4] of cell WORD[42].W (WORD32)
    port Do[4] of cell WORD[43].W (WORD32)
    port Do[4] of cell WORD[44].W (WORD32)
    port Do[4] of cell WORD[45].W (WORD32)
    port Do[4] of cell WORD[46].W (WORD32)
    port Do[4] of cell WORD[47].W (WORD32)
    port Do[4] of cell WORD[48].W (WORD32)
    port Do[4] of cell WORD[49].W (WORD32)
    port Do[4] of cell WORD[4].W (WORD32)
    port Do[4] of cell WORD[50].W (WORD32)
    port Do[4] of cell WORD[51].W (WORD32)
    port Do[4] of cell WORD[52].W (WORD32)
    port Do[4] of cell WORD[53].W (WORD32)
    port Do[4] of cell WORD[54].W (WORD32)
    port Do[4] of cell WORD[55].W (WORD32)
    port Do[4] of cell WORD[56].W (WORD32)
    port Do[4] of cell WORD[57].W (WORD32)
    port Do[4] of cell WORD[58].W (WORD32)
    port Do[4] of cell WORD[59].W (WORD32)
    port Do[4] of cell WORD[5].W (WORD32)
    port Do[4] of cell WORD[60].W (WORD32)
    port Do[4] of cell WORD[61].W (WORD32)
    port Do[4] of cell WORD[62].W (WORD32)
    port Do[4] of cell WORD[63].W (WORD32)
    port Do[4] of cell WORD[6].W (WORD32)
    port Do[4] of cell WORD[7].W (WORD32)
    port Do[4] of cell WORD[8].W (WORD32)
    port Do[4] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[3]:
    port Z[0] of cell FLOATBUF[3] (sky130_fd_sc_hd__ebufn_4)
    port Do[3] of cell WORD[0].W (WORD32)
    port Do[3] of cell WORD[10].W (WORD32)
    port Do[3] of cell WORD[11].W (WORD32)
    port Do[3] of cell WORD[12].W (WORD32)
    port Do[3] of cell WORD[13].W (WORD32)
    port Do[3] of cell WORD[14].W (WORD32)
    port Do[3] of cell WORD[15].W (WORD32)
    port Do[3] of cell WORD[16].W (WORD32)
    port Do[3] of cell WORD[17].W (WORD32)
    port Do[3] of cell WORD[18].W (WORD32)
    port Do[3] of cell WORD[19].W (WORD32)
    port Do[3] of cell WORD[1].W (WORD32)
    port Do[3] of cell WORD[20].W (WORD32)
    port Do[3] of cell WORD[21].W (WORD32)
    port Do[3] of cell WORD[22].W (WORD32)
    port Do[3] of cell WORD[23].W (WORD32)
    port Do[3] of cell WORD[24].W (WORD32)
    port Do[3] of cell WORD[25].W (WORD32)
    port Do[3] of cell WORD[26].W (WORD32)
    port Do[3] of cell WORD[27].W (WORD32)
    port Do[3] of cell WORD[28].W (WORD32)
    port Do[3] of cell WORD[29].W (WORD32)
    port Do[3] of cell WORD[2].W (WORD32)
    port Do[3] of cell WORD[30].W (WORD32)
    port Do[3] of cell WORD[31].W (WORD32)
    port Do[3] of cell WORD[32].W (WORD32)
    port Do[3] of cell WORD[33].W (WORD32)
    port Do[3] of cell WORD[34].W (WORD32)
    port Do[3] of cell WORD[35].W (WORD32)
    port Do[3] of cell WORD[36].W (WORD32)
    port Do[3] of cell WORD[37].W (WORD32)
    port Do[3] of cell WORD[38].W (WORD32)
    port Do[3] of cell WORD[39].W (WORD32)
    port Do[3] of cell WORD[3].W (WORD32)
    port Do[3] of cell WORD[40].W (WORD32)
    port Do[3] of cell WORD[41].W (WORD32)
    port Do[3] of cell WORD[42].W (WORD32)
    port Do[3] of cell WORD[43].W (WORD32)
    port Do[3] of cell WORD[44].W (WORD32)
    port Do[3] of cell WORD[45].W (WORD32)
    port Do[3] of cell WORD[46].W (WORD32)
    port Do[3] of cell WORD[47].W (WORD32)
    port Do[3] of cell WORD[48].W (WORD32)
    port Do[3] of cell WORD[49].W (WORD32)
    port Do[3] of cell WORD[4].W (WORD32)
    port Do[3] of cell WORD[50].W (WORD32)
    port Do[3] of cell WORD[51].W (WORD32)
    port Do[3] of cell WORD[52].W (WORD32)
    port Do[3] of cell WORD[53].W (WORD32)
    port Do[3] of cell WORD[54].W (WORD32)
    port Do[3] of cell WORD[55].W (WORD32)
    port Do[3] of cell WORD[56].W (WORD32)
    port Do[3] of cell WORD[57].W (WORD32)
    port Do[3] of cell WORD[58].W (WORD32)
    port Do[3] of cell WORD[59].W (WORD32)
    port Do[3] of cell WORD[5].W (WORD32)
    port Do[3] of cell WORD[60].W (WORD32)
    port Do[3] of cell WORD[61].W (WORD32)
    port Do[3] of cell WORD[62].W (WORD32)
    port Do[3] of cell WORD[63].W (WORD32)
    port Do[3] of cell WORD[6].W (WORD32)
    port Do[3] of cell WORD[7].W (WORD32)
    port Do[3] of cell WORD[8].W (WORD32)
    port Do[3] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[31]:
    port Z[0] of cell FLOATBUF[31] (sky130_fd_sc_hd__ebufn_4)
    port Do[31] of cell WORD[0].W (WORD32)
    port Do[31] of cell WORD[10].W (WORD32)
    port Do[31] of cell WORD[11].W (WORD32)
    port Do[31] of cell WORD[12].W (WORD32)
    port Do[31] of cell WORD[13].W (WORD32)
    port Do[31] of cell WORD[14].W (WORD32)
    port Do[31] of cell WORD[15].W (WORD32)
    port Do[31] of cell WORD[16].W (WORD32)
    port Do[31] of cell WORD[17].W (WORD32)
    port Do[31] of cell WORD[18].W (WORD32)
    port Do[31] of cell WORD[19].W (WORD32)
    port Do[31] of cell WORD[1].W (WORD32)
    port Do[31] of cell WORD[20].W (WORD32)
    port Do[31] of cell WORD[21].W (WORD32)
    port Do[31] of cell WORD[22].W (WORD32)
    port Do[31] of cell WORD[23].W (WORD32)
    port Do[31] of cell WORD[24].W (WORD32)
    port Do[31] of cell WORD[25].W (WORD32)
    port Do[31] of cell WORD[26].W (WORD32)
    port Do[31] of cell WORD[27].W (WORD32)
    port Do[31] of cell WORD[28].W (WORD32)
    port Do[31] of cell WORD[29].W (WORD32)
    port Do[31] of cell WORD[2].W (WORD32)
    port Do[31] of cell WORD[30].W (WORD32)
    port Do[31] of cell WORD[31].W (WORD32)
    port Do[31] of cell WORD[32].W (WORD32)
    port Do[31] of cell WORD[33].W (WORD32)
    port Do[31] of cell WORD[34].W (WORD32)
    port Do[31] of cell WORD[35].W (WORD32)
    port Do[31] of cell WORD[36].W (WORD32)
    port Do[31] of cell WORD[37].W (WORD32)
    port Do[31] of cell WORD[38].W (WORD32)
    port Do[31] of cell WORD[39].W (WORD32)
    port Do[31] of cell WORD[3].W (WORD32)
    port Do[31] of cell WORD[40].W (WORD32)
    port Do[31] of cell WORD[41].W (WORD32)
    port Do[31] of cell WORD[42].W (WORD32)
    port Do[31] of cell WORD[43].W (WORD32)
    port Do[31] of cell WORD[44].W (WORD32)
    port Do[31] of cell WORD[45].W (WORD32)
    port Do[31] of cell WORD[46].W (WORD32)
    port Do[31] of cell WORD[47].W (WORD32)
    port Do[31] of cell WORD[48].W (WORD32)
    port Do[31] of cell WORD[49].W (WORD32)
    port Do[31] of cell WORD[4].W (WORD32)
    port Do[31] of cell WORD[50].W (WORD32)
    port Do[31] of cell WORD[51].W (WORD32)
    port Do[31] of cell WORD[52].W (WORD32)
    port Do[31] of cell WORD[53].W (WORD32)
    port Do[31] of cell WORD[54].W (WORD32)
    port Do[31] of cell WORD[55].W (WORD32)
    port Do[31] of cell WORD[56].W (WORD32)
    port Do[31] of cell WORD[57].W (WORD32)
    port Do[31] of cell WORD[58].W (WORD32)
    port Do[31] of cell WORD[59].W (WORD32)
    port Do[31] of cell WORD[5].W (WORD32)
    port Do[31] of cell WORD[60].W (WORD32)
    port Do[31] of cell WORD[61].W (WORD32)
    port Do[31] of cell WORD[62].W (WORD32)
    port Do[31] of cell WORD[63].W (WORD32)
    port Do[31] of cell WORD[6].W (WORD32)
    port Do[31] of cell WORD[7].W (WORD32)
    port Do[31] of cell WORD[8].W (WORD32)
    port Do[31] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[30]:
    port Z[0] of cell FLOATBUF[30] (sky130_fd_sc_hd__ebufn_4)
    port Do[30] of cell WORD[0].W (WORD32)
    port Do[30] of cell WORD[10].W (WORD32)
    port Do[30] of cell WORD[11].W (WORD32)
    port Do[30] of cell WORD[12].W (WORD32)
    port Do[30] of cell WORD[13].W (WORD32)
    port Do[30] of cell WORD[14].W (WORD32)
    port Do[30] of cell WORD[15].W (WORD32)
    port Do[30] of cell WORD[16].W (WORD32)
    port Do[30] of cell WORD[17].W (WORD32)
    port Do[30] of cell WORD[18].W (WORD32)
    port Do[30] of cell WORD[19].W (WORD32)
    port Do[30] of cell WORD[1].W (WORD32)
    port Do[30] of cell WORD[20].W (WORD32)
    port Do[30] of cell WORD[21].W (WORD32)
    port Do[30] of cell WORD[22].W (WORD32)
    port Do[30] of cell WORD[23].W (WORD32)
    port Do[30] of cell WORD[24].W (WORD32)
    port Do[30] of cell WORD[25].W (WORD32)
    port Do[30] of cell WORD[26].W (WORD32)
    port Do[30] of cell WORD[27].W (WORD32)
    port Do[30] of cell WORD[28].W (WORD32)
    port Do[30] of cell WORD[29].W (WORD32)
    port Do[30] of cell WORD[2].W (WORD32)
    port Do[30] of cell WORD[30].W (WORD32)
    port Do[30] of cell WORD[31].W (WORD32)
    port Do[30] of cell WORD[32].W (WORD32)
    port Do[30] of cell WORD[33].W (WORD32)
    port Do[30] of cell WORD[34].W (WORD32)
    port Do[30] of cell WORD[35].W (WORD32)
    port Do[30] of cell WORD[36].W (WORD32)
    port Do[30] of cell WORD[37].W (WORD32)
    port Do[30] of cell WORD[38].W (WORD32)
    port Do[30] of cell WORD[39].W (WORD32)
    port Do[30] of cell WORD[3].W (WORD32)
    port Do[30] of cell WORD[40].W (WORD32)
    port Do[30] of cell WORD[41].W (WORD32)
    port Do[30] of cell WORD[42].W (WORD32)
    port Do[30] of cell WORD[43].W (WORD32)
    port Do[30] of cell WORD[44].W (WORD32)
    port Do[30] of cell WORD[45].W (WORD32)
    port Do[30] of cell WORD[46].W (WORD32)
    port Do[30] of cell WORD[47].W (WORD32)
    port Do[30] of cell WORD[48].W (WORD32)
    port Do[30] of cell WORD[49].W (WORD32)
    port Do[30] of cell WORD[4].W (WORD32)
    port Do[30] of cell WORD[50].W (WORD32)
    port Do[30] of cell WORD[51].W (WORD32)
    port Do[30] of cell WORD[52].W (WORD32)
    port Do[30] of cell WORD[53].W (WORD32)
    port Do[30] of cell WORD[54].W (WORD32)
    port Do[30] of cell WORD[55].W (WORD32)
    port Do[30] of cell WORD[56].W (WORD32)
    port Do[30] of cell WORD[57].W (WORD32)
    port Do[30] of cell WORD[58].W (WORD32)
    port Do[30] of cell WORD[59].W (WORD32)
    port Do[30] of cell WORD[5].W (WORD32)
    port Do[30] of cell WORD[60].W (WORD32)
    port Do[30] of cell WORD[61].W (WORD32)
    port Do[30] of cell WORD[62].W (WORD32)
    port Do[30] of cell WORD[63].W (WORD32)
    port Do[30] of cell WORD[6].W (WORD32)
    port Do[30] of cell WORD[7].W (WORD32)
    port Do[30] of cell WORD[8].W (WORD32)
    port Do[30] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[2]:
    port Z[0] of cell FLOATBUF[2] (sky130_fd_sc_hd__ebufn_4)
    port Do[2] of cell WORD[0].W (WORD32)
    port Do[2] of cell WORD[10].W (WORD32)
    port Do[2] of cell WORD[11].W (WORD32)
    port Do[2] of cell WORD[12].W (WORD32)
    port Do[2] of cell WORD[13].W (WORD32)
    port Do[2] of cell WORD[14].W (WORD32)
    port Do[2] of cell WORD[15].W (WORD32)
    port Do[2] of cell WORD[16].W (WORD32)
    port Do[2] of cell WORD[17].W (WORD32)
    port Do[2] of cell WORD[18].W (WORD32)
    port Do[2] of cell WORD[19].W (WORD32)
    port Do[2] of cell WORD[1].W (WORD32)
    port Do[2] of cell WORD[20].W (WORD32)
    port Do[2] of cell WORD[21].W (WORD32)
    port Do[2] of cell WORD[22].W (WORD32)
    port Do[2] of cell WORD[23].W (WORD32)
    port Do[2] of cell WORD[24].W (WORD32)
    port Do[2] of cell WORD[25].W (WORD32)
    port Do[2] of cell WORD[26].W (WORD32)
    port Do[2] of cell WORD[27].W (WORD32)
    port Do[2] of cell WORD[28].W (WORD32)
    port Do[2] of cell WORD[29].W (WORD32)
    port Do[2] of cell WORD[2].W (WORD32)
    port Do[2] of cell WORD[30].W (WORD32)
    port Do[2] of cell WORD[31].W (WORD32)
    port Do[2] of cell WORD[32].W (WORD32)
    port Do[2] of cell WORD[33].W (WORD32)
    port Do[2] of cell WORD[34].W (WORD32)
    port Do[2] of cell WORD[35].W (WORD32)
    port Do[2] of cell WORD[36].W (WORD32)
    port Do[2] of cell WORD[37].W (WORD32)
    port Do[2] of cell WORD[38].W (WORD32)
    port Do[2] of cell WORD[39].W (WORD32)
    port Do[2] of cell WORD[3].W (WORD32)
    port Do[2] of cell WORD[40].W (WORD32)
    port Do[2] of cell WORD[41].W (WORD32)
    port Do[2] of cell WORD[42].W (WORD32)
    port Do[2] of cell WORD[43].W (WORD32)
    port Do[2] of cell WORD[44].W (WORD32)
    port Do[2] of cell WORD[45].W (WORD32)
    port Do[2] of cell WORD[46].W (WORD32)
    port Do[2] of cell WORD[47].W (WORD32)
    port Do[2] of cell WORD[48].W (WORD32)
    port Do[2] of cell WORD[49].W (WORD32)
    port Do[2] of cell WORD[4].W (WORD32)
    port Do[2] of cell WORD[50].W (WORD32)
    port Do[2] of cell WORD[51].W (WORD32)
    port Do[2] of cell WORD[52].W (WORD32)
    port Do[2] of cell WORD[53].W (WORD32)
    port Do[2] of cell WORD[54].W (WORD32)
    port Do[2] of cell WORD[55].W (WORD32)
    port Do[2] of cell WORD[56].W (WORD32)
    port Do[2] of cell WORD[57].W (WORD32)
    port Do[2] of cell WORD[58].W (WORD32)
    port Do[2] of cell WORD[59].W (WORD32)
    port Do[2] of cell WORD[5].W (WORD32)
    port Do[2] of cell WORD[60].W (WORD32)
    port Do[2] of cell WORD[61].W (WORD32)
    port Do[2] of cell WORD[62].W (WORD32)
    port Do[2] of cell WORD[63].W (WORD32)
    port Do[2] of cell WORD[6].W (WORD32)
    port Do[2] of cell WORD[7].W (WORD32)
    port Do[2] of cell WORD[8].W (WORD32)
    port Do[2] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[29]:
    port Z[0] of cell FLOATBUF[29] (sky130_fd_sc_hd__ebufn_4)
    port Do[29] of cell WORD[0].W (WORD32)
    port Do[29] of cell WORD[10].W (WORD32)
    port Do[29] of cell WORD[11].W (WORD32)
    port Do[29] of cell WORD[12].W (WORD32)
    port Do[29] of cell WORD[13].W (WORD32)
    port Do[29] of cell WORD[14].W (WORD32)
    port Do[29] of cell WORD[15].W (WORD32)
    port Do[29] of cell WORD[16].W (WORD32)
    port Do[29] of cell WORD[17].W (WORD32)
    port Do[29] of cell WORD[18].W (WORD32)
    port Do[29] of cell WORD[19].W (WORD32)
    port Do[29] of cell WORD[1].W (WORD32)
    port Do[29] of cell WORD[20].W (WORD32)
    port Do[29] of cell WORD[21].W (WORD32)
    port Do[29] of cell WORD[22].W (WORD32)
    port Do[29] of cell WORD[23].W (WORD32)
    port Do[29] of cell WORD[24].W (WORD32)
    port Do[29] of cell WORD[25].W (WORD32)
    port Do[29] of cell WORD[26].W (WORD32)
    port Do[29] of cell WORD[27].W (WORD32)
    port Do[29] of cell WORD[28].W (WORD32)
    port Do[29] of cell WORD[29].W (WORD32)
    port Do[29] of cell WORD[2].W (WORD32)
    port Do[29] of cell WORD[30].W (WORD32)
    port Do[29] of cell WORD[31].W (WORD32)
    port Do[29] of cell WORD[32].W (WORD32)
    port Do[29] of cell WORD[33].W (WORD32)
    port Do[29] of cell WORD[34].W (WORD32)
    port Do[29] of cell WORD[35].W (WORD32)
    port Do[29] of cell WORD[36].W (WORD32)
    port Do[29] of cell WORD[37].W (WORD32)
    port Do[29] of cell WORD[38].W (WORD32)
    port Do[29] of cell WORD[39].W (WORD32)
    port Do[29] of cell WORD[3].W (WORD32)
    port Do[29] of cell WORD[40].W (WORD32)
    port Do[29] of cell WORD[41].W (WORD32)
    port Do[29] of cell WORD[42].W (WORD32)
    port Do[29] of cell WORD[43].W (WORD32)
    port Do[29] of cell WORD[44].W (WORD32)
    port Do[29] of cell WORD[45].W (WORD32)
    port Do[29] of cell WORD[46].W (WORD32)
    port Do[29] of cell WORD[47].W (WORD32)
    port Do[29] of cell WORD[48].W (WORD32)
    port Do[29] of cell WORD[49].W (WORD32)
    port Do[29] of cell WORD[4].W (WORD32)
    port Do[29] of cell WORD[50].W (WORD32)
    port Do[29] of cell WORD[51].W (WORD32)
    port Do[29] of cell WORD[52].W (WORD32)
    port Do[29] of cell WORD[53].W (WORD32)
    port Do[29] of cell WORD[54].W (WORD32)
    port Do[29] of cell WORD[55].W (WORD32)
    port Do[29] of cell WORD[56].W (WORD32)
    port Do[29] of cell WORD[57].W (WORD32)
    port Do[29] of cell WORD[58].W (WORD32)
    port Do[29] of cell WORD[59].W (WORD32)
    port Do[29] of cell WORD[5].W (WORD32)
    port Do[29] of cell WORD[60].W (WORD32)
    port Do[29] of cell WORD[61].W (WORD32)
    port Do[29] of cell WORD[62].W (WORD32)
    port Do[29] of cell WORD[63].W (WORD32)
    port Do[29] of cell WORD[6].W (WORD32)
    port Do[29] of cell WORD[7].W (WORD32)
    port Do[29] of cell WORD[8].W (WORD32)
    port Do[29] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[28]:
    port Z[0] of cell FLOATBUF[28] (sky130_fd_sc_hd__ebufn_4)
    port Do[28] of cell WORD[0].W (WORD32)
    port Do[28] of cell WORD[10].W (WORD32)
    port Do[28] of cell WORD[11].W (WORD32)
    port Do[28] of cell WORD[12].W (WORD32)
    port Do[28] of cell WORD[13].W (WORD32)
    port Do[28] of cell WORD[14].W (WORD32)
    port Do[28] of cell WORD[15].W (WORD32)
    port Do[28] of cell WORD[16].W (WORD32)
    port Do[28] of cell WORD[17].W (WORD32)
    port Do[28] of cell WORD[18].W (WORD32)
    port Do[28] of cell WORD[19].W (WORD32)
    port Do[28] of cell WORD[1].W (WORD32)
    port Do[28] of cell WORD[20].W (WORD32)
    port Do[28] of cell WORD[21].W (WORD32)
    port Do[28] of cell WORD[22].W (WORD32)
    port Do[28] of cell WORD[23].W (WORD32)
    port Do[28] of cell WORD[24].W (WORD32)
    port Do[28] of cell WORD[25].W (WORD32)
    port Do[28] of cell WORD[26].W (WORD32)
    port Do[28] of cell WORD[27].W (WORD32)
    port Do[28] of cell WORD[28].W (WORD32)
    port Do[28] of cell WORD[29].W (WORD32)
    port Do[28] of cell WORD[2].W (WORD32)
    port Do[28] of cell WORD[30].W (WORD32)
    port Do[28] of cell WORD[31].W (WORD32)
    port Do[28] of cell WORD[32].W (WORD32)
    port Do[28] of cell WORD[33].W (WORD32)
    port Do[28] of cell WORD[34].W (WORD32)
    port Do[28] of cell WORD[35].W (WORD32)
    port Do[28] of cell WORD[36].W (WORD32)
    port Do[28] of cell WORD[37].W (WORD32)
    port Do[28] of cell WORD[38].W (WORD32)
    port Do[28] of cell WORD[39].W (WORD32)
    port Do[28] of cell WORD[3].W (WORD32)
    port Do[28] of cell WORD[40].W (WORD32)
    port Do[28] of cell WORD[41].W (WORD32)
    port Do[28] of cell WORD[42].W (WORD32)
    port Do[28] of cell WORD[43].W (WORD32)
    port Do[28] of cell WORD[44].W (WORD32)
    port Do[28] of cell WORD[45].W (WORD32)
    port Do[28] of cell WORD[46].W (WORD32)
    port Do[28] of cell WORD[47].W (WORD32)
    port Do[28] of cell WORD[48].W (WORD32)
    port Do[28] of cell WORD[49].W (WORD32)
    port Do[28] of cell WORD[4].W (WORD32)
    port Do[28] of cell WORD[50].W (WORD32)
    port Do[28] of cell WORD[51].W (WORD32)
    port Do[28] of cell WORD[52].W (WORD32)
    port Do[28] of cell WORD[53].W (WORD32)
    port Do[28] of cell WORD[54].W (WORD32)
    port Do[28] of cell WORD[55].W (WORD32)
    port Do[28] of cell WORD[56].W (WORD32)
    port Do[28] of cell WORD[57].W (WORD32)
    port Do[28] of cell WORD[58].W (WORD32)
    port Do[28] of cell WORD[59].W (WORD32)
    port Do[28] of cell WORD[5].W (WORD32)
    port Do[28] of cell WORD[60].W (WORD32)
    port Do[28] of cell WORD[61].W (WORD32)
    port Do[28] of cell WORD[62].W (WORD32)
    port Do[28] of cell WORD[63].W (WORD32)
    port Do[28] of cell WORD[6].W (WORD32)
    port Do[28] of cell WORD[7].W (WORD32)
    port Do[28] of cell WORD[8].W (WORD32)
    port Do[28] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[27]:
    port Z[0] of cell FLOATBUF[27] (sky130_fd_sc_hd__ebufn_4)
    port Do[27] of cell WORD[0].W (WORD32)
    port Do[27] of cell WORD[10].W (WORD32)
    port Do[27] of cell WORD[11].W (WORD32)
    port Do[27] of cell WORD[12].W (WORD32)
    port Do[27] of cell WORD[13].W (WORD32)
    port Do[27] of cell WORD[14].W (WORD32)
    port Do[27] of cell WORD[15].W (WORD32)
    port Do[27] of cell WORD[16].W (WORD32)
    port Do[27] of cell WORD[17].W (WORD32)
    port Do[27] of cell WORD[18].W (WORD32)
    port Do[27] of cell WORD[19].W (WORD32)
    port Do[27] of cell WORD[1].W (WORD32)
    port Do[27] of cell WORD[20].W (WORD32)
    port Do[27] of cell WORD[21].W (WORD32)
    port Do[27] of cell WORD[22].W (WORD32)
    port Do[27] of cell WORD[23].W (WORD32)
    port Do[27] of cell WORD[24].W (WORD32)
    port Do[27] of cell WORD[25].W (WORD32)
    port Do[27] of cell WORD[26].W (WORD32)
    port Do[27] of cell WORD[27].W (WORD32)
    port Do[27] of cell WORD[28].W (WORD32)
    port Do[27] of cell WORD[29].W (WORD32)
    port Do[27] of cell WORD[2].W (WORD32)
    port Do[27] of cell WORD[30].W (WORD32)
    port Do[27] of cell WORD[31].W (WORD32)
    port Do[27] of cell WORD[32].W (WORD32)
    port Do[27] of cell WORD[33].W (WORD32)
    port Do[27] of cell WORD[34].W (WORD32)
    port Do[27] of cell WORD[35].W (WORD32)
    port Do[27] of cell WORD[36].W (WORD32)
    port Do[27] of cell WORD[37].W (WORD32)
    port Do[27] of cell WORD[38].W (WORD32)
    port Do[27] of cell WORD[39].W (WORD32)
    port Do[27] of cell WORD[3].W (WORD32)
    port Do[27] of cell WORD[40].W (WORD32)
    port Do[27] of cell WORD[41].W (WORD32)
    port Do[27] of cell WORD[42].W (WORD32)
    port Do[27] of cell WORD[43].W (WORD32)
    port Do[27] of cell WORD[44].W (WORD32)
    port Do[27] of cell WORD[45].W (WORD32)
    port Do[27] of cell WORD[46].W (WORD32)
    port Do[27] of cell WORD[47].W (WORD32)
    port Do[27] of cell WORD[48].W (WORD32)
    port Do[27] of cell WORD[49].W (WORD32)
    port Do[27] of cell WORD[4].W (WORD32)
    port Do[27] of cell WORD[50].W (WORD32)
    port Do[27] of cell WORD[51].W (WORD32)
    port Do[27] of cell WORD[52].W (WORD32)
    port Do[27] of cell WORD[53].W (WORD32)
    port Do[27] of cell WORD[54].W (WORD32)
    port Do[27] of cell WORD[55].W (WORD32)
    port Do[27] of cell WORD[56].W (WORD32)
    port Do[27] of cell WORD[57].W (WORD32)
    port Do[27] of cell WORD[58].W (WORD32)
    port Do[27] of cell WORD[59].W (WORD32)
    port Do[27] of cell WORD[5].W (WORD32)
    port Do[27] of cell WORD[60].W (WORD32)
    port Do[27] of cell WORD[61].W (WORD32)
    port Do[27] of cell WORD[62].W (WORD32)
    port Do[27] of cell WORD[63].W (WORD32)
    port Do[27] of cell WORD[6].W (WORD32)
    port Do[27] of cell WORD[7].W (WORD32)
    port Do[27] of cell WORD[8].W (WORD32)
    port Do[27] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[26]:
    port Z[0] of cell FLOATBUF[26] (sky130_fd_sc_hd__ebufn_4)
    port Do[26] of cell WORD[0].W (WORD32)
    port Do[26] of cell WORD[10].W (WORD32)
    port Do[26] of cell WORD[11].W (WORD32)
    port Do[26] of cell WORD[12].W (WORD32)
    port Do[26] of cell WORD[13].W (WORD32)
    port Do[26] of cell WORD[14].W (WORD32)
    port Do[26] of cell WORD[15].W (WORD32)
    port Do[26] of cell WORD[16].W (WORD32)
    port Do[26] of cell WORD[17].W (WORD32)
    port Do[26] of cell WORD[18].W (WORD32)
    port Do[26] of cell WORD[19].W (WORD32)
    port Do[26] of cell WORD[1].W (WORD32)
    port Do[26] of cell WORD[20].W (WORD32)
    port Do[26] of cell WORD[21].W (WORD32)
    port Do[26] of cell WORD[22].W (WORD32)
    port Do[26] of cell WORD[23].W (WORD32)
    port Do[26] of cell WORD[24].W (WORD32)
    port Do[26] of cell WORD[25].W (WORD32)
    port Do[26] of cell WORD[26].W (WORD32)
    port Do[26] of cell WORD[27].W (WORD32)
    port Do[26] of cell WORD[28].W (WORD32)
    port Do[26] of cell WORD[29].W (WORD32)
    port Do[26] of cell WORD[2].W (WORD32)
    port Do[26] of cell WORD[30].W (WORD32)
    port Do[26] of cell WORD[31].W (WORD32)
    port Do[26] of cell WORD[32].W (WORD32)
    port Do[26] of cell WORD[33].W (WORD32)
    port Do[26] of cell WORD[34].W (WORD32)
    port Do[26] of cell WORD[35].W (WORD32)
    port Do[26] of cell WORD[36].W (WORD32)
    port Do[26] of cell WORD[37].W (WORD32)
    port Do[26] of cell WORD[38].W (WORD32)
    port Do[26] of cell WORD[39].W (WORD32)
    port Do[26] of cell WORD[3].W (WORD32)
    port Do[26] of cell WORD[40].W (WORD32)
    port Do[26] of cell WORD[41].W (WORD32)
    port Do[26] of cell WORD[42].W (WORD32)
    port Do[26] of cell WORD[43].W (WORD32)
    port Do[26] of cell WORD[44].W (WORD32)
    port Do[26] of cell WORD[45].W (WORD32)
    port Do[26] of cell WORD[46].W (WORD32)
    port Do[26] of cell WORD[47].W (WORD32)
    port Do[26] of cell WORD[48].W (WORD32)
    port Do[26] of cell WORD[49].W (WORD32)
    port Do[26] of cell WORD[4].W (WORD32)
    port Do[26] of cell WORD[50].W (WORD32)
    port Do[26] of cell WORD[51].W (WORD32)
    port Do[26] of cell WORD[52].W (WORD32)
    port Do[26] of cell WORD[53].W (WORD32)
    port Do[26] of cell WORD[54].W (WORD32)
    port Do[26] of cell WORD[55].W (WORD32)
    port Do[26] of cell WORD[56].W (WORD32)
    port Do[26] of cell WORD[57].W (WORD32)
    port Do[26] of cell WORD[58].W (WORD32)
    port Do[26] of cell WORD[59].W (WORD32)
    port Do[26] of cell WORD[5].W (WORD32)
    port Do[26] of cell WORD[60].W (WORD32)
    port Do[26] of cell WORD[61].W (WORD32)
    port Do[26] of cell WORD[62].W (WORD32)
    port Do[26] of cell WORD[63].W (WORD32)
    port Do[26] of cell WORD[6].W (WORD32)
    port Do[26] of cell WORD[7].W (WORD32)
    port Do[26] of cell WORD[8].W (WORD32)
    port Do[26] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[25]:
    port Z[0] of cell FLOATBUF[25] (sky130_fd_sc_hd__ebufn_4)
    port Do[25] of cell WORD[0].W (WORD32)
    port Do[25] of cell WORD[10].W (WORD32)
    port Do[25] of cell WORD[11].W (WORD32)
    port Do[25] of cell WORD[12].W (WORD32)
    port Do[25] of cell WORD[13].W (WORD32)
    port Do[25] of cell WORD[14].W (WORD32)
    port Do[25] of cell WORD[15].W (WORD32)
    port Do[25] of cell WORD[16].W (WORD32)
    port Do[25] of cell WORD[17].W (WORD32)
    port Do[25] of cell WORD[18].W (WORD32)
    port Do[25] of cell WORD[19].W (WORD32)
    port Do[25] of cell WORD[1].W (WORD32)
    port Do[25] of cell WORD[20].W (WORD32)
    port Do[25] of cell WORD[21].W (WORD32)
    port Do[25] of cell WORD[22].W (WORD32)
    port Do[25] of cell WORD[23].W (WORD32)
    port Do[25] of cell WORD[24].W (WORD32)
    port Do[25] of cell WORD[25].W (WORD32)
    port Do[25] of cell WORD[26].W (WORD32)
    port Do[25] of cell WORD[27].W (WORD32)
    port Do[25] of cell WORD[28].W (WORD32)
    port Do[25] of cell WORD[29].W (WORD32)
    port Do[25] of cell WORD[2].W (WORD32)
    port Do[25] of cell WORD[30].W (WORD32)
    port Do[25] of cell WORD[31].W (WORD32)
    port Do[25] of cell WORD[32].W (WORD32)
    port Do[25] of cell WORD[33].W (WORD32)
    port Do[25] of cell WORD[34].W (WORD32)
    port Do[25] of cell WORD[35].W (WORD32)
    port Do[25] of cell WORD[36].W (WORD32)
    port Do[25] of cell WORD[37].W (WORD32)
    port Do[25] of cell WORD[38].W (WORD32)
    port Do[25] of cell WORD[39].W (WORD32)
    port Do[25] of cell WORD[3].W (WORD32)
    port Do[25] of cell WORD[40].W (WORD32)
    port Do[25] of cell WORD[41].W (WORD32)
    port Do[25] of cell WORD[42].W (WORD32)
    port Do[25] of cell WORD[43].W (WORD32)
    port Do[25] of cell WORD[44].W (WORD32)
    port Do[25] of cell WORD[45].W (WORD32)
    port Do[25] of cell WORD[46].W (WORD32)
    port Do[25] of cell WORD[47].W (WORD32)
    port Do[25] of cell WORD[48].W (WORD32)
    port Do[25] of cell WORD[49].W (WORD32)
    port Do[25] of cell WORD[4].W (WORD32)
    port Do[25] of cell WORD[50].W (WORD32)
    port Do[25] of cell WORD[51].W (WORD32)
    port Do[25] of cell WORD[52].W (WORD32)
    port Do[25] of cell WORD[53].W (WORD32)
    port Do[25] of cell WORD[54].W (WORD32)
    port Do[25] of cell WORD[55].W (WORD32)
    port Do[25] of cell WORD[56].W (WORD32)
    port Do[25] of cell WORD[57].W (WORD32)
    port Do[25] of cell WORD[58].W (WORD32)
    port Do[25] of cell WORD[59].W (WORD32)
    port Do[25] of cell WORD[5].W (WORD32)
    port Do[25] of cell WORD[60].W (WORD32)
    port Do[25] of cell WORD[61].W (WORD32)
    port Do[25] of cell WORD[62].W (WORD32)
    port Do[25] of cell WORD[63].W (WORD32)
    port Do[25] of cell WORD[6].W (WORD32)
    port Do[25] of cell WORD[7].W (WORD32)
    port Do[25] of cell WORD[8].W (WORD32)
    port Do[25] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[24]:
    port Z[0] of cell FLOATBUF[24] (sky130_fd_sc_hd__ebufn_4)
    port Do[24] of cell WORD[0].W (WORD32)
    port Do[24] of cell WORD[10].W (WORD32)
    port Do[24] of cell WORD[11].W (WORD32)
    port Do[24] of cell WORD[12].W (WORD32)
    port Do[24] of cell WORD[13].W (WORD32)
    port Do[24] of cell WORD[14].W (WORD32)
    port Do[24] of cell WORD[15].W (WORD32)
    port Do[24] of cell WORD[16].W (WORD32)
    port Do[24] of cell WORD[17].W (WORD32)
    port Do[24] of cell WORD[18].W (WORD32)
    port Do[24] of cell WORD[19].W (WORD32)
    port Do[24] of cell WORD[1].W (WORD32)
    port Do[24] of cell WORD[20].W (WORD32)
    port Do[24] of cell WORD[21].W (WORD32)
    port Do[24] of cell WORD[22].W (WORD32)
    port Do[24] of cell WORD[23].W (WORD32)
    port Do[24] of cell WORD[24].W (WORD32)
    port Do[24] of cell WORD[25].W (WORD32)
    port Do[24] of cell WORD[26].W (WORD32)
    port Do[24] of cell WORD[27].W (WORD32)
    port Do[24] of cell WORD[28].W (WORD32)
    port Do[24] of cell WORD[29].W (WORD32)
    port Do[24] of cell WORD[2].W (WORD32)
    port Do[24] of cell WORD[30].W (WORD32)
    port Do[24] of cell WORD[31].W (WORD32)
    port Do[24] of cell WORD[32].W (WORD32)
    port Do[24] of cell WORD[33].W (WORD32)
    port Do[24] of cell WORD[34].W (WORD32)
    port Do[24] of cell WORD[35].W (WORD32)
    port Do[24] of cell WORD[36].W (WORD32)
    port Do[24] of cell WORD[37].W (WORD32)
    port Do[24] of cell WORD[38].W (WORD32)
    port Do[24] of cell WORD[39].W (WORD32)
    port Do[24] of cell WORD[3].W (WORD32)
    port Do[24] of cell WORD[40].W (WORD32)
    port Do[24] of cell WORD[41].W (WORD32)
    port Do[24] of cell WORD[42].W (WORD32)
    port Do[24] of cell WORD[43].W (WORD32)
    port Do[24] of cell WORD[44].W (WORD32)
    port Do[24] of cell WORD[45].W (WORD32)
    port Do[24] of cell WORD[46].W (WORD32)
    port Do[24] of cell WORD[47].W (WORD32)
    port Do[24] of cell WORD[48].W (WORD32)
    port Do[24] of cell WORD[49].W (WORD32)
    port Do[24] of cell WORD[4].W (WORD32)
    port Do[24] of cell WORD[50].W (WORD32)
    port Do[24] of cell WORD[51].W (WORD32)
    port Do[24] of cell WORD[52].W (WORD32)
    port Do[24] of cell WORD[53].W (WORD32)
    port Do[24] of cell WORD[54].W (WORD32)
    port Do[24] of cell WORD[55].W (WORD32)
    port Do[24] of cell WORD[56].W (WORD32)
    port Do[24] of cell WORD[57].W (WORD32)
    port Do[24] of cell WORD[58].W (WORD32)
    port Do[24] of cell WORD[59].W (WORD32)
    port Do[24] of cell WORD[5].W (WORD32)
    port Do[24] of cell WORD[60].W (WORD32)
    port Do[24] of cell WORD[61].W (WORD32)
    port Do[24] of cell WORD[62].W (WORD32)
    port Do[24] of cell WORD[63].W (WORD32)
    port Do[24] of cell WORD[6].W (WORD32)
    port Do[24] of cell WORD[7].W (WORD32)
    port Do[24] of cell WORD[8].W (WORD32)
    port Do[24] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[23]:
    port Z[0] of cell FLOATBUF[23] (sky130_fd_sc_hd__ebufn_4)
    port Do[23] of cell WORD[0].W (WORD32)
    port Do[23] of cell WORD[10].W (WORD32)
    port Do[23] of cell WORD[11].W (WORD32)
    port Do[23] of cell WORD[12].W (WORD32)
    port Do[23] of cell WORD[13].W (WORD32)
    port Do[23] of cell WORD[14].W (WORD32)
    port Do[23] of cell WORD[15].W (WORD32)
    port Do[23] of cell WORD[16].W (WORD32)
    port Do[23] of cell WORD[17].W (WORD32)
    port Do[23] of cell WORD[18].W (WORD32)
    port Do[23] of cell WORD[19].W (WORD32)
    port Do[23] of cell WORD[1].W (WORD32)
    port Do[23] of cell WORD[20].W (WORD32)
    port Do[23] of cell WORD[21].W (WORD32)
    port Do[23] of cell WORD[22].W (WORD32)
    port Do[23] of cell WORD[23].W (WORD32)
    port Do[23] of cell WORD[24].W (WORD32)
    port Do[23] of cell WORD[25].W (WORD32)
    port Do[23] of cell WORD[26].W (WORD32)
    port Do[23] of cell WORD[27].W (WORD32)
    port Do[23] of cell WORD[28].W (WORD32)
    port Do[23] of cell WORD[29].W (WORD32)
    port Do[23] of cell WORD[2].W (WORD32)
    port Do[23] of cell WORD[30].W (WORD32)
    port Do[23] of cell WORD[31].W (WORD32)
    port Do[23] of cell WORD[32].W (WORD32)
    port Do[23] of cell WORD[33].W (WORD32)
    port Do[23] of cell WORD[34].W (WORD32)
    port Do[23] of cell WORD[35].W (WORD32)
    port Do[23] of cell WORD[36].W (WORD32)
    port Do[23] of cell WORD[37].W (WORD32)
    port Do[23] of cell WORD[38].W (WORD32)
    port Do[23] of cell WORD[39].W (WORD32)
    port Do[23] of cell WORD[3].W (WORD32)
    port Do[23] of cell WORD[40].W (WORD32)
    port Do[23] of cell WORD[41].W (WORD32)
    port Do[23] of cell WORD[42].W (WORD32)
    port Do[23] of cell WORD[43].W (WORD32)
    port Do[23] of cell WORD[44].W (WORD32)
    port Do[23] of cell WORD[45].W (WORD32)
    port Do[23] of cell WORD[46].W (WORD32)
    port Do[23] of cell WORD[47].W (WORD32)
    port Do[23] of cell WORD[48].W (WORD32)
    port Do[23] of cell WORD[49].W (WORD32)
    port Do[23] of cell WORD[4].W (WORD32)
    port Do[23] of cell WORD[50].W (WORD32)
    port Do[23] of cell WORD[51].W (WORD32)
    port Do[23] of cell WORD[52].W (WORD32)
    port Do[23] of cell WORD[53].W (WORD32)
    port Do[23] of cell WORD[54].W (WORD32)
    port Do[23] of cell WORD[55].W (WORD32)
    port Do[23] of cell WORD[56].W (WORD32)
    port Do[23] of cell WORD[57].W (WORD32)
    port Do[23] of cell WORD[58].W (WORD32)
    port Do[23] of cell WORD[59].W (WORD32)
    port Do[23] of cell WORD[5].W (WORD32)
    port Do[23] of cell WORD[60].W (WORD32)
    port Do[23] of cell WORD[61].W (WORD32)
    port Do[23] of cell WORD[62].W (WORD32)
    port Do[23] of cell WORD[63].W (WORD32)
    port Do[23] of cell WORD[6].W (WORD32)
    port Do[23] of cell WORD[7].W (WORD32)
    port Do[23] of cell WORD[8].W (WORD32)
    port Do[23] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[22]:
    port Z[0] of cell FLOATBUF[22] (sky130_fd_sc_hd__ebufn_4)
    port Do[22] of cell WORD[0].W (WORD32)
    port Do[22] of cell WORD[10].W (WORD32)
    port Do[22] of cell WORD[11].W (WORD32)
    port Do[22] of cell WORD[12].W (WORD32)
    port Do[22] of cell WORD[13].W (WORD32)
    port Do[22] of cell WORD[14].W (WORD32)
    port Do[22] of cell WORD[15].W (WORD32)
    port Do[22] of cell WORD[16].W (WORD32)
    port Do[22] of cell WORD[17].W (WORD32)
    port Do[22] of cell WORD[18].W (WORD32)
    port Do[22] of cell WORD[19].W (WORD32)
    port Do[22] of cell WORD[1].W (WORD32)
    port Do[22] of cell WORD[20].W (WORD32)
    port Do[22] of cell WORD[21].W (WORD32)
    port Do[22] of cell WORD[22].W (WORD32)
    port Do[22] of cell WORD[23].W (WORD32)
    port Do[22] of cell WORD[24].W (WORD32)
    port Do[22] of cell WORD[25].W (WORD32)
    port Do[22] of cell WORD[26].W (WORD32)
    port Do[22] of cell WORD[27].W (WORD32)
    port Do[22] of cell WORD[28].W (WORD32)
    port Do[22] of cell WORD[29].W (WORD32)
    port Do[22] of cell WORD[2].W (WORD32)
    port Do[22] of cell WORD[30].W (WORD32)
    port Do[22] of cell WORD[31].W (WORD32)
    port Do[22] of cell WORD[32].W (WORD32)
    port Do[22] of cell WORD[33].W (WORD32)
    port Do[22] of cell WORD[34].W (WORD32)
    port Do[22] of cell WORD[35].W (WORD32)
    port Do[22] of cell WORD[36].W (WORD32)
    port Do[22] of cell WORD[37].W (WORD32)
    port Do[22] of cell WORD[38].W (WORD32)
    port Do[22] of cell WORD[39].W (WORD32)
    port Do[22] of cell WORD[3].W (WORD32)
    port Do[22] of cell WORD[40].W (WORD32)
    port Do[22] of cell WORD[41].W (WORD32)
    port Do[22] of cell WORD[42].W (WORD32)
    port Do[22] of cell WORD[43].W (WORD32)
    port Do[22] of cell WORD[44].W (WORD32)
    port Do[22] of cell WORD[45].W (WORD32)
    port Do[22] of cell WORD[46].W (WORD32)
    port Do[22] of cell WORD[47].W (WORD32)
    port Do[22] of cell WORD[48].W (WORD32)
    port Do[22] of cell WORD[49].W (WORD32)
    port Do[22] of cell WORD[4].W (WORD32)
    port Do[22] of cell WORD[50].W (WORD32)
    port Do[22] of cell WORD[51].W (WORD32)
    port Do[22] of cell WORD[52].W (WORD32)
    port Do[22] of cell WORD[53].W (WORD32)
    port Do[22] of cell WORD[54].W (WORD32)
    port Do[22] of cell WORD[55].W (WORD32)
    port Do[22] of cell WORD[56].W (WORD32)
    port Do[22] of cell WORD[57].W (WORD32)
    port Do[22] of cell WORD[58].W (WORD32)
    port Do[22] of cell WORD[59].W (WORD32)
    port Do[22] of cell WORD[5].W (WORD32)
    port Do[22] of cell WORD[60].W (WORD32)
    port Do[22] of cell WORD[61].W (WORD32)
    port Do[22] of cell WORD[62].W (WORD32)
    port Do[22] of cell WORD[63].W (WORD32)
    port Do[22] of cell WORD[6].W (WORD32)
    port Do[22] of cell WORD[7].W (WORD32)
    port Do[22] of cell WORD[8].W (WORD32)
    port Do[22] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[21]:
    port Z[0] of cell FLOATBUF[21] (sky130_fd_sc_hd__ebufn_4)
    port Do[21] of cell WORD[0].W (WORD32)
    port Do[21] of cell WORD[10].W (WORD32)
    port Do[21] of cell WORD[11].W (WORD32)
    port Do[21] of cell WORD[12].W (WORD32)
    port Do[21] of cell WORD[13].W (WORD32)
    port Do[21] of cell WORD[14].W (WORD32)
    port Do[21] of cell WORD[15].W (WORD32)
    port Do[21] of cell WORD[16].W (WORD32)
    port Do[21] of cell WORD[17].W (WORD32)
    port Do[21] of cell WORD[18].W (WORD32)
    port Do[21] of cell WORD[19].W (WORD32)
    port Do[21] of cell WORD[1].W (WORD32)
    port Do[21] of cell WORD[20].W (WORD32)
    port Do[21] of cell WORD[21].W (WORD32)
    port Do[21] of cell WORD[22].W (WORD32)
    port Do[21] of cell WORD[23].W (WORD32)
    port Do[21] of cell WORD[24].W (WORD32)
    port Do[21] of cell WORD[25].W (WORD32)
    port Do[21] of cell WORD[26].W (WORD32)
    port Do[21] of cell WORD[27].W (WORD32)
    port Do[21] of cell WORD[28].W (WORD32)
    port Do[21] of cell WORD[29].W (WORD32)
    port Do[21] of cell WORD[2].W (WORD32)
    port Do[21] of cell WORD[30].W (WORD32)
    port Do[21] of cell WORD[31].W (WORD32)
    port Do[21] of cell WORD[32].W (WORD32)
    port Do[21] of cell WORD[33].W (WORD32)
    port Do[21] of cell WORD[34].W (WORD32)
    port Do[21] of cell WORD[35].W (WORD32)
    port Do[21] of cell WORD[36].W (WORD32)
    port Do[21] of cell WORD[37].W (WORD32)
    port Do[21] of cell WORD[38].W (WORD32)
    port Do[21] of cell WORD[39].W (WORD32)
    port Do[21] of cell WORD[3].W (WORD32)
    port Do[21] of cell WORD[40].W (WORD32)
    port Do[21] of cell WORD[41].W (WORD32)
    port Do[21] of cell WORD[42].W (WORD32)
    port Do[21] of cell WORD[43].W (WORD32)
    port Do[21] of cell WORD[44].W (WORD32)
    port Do[21] of cell WORD[45].W (WORD32)
    port Do[21] of cell WORD[46].W (WORD32)
    port Do[21] of cell WORD[47].W (WORD32)
    port Do[21] of cell WORD[48].W (WORD32)
    port Do[21] of cell WORD[49].W (WORD32)
    port Do[21] of cell WORD[4].W (WORD32)
    port Do[21] of cell WORD[50].W (WORD32)
    port Do[21] of cell WORD[51].W (WORD32)
    port Do[21] of cell WORD[52].W (WORD32)
    port Do[21] of cell WORD[53].W (WORD32)
    port Do[21] of cell WORD[54].W (WORD32)
    port Do[21] of cell WORD[55].W (WORD32)
    port Do[21] of cell WORD[56].W (WORD32)
    port Do[21] of cell WORD[57].W (WORD32)
    port Do[21] of cell WORD[58].W (WORD32)
    port Do[21] of cell WORD[59].W (WORD32)
    port Do[21] of cell WORD[5].W (WORD32)
    port Do[21] of cell WORD[60].W (WORD32)
    port Do[21] of cell WORD[61].W (WORD32)
    port Do[21] of cell WORD[62].W (WORD32)
    port Do[21] of cell WORD[63].W (WORD32)
    port Do[21] of cell WORD[6].W (WORD32)
    port Do[21] of cell WORD[7].W (WORD32)
    port Do[21] of cell WORD[8].W (WORD32)
    port Do[21] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[20]:
    port Z[0] of cell FLOATBUF[20] (sky130_fd_sc_hd__ebufn_4)
    port Do[20] of cell WORD[0].W (WORD32)
    port Do[20] of cell WORD[10].W (WORD32)
    port Do[20] of cell WORD[11].W (WORD32)
    port Do[20] of cell WORD[12].W (WORD32)
    port Do[20] of cell WORD[13].W (WORD32)
    port Do[20] of cell WORD[14].W (WORD32)
    port Do[20] of cell WORD[15].W (WORD32)
    port Do[20] of cell WORD[16].W (WORD32)
    port Do[20] of cell WORD[17].W (WORD32)
    port Do[20] of cell WORD[18].W (WORD32)
    port Do[20] of cell WORD[19].W (WORD32)
    port Do[20] of cell WORD[1].W (WORD32)
    port Do[20] of cell WORD[20].W (WORD32)
    port Do[20] of cell WORD[21].W (WORD32)
    port Do[20] of cell WORD[22].W (WORD32)
    port Do[20] of cell WORD[23].W (WORD32)
    port Do[20] of cell WORD[24].W (WORD32)
    port Do[20] of cell WORD[25].W (WORD32)
    port Do[20] of cell WORD[26].W (WORD32)
    port Do[20] of cell WORD[27].W (WORD32)
    port Do[20] of cell WORD[28].W (WORD32)
    port Do[20] of cell WORD[29].W (WORD32)
    port Do[20] of cell WORD[2].W (WORD32)
    port Do[20] of cell WORD[30].W (WORD32)
    port Do[20] of cell WORD[31].W (WORD32)
    port Do[20] of cell WORD[32].W (WORD32)
    port Do[20] of cell WORD[33].W (WORD32)
    port Do[20] of cell WORD[34].W (WORD32)
    port Do[20] of cell WORD[35].W (WORD32)
    port Do[20] of cell WORD[36].W (WORD32)
    port Do[20] of cell WORD[37].W (WORD32)
    port Do[20] of cell WORD[38].W (WORD32)
    port Do[20] of cell WORD[39].W (WORD32)
    port Do[20] of cell WORD[3].W (WORD32)
    port Do[20] of cell WORD[40].W (WORD32)
    port Do[20] of cell WORD[41].W (WORD32)
    port Do[20] of cell WORD[42].W (WORD32)
    port Do[20] of cell WORD[43].W (WORD32)
    port Do[20] of cell WORD[44].W (WORD32)
    port Do[20] of cell WORD[45].W (WORD32)
    port Do[20] of cell WORD[46].W (WORD32)
    port Do[20] of cell WORD[47].W (WORD32)
    port Do[20] of cell WORD[48].W (WORD32)
    port Do[20] of cell WORD[49].W (WORD32)
    port Do[20] of cell WORD[4].W (WORD32)
    port Do[20] of cell WORD[50].W (WORD32)
    port Do[20] of cell WORD[51].W (WORD32)
    port Do[20] of cell WORD[52].W (WORD32)
    port Do[20] of cell WORD[53].W (WORD32)
    port Do[20] of cell WORD[54].W (WORD32)
    port Do[20] of cell WORD[55].W (WORD32)
    port Do[20] of cell WORD[56].W (WORD32)
    port Do[20] of cell WORD[57].W (WORD32)
    port Do[20] of cell WORD[58].W (WORD32)
    port Do[20] of cell WORD[59].W (WORD32)
    port Do[20] of cell WORD[5].W (WORD32)
    port Do[20] of cell WORD[60].W (WORD32)
    port Do[20] of cell WORD[61].W (WORD32)
    port Do[20] of cell WORD[62].W (WORD32)
    port Do[20] of cell WORD[63].W (WORD32)
    port Do[20] of cell WORD[6].W (WORD32)
    port Do[20] of cell WORD[7].W (WORD32)
    port Do[20] of cell WORD[8].W (WORD32)
    port Do[20] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[1]:
    port Z[0] of cell FLOATBUF[1] (sky130_fd_sc_hd__ebufn_4)
    port Do[1] of cell WORD[0].W (WORD32)
    port Do[1] of cell WORD[10].W (WORD32)
    port Do[1] of cell WORD[11].W (WORD32)
    port Do[1] of cell WORD[12].W (WORD32)
    port Do[1] of cell WORD[13].W (WORD32)
    port Do[1] of cell WORD[14].W (WORD32)
    port Do[1] of cell WORD[15].W (WORD32)
    port Do[1] of cell WORD[16].W (WORD32)
    port Do[1] of cell WORD[17].W (WORD32)
    port Do[1] of cell WORD[18].W (WORD32)
    port Do[1] of cell WORD[19].W (WORD32)
    port Do[1] of cell WORD[1].W (WORD32)
    port Do[1] of cell WORD[20].W (WORD32)
    port Do[1] of cell WORD[21].W (WORD32)
    port Do[1] of cell WORD[22].W (WORD32)
    port Do[1] of cell WORD[23].W (WORD32)
    port Do[1] of cell WORD[24].W (WORD32)
    port Do[1] of cell WORD[25].W (WORD32)
    port Do[1] of cell WORD[26].W (WORD32)
    port Do[1] of cell WORD[27].W (WORD32)
    port Do[1] of cell WORD[28].W (WORD32)
    port Do[1] of cell WORD[29].W (WORD32)
    port Do[1] of cell WORD[2].W (WORD32)
    port Do[1] of cell WORD[30].W (WORD32)
    port Do[1] of cell WORD[31].W (WORD32)
    port Do[1] of cell WORD[32].W (WORD32)
    port Do[1] of cell WORD[33].W (WORD32)
    port Do[1] of cell WORD[34].W (WORD32)
    port Do[1] of cell WORD[35].W (WORD32)
    port Do[1] of cell WORD[36].W (WORD32)
    port Do[1] of cell WORD[37].W (WORD32)
    port Do[1] of cell WORD[38].W (WORD32)
    port Do[1] of cell WORD[39].W (WORD32)
    port Do[1] of cell WORD[3].W (WORD32)
    port Do[1] of cell WORD[40].W (WORD32)
    port Do[1] of cell WORD[41].W (WORD32)
    port Do[1] of cell WORD[42].W (WORD32)
    port Do[1] of cell WORD[43].W (WORD32)
    port Do[1] of cell WORD[44].W (WORD32)
    port Do[1] of cell WORD[45].W (WORD32)
    port Do[1] of cell WORD[46].W (WORD32)
    port Do[1] of cell WORD[47].W (WORD32)
    port Do[1] of cell WORD[48].W (WORD32)
    port Do[1] of cell WORD[49].W (WORD32)
    port Do[1] of cell WORD[4].W (WORD32)
    port Do[1] of cell WORD[50].W (WORD32)
    port Do[1] of cell WORD[51].W (WORD32)
    port Do[1] of cell WORD[52].W (WORD32)
    port Do[1] of cell WORD[53].W (WORD32)
    port Do[1] of cell WORD[54].W (WORD32)
    port Do[1] of cell WORD[55].W (WORD32)
    port Do[1] of cell WORD[56].W (WORD32)
    port Do[1] of cell WORD[57].W (WORD32)
    port Do[1] of cell WORD[58].W (WORD32)
    port Do[1] of cell WORD[59].W (WORD32)
    port Do[1] of cell WORD[5].W (WORD32)
    port Do[1] of cell WORD[60].W (WORD32)
    port Do[1] of cell WORD[61].W (WORD32)
    port Do[1] of cell WORD[62].W (WORD32)
    port Do[1] of cell WORD[63].W (WORD32)
    port Do[1] of cell WORD[6].W (WORD32)
    port Do[1] of cell WORD[7].W (WORD32)
    port Do[1] of cell WORD[8].W (WORD32)
    port Do[1] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[19]:
    port Z[0] of cell FLOATBUF[19] (sky130_fd_sc_hd__ebufn_4)
    port Do[19] of cell WORD[0].W (WORD32)
    port Do[19] of cell WORD[10].W (WORD32)
    port Do[19] of cell WORD[11].W (WORD32)
    port Do[19] of cell WORD[12].W (WORD32)
    port Do[19] of cell WORD[13].W (WORD32)
    port Do[19] of cell WORD[14].W (WORD32)
    port Do[19] of cell WORD[15].W (WORD32)
    port Do[19] of cell WORD[16].W (WORD32)
    port Do[19] of cell WORD[17].W (WORD32)
    port Do[19] of cell WORD[18].W (WORD32)
    port Do[19] of cell WORD[19].W (WORD32)
    port Do[19] of cell WORD[1].W (WORD32)
    port Do[19] of cell WORD[20].W (WORD32)
    port Do[19] of cell WORD[21].W (WORD32)
    port Do[19] of cell WORD[22].W (WORD32)
    port Do[19] of cell WORD[23].W (WORD32)
    port Do[19] of cell WORD[24].W (WORD32)
    port Do[19] of cell WORD[25].W (WORD32)
    port Do[19] of cell WORD[26].W (WORD32)
    port Do[19] of cell WORD[27].W (WORD32)
    port Do[19] of cell WORD[28].W (WORD32)
    port Do[19] of cell WORD[29].W (WORD32)
    port Do[19] of cell WORD[2].W (WORD32)
    port Do[19] of cell WORD[30].W (WORD32)
    port Do[19] of cell WORD[31].W (WORD32)
    port Do[19] of cell WORD[32].W (WORD32)
    port Do[19] of cell WORD[33].W (WORD32)
    port Do[19] of cell WORD[34].W (WORD32)
    port Do[19] of cell WORD[35].W (WORD32)
    port Do[19] of cell WORD[36].W (WORD32)
    port Do[19] of cell WORD[37].W (WORD32)
    port Do[19] of cell WORD[38].W (WORD32)
    port Do[19] of cell WORD[39].W (WORD32)
    port Do[19] of cell WORD[3].W (WORD32)
    port Do[19] of cell WORD[40].W (WORD32)
    port Do[19] of cell WORD[41].W (WORD32)
    port Do[19] of cell WORD[42].W (WORD32)
    port Do[19] of cell WORD[43].W (WORD32)
    port Do[19] of cell WORD[44].W (WORD32)
    port Do[19] of cell WORD[45].W (WORD32)
    port Do[19] of cell WORD[46].W (WORD32)
    port Do[19] of cell WORD[47].W (WORD32)
    port Do[19] of cell WORD[48].W (WORD32)
    port Do[19] of cell WORD[49].W (WORD32)
    port Do[19] of cell WORD[4].W (WORD32)
    port Do[19] of cell WORD[50].W (WORD32)
    port Do[19] of cell WORD[51].W (WORD32)
    port Do[19] of cell WORD[52].W (WORD32)
    port Do[19] of cell WORD[53].W (WORD32)
    port Do[19] of cell WORD[54].W (WORD32)
    port Do[19] of cell WORD[55].W (WORD32)
    port Do[19] of cell WORD[56].W (WORD32)
    port Do[19] of cell WORD[57].W (WORD32)
    port Do[19] of cell WORD[58].W (WORD32)
    port Do[19] of cell WORD[59].W (WORD32)
    port Do[19] of cell WORD[5].W (WORD32)
    port Do[19] of cell WORD[60].W (WORD32)
    port Do[19] of cell WORD[61].W (WORD32)
    port Do[19] of cell WORD[62].W (WORD32)
    port Do[19] of cell WORD[63].W (WORD32)
    port Do[19] of cell WORD[6].W (WORD32)
    port Do[19] of cell WORD[7].W (WORD32)
    port Do[19] of cell WORD[8].W (WORD32)
    port Do[19] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[18]:
    port Z[0] of cell FLOATBUF[18] (sky130_fd_sc_hd__ebufn_4)
    port Do[18] of cell WORD[0].W (WORD32)
    port Do[18] of cell WORD[10].W (WORD32)
    port Do[18] of cell WORD[11].W (WORD32)
    port Do[18] of cell WORD[12].W (WORD32)
    port Do[18] of cell WORD[13].W (WORD32)
    port Do[18] of cell WORD[14].W (WORD32)
    port Do[18] of cell WORD[15].W (WORD32)
    port Do[18] of cell WORD[16].W (WORD32)
    port Do[18] of cell WORD[17].W (WORD32)
    port Do[18] of cell WORD[18].W (WORD32)
    port Do[18] of cell WORD[19].W (WORD32)
    port Do[18] of cell WORD[1].W (WORD32)
    port Do[18] of cell WORD[20].W (WORD32)
    port Do[18] of cell WORD[21].W (WORD32)
    port Do[18] of cell WORD[22].W (WORD32)
    port Do[18] of cell WORD[23].W (WORD32)
    port Do[18] of cell WORD[24].W (WORD32)
    port Do[18] of cell WORD[25].W (WORD32)
    port Do[18] of cell WORD[26].W (WORD32)
    port Do[18] of cell WORD[27].W (WORD32)
    port Do[18] of cell WORD[28].W (WORD32)
    port Do[18] of cell WORD[29].W (WORD32)
    port Do[18] of cell WORD[2].W (WORD32)
    port Do[18] of cell WORD[30].W (WORD32)
    port Do[18] of cell WORD[31].W (WORD32)
    port Do[18] of cell WORD[32].W (WORD32)
    port Do[18] of cell WORD[33].W (WORD32)
    port Do[18] of cell WORD[34].W (WORD32)
    port Do[18] of cell WORD[35].W (WORD32)
    port Do[18] of cell WORD[36].W (WORD32)
    port Do[18] of cell WORD[37].W (WORD32)
    port Do[18] of cell WORD[38].W (WORD32)
    port Do[18] of cell WORD[39].W (WORD32)
    port Do[18] of cell WORD[3].W (WORD32)
    port Do[18] of cell WORD[40].W (WORD32)
    port Do[18] of cell WORD[41].W (WORD32)
    port Do[18] of cell WORD[42].W (WORD32)
    port Do[18] of cell WORD[43].W (WORD32)
    port Do[18] of cell WORD[44].W (WORD32)
    port Do[18] of cell WORD[45].W (WORD32)
    port Do[18] of cell WORD[46].W (WORD32)
    port Do[18] of cell WORD[47].W (WORD32)
    port Do[18] of cell WORD[48].W (WORD32)
    port Do[18] of cell WORD[49].W (WORD32)
    port Do[18] of cell WORD[4].W (WORD32)
    port Do[18] of cell WORD[50].W (WORD32)
    port Do[18] of cell WORD[51].W (WORD32)
    port Do[18] of cell WORD[52].W (WORD32)
    port Do[18] of cell WORD[53].W (WORD32)
    port Do[18] of cell WORD[54].W (WORD32)
    port Do[18] of cell WORD[55].W (WORD32)
    port Do[18] of cell WORD[56].W (WORD32)
    port Do[18] of cell WORD[57].W (WORD32)
    port Do[18] of cell WORD[58].W (WORD32)
    port Do[18] of cell WORD[59].W (WORD32)
    port Do[18] of cell WORD[5].W (WORD32)
    port Do[18] of cell WORD[60].W (WORD32)
    port Do[18] of cell WORD[61].W (WORD32)
    port Do[18] of cell WORD[62].W (WORD32)
    port Do[18] of cell WORD[63].W (WORD32)
    port Do[18] of cell WORD[6].W (WORD32)
    port Do[18] of cell WORD[7].W (WORD32)
    port Do[18] of cell WORD[8].W (WORD32)
    port Do[18] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[17]:
    port Z[0] of cell FLOATBUF[17] (sky130_fd_sc_hd__ebufn_4)
    port Do[17] of cell WORD[0].W (WORD32)
    port Do[17] of cell WORD[10].W (WORD32)
    port Do[17] of cell WORD[11].W (WORD32)
    port Do[17] of cell WORD[12].W (WORD32)
    port Do[17] of cell WORD[13].W (WORD32)
    port Do[17] of cell WORD[14].W (WORD32)
    port Do[17] of cell WORD[15].W (WORD32)
    port Do[17] of cell WORD[16].W (WORD32)
    port Do[17] of cell WORD[17].W (WORD32)
    port Do[17] of cell WORD[18].W (WORD32)
    port Do[17] of cell WORD[19].W (WORD32)
    port Do[17] of cell WORD[1].W (WORD32)
    port Do[17] of cell WORD[20].W (WORD32)
    port Do[17] of cell WORD[21].W (WORD32)
    port Do[17] of cell WORD[22].W (WORD32)
    port Do[17] of cell WORD[23].W (WORD32)
    port Do[17] of cell WORD[24].W (WORD32)
    port Do[17] of cell WORD[25].W (WORD32)
    port Do[17] of cell WORD[26].W (WORD32)
    port Do[17] of cell WORD[27].W (WORD32)
    port Do[17] of cell WORD[28].W (WORD32)
    port Do[17] of cell WORD[29].W (WORD32)
    port Do[17] of cell WORD[2].W (WORD32)
    port Do[17] of cell WORD[30].W (WORD32)
    port Do[17] of cell WORD[31].W (WORD32)
    port Do[17] of cell WORD[32].W (WORD32)
    port Do[17] of cell WORD[33].W (WORD32)
    port Do[17] of cell WORD[34].W (WORD32)
    port Do[17] of cell WORD[35].W (WORD32)
    port Do[17] of cell WORD[36].W (WORD32)
    port Do[17] of cell WORD[37].W (WORD32)
    port Do[17] of cell WORD[38].W (WORD32)
    port Do[17] of cell WORD[39].W (WORD32)
    port Do[17] of cell WORD[3].W (WORD32)
    port Do[17] of cell WORD[40].W (WORD32)
    port Do[17] of cell WORD[41].W (WORD32)
    port Do[17] of cell WORD[42].W (WORD32)
    port Do[17] of cell WORD[43].W (WORD32)
    port Do[17] of cell WORD[44].W (WORD32)
    port Do[17] of cell WORD[45].W (WORD32)
    port Do[17] of cell WORD[46].W (WORD32)
    port Do[17] of cell WORD[47].W (WORD32)
    port Do[17] of cell WORD[48].W (WORD32)
    port Do[17] of cell WORD[49].W (WORD32)
    port Do[17] of cell WORD[4].W (WORD32)
    port Do[17] of cell WORD[50].W (WORD32)
    port Do[17] of cell WORD[51].W (WORD32)
    port Do[17] of cell WORD[52].W (WORD32)
    port Do[17] of cell WORD[53].W (WORD32)
    port Do[17] of cell WORD[54].W (WORD32)
    port Do[17] of cell WORD[55].W (WORD32)
    port Do[17] of cell WORD[56].W (WORD32)
    port Do[17] of cell WORD[57].W (WORD32)
    port Do[17] of cell WORD[58].W (WORD32)
    port Do[17] of cell WORD[59].W (WORD32)
    port Do[17] of cell WORD[5].W (WORD32)
    port Do[17] of cell WORD[60].W (WORD32)
    port Do[17] of cell WORD[61].W (WORD32)
    port Do[17] of cell WORD[62].W (WORD32)
    port Do[17] of cell WORD[63].W (WORD32)
    port Do[17] of cell WORD[6].W (WORD32)
    port Do[17] of cell WORD[7].W (WORD32)
    port Do[17] of cell WORD[8].W (WORD32)
    port Do[17] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[16]:
    port Z[0] of cell FLOATBUF[16] (sky130_fd_sc_hd__ebufn_4)
    port Do[16] of cell WORD[0].W (WORD32)
    port Do[16] of cell WORD[10].W (WORD32)
    port Do[16] of cell WORD[11].W (WORD32)
    port Do[16] of cell WORD[12].W (WORD32)
    port Do[16] of cell WORD[13].W (WORD32)
    port Do[16] of cell WORD[14].W (WORD32)
    port Do[16] of cell WORD[15].W (WORD32)
    port Do[16] of cell WORD[16].W (WORD32)
    port Do[16] of cell WORD[17].W (WORD32)
    port Do[16] of cell WORD[18].W (WORD32)
    port Do[16] of cell WORD[19].W (WORD32)
    port Do[16] of cell WORD[1].W (WORD32)
    port Do[16] of cell WORD[20].W (WORD32)
    port Do[16] of cell WORD[21].W (WORD32)
    port Do[16] of cell WORD[22].W (WORD32)
    port Do[16] of cell WORD[23].W (WORD32)
    port Do[16] of cell WORD[24].W (WORD32)
    port Do[16] of cell WORD[25].W (WORD32)
    port Do[16] of cell WORD[26].W (WORD32)
    port Do[16] of cell WORD[27].W (WORD32)
    port Do[16] of cell WORD[28].W (WORD32)
    port Do[16] of cell WORD[29].W (WORD32)
    port Do[16] of cell WORD[2].W (WORD32)
    port Do[16] of cell WORD[30].W (WORD32)
    port Do[16] of cell WORD[31].W (WORD32)
    port Do[16] of cell WORD[32].W (WORD32)
    port Do[16] of cell WORD[33].W (WORD32)
    port Do[16] of cell WORD[34].W (WORD32)
    port Do[16] of cell WORD[35].W (WORD32)
    port Do[16] of cell WORD[36].W (WORD32)
    port Do[16] of cell WORD[37].W (WORD32)
    port Do[16] of cell WORD[38].W (WORD32)
    port Do[16] of cell WORD[39].W (WORD32)
    port Do[16] of cell WORD[3].W (WORD32)
    port Do[16] of cell WORD[40].W (WORD32)
    port Do[16] of cell WORD[41].W (WORD32)
    port Do[16] of cell WORD[42].W (WORD32)
    port Do[16] of cell WORD[43].W (WORD32)
    port Do[16] of cell WORD[44].W (WORD32)
    port Do[16] of cell WORD[45].W (WORD32)
    port Do[16] of cell WORD[46].W (WORD32)
    port Do[16] of cell WORD[47].W (WORD32)
    port Do[16] of cell WORD[48].W (WORD32)
    port Do[16] of cell WORD[49].W (WORD32)
    port Do[16] of cell WORD[4].W (WORD32)
    port Do[16] of cell WORD[50].W (WORD32)
    port Do[16] of cell WORD[51].W (WORD32)
    port Do[16] of cell WORD[52].W (WORD32)
    port Do[16] of cell WORD[53].W (WORD32)
    port Do[16] of cell WORD[54].W (WORD32)
    port Do[16] of cell WORD[55].W (WORD32)
    port Do[16] of cell WORD[56].W (WORD32)
    port Do[16] of cell WORD[57].W (WORD32)
    port Do[16] of cell WORD[58].W (WORD32)
    port Do[16] of cell WORD[59].W (WORD32)
    port Do[16] of cell WORD[5].W (WORD32)
    port Do[16] of cell WORD[60].W (WORD32)
    port Do[16] of cell WORD[61].W (WORD32)
    port Do[16] of cell WORD[62].W (WORD32)
    port Do[16] of cell WORD[63].W (WORD32)
    port Do[16] of cell WORD[6].W (WORD32)
    port Do[16] of cell WORD[7].W (WORD32)
    port Do[16] of cell WORD[8].W (WORD32)
    port Do[16] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[15]:
    port Z[0] of cell FLOATBUF[15] (sky130_fd_sc_hd__ebufn_4)
    port Do[15] of cell WORD[0].W (WORD32)
    port Do[15] of cell WORD[10].W (WORD32)
    port Do[15] of cell WORD[11].W (WORD32)
    port Do[15] of cell WORD[12].W (WORD32)
    port Do[15] of cell WORD[13].W (WORD32)
    port Do[15] of cell WORD[14].W (WORD32)
    port Do[15] of cell WORD[15].W (WORD32)
    port Do[15] of cell WORD[16].W (WORD32)
    port Do[15] of cell WORD[17].W (WORD32)
    port Do[15] of cell WORD[18].W (WORD32)
    port Do[15] of cell WORD[19].W (WORD32)
    port Do[15] of cell WORD[1].W (WORD32)
    port Do[15] of cell WORD[20].W (WORD32)
    port Do[15] of cell WORD[21].W (WORD32)
    port Do[15] of cell WORD[22].W (WORD32)
    port Do[15] of cell WORD[23].W (WORD32)
    port Do[15] of cell WORD[24].W (WORD32)
    port Do[15] of cell WORD[25].W (WORD32)
    port Do[15] of cell WORD[26].W (WORD32)
    port Do[15] of cell WORD[27].W (WORD32)
    port Do[15] of cell WORD[28].W (WORD32)
    port Do[15] of cell WORD[29].W (WORD32)
    port Do[15] of cell WORD[2].W (WORD32)
    port Do[15] of cell WORD[30].W (WORD32)
    port Do[15] of cell WORD[31].W (WORD32)
    port Do[15] of cell WORD[32].W (WORD32)
    port Do[15] of cell WORD[33].W (WORD32)
    port Do[15] of cell WORD[34].W (WORD32)
    port Do[15] of cell WORD[35].W (WORD32)
    port Do[15] of cell WORD[36].W (WORD32)
    port Do[15] of cell WORD[37].W (WORD32)
    port Do[15] of cell WORD[38].W (WORD32)
    port Do[15] of cell WORD[39].W (WORD32)
    port Do[15] of cell WORD[3].W (WORD32)
    port Do[15] of cell WORD[40].W (WORD32)
    port Do[15] of cell WORD[41].W (WORD32)
    port Do[15] of cell WORD[42].W (WORD32)
    port Do[15] of cell WORD[43].W (WORD32)
    port Do[15] of cell WORD[44].W (WORD32)
    port Do[15] of cell WORD[45].W (WORD32)
    port Do[15] of cell WORD[46].W (WORD32)
    port Do[15] of cell WORD[47].W (WORD32)
    port Do[15] of cell WORD[48].W (WORD32)
    port Do[15] of cell WORD[49].W (WORD32)
    port Do[15] of cell WORD[4].W (WORD32)
    port Do[15] of cell WORD[50].W (WORD32)
    port Do[15] of cell WORD[51].W (WORD32)
    port Do[15] of cell WORD[52].W (WORD32)
    port Do[15] of cell WORD[53].W (WORD32)
    port Do[15] of cell WORD[54].W (WORD32)
    port Do[15] of cell WORD[55].W (WORD32)
    port Do[15] of cell WORD[56].W (WORD32)
    port Do[15] of cell WORD[57].W (WORD32)
    port Do[15] of cell WORD[58].W (WORD32)
    port Do[15] of cell WORD[59].W (WORD32)
    port Do[15] of cell WORD[5].W (WORD32)
    port Do[15] of cell WORD[60].W (WORD32)
    port Do[15] of cell WORD[61].W (WORD32)
    port Do[15] of cell WORD[62].W (WORD32)
    port Do[15] of cell WORD[63].W (WORD32)
    port Do[15] of cell WORD[6].W (WORD32)
    port Do[15] of cell WORD[7].W (WORD32)
    port Do[15] of cell WORD[8].W (WORD32)
    port Do[15] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[14]:
    port Z[0] of cell FLOATBUF[14] (sky130_fd_sc_hd__ebufn_4)
    port Do[14] of cell WORD[0].W (WORD32)
    port Do[14] of cell WORD[10].W (WORD32)
    port Do[14] of cell WORD[11].W (WORD32)
    port Do[14] of cell WORD[12].W (WORD32)
    port Do[14] of cell WORD[13].W (WORD32)
    port Do[14] of cell WORD[14].W (WORD32)
    port Do[14] of cell WORD[15].W (WORD32)
    port Do[14] of cell WORD[16].W (WORD32)
    port Do[14] of cell WORD[17].W (WORD32)
    port Do[14] of cell WORD[18].W (WORD32)
    port Do[14] of cell WORD[19].W (WORD32)
    port Do[14] of cell WORD[1].W (WORD32)
    port Do[14] of cell WORD[20].W (WORD32)
    port Do[14] of cell WORD[21].W (WORD32)
    port Do[14] of cell WORD[22].W (WORD32)
    port Do[14] of cell WORD[23].W (WORD32)
    port Do[14] of cell WORD[24].W (WORD32)
    port Do[14] of cell WORD[25].W (WORD32)
    port Do[14] of cell WORD[26].W (WORD32)
    port Do[14] of cell WORD[27].W (WORD32)
    port Do[14] of cell WORD[28].W (WORD32)
    port Do[14] of cell WORD[29].W (WORD32)
    port Do[14] of cell WORD[2].W (WORD32)
    port Do[14] of cell WORD[30].W (WORD32)
    port Do[14] of cell WORD[31].W (WORD32)
    port Do[14] of cell WORD[32].W (WORD32)
    port Do[14] of cell WORD[33].W (WORD32)
    port Do[14] of cell WORD[34].W (WORD32)
    port Do[14] of cell WORD[35].W (WORD32)
    port Do[14] of cell WORD[36].W (WORD32)
    port Do[14] of cell WORD[37].W (WORD32)
    port Do[14] of cell WORD[38].W (WORD32)
    port Do[14] of cell WORD[39].W (WORD32)
    port Do[14] of cell WORD[3].W (WORD32)
    port Do[14] of cell WORD[40].W (WORD32)
    port Do[14] of cell WORD[41].W (WORD32)
    port Do[14] of cell WORD[42].W (WORD32)
    port Do[14] of cell WORD[43].W (WORD32)
    port Do[14] of cell WORD[44].W (WORD32)
    port Do[14] of cell WORD[45].W (WORD32)
    port Do[14] of cell WORD[46].W (WORD32)
    port Do[14] of cell WORD[47].W (WORD32)
    port Do[14] of cell WORD[48].W (WORD32)
    port Do[14] of cell WORD[49].W (WORD32)
    port Do[14] of cell WORD[4].W (WORD32)
    port Do[14] of cell WORD[50].W (WORD32)
    port Do[14] of cell WORD[51].W (WORD32)
    port Do[14] of cell WORD[52].W (WORD32)
    port Do[14] of cell WORD[53].W (WORD32)
    port Do[14] of cell WORD[54].W (WORD32)
    port Do[14] of cell WORD[55].W (WORD32)
    port Do[14] of cell WORD[56].W (WORD32)
    port Do[14] of cell WORD[57].W (WORD32)
    port Do[14] of cell WORD[58].W (WORD32)
    port Do[14] of cell WORD[59].W (WORD32)
    port Do[14] of cell WORD[5].W (WORD32)
    port Do[14] of cell WORD[60].W (WORD32)
    port Do[14] of cell WORD[61].W (WORD32)
    port Do[14] of cell WORD[62].W (WORD32)
    port Do[14] of cell WORD[63].W (WORD32)
    port Do[14] of cell WORD[6].W (WORD32)
    port Do[14] of cell WORD[7].W (WORD32)
    port Do[14] of cell WORD[8].W (WORD32)
    port Do[14] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[13]:
    port Z[0] of cell FLOATBUF[13] (sky130_fd_sc_hd__ebufn_4)
    port Do[13] of cell WORD[0].W (WORD32)
    port Do[13] of cell WORD[10].W (WORD32)
    port Do[13] of cell WORD[11].W (WORD32)
    port Do[13] of cell WORD[12].W (WORD32)
    port Do[13] of cell WORD[13].W (WORD32)
    port Do[13] of cell WORD[14].W (WORD32)
    port Do[13] of cell WORD[15].W (WORD32)
    port Do[13] of cell WORD[16].W (WORD32)
    port Do[13] of cell WORD[17].W (WORD32)
    port Do[13] of cell WORD[18].W (WORD32)
    port Do[13] of cell WORD[19].W (WORD32)
    port Do[13] of cell WORD[1].W (WORD32)
    port Do[13] of cell WORD[20].W (WORD32)
    port Do[13] of cell WORD[21].W (WORD32)
    port Do[13] of cell WORD[22].W (WORD32)
    port Do[13] of cell WORD[23].W (WORD32)
    port Do[13] of cell WORD[24].W (WORD32)
    port Do[13] of cell WORD[25].W (WORD32)
    port Do[13] of cell WORD[26].W (WORD32)
    port Do[13] of cell WORD[27].W (WORD32)
    port Do[13] of cell WORD[28].W (WORD32)
    port Do[13] of cell WORD[29].W (WORD32)
    port Do[13] of cell WORD[2].W (WORD32)
    port Do[13] of cell WORD[30].W (WORD32)
    port Do[13] of cell WORD[31].W (WORD32)
    port Do[13] of cell WORD[32].W (WORD32)
    port Do[13] of cell WORD[33].W (WORD32)
    port Do[13] of cell WORD[34].W (WORD32)
    port Do[13] of cell WORD[35].W (WORD32)
    port Do[13] of cell WORD[36].W (WORD32)
    port Do[13] of cell WORD[37].W (WORD32)
    port Do[13] of cell WORD[38].W (WORD32)
    port Do[13] of cell WORD[39].W (WORD32)
    port Do[13] of cell WORD[3].W (WORD32)
    port Do[13] of cell WORD[40].W (WORD32)
    port Do[13] of cell WORD[41].W (WORD32)
    port Do[13] of cell WORD[42].W (WORD32)
    port Do[13] of cell WORD[43].W (WORD32)
    port Do[13] of cell WORD[44].W (WORD32)
    port Do[13] of cell WORD[45].W (WORD32)
    port Do[13] of cell WORD[46].W (WORD32)
    port Do[13] of cell WORD[47].W (WORD32)
    port Do[13] of cell WORD[48].W (WORD32)
    port Do[13] of cell WORD[49].W (WORD32)
    port Do[13] of cell WORD[4].W (WORD32)
    port Do[13] of cell WORD[50].W (WORD32)
    port Do[13] of cell WORD[51].W (WORD32)
    port Do[13] of cell WORD[52].W (WORD32)
    port Do[13] of cell WORD[53].W (WORD32)
    port Do[13] of cell WORD[54].W (WORD32)
    port Do[13] of cell WORD[55].W (WORD32)
    port Do[13] of cell WORD[56].W (WORD32)
    port Do[13] of cell WORD[57].W (WORD32)
    port Do[13] of cell WORD[58].W (WORD32)
    port Do[13] of cell WORD[59].W (WORD32)
    port Do[13] of cell WORD[5].W (WORD32)
    port Do[13] of cell WORD[60].W (WORD32)
    port Do[13] of cell WORD[61].W (WORD32)
    port Do[13] of cell WORD[62].W (WORD32)
    port Do[13] of cell WORD[63].W (WORD32)
    port Do[13] of cell WORD[6].W (WORD32)
    port Do[13] of cell WORD[7].W (WORD32)
    port Do[13] of cell WORD[8].W (WORD32)
    port Do[13] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[12]:
    port Z[0] of cell FLOATBUF[12] (sky130_fd_sc_hd__ebufn_4)
    port Do[12] of cell WORD[0].W (WORD32)
    port Do[12] of cell WORD[10].W (WORD32)
    port Do[12] of cell WORD[11].W (WORD32)
    port Do[12] of cell WORD[12].W (WORD32)
    port Do[12] of cell WORD[13].W (WORD32)
    port Do[12] of cell WORD[14].W (WORD32)
    port Do[12] of cell WORD[15].W (WORD32)
    port Do[12] of cell WORD[16].W (WORD32)
    port Do[12] of cell WORD[17].W (WORD32)
    port Do[12] of cell WORD[18].W (WORD32)
    port Do[12] of cell WORD[19].W (WORD32)
    port Do[12] of cell WORD[1].W (WORD32)
    port Do[12] of cell WORD[20].W (WORD32)
    port Do[12] of cell WORD[21].W (WORD32)
    port Do[12] of cell WORD[22].W (WORD32)
    port Do[12] of cell WORD[23].W (WORD32)
    port Do[12] of cell WORD[24].W (WORD32)
    port Do[12] of cell WORD[25].W (WORD32)
    port Do[12] of cell WORD[26].W (WORD32)
    port Do[12] of cell WORD[27].W (WORD32)
    port Do[12] of cell WORD[28].W (WORD32)
    port Do[12] of cell WORD[29].W (WORD32)
    port Do[12] of cell WORD[2].W (WORD32)
    port Do[12] of cell WORD[30].W (WORD32)
    port Do[12] of cell WORD[31].W (WORD32)
    port Do[12] of cell WORD[32].W (WORD32)
    port Do[12] of cell WORD[33].W (WORD32)
    port Do[12] of cell WORD[34].W (WORD32)
    port Do[12] of cell WORD[35].W (WORD32)
    port Do[12] of cell WORD[36].W (WORD32)
    port Do[12] of cell WORD[37].W (WORD32)
    port Do[12] of cell WORD[38].W (WORD32)
    port Do[12] of cell WORD[39].W (WORD32)
    port Do[12] of cell WORD[3].W (WORD32)
    port Do[12] of cell WORD[40].W (WORD32)
    port Do[12] of cell WORD[41].W (WORD32)
    port Do[12] of cell WORD[42].W (WORD32)
    port Do[12] of cell WORD[43].W (WORD32)
    port Do[12] of cell WORD[44].W (WORD32)
    port Do[12] of cell WORD[45].W (WORD32)
    port Do[12] of cell WORD[46].W (WORD32)
    port Do[12] of cell WORD[47].W (WORD32)
    port Do[12] of cell WORD[48].W (WORD32)
    port Do[12] of cell WORD[49].W (WORD32)
    port Do[12] of cell WORD[4].W (WORD32)
    port Do[12] of cell WORD[50].W (WORD32)
    port Do[12] of cell WORD[51].W (WORD32)
    port Do[12] of cell WORD[52].W (WORD32)
    port Do[12] of cell WORD[53].W (WORD32)
    port Do[12] of cell WORD[54].W (WORD32)
    port Do[12] of cell WORD[55].W (WORD32)
    port Do[12] of cell WORD[56].W (WORD32)
    port Do[12] of cell WORD[57].W (WORD32)
    port Do[12] of cell WORD[58].W (WORD32)
    port Do[12] of cell WORD[59].W (WORD32)
    port Do[12] of cell WORD[5].W (WORD32)
    port Do[12] of cell WORD[60].W (WORD32)
    port Do[12] of cell WORD[61].W (WORD32)
    port Do[12] of cell WORD[62].W (WORD32)
    port Do[12] of cell WORD[63].W (WORD32)
    port Do[12] of cell WORD[6].W (WORD32)
    port Do[12] of cell WORD[7].W (WORD32)
    port Do[12] of cell WORD[8].W (WORD32)
    port Do[12] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[11]:
    port Z[0] of cell FLOATBUF[11] (sky130_fd_sc_hd__ebufn_4)
    port Do[11] of cell WORD[0].W (WORD32)
    port Do[11] of cell WORD[10].W (WORD32)
    port Do[11] of cell WORD[11].W (WORD32)
    port Do[11] of cell WORD[12].W (WORD32)
    port Do[11] of cell WORD[13].W (WORD32)
    port Do[11] of cell WORD[14].W (WORD32)
    port Do[11] of cell WORD[15].W (WORD32)
    port Do[11] of cell WORD[16].W (WORD32)
    port Do[11] of cell WORD[17].W (WORD32)
    port Do[11] of cell WORD[18].W (WORD32)
    port Do[11] of cell WORD[19].W (WORD32)
    port Do[11] of cell WORD[1].W (WORD32)
    port Do[11] of cell WORD[20].W (WORD32)
    port Do[11] of cell WORD[21].W (WORD32)
    port Do[11] of cell WORD[22].W (WORD32)
    port Do[11] of cell WORD[23].W (WORD32)
    port Do[11] of cell WORD[24].W (WORD32)
    port Do[11] of cell WORD[25].W (WORD32)
    port Do[11] of cell WORD[26].W (WORD32)
    port Do[11] of cell WORD[27].W (WORD32)
    port Do[11] of cell WORD[28].W (WORD32)
    port Do[11] of cell WORD[29].W (WORD32)
    port Do[11] of cell WORD[2].W (WORD32)
    port Do[11] of cell WORD[30].W (WORD32)
    port Do[11] of cell WORD[31].W (WORD32)
    port Do[11] of cell WORD[32].W (WORD32)
    port Do[11] of cell WORD[33].W (WORD32)
    port Do[11] of cell WORD[34].W (WORD32)
    port Do[11] of cell WORD[35].W (WORD32)
    port Do[11] of cell WORD[36].W (WORD32)
    port Do[11] of cell WORD[37].W (WORD32)
    port Do[11] of cell WORD[38].W (WORD32)
    port Do[11] of cell WORD[39].W (WORD32)
    port Do[11] of cell WORD[3].W (WORD32)
    port Do[11] of cell WORD[40].W (WORD32)
    port Do[11] of cell WORD[41].W (WORD32)
    port Do[11] of cell WORD[42].W (WORD32)
    port Do[11] of cell WORD[43].W (WORD32)
    port Do[11] of cell WORD[44].W (WORD32)
    port Do[11] of cell WORD[45].W (WORD32)
    port Do[11] of cell WORD[46].W (WORD32)
    port Do[11] of cell WORD[47].W (WORD32)
    port Do[11] of cell WORD[48].W (WORD32)
    port Do[11] of cell WORD[49].W (WORD32)
    port Do[11] of cell WORD[4].W (WORD32)
    port Do[11] of cell WORD[50].W (WORD32)
    port Do[11] of cell WORD[51].W (WORD32)
    port Do[11] of cell WORD[52].W (WORD32)
    port Do[11] of cell WORD[53].W (WORD32)
    port Do[11] of cell WORD[54].W (WORD32)
    port Do[11] of cell WORD[55].W (WORD32)
    port Do[11] of cell WORD[56].W (WORD32)
    port Do[11] of cell WORD[57].W (WORD32)
    port Do[11] of cell WORD[58].W (WORD32)
    port Do[11] of cell WORD[59].W (WORD32)
    port Do[11] of cell WORD[5].W (WORD32)
    port Do[11] of cell WORD[60].W (WORD32)
    port Do[11] of cell WORD[61].W (WORD32)
    port Do[11] of cell WORD[62].W (WORD32)
    port Do[11] of cell WORD[63].W (WORD32)
    port Do[11] of cell WORD[6].W (WORD32)
    port Do[11] of cell WORD[7].W (WORD32)
    port Do[11] of cell WORD[8].W (WORD32)
    port Do[11] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[10]:
    port Z[0] of cell FLOATBUF[10] (sky130_fd_sc_hd__ebufn_4)
    port Do[10] of cell WORD[0].W (WORD32)
    port Do[10] of cell WORD[10].W (WORD32)
    port Do[10] of cell WORD[11].W (WORD32)
    port Do[10] of cell WORD[12].W (WORD32)
    port Do[10] of cell WORD[13].W (WORD32)
    port Do[10] of cell WORD[14].W (WORD32)
    port Do[10] of cell WORD[15].W (WORD32)
    port Do[10] of cell WORD[16].W (WORD32)
    port Do[10] of cell WORD[17].W (WORD32)
    port Do[10] of cell WORD[18].W (WORD32)
    port Do[10] of cell WORD[19].W (WORD32)
    port Do[10] of cell WORD[1].W (WORD32)
    port Do[10] of cell WORD[20].W (WORD32)
    port Do[10] of cell WORD[21].W (WORD32)
    port Do[10] of cell WORD[22].W (WORD32)
    port Do[10] of cell WORD[23].W (WORD32)
    port Do[10] of cell WORD[24].W (WORD32)
    port Do[10] of cell WORD[25].W (WORD32)
    port Do[10] of cell WORD[26].W (WORD32)
    port Do[10] of cell WORD[27].W (WORD32)
    port Do[10] of cell WORD[28].W (WORD32)
    port Do[10] of cell WORD[29].W (WORD32)
    port Do[10] of cell WORD[2].W (WORD32)
    port Do[10] of cell WORD[30].W (WORD32)
    port Do[10] of cell WORD[31].W (WORD32)
    port Do[10] of cell WORD[32].W (WORD32)
    port Do[10] of cell WORD[33].W (WORD32)
    port Do[10] of cell WORD[34].W (WORD32)
    port Do[10] of cell WORD[35].W (WORD32)
    port Do[10] of cell WORD[36].W (WORD32)
    port Do[10] of cell WORD[37].W (WORD32)
    port Do[10] of cell WORD[38].W (WORD32)
    port Do[10] of cell WORD[39].W (WORD32)
    port Do[10] of cell WORD[3].W (WORD32)
    port Do[10] of cell WORD[40].W (WORD32)
    port Do[10] of cell WORD[41].W (WORD32)
    port Do[10] of cell WORD[42].W (WORD32)
    port Do[10] of cell WORD[43].W (WORD32)
    port Do[10] of cell WORD[44].W (WORD32)
    port Do[10] of cell WORD[45].W (WORD32)
    port Do[10] of cell WORD[46].W (WORD32)
    port Do[10] of cell WORD[47].W (WORD32)
    port Do[10] of cell WORD[48].W (WORD32)
    port Do[10] of cell WORD[49].W (WORD32)
    port Do[10] of cell WORD[4].W (WORD32)
    port Do[10] of cell WORD[50].W (WORD32)
    port Do[10] of cell WORD[51].W (WORD32)
    port Do[10] of cell WORD[52].W (WORD32)
    port Do[10] of cell WORD[53].W (WORD32)
    port Do[10] of cell WORD[54].W (WORD32)
    port Do[10] of cell WORD[55].W (WORD32)
    port Do[10] of cell WORD[56].W (WORD32)
    port Do[10] of cell WORD[57].W (WORD32)
    port Do[10] of cell WORD[58].W (WORD32)
    port Do[10] of cell WORD[59].W (WORD32)
    port Do[10] of cell WORD[5].W (WORD32)
    port Do[10] of cell WORD[60].W (WORD32)
    port Do[10] of cell WORD[61].W (WORD32)
    port Do[10] of cell WORD[62].W (WORD32)
    port Do[10] of cell WORD[63].W (WORD32)
    port Do[10] of cell WORD[6].W (WORD32)
    port Do[10] of cell WORD[7].W (WORD32)
    port Do[10] of cell WORD[8].W (WORD32)
    port Do[10] of cell WORD[9].W (WORD32)
Warning: multiple conflicting drivers for SRAM64x32.\Do_pre[0]:
    port Z[0] of cell FLOATBUF[0] (sky130_fd_sc_hd__ebufn_4)
    port Do[0] of cell WORD[0].W (WORD32)
    port Do[0] of cell WORD[10].W (WORD32)
    port Do[0] of cell WORD[11].W (WORD32)
    port Do[0] of cell WORD[12].W (WORD32)
    port Do[0] of cell WORD[13].W (WORD32)
    port Do[0] of cell WORD[14].W (WORD32)
    port Do[0] of cell WORD[15].W (WORD32)
    port Do[0] of cell WORD[16].W (WORD32)
    port Do[0] of cell WORD[17].W (WORD32)
    port Do[0] of cell WORD[18].W (WORD32)
    port Do[0] of cell WORD[19].W (WORD32)
    port Do[0] of cell WORD[1].W (WORD32)
    port Do[0] of cell WORD[20].W (WORD32)
    port Do[0] of cell WORD[21].W (WORD32)
    port Do[0] of cell WORD[22].W (WORD32)
    port Do[0] of cell WORD[23].W (WORD32)
    port Do[0] of cell WORD[24].W (WORD32)
    port Do[0] of cell WORD[25].W (WORD32)
    port Do[0] of cell WORD[26].W (WORD32)
    port Do[0] of cell WORD[27].W (WORD32)
    port Do[0] of cell WORD[28].W (WORD32)
    port Do[0] of cell WORD[29].W (WORD32)
    port Do[0] of cell WORD[2].W (WORD32)
    port Do[0] of cell WORD[30].W (WORD32)
    port Do[0] of cell WORD[31].W (WORD32)
    port Do[0] of cell WORD[32].W (WORD32)
    port Do[0] of cell WORD[33].W (WORD32)
    port Do[0] of cell WORD[34].W (WORD32)
    port Do[0] of cell WORD[35].W (WORD32)
    port Do[0] of cell WORD[36].W (WORD32)
    port Do[0] of cell WORD[37].W (WORD32)
    port Do[0] of cell WORD[38].W (WORD32)
    port Do[0] of cell WORD[39].W (WORD32)
    port Do[0] of cell WORD[3].W (WORD32)
    port Do[0] of cell WORD[40].W (WORD32)
    port Do[0] of cell WORD[41].W (WORD32)
    port Do[0] of cell WORD[42].W (WORD32)
    port Do[0] of cell WORD[43].W (WORD32)
    port Do[0] of cell WORD[44].W (WORD32)
    port Do[0] of cell WORD[45].W (WORD32)
    port Do[0] of cell WORD[46].W (WORD32)
    port Do[0] of cell WORD[47].W (WORD32)
    port Do[0] of cell WORD[48].W (WORD32)
    port Do[0] of cell WORD[49].W (WORD32)
    port Do[0] of cell WORD[4].W (WORD32)
    port Do[0] of cell WORD[50].W (WORD32)
    port Do[0] of cell WORD[51].W (WORD32)
    port Do[0] of cell WORD[52].W (WORD32)
    port Do[0] of cell WORD[53].W (WORD32)
    port Do[0] of cell WORD[54].W (WORD32)
    port Do[0] of cell WORD[55].W (WORD32)
    port Do[0] of cell WORD[56].W (WORD32)
    port Do[0] of cell WORD[57].W (WORD32)
    port Do[0] of cell WORD[58].W (WORD32)
    port Do[0] of cell WORD[59].W (WORD32)
    port Do[0] of cell WORD[5].W (WORD32)
    port Do[0] of cell WORD[60].W (WORD32)
    port Do[0] of cell WORD[61].W (WORD32)
    port Do[0] of cell WORD[62].W (WORD32)
    port Do[0] of cell WORD[63].W (WORD32)
    port Do[0] of cell WORD[6].W (WORD32)
    port Do[0] of cell WORD[7].W (WORD32)
    port Do[0] of cell WORD[8].W (WORD32)
    port Do[0] of cell WORD[9].W (WORD32)
checking module WORD32..
found and reported 32 problems.

10. Printing statistics.

=== BYTE ===

   Number of wires:                 16
   Number of wire bits:             30
   Number of public wires:          16
   Number of public wire bits:      30
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 19
     sky130_fd_sc_hd__and2_1         1
     sky130_fd_sc_hd__dfxtp_1        8
     sky130_fd_sc_hd__dlclkp_1       1
     sky130_fd_sc_hd__ebufn_2        8
     sky130_fd_sc_hd__inv_1          1

   Area for cell type \sky130_fd_sc_hd__and2_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__dfxtp_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__dlclkp_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__ebufn_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__inv_1 is unknown!

=== DEC2x4 ===

   Number of wires:                  3
   Number of wire bits:              7
   Number of public wires:           3
   Number of public wire bits:       7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     sky130_fd_sc_hd__and3_4         1
     sky130_fd_sc_hd__and3b_4        2
     sky130_fd_sc_hd__nor3b_4        1

   Area for cell type \sky130_fd_sc_hd__and3b_4 is unknown!
   Area for cell type \sky130_fd_sc_hd__nor3b_4 is unknown!

   Chip area for module '\DEC2x4': 11.260800

=== DEC3x8 ===

   Number of wires:                  3
   Number of wire bits:             12
   Number of public wires:           3
   Number of public wire bits:      12
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  8
     sky130_fd_sc_hd__and4_2         1
     sky130_fd_sc_hd__and4b_2        3
     sky130_fd_sc_hd__and4bb_2       3
     sky130_fd_sc_hd__nor4b_2        1

   Area for cell type \sky130_fd_sc_hd__and4_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__and4b_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__and4bb_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__nor4b_2 is unknown!

=== DEC6x64 ===

   Number of wires:                 14
   Number of wire bits:             82
   Number of public wires:          14
   Number of public wire bits:      82
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 12
     DEC3x8                          9
     sky130_fd_sc_hd__clkbuf_16      3

   Area for cell type \sky130_fd_sc_hd__clkbuf_16 is unknown!
   Area for cell type \DEC3x8 is unknown!

=== DFFRAM ===

   Number of wires:                 71
   Number of wire bits:            143
   Number of public wires:          71
   Number of public wire bits:     143
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 35
     DFFRAM_COL4                     1
     PASS                            1
     sky130_fd_sc_hd__clkbuf_4      33

   Area for cell type \sky130_fd_sc_hd__clkbuf_4 is unknown!
   Area for cell type \DFFRAM_COL4 is unknown!
   Area for cell type \PASS is unknown!

=== DFFRAM_COL4 ===

   Number of wires:                210
   Number of wire bits:            282
   Number of public wires:         210
   Number of public wire bits:     282
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 46
     DEC2x4                          1
     MUX4x1_32                       1
     SRAM64x32                       4
     sky130_fd_sc_hd__clkbuf_16      3
     sky130_fd_sc_hd__clkbuf_8      37

   Area for cell type \sky130_fd_sc_hd__clkbuf_16 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkbuf_8 is unknown!
   Area for cell type \DEC2x4 is unknown!
   Area for cell type \MUX4x1_32 is unknown!
   Area for cell type \SRAM64x32 is unknown!

=== MUX4x1_32 ===

   Number of wires:                  6
   Number of wire bits:            162
   Number of public wires:           6
   Number of public wire bits:     162
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     sky130_fd_sc_hd__mux4_1        32

   Area for cell type \sky130_fd_sc_hd__mux4_1 is unknown!

=== PASS ===

   Number of wires:                  2
   Number of wire bits:             64
   Number of public wires:           2
   Number of public wire bits:      64
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

=== SRAM64x32 ===

   Number of wires:                141
   Number of wire bits:            211
   Number of public wires:         141
   Number of public wire bits:     211
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                168
     DEC6x64                         1
     WORD32                         64
     sky130_fd_sc_hd__clkbuf_16     37
     sky130_fd_sc_hd__clkbuf_4       1
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfxtp_1       32
     sky130_fd_sc_hd__ebufn_4       32

   Area for cell type \sky130_fd_sc_hd__clkbuf_16 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkbuf_4 is unknown!
   Area for cell type \sky130_fd_sc_hd__dfxtp_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__ebufn_4 is unknown!
   Area for cell type \WORD32 is unknown!
   Area for cell type \DEC6x64 is unknown!

   Chip area for module '\SRAM64x32': 3.753600

=== WORD32 ===

   Number of wires:                  5
   Number of wire bits:             70
   Number of public wires:           5
   Number of public wire bits:      70
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     BYTE                            4

   Area for cell type \BYTE is unknown!

=== design hierarchy ===

   DFFRAM                            1
     DFFRAM_COL4                     1
       DEC2x4                        1
       MUX4x1_32                     1
       SRAM64x32                     4
         DEC6x64                     1
           DEC3x8                    9
         WORD32                     64
           BYTE                      4
     PASS                            1

   Number of wires:              18684
   Number of wire bits:          50902
   Number of public wires:       18684
   Number of public wire bits:   50902
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              20277
     sky130_fd_sc_hd__and2_1      1024
     sky130_fd_sc_hd__and3_4         1
     sky130_fd_sc_hd__and3b_4        2
     sky130_fd_sc_hd__and4_2        36
     sky130_fd_sc_hd__and4b_2      108
     sky130_fd_sc_hd__and4bb_2     108
     sky130_fd_sc_hd__clkbuf_16    163
     sky130_fd_sc_hd__clkbuf_4      37
     sky130_fd_sc_hd__clkbuf_8      37
     sky130_fd_sc_hd__conb_1         4
     sky130_fd_sc_hd__dfxtp_1     8320
     sky130_fd_sc_hd__dlclkp_1    1024
     sky130_fd_sc_hd__ebufn_2     8192
     sky130_fd_sc_hd__ebufn_4      128
     sky130_fd_sc_hd__inv_1       1024
     sky130_fd_sc_hd__mux4_1        32
     sky130_fd_sc_hd__nor3b_4        1
     sky130_fd_sc_hd__nor4b_2       36

   Chip area for top module '\DFFRAM': 26.275200

11. Executing Verilog backend.
Dumping module `\BYTE'.
Dumping module `\DEC2x4'.
Dumping module `\DEC3x8'.
Dumping module `\DEC6x64'.
Dumping module `\DFFRAM'.
Dumping module `\DFFRAM_COL4'.
Dumping module `\MUX4x1_32'.
Dumping module `\PASS'.
Dumping module `\SRAM64x32'.
Dumping module `\WORD32'.

Warnings: 32 unique messages, 32 total
End of script. Logfile hash: 93ef28fe03, CPU: user 1.91s system 0.04s, MEM: 42.19 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 48% 2x write_verilog (0 sec), 41% 2x read_liberty (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/DFFRAM/runs/DFFRAM/results/synthesis/DFFRAM.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Info: Added 185 rows of 1606 sites.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 738.96
[INFO]: Core area height: 503.24
[INFO]: Changing layout from 0 to /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def
Notice 0: Reading LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: DFFRAM
Notice 0:     Created 78 pins.
Notice 0:     Created 20277 components and 100828 component-terminals.
Notice 0:     Created 12163 nets and 60270 connections.
Notice 0: Finished DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def
Top-level design name: DFFRAM
Block boundaries: 0 0 750000 525000
Writing /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/verilog2def_openroad.def to /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def
Notice 0: Design: DFFRAM
Notice 0:     Created 78 pins.
Notice 0:     Created 20277 components and 100828 component-terminals.
Notice 0:     Created 12163 nets and 60270 connections.
Notice 0: Finished DEF file: /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 0
[INFO] #Original rows: 185
[INFO] #Cut rows: 0
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 370
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 4860
Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/DFFRAM/runs/DFFRAM/tmp/floorplan/ioPlacer.def to /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def
[INFO]: Running Placement...
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def
Notice 0: Design: DFFRAM
Notice 0:     Created 78 pins.
Notice 0:     Created 25507 components and 111288 component-terminals.
Notice 0:     Created 12163 nets and 60270 connections.
Notice 0: Finished DEF file: /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def
[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (744280, 514080)
[INFO] NumInstances = 25507
[INFO] NumPlaceInstances = 20277
[INFO] NumFixedInstances = 5230
[INFO] NumDummyInstances = 0
[INFO] NumNets = 12163
[INFO] NumPins = 60348
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (750000, 525000)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (744280, 514080)
[INFO] CoreArea = 371744032000
[INFO] NonPlaceInstsArea = 7469664000
[INFO] PlaceInstsArea = 298322364800
[INFO] Util(%) = 81.894974
[INFO] StdInstsArea = 298322364800
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 0.00127764 HPWL: 161817324
[InitialPlace]  Iter: 2 CG Error: 0.000647573 HPWL: 184741169
[InitialPlace]  Iter: 3 CG Error: 0.000195701 HPWL: 189760398
[InitialPlace]  Iter: 4 CG Error: 0.000103155 HPWL: 190814756
[InitialPlace]  Iter: 5 CG Error: 0.000107622 HPWL: 190736005
[InitialPlace]  Iter: 6 CG Error: 0.000729092 HPWL: 190804761
[InitialPlace]  Iter: 7 CG Error: 6.74333e-05 HPWL: 190489892
[InitialPlace]  Iter: 8 CG Error: 6.94999e-05 HPWL: 190662552
[InitialPlace]  Iter: 9 CG Error: 3.36633e-05 HPWL: 190512094
[InitialPlace]  Iter: 10 CG Error: 5.18533e-05 HPWL: 190610472
[InitialPlace]  Iter: 11 CG Error: 5.30023e-05 HPWL: 190560818
[InitialPlace]  Iter: 12 CG Error: 5.6628e-05 HPWL: 190648774
[InitialPlace]  Iter: 13 CG Error: 2.82688e-05 HPWL: 190494353
[InitialPlace]  Iter: 14 CG Error: 4.78211e-05 HPWL: 190642021
[InitialPlace]  Iter: 15 CG Error: 7.76779e-05 HPWL: 190535584
[InitialPlace]  Iter: 16 CG Error: 5.8144e-05 HPWL: 190662477
[InitialPlace]  Iter: 17 CG Error: 4.74044e-05 HPWL: 190534521
[InitialPlace]  Iter: 18 CG Error: 8.7525e-05 HPWL: 190605707
[InitialPlace]  Iter: 19 CG Error: 4.43859e-05 HPWL: 190518095
[InitialPlace]  Iter: 20 CG Error: 3.95577e-05 HPWL: 190642137
[INFO] FillerInit: NumGCells = 21032
[INFO] FillerInit: NumGNets = 12163
[INFO] FillerInit: NumGPins = 60348
[INFO] TargetDensity = 0.850000
[INFO] AveragePlaceInstArea = 14712352
[INFO] IdealBinArea = 17308648
[INFO] IdealBinCnt = 21477
[INFO] TotalBinArea = 371744032000
[INFO] BinCnt = (128, 128)
[INFO] BinSize = (5772, 3932)
[INFO] NumBins = 16384
[NesterovSolve] Iter: 1 overflow: 0.995306 HPWL: 43130518
[NesterovSolve] Iter: 10 overflow: 0.977331 HPWL: 99726567
[NesterovSolve] Iter: 20 overflow: 0.975976 HPWL: 107110791
[NesterovSolve] Iter: 30 overflow: 0.976886 HPWL: 105711777
[NesterovSolve] Iter: 40 overflow: 0.976318 HPWL: 106278897
[NesterovSolve] Iter: 50 overflow: 0.976224 HPWL: 107071456
[NesterovSolve] Iter: 60 overflow: 0.976781 HPWL: 106594415
[NesterovSolve] Iter: 70 overflow: 0.976044 HPWL: 106516226
[NesterovSolve] Iter: 80 overflow: 0.975906 HPWL: 106341252
[NesterovSolve] Iter: 90 overflow: 0.975995 HPWL: 106302937
[NesterovSolve] Iter: 100 overflow: 0.976049 HPWL: 106538513
[NesterovSolve] Iter: 110 overflow: 0.976237 HPWL: 106896123
[NesterovSolve] Iter: 120 overflow: 0.976414 HPWL: 107342467
[NesterovSolve] Iter: 130 overflow: 0.976962 HPWL: 107997356
[NesterovSolve] Iter: 140 overflow: 0.976717 HPWL: 109054210
[NesterovSolve] Iter: 150 overflow: 0.976401 HPWL: 110676803
[NesterovSolve] Iter: 160 overflow: 0.975101 HPWL: 113533106
[NesterovSolve] Iter: 170 overflow: 0.971804 HPWL: 117182924
[NesterovSolve] Iter: 180 overflow: 0.96735 HPWL: 119399228
[NesterovSolve] Iter: 190 overflow: 0.964292 HPWL: 120165690
[NesterovSolve] Iter: 200 overflow: 0.962187 HPWL: 122262991
[NesterovSolve] Iter: 210 overflow: 0.958776 HPWL: 129199761
[NesterovSolve] Iter: 220 overflow: 0.95496 HPWL: 138924197
[NesterovSolve] Iter: 230 overflow: 0.945282 HPWL: 149995824
[NesterovSolve] Iter: 240 overflow: 0.934061 HPWL: 161813746
[NesterovSolve] Iter: 250 overflow: 0.918891 HPWL: 177567756
[NesterovSolve] Iter: 260 overflow: 0.892171 HPWL: 195242312
[NesterovSolve] Iter: 270 overflow: 0.862029 HPWL: 211007793
[NesterovSolve] Iter: 280 overflow: 0.831092 HPWL: 226141550
[NesterovSolve] Iter: 290 overflow: 0.794426 HPWL: 240337866
[NesterovSolve] Iter: 300 overflow: 0.753771 HPWL: 252452894
[NesterovSolve] Iter: 310 overflow: 0.711305 HPWL: 261970837
[NesterovSolve] Iter: 320 overflow: 0.663584 HPWL: 268990076
[NesterovSolve] Iter: 330 overflow: 0.614988 HPWL: 286063253
[NesterovSolve] Iter: 340 overflow: 0.577547 HPWL: 295354800
[NesterovSolve] Iter: 350 overflow: 0.550713 HPWL: 289612266
[NesterovSolve] Iter: 360 overflow: 0.538835 HPWL: 283307432
[NesterovSolve] Iter: 370 overflow: 0.521607 HPWL: 280647967
[NesterovSolve] Iter: 380 overflow: 0.503481 HPWL: 278605790
[NesterovSolve] Iter: 390 overflow: 0.453249 HPWL: 275931027
[NesterovSolve] Iter: 400 overflow: 0.398416 HPWL: 272872388
[NesterovSolve] Iter: 410 overflow: 0.354364 HPWL: 271433471
[NesterovSolve] Iter: 420 overflow: 0.315779 HPWL: 269484710
[NesterovSolve] Iter: 430 overflow: 0.28182 HPWL: 271082485
[NesterovSolve] Iter: 440 overflow: 0.250037 HPWL: 273088649
[NesterovSolve] Iter: 450 overflow: 0.213562 HPWL: 274578155
[NesterovSolve] Iter: 460 overflow: 0.177968 HPWL: 276412564
[NesterovSolve] Iter: 470 overflow: 0.142648 HPWL: 277649984
[NesterovSolve] Iter: 480 overflow: 0.114138 HPWL: 279039612
[NesterovSolve] Finished with Overflow: 0.0988869
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/DFFRAM/runs/DFFRAM/results/floorplan/DFFRAM.floorplan.def to /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def
[INFO]: Running Detailed Placement...
===========================================================================
   Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 >    
   Developers : SangGi Do, Mingyu Woo                                      
===========================================================================
Parsed 10000 number of lines!!
Parsed 20000 number of lines!!
Parsed 30000 number of lines!!
Parsed 40000 number of lines!!
Parsed 50000 number of lines!!
Parsed 60000 number of lines!!
Reading /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef is Done

-------------------- INPUT FILES ----------------------------------
 benchmark name    : placement
 directory         : /project/openlane/DFFRAM/runs/DFFRAM/tmp
 lef               : /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef
 def               : /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def
-------------------------------------------------------------------
Parsed 10000 number of lines!!
Parsed 20000 number of lines!!
Parsed 30000 number of lines!!
Parsed 40000 number of lines!!
CoreArea: 
5520.000000 : 10880.000000 - 744280.000000 : 514080.000000
DieArea: 
0.000000 : 0.000000 - 738760.000000 : 503200.000000
Reading /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def is Done
-------------------- DESIGN ANALYSIS ------------------------------
  total cells              : 25507
  multi cells              : 0
  fixed cells              : 5230
  total nets               : 12163
  design area              : 3.71744e+11
  total f_area             : 7.46966e+09
  total m_area             : 2.98322e+11
  design util              : 81.895
  num rows                 : 185
  row height               : 2720
-------------------------------------------------------------------
 non_group_cell_region_assign done ..
 - - - - - - - - - - - - - - - - - - - - - - - - 
 non_group_cell_placement done .. 
 - - - - - - - - - - - - - - - - - - - - - - - - 
Reading /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def is Done
 DEF file write success !! 
 location : /project/openlane/DFFRAM/runs/DFFRAM/results/placement/DFFRAM.placement.def
-------------------------------------------------------------------
 tasks                          Wtime      Ctime
 Parser                         1.120      1.110
 resgin assign                  1.124      1.110
 pre-placement                  1.124      1.110
 non Group cell placement       1.215      1.200
 All                            1.224      1.210
 - - - - - EVALUATION - - - - - 
 AVG_displacement : 2936.64
 SUM_displacement : 7.49049e+07
 MAX_displacement : 49550
 - - - - - - - - - - - - - - - - 
[ERROR]: during executing: "opendp -lef /project/openlane/DFFRAM/runs/DFFRAM/tmp/merged.lef -def /project/openlane/DFFRAM/runs/DFFRAM/tmp/placement/replace.def -output_def /project/openlane/DFFRAM/runs/DFFRAM/results/placement/DFFRAM.placement.def |& tee >&@stdout /project/openlane/DFFRAM/runs/DFFRAM/logs/placement/opendp.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: segmentation violation

[ERROR]: Please check opendp  log file
[ERROR]: Dumping to /project/openlane/DFFRAM/runs/DFFRAM/error.log

    while executing
"try_catch opendp  -lef $::env(MERGED_LEF)  -def $::env(CURRENT_DEF)  -output_def $::env(opendp_result_file_tag).def  |& tee $::env(TERMINAL_OUTPUT) $:..."
    (procedure "detailed_placement" line 4)
    invoked from within
"detailed_placement"
    (procedure "run_placement" line 16)
    invoked from within
"run_placement"
    (procedure "run_non_interactive_mode" line 13)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: DFFRAM] Fehler 1

Submodule: digital_pll

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/digital_pll/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/digital_pll/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/digital_pll/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/digital_pll/runs/digital_pll
[WARNING]: Removing exisiting run /project/openlane/digital_pll/runs/digital_pll
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 1.84
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/digital_pll/../../verilog/rtl/digital_pll.v
Parsing Verilog input from `/project/openlane/digital_pll/../../verilog/rtl/digital_pll.v' to AST representation.
Generating RTLIL representation for module `\digital_pll_controller'.
Generating RTLIL representation for module `\delay_stage'.
Generating RTLIL representation for module `\start_stage'.
Generating RTLIL representation for module `\ring_osc2x13'.
Generating RTLIL representation for module `\digital_pll'.
Successfully finished Verilog frontend.

3. Executing HIERARCHY pass (managing design hierarchy).

3.1. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage

3.2. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage
Removed 0 unused modules.

4. Executing SYNTH pass.

4.1. Executing HIERARCHY pass (managing design hierarchy).

4.1.1. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage

4.1.2. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage
Removed 0 unused modules.

4.2. Executing PROC pass (convert processes to netlists).

4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 3 switch rules as full_case in process $proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54 in module digital_pll_controller.
Removed a total of 0 dead cases.

4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 0 assignments to connections.

4.2.4. Executing PROC_INIT pass (extract init attributes).

4.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \reset in `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.

4.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
     1/5: $0\oscbuf[2:0]
     2/5: $0\tval[6:0]
     3/5: $0\count1[4:0]
     4/5: $0\count0[4:0]
     5/5: $0\prep[2:0]

4.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

4.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\digital_pll_controller.\oscbuf' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$98' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\prep' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$99' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\count0' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$100' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\count1' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$101' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\tval' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$102' with positive edge clock and positive level reset.

4.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 7 empty switches in `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
Removing empty process `digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
Cleaned up 7 empty switches.

4.3. Executing FLATTEN pass (flatten design).
Deleting now unused module ring_osc2x13.
Deleting now unused module start_stage.
Deleting now unused module delay_stage.
Deleting now unused module digital_pll_controller.


4.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 2 unused cells and 23 unused wires.


4.6. Executing CHECK pass (checking for obvious problems).
checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:
    port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:
    port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8)
    port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:
    port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:
    port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:
    port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:
    port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:
    port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:
    port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:
    port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:
    port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:
    port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:
    port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:
    port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:
    port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:
    port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:
    port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:
    port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:
    port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:
    port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:
    port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:
    port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:
    port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:
    port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:
    port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:
    port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:
    port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
found and reported 26 problems.

4.7. Executing OPT pass (performing simple optimizations).

4.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.7.6. Executing OPT_DFF pass (perform DFF optimizations).

4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.7.9. Finished OPT passes. (There is nothing left to do.)

4.8. Executing FSM pass (extract and optimize FSM).

4.8.1. Executing FSM_DETECT pass (finding FSMs in design).

4.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

4.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

4.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

4.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

4.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

4.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

4.9. Executing OPT pass (performing simple optimizations).

4.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.9.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\pll_control.$procdff$99 ($adff) from module digital_pll (D = { \pll_control.prep [1:0] 1'1 }, Q = \pll_control.prep).
Adding EN signal on $flatten\pll_control.$procdff$102 ($adff) from module digital_pll (D = $flatten\pll_control.$procmux$81_Y, Q = \pll_control.tval).
Adding EN signal on $flatten\pll_control.$procdff$101 ($adff) from module digital_pll (D = \pll_control.count0, Q = \pll_control.count1).
Adding EN signal on $flatten\pll_control.$procdff$100 ($adff) from module digital_pll (D = $flatten\pll_control.$0\count0[4:0], Q = \pll_control.count0).

4.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 4 unused cells and 4 unused wires.


4.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.9.9. Rerunning OPT passes. (Maybe there is more to do..)

4.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.9.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.9.13. Executing OPT_DFF pass (perform DFF optimizations).

4.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.9.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.9.16. Finished OPT passes. (There is nothing left to do.)

4.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 1 bits (of 3) from port B of cell digital_pll.$auto$opt_dff.cc:218:make_patterns_logic$105 ($ne).
Removed cell digital_pll.$flatten\pll_control.$procmux$90 ($mux).
Removed cell digital_pll.$flatten\pll_control.$procmux$79 ($mux).
Removed cell digital_pll.$flatten\pll_control.$procmux$76 ($mux).
Removed cell digital_pll.$flatten\pll_control.$procmux$74 ($mux).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add).
Removed top 27 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub).
Removed top 25 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62 ($gt).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add).
Removed top 25 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add).
Removed top 25 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59 ($lt).
Removed top 5 bits (of 26) from mux cell digital_pll.$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28 ($mux).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$17 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$16 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$15 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$14 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$13 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$12 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$11 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$10 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$9 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$8 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$7 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$6 ($eq).
Removed top 3 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$5 ($eq).
Removed top 3 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$4 ($eq).
Removed top 4 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$3 ($eq).
Removed top 5 bits (of 26) from wire digital_pll.$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28_Y.

4.11. Executing PEEPOPT pass (run peephole optimizers).

4.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 5 unused wires.


4.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module digital_pll:
  creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add).
  creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add).
  creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1 ($add).
  creating $macc model for $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub).
  creating $alu model for $macc $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63.
  creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1.
  creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65.
  creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60.
  creating $alu model for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58 ($gt): new $alu
  creating $alu model for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62 ($gt): new $alu
  creating $alu model for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59 ($lt): new $alu
  creating $alu model for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:106$61 ($lt): merged with $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58.
  creating $alu cell for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59: $auto$alumacc.cc:485:replace_alu$121
  creating $alu cell for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62: $auto$alumacc.cc:485:replace_alu$126
  creating $alu cell for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58, $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:106$61: $auto$alumacc.cc:485:replace_alu$131
  creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60: $auto$alumacc.cc:485:replace_alu$142
  creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65: $auto$alumacc.cc:485:replace_alu$145
  creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1: $auto$alumacc.cc:485:replace_alu$148
  creating $alu cell for $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63: $auto$alumacc.cc:485:replace_alu$151
  created 7 $alu and 0 $macc cells.

4.14. Executing SHARE pass (SAT-based resource sharing).

4.15. Executing OPT pass (performing simple optimizations).

4.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.15.6. Executing OPT_DFF pass (perform DFF optimizations).

4.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 4 unused wires.


4.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.15.9. Rerunning OPT passes. (Maybe there is more to do..)

4.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.15.13. Executing OPT_DFF pass (perform DFF optimizations).

4.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.15.16. Finished OPT passes. (There is nothing left to do.)

4.16. Executing MEMORY pass.

4.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

4.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

4.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

4.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.18. Executing OPT pass (performing simple optimizations).

4.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.18.3. Executing OPT_DFF pass (perform DFF optimizations).

4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.18.5. Finished fast OPT passes.

4.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

4.20. Executing OPT pass (performing simple optimizations).

4.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29:
      Old ports: A={ 5'11111 $auto$wreduce.cc:454:run$117 [20:0] }, B=26'11111011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y
      New ports: A=$auto$wreduce.cc:454:run$117 [20:0], B=21'011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [25:21] = 5'11111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28:
      Old ports: A=21'111111111111111111111, B=21'011111111111111111111, Y=$auto$wreduce.cc:454:run$117 [20:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$117 [20]
      New connections: $auto$wreduce.cc:454:run$117 [19:0] = 20'11111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y, B=26'10111011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0] }, B=22'0011111011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [23:21] } = 4'1111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29:
      Old ports: A=$auto$wreduce.cc:454:run$117 [20:0], B=21'011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0]
      New ports: A={ $auto$wreduce.cc:454:run$117 [20] 1'1 }, B=2'00, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [19:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [13:0] } = 19'1111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y, B=26'10111011011011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }, B=22'0011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [23:21] } = 4'1111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30:
      Old ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0] }, B=22'0011111011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [14] }, B=3'000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [19:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [13:0] } = 19'1111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y, B=26'10101011011011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }, B=23'00011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [21] } = 3'111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }, B=22'0011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [14] }, B=4'0000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [16:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [13:0] } = 18'111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y, B=26'10101011010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }, B=23'00011010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [21] } = 3'111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }, B=23'00011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [14] }, B=5'00000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [16:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [13:0] } = 18'111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y, B=26'10101010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }, B=23'00010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [21] } = 3'111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }, B=23'00011010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [17] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [14] }, B=6'000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [13:0] } = 17'11111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y, B=26'00101010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }, B=24'000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [21] } = 2'11
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }, B=23'00010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [15:14] }, B=7'0000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [13:0] } = 16'1111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y, B=26'00100010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }, B=25'0000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [23] = 1'1
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35:
      Old ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }, B=24'000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [15:14] }, B=8'00000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [13:0] } = 16'1111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y, B=26'00100010000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }, B=25'0000010000011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:0] }
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [23] = 1'1
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }, B=25'0000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [15:14] }, B=9'000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [13:0] } = 16'1111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }, B=25'0000010000011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [18:17] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [15:14] }, B=10'0000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [18:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [13:0] } = 15'111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y, B=26'00000010000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [18:14] }, B=11'00000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [25:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [18:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [13:0] } = 15'111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y, B=26'00000000000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [25:20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [18:14] }, B=12'000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [25:14]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [13:0] = 14'11111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y, B=26'00000000000001111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [25:14] 1'1 }, B=13'0000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [25:13]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [12:0] = 13'1111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y, B=26'00000000000001111101111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [25:13] 1'1 }, B=14'00000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [7] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [12:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [6:0] } = 12'111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y, B=26'00000000000001111101111101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [7] 1'1 }, B=15'000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [12:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [6:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [0] } = 11'11111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y, B=26'00000000000001011101111101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [25:13] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [1] }, B=16'0000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [10:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [6:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [0] } = 10'1111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y, B=26'00000000000001011101101101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [1] }, B=17'00000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [10:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [3:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [0] } = 9'111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y, B=26'00000000000001010101101101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [11] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [1] }, B=18'000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [3:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [0] } = 8'11111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y, B=26'00000000000001010101101001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [4] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [1] }, B=19'0000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [0] } = 7'1111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y, B=26'00000000000001010101001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [2:1] }, B=20'00000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [0] } = 6'111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y, B=26'00000000000000010101001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [25:13] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [2:1] }, B=21'000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [0] } = 5'11111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y, B=26'00000000000000010001001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [9] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [2:1] }, B=22'0000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [0] } = 4'1111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y, B=26'00000000000000010001000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [5:4] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [2:1] }, B=23'00000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [5:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [0] } = 3'111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y, B=26'00000000000000000001000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [25:11] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [5:1] }, B=24'000000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [25:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [5:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [0] } = 2'11
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y, B=26'00000000000000000000000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [25:7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [5:1] }, B=25'0000000000000000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y [25:1]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y [0] = 1'1
  Optimizing cells in module \digital_pll.
Performed a total of 34 changes.

4.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.20.6. Executing OPT_SHARE pass.
    Found cells that share an operand and can be merged by moving the $mux $flatten\pll_control.$procmux$81 in front of them:
        $auto$alumacc.cc:485:replace_alu$151
        $auto$alumacc.cc:485:replace_alu$142

4.20.7. Executing OPT_DFF pass (perform DFF optimizations).

4.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 6 unused wires.


4.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.20.10. Rerunning OPT passes. (Maybe there is more to do..)

4.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $auto$opt_share.cc:241:merge_operators$157:
      Old ports: A=$auto$rtlil.cc:2123:Neg$155, B=7'0000001, Y=$auto$rtlil.cc:2218:Mux$158
      New ports: A=1'1, B=1'0, Y=$auto$rtlil.cc:2218:Mux$158 [1]
      New connections: { $auto$rtlil.cc:2218:Mux$158 [6:2] $auto$rtlil.cc:2218:Mux$158 [0] } = { $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] 1'1 }
  Optimizing cells in module \digital_pll.
Performed a total of 1 changes.

4.20.13. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.20.14. Executing OPT_SHARE pass.

4.20.15. Executing OPT_DFF pass (perform DFF optimizations).

4.20.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 2 unused wires.


4.20.17. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.20.18. Rerunning OPT passes. (Maybe there is more to do..)

4.20.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.20.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.20.21. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.

Removed a total of 1 cells.

4.20.22. Executing OPT_SHARE pass.

4.20.23. Executing OPT_DFF pass (perform DFF optimizations).

4.20.24. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 1 unused wires.


4.20.25. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.20.26. Rerunning OPT passes. (Maybe there is more to do..)

4.20.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


4.20.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

4.20.29. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.20.30. Executing OPT_SHARE pass.

4.20.31. Executing OPT_DFF pass (perform DFF optimizations).

4.20.32. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

4.20.33. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

4.20.34. Finished OPT passes. (There is nothing left to do.)

4.21. Executing TECHMAP pass (map to technology primitives).

4.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

4.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
Using extmapper simplemap for cells of type $adffe.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $adff.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $and.
Using template $paramod\_90_lcu\WIDTH=7 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=6 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=5 for cells of type $lcu.
No more expansions possible.


4.22. Executing OPT pass (performing simple optimizations).

4.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.

Removed a total of 121 cells.

4.22.3. Executing OPT_DFF pass (perform DFF optimizations).

4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 61 unused cells and 376 unused wires.


4.22.5. Finished fast OPT passes.

4.23. Executing ABC pass (technology mapping using ABC).

4.23.1. Extracting gate netlist of module `\digital_pll' to `/input.blif'..
Extracted 556 gates and 614 wires to a netlist network with 56 inputs and 43 outputs.

4.23.1.1. Executing ABC.
Running ABC command: /yosys-abc -s -f /abc.script 2>&1
ABC: ABC command line: "source /abc.script".
ABC: 
ABC: + read_blif /input.blif 
ABC: + read_library /stdcells.genlib 
ABC: Entered genlib library with 13 gates from file "/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif /output.blif 

4.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        4
ABC RESULTS:            ANDNOT cells:       89
ABC RESULTS:               MUX cells:       27
ABC RESULTS:              NAND cells:       17
ABC RESULTS:               NOR cells:       11
ABC RESULTS:               NOT cells:        6
ABC RESULTS:                OR cells:      331
ABC RESULTS:             ORNOT cells:       10
ABC RESULTS:              XNOR cells:       12
ABC RESULTS:               XOR cells:       19
ABC RESULTS:        internal signals:      515
ABC RESULTS:           input signals:       56
ABC RESULTS:          output signals:       43
Removing temp directory.

4.24. Executing OPT pass (performing simple optimizations).

4.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.


4.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

4.24.3. Executing OPT_DFF pass (perform DFF optimizations).

4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 242 unused wires.


4.24.5. Finished fast OPT passes.

4.25. Executing HIERARCHY pass (managing design hierarchy).

4.25.1. Analyzing design hierarchy..
Top module:  \digital_pll

4.25.2. Analyzing design hierarchy..
Top module:  \digital_pll
Removed 0 unused modules.

4.26. Printing statistics.

=== digital_pll ===

   Number of wires:                613
   Number of wire bits:            808
   Number of public wires:         120
   Number of public wire bits:     303
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                646
     $_ANDNOT_                      89
     $_AND_                          4
     $_DFFE_PP0N_                    8
     $_DFFE_PP0P_                   12
     $_DFF_PP0_                      3
     $_MUX_                         27
     $_NAND_                        17
     $_NOR_                         11
     $_NOT_                          6
     $_ORNOT_                       10
     $_OR_                         331
     $_XNOR_                        12
     $_XOR_                         19
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__or2_2          1

4.27. Executing CHECK pass (checking for obvious problems).
checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:
    port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:
    port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8)
    port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:
    port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:
    port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:
    port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:
    port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:
    port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:
    port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:
    port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:
    port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:
    port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:
    port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:
    port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:
    port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:
    port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:
    port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:
    port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:
    port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:
    port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:
    port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:
    port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:
    port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:
    port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:
    port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:
    port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:
    port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
found and reported 26 problems.

5. Executing SHARE pass (SAT-based resource sharing).

6. Executing OPT pass (performing simple optimizations).

6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

6.6. Executing OPT_DFF pass (perform DFF optimizations).

6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

6.9. Finished OPT passes. (There is nothing left to do.)

7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 24 unused wires.


8. Printing statistics.

=== digital_pll ===

   Number of wires:                589
   Number of wire bits:            667
   Number of public wires:          96
   Number of public wire bits:     162
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                646
     $_ANDNOT_                      89
     $_AND_                          4
     $_DFFE_PP0N_                    8
     $_DFFE_PP0P_                   12
     $_DFF_PP0_                      3
     $_MUX_                         27
     $_NAND_                        17
     $_NOR_                         11
     $_NOT_                          6
     $_ORNOT_                       10
     $_OR_                         331
     $_XNOR_                        12
     $_XOR_                         19
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__or2_2          1

9. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

9.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\digital_pll':
  mapped 23 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells.

10. Printing statistics.
[INFO]: ABC: WireLoad : S_2

=== digital_pll ===

   Number of wires:                632
   Number of wire bits:            710
   Number of public wires:          96
   Number of public wire bits:     162
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                689
     $_ANDNOT_                      89
     $_AND_                          4
     $_MUX_                         47
     $_NAND_                        17
     $_NOR_                         11
     $_NOT_                         29
     $_ORNOT_                       10
     $_OR_                         331
     $_XNOR_                        12
     $_XOR_                         19
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfrtp_4       23
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__or2_2          1

11. Executing ABC pass (technology mapping using ABC).

11.1. Extracting gate netlist of module `\digital_pll' to `/tmp/yosys-abc-LXniTP/input.blif'..
Extracted 569 gates and 626 wires to a netlist network with 56 inputs and 70 outputs.

11.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-LXniTP/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-LXniTP/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-LXniTP/input.blif 
ABC: + read_lib -w /project/openlane/digital_pll/runs/digital_pll/tmp/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.06 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/digital_pll/runs/digital_pll/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.08 sec
ABC: Memory =    1.92 MB. Time =     0.08 sec
ABC: + read_constr -v /project/openlane/digital_pll/runs/digital_pll/tmp/synthesis/yosys.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
ABC: Setting output load to be 17.650000.
ABC: + read_constr /project/openlane/digital_pll/runs/digital_pll/tmp/synthesis/yosys.sdc 
ABC: + fx 
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 10000 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 10000 
ABC: + 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =    270 ( 20.7 %)   Cap = 13.9 ff (  0.0 %)   Area =     3324.44 (100.0 %)   Delay =  3638.60 ps  (  8.1 %)               
ABC: Path  0 --       7 : 0    3 pi                        A =   0.00  Df =  27.5  -17.7 ps  S =  45.0 ps  Cin =  0.0 ff  Cout =  23.6 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --     133 : 1    5 sky130_fd_sc_hd__inv_8    A =  11.26  Df =  60.8   -2.8 ps  S =  44.0 ps  Cin = 17.7 ff  Cout =  22.9 ff  Cmax =1035.5 ff  G =  123  
ABC: Path  2 --     170 : 4    2 sky130_fd_sc_hd__o22a_4   A =  17.52  Df = 517.5  -65.9 ps  S =  80.4 ps  Cin =  4.6 ff  Cout =  22.0 ff  Cmax = 530.1 ff  G =  461  
ABC: Path  3 --     171 : 4    3 sky130_fd_sc_hd__o22a_4   A =  17.52  Df = 720.7 -118.1 ps  S =  58.3 ps  Cin =  4.6 ff  Cout =  13.8 ff  Cmax = 530.1 ff  G =  286  
ABC: Path  4 --     172 : 4    3 sky130_fd_sc_hd__a2bb2o_4 A =  20.02  Df = 945.1   -0.3 ps  S =  73.9 ps  Cin =  4.6 ff  Cout =  19.1 ff  Cmax = 502.6 ff  G =  388  
ABC: Path  5 --     176 : 3    2 sky130_fd_sc_hd__a21bo_4  A =  16.27  Df =1163.4  -87.3 ps  S =  48.1 ps  Cin =  3.9 ff  Cout =   9.5 ff  Cmax = 475.2 ff  G =  231  
ABC: Path  6 --     178 : 4    2 sky130_fd_sc_hd__a211o_4  A =  17.52  Df =1466.3 -257.2 ps  S =  92.2 ps  Cin =  4.6 ff  Cout =  27.6 ff  Cmax = 559.4 ff  G =  570  
ABC: Path  7 --     179 : 1    1 sky130_fd_sc_hd__inv_8    A =  11.26  Df =1519.7 -284.1 ps  S =  27.9 ps  Cin = 17.7 ff  Cout =   4.7 ff  Cmax =1035.5 ff  G =   25  
ABC: Path  8 --     180 : 3    1 sky130_fd_sc_hd__o21a_4   A =  15.01  Df =1634.2 -293.6 ps  S =  47.3 ps  Cin =  4.6 ff  Cout =   9.0 ff  Cmax = 510.0 ff  G =  182  
ABC: Path  9 --     186 : 3    1 sky130_fd_sc_hd__nor3_4   A =  16.27  Df =1663.8 -205.4 ps  S = 106.7 ps  Cin =  8.7 ff  Cout =   2.5 ff  Cmax = 153.8 ff  G =   27  
ABC: Path 10 --     189 : 2   10 sky130_fd_sc_hd__or2_4    A =   8.76  Df =1987.6 -274.2 ps  S = 202.1 ps  Cin =  2.4 ff  Cout =  64.6 ff  Cmax = 514.5 ff  G = 2551  
ABC: Path 11 --     207 : 3    3 sky130_fd_sc_hd__o21ai_4  A =  16.27  Df =2390.9   -7.7 ps  S = 170.3 ps  Cin =  8.8 ff  Cout =  16.1 ff  Cmax = 224.3 ff  G =  175  
ABC: Path 12 --     215 : 5    3 sky130_fd_sc_hd__a32o_4   A =  21.27  Df =2729.1  -98.3 ps  S =  79.2 ps  Cin =  4.3 ff  Cout =  16.1 ff  Cmax = 536.5 ff  G =  355  
ABC: Path 13 --     219 : 5    2 sky130_fd_sc_hd__a32o_4   A =  21.27  Df =3056.4 -210.9 ps  S =  66.1 ps  Cin =  4.3 ff  Cout =  11.3 ff  Cmax = 536.5 ff  G =  252  
ABC: Path 14 --     221 : 2    1 sky130_fd_sc_hd__or2_4    A =   8.76  Df =3301.2 -342.4 ps  S =  46.3 ps  Cin =  2.4 ff  Cout =   4.7 ff  Cmax = 514.5 ff  G =  186  
ABC: Path 15 --     223 : 5    1 sky130_fd_sc_hd__a32o_4   A =  21.27  Df =3638.6 -310.4 ps  S =  83.1 ps  Cin =  4.3 ff  Cout =  17.6 ff  Cmax = 536.5 ff  G =  407  
ABC: Start-point = pi6 (\pll_control.count0 [1]).  End-point = po16 ($auto$rtlil.cc:2290:MuxGate$2331).
ABC: + print_stats -m 
ABC: netlist                       : i/o =   56/   70  lat =    0  nd =   270  edge =    709  area =3324.55  delay =20.00  lev = 20
ABC: + write_blif /tmp/yosys-abc-LXniTP/output.blif 

11.1.2. Re-integrating ABC results.
ABC RESULTS:   sky130_fd_sc_hd__a211o_4 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__a21bo_4 cells:       21
ABC RESULTS:   sky130_fd_sc_hd__a21o_4 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__a21oi_4 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__a2bb2o_4 cells:       13
ABC RESULTS:   sky130_fd_sc_hd__a32o_4 cells:       10
ABC RESULTS:   sky130_fd_sc_hd__and2_4 cells:       11
ABC RESULTS:   sky130_fd_sc_hd__and3_4 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__and4_4 cells:       21
ABC RESULTS:   sky130_fd_sc_hd__buf_1 cells:       22
ABC RESULTS:   sky130_fd_sc_hd__inv_8 cells:       34
ABC RESULTS:   sky130_fd_sc_hd__nand2_4 cells:        8
ABC RESULTS:   sky130_fd_sc_hd__nand4_4 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__nor2_4 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__nor3_4 cells:        6
ABC RESULTS:   sky130_fd_sc_hd__nor4_4 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__o21a_4 cells:        7
ABC RESULTS:   sky130_fd_sc_hd__o21ai_4 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__o22a_4 cells:       11
ABC RESULTS:   sky130_fd_sc_hd__o32a_4 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__or2_4 cells:       55
ABC RESULTS:   sky130_fd_sc_hd__or3_4 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__or4_4 cells:       15
ABC RESULTS:   sky130_fd_sc_hd__xnor2_4 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__xor2_4 cells:        1
ABC RESULTS:        internal signals:      500
ABC RESULTS:           input signals:       56
ABC RESULTS:          output signals:       70
Removing temp directory.

12. Executing SETUNDEF pass (replace undef values with defined constants).

13. Executing HILOMAP pass (mapping to constant drivers).

14. Executing SPLITNETS pass (splitting up multi-bit signals).

15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 637 unused wires.


16. Executing INSBUF pass (insert buffer cells for connected wires).
Added digital_pll.$auto$insbuf.cc:79:execute$2637: \pll_control.clock -> \clockp [0]

17. Executing CHECK pass (checking for obvious problems).
checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:
    port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:
    port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8)
    port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:
    port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:
    port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:
    port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:
    port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:
    port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:
    port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:
    port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:
    port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:
    port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:
    port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:
    port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:
    port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:
    port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:
    port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:
    port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:
    port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:
    port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:
    port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:
    port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:
    port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:
    port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:
    port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:
    port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:
    port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
found and reported 26 problems.

18. Printing statistics.

=== digital_pll ===

   Number of wires:                369
   Number of wire bits:            399
   Number of public wires:         126
   Number of public wire bits:     156
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                391
     sky130_fd_sc_hd__a211o_4        4
     sky130_fd_sc_hd__a21bo_4       21
     sky130_fd_sc_hd__a21o_4         4
     sky130_fd_sc_hd__a21oi_4        2
     sky130_fd_sc_hd__a2bb2o_4      13
     sky130_fd_sc_hd__a32o_4        10
     sky130_fd_sc_hd__and2_4        11
     sky130_fd_sc_hd__and3_4         3
     sky130_fd_sc_hd__and4_4        21
     sky130_fd_sc_hd__buf_1         22
     sky130_fd_sc_hd__buf_2          1
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfrtp_4       23
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__inv_8         34
     sky130_fd_sc_hd__nand2_4        8
     sky130_fd_sc_hd__nand4_4        1
     sky130_fd_sc_hd__nor2_4         5
     sky130_fd_sc_hd__nor3_4         6
     sky130_fd_sc_hd__nor4_4         3
     sky130_fd_sc_hd__o21a_4         7
     sky130_fd_sc_hd__o21ai_4        5
     sky130_fd_sc_hd__o22a_4        11
     sky130_fd_sc_hd__o32a_4         2
     sky130_fd_sc_hd__or2_2          1
     sky130_fd_sc_hd__or2_4         55
     sky130_fd_sc_hd__or3_4          5
     sky130_fd_sc_hd__or4_4         15
     sky130_fd_sc_hd__xnor2_4        1
     sky130_fd_sc_hd__xor2_4         1

   Area for cell type \sky130_fd_sc_hd__buf_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkbuf_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkbuf_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkinv_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkinv_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__clkinv_8 is unknown!
   Area for cell type \sky130_fd_sc_hd__einvn_4 is unknown!
   Area for cell type \sky130_fd_sc_hd__einvn_8 is unknown!
   Area for cell type \sky130_fd_sc_hd__einvp_1 is unknown!
   Area for cell type \sky130_fd_sc_hd__einvp_2 is unknown!
   Area for cell type \sky130_fd_sc_hd__or2_2 is unknown!

   Chip area for module '\digital_pll': 3990.076800

19. Executing Verilog backend.
Dumping module `\digital_pll'.

Warnings: 26 unique messages, 78 total
End of script. Logfile hash: 835af948d2, CPU: user 3.12s system 0.08s, MEM: 43.74 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 45% 2x abc (2 sec), 10% 2x read_liberty (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Info: Added 43 rows of 254 sites.
[INFO] Extracting DIE_AREA and CORE_AREA from the floorplan
[INFO] Floorplanned on a die area of 0.0 0.0 128.205 138.925 (microns). Saving to /project/openlane/digital_pll/runs/digital_pll/reports/floorplan/verilog2def.die_area.rpt.
[INFO] Floorplanned on a core area of 5.52 10.88 122.36 127.84 (microns). Saving to /project/openlane/digital_pll/runs/digital_pll/reports/floorplan/verilog2def.core_area.rpt.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 116.84
[INFO]: Core area height: 116.96000000000001
[INFO]: Changing layout from 0 to /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def
[INFO]: Running IO Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 391 components and 2103 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def
#Macro blocks found: 0
Warning: using the default boundaries offset (5 microns)
Warning: using the default min distance between IO pins (2 tracks)
WARNING: force pin spread option has no effect when using random pin placement
 > Running IO placement
 * Num of slots          458
 * Num of I/O            37
 * Num of I/O w/sink     37
 * Num of I/O w/o sink   0
 * Slots Per Section     200
 * Slots Increase Factor 0.01
 * Usage Per Section     0.8
 * Usage Increase Factor 0.01
 * Force Pin Spread      1

WARNING: running random pin placement
RandomMode Even
 > IO placement done.
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/verilog2def_openroad.def to /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 391 components and 2103 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 0
[INFO] #Original rows: 43
[INFO] #Cut rows: 0
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 86
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 180
Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/floorplan/ioPlacer.def to /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def
[INFO]: Running Placement...
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 657 components and 2635 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def
[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (122360, 127840)
[INFO] NumInstances = 657
[INFO] NumPlaceInstances = 391
[INFO] NumFixedInstances = 266
[INFO] NumDummyInstances = 0
[INFO] NumNets = 399
[INFO] NumPins = 1357
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (128205, 138925)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (122360, 127840)
[INFO] CoreArea = 13665606400
[INFO] NonPlaceInstsArea = 548025600
[INFO] PlaceInstsArea = 4907206400
[INFO] Util(%) = 37.409386
[INFO] StdInstsArea = 4907206400
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 9.07291e-08 HPWL: 8510935
[InitialPlace]  Iter: 2 CG Error: 1.08554e-07 HPWL: 7551106
[InitialPlace]  Iter: 3 CG Error: 3.58893e-08 HPWL: 7577907
[InitialPlace]  Iter: 4 CG Error: 7.62758e-08 HPWL: 7586893
[InitialPlace]  Iter: 5 CG Error: 9.26014e-08 HPWL: 7594502
[INFO] FillerInit: NumGCells = 581
[INFO] FillerInit: NumGNets = 399
[INFO] FillerInit: NumGPins = 1357
[INFO] TargetDensity = 0.550000
[INFO] AveragePlaceInstArea = 12550400
[INFO] IdealBinArea = 22818908
[INFO] IdealBinCnt = 598
[INFO] TotalBinArea = 13665606400
[INFO] BinCnt = (16, 16)
[INFO] BinSize = (7303, 7310)
[INFO] NumBins = 256
[NesterovSolve] Iter: 1 overflow: 0.829049 HPWL: 5120479
[NesterovSolve] Iter: 10 overflow: 0.659243 HPWL: 6422500
[NesterovSolve] Iter: 20 overflow: 0.645066 HPWL: 6376095
[NesterovSolve] Iter: 30 overflow: 0.639655 HPWL: 6359602
[NesterovSolve] Iter: 40 overflow: 0.639009 HPWL: 6355749
[NesterovSolve] Iter: 50 overflow: 0.639255 HPWL: 6356390
[NesterovSolve] Iter: 60 overflow: 0.639833 HPWL: 6356298
[NesterovSolve] Iter: 70 overflow: 0.639345 HPWL: 6354037
[NesterovSolve] Iter: 80 overflow: 0.638459 HPWL: 6354082
[NesterovSolve] Iter: 90 overflow: 0.63835 HPWL: 6354720
[NesterovSolve] Iter: 100 overflow: 0.638407 HPWL: 6354278
[NesterovSolve] Iter: 110 overflow: 0.638583 HPWL: 6354843
[NesterovSolve] Iter: 120 overflow: 0.63842 HPWL: 6355911
[NesterovSolve] Iter: 130 overflow: 0.637903 HPWL: 6357122
[NesterovSolve] Iter: 140 overflow: 0.637205 HPWL: 6360954
[NesterovSolve] Iter: 150 overflow: 0.636317 HPWL: 6366812
[NesterovSolve] Iter: 160 overflow: 0.63491 HPWL: 6375721
[NesterovSolve] Iter: 170 overflow: 0.632598 HPWL: 6386753
[NesterovSolve] Iter: 180 overflow: 0.628515 HPWL: 6399743
[NesterovSolve] Iter: 190 overflow: 0.618267 HPWL: 6418631
[NesterovSolve] Iter: 200 overflow: 0.607508 HPWL: 6453097
[NesterovSolve] Iter: 210 overflow: 0.59483 HPWL: 6507751
[NesterovSolve] Iter: 220 overflow: 0.57804 HPWL: 6568625
[NesterovSolve] Iter: 230 overflow: 0.55541 HPWL: 6671420
[NesterovSolve] Iter: 240 overflow: 0.527597 HPWL: 6779189
[NesterovSolve] Iter: 250 overflow: 0.488521 HPWL: 6864908
[NesterovSolve] Iter: 260 overflow: 0.448009 HPWL: 6870369
[NesterovSolve] Iter: 270 overflow: 0.411036 HPWL: 6921435
[NesterovSolve] Iter: 280 overflow: 0.371938 HPWL: 7007490
[NesterovSolve] Iter: 290 overflow: 0.333982 HPWL: 7099616
[NesterovSolve] Iter: 300 overflow: 0.298876 HPWL: 7183504
[NesterovSolve] Iter: 310 overflow: 0.259567 HPWL: 7236857
[NesterovSolve] Iter: 320 overflow: 0.228557 HPWL: 7325040
[NesterovSolve] Iter: 330 overflow: 0.201717 HPWL: 7429722
[NesterovSolve] Iter: 340 overflow: 0.168847 HPWL: 7491825
[NesterovSolve] Iter: 350 overflow: 0.143018 HPWL: 7541160
[NesterovSolve] Iter: 360 overflow: 0.123883 HPWL: 7593098
[NesterovSolve] Iter: 370 overflow: 0.0987641 HPWL: 7634093
[NesterovSolve] Finished with Overflow: 0.0987641
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/results/floorplan/digital_pll.floorplan.def to /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def
[INFO]: Running OpenPhySyn Timing Optimization...
[INFO]: Trimming Liberty...
[OpenPhySyn] [2020-11-20 15:12:40.015] [info] Loaded 6 transforms.
[OpenPhySyn] [2020-11-20 15:12:42.302] [info] OpenPhySyn: 1.8.1
Warning: /project/openlane/digital_pll/runs/digital_pll/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 657 components and 2635 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
=============== Initial Reports =============
No paths found.
Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Initial area: 54552 um2
OpenPhySyn timing repair:
[OpenPhySyn] [2020-11-20 15:13:42.186] [info] Invoking repair_timing transform
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Buffer library: sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_1
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Inverter library: None
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Buffering: enabled
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Driver sizing: enabled
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Pin-swapping: enabled
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Mode: Timing-Driven
[OpenPhySyn] [2020-11-20 15:13:42.205] [info] Iteration 1
[OpenPhySyn] [2020-11-20 15:13:42.424] [info] No more violations or cannot find more optimal buffer
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Runtime: 0s
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Buffers: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Resize up: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Resize down: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Pin Swap: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Buffered nets: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Fanout violations: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Transition violations: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Capacitance violations: 0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Slack gain: 0.0
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Initial area: 5455
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] New area: 5455
[OpenPhySyn] [2020-11-20 15:13:42.425] [info] Finished repair_timing transform (0)
Added/updated 0 cells
=============== Final Reports =============
No paths found.
Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Final area: 54552 um2
Export optimized design
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/placement/replace.def to /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 657 components and 2635 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def
[INFO]: Changing netlist from /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis.v to /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis_optimized.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/digital_pll/runs/digital_pll/results/synthesis/digital_pll.synthesis_optimized.v, line 1422 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found.  Creating black box for PHY_86.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
tns 0.00
wns 0.00
[INFO]: Running Detailed Placement...
===========================================================================
   Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 >    
   Developers : SangGi Do, Mingyu Woo                                      
===========================================================================
Parsed 10000 number of lines!!
Parsed 20000 number of lines!!
Parsed 30000 number of lines!!
Parsed 40000 number of lines!!
Parsed 50000 number of lines!!
Parsed 60000 number of lines!!
Reading /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef is Done

-------------------- INPUT FILES ----------------------------------
 benchmark name    : placement
 directory         : /project/openlane/digital_pll/runs/digital_pll/tmp
 lef               : /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
 def               : /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def
-------------------------------------------------------------------
CoreArea: 
5520.000000 : 10880.000000 - 122360.000000 : 127840.000000
DieArea: 
0.000000 : 0.000000 - 116840.000000 : 116960.000000
Reading /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def is Done
-------------------- DESIGN ANALYSIS ------------------------------
  total cells              : 657
  multi cells              : 0
  fixed cells              : 266
  total nets               : 399
  design area              : 1.36656e+10
  total f_area             : 5.48026e+08
  total m_area             : 6.86408e+09
  design util              : 52.3274
  num rows                 : 43
  row height               : 2720
-------------------------------------------------------------------
 non_group_cell_region_assign done ..
 - - - - - - - - - - - - - - - - - - - - - - - - 
 non_group_cell_placement done .. 
 - - - - - - - - - - - - - - - - - - - - - - - - 
Reading /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def is Done
 DEF file write success !! 
 location : /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def
-------------------------------------------------------------------
 tasks                          Wtime      Ctime
 Parser                         0.198      0.180
 resgin assign                  0.198      0.180
 pre-placement                  0.198      0.180
 non Group cell placement       0.200      0.190
 All                            0.200      0.190
 - - - - - EVALUATION - - - - - 
 AVG_displacement : 2566.91
 SUM_displacement : 1.68646e+06
 MAX_displacement : 34227
 - - - - - - - - - - - - - - - - 
 GP HPWL          : 7781.67
 HPWL             : 9750.33
 avg_Disp_site    : 5.58023
 avg_Disp_row     : 0.943716
 delta_HPWL       : 25.2987
 ==== CHECK LEGALITY ==== 
 row_check ==>> PASS 
 site_check ==>> PASS 
 power_check ==>> PASS 
 edge_check ==>> PASS 
 placed_check ==>> PASS 
 overlap_check ==>> PASS 
 - - - - - < Program END > - - - - - 
[INFO]: Changing layout from /project/openlane/digital_pll/runs/digital_pll/tmp/placement/openphysyn.def to /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def
[INFO]: ::env(CLOCK_PORT) is not set
[WARNING]: Skipping CTS...
[INFO]: Generating PDN...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def
Notice 0: Design: digital_pll
Notice 0:     Created 37 pins.
Notice 0:     Created 657 components and 2635 component-terminals.
Notice 0:     Created 399 nets and 1320 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/results/placement/digital_pll.placement.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /project/openlane/digital_pll/pdn.tcl
Error: pdn.tcl, 20 can't read "::env(FP_PDN_CORE_RING_HWIDTH)": no such variable
[INFO] [PDNG-0008] Design Name is digital_pll
[INFO] [PDNG-0009] Reading technology data
[CRIT] [PDNG-0017] No stdcell grid specification found - no rails can be inserted
Execution stopped
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/new_pdn.tcl |& tee >&@stdout /project/openlane/digital_pll/runs/digital_pll/logs/floorplan/pdn.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check openroad  log file
[ERROR]: Dumping to /project/openlane/digital_pll/runs/digital_pll/error.log

    while executing
"try_catch openroad -exit $::env(SCRIPTS_DIR)/new_pdn.tcl  |& tee $::env(TERMINAL_OUTPUT) $::env(pdn_log_file_tag).log"
    (procedure "gen_pdn" line 8)
    invoked from within
"gen_pdn"
    (procedure "run_non_interactive_mode" line 15)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: digital_pll] Fehler 1

Submodule: gpio_control_block

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/gpio_control_block/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/gpio_control_block/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/gpio_control_block/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/gpio_control_block/runs/gpio_control_block
[WARNING]: Removing exisiting run /project/openlane/gpio_control_block/runs/gpio_control_block
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 3.68
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/gpio_control_block/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/gpio_control_block/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v
Parsing Verilog input from `/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:200)
Generating RTLIL representation for module `\gpio_control_block'.
Successfully finished Verilog frontend.

4. Executing HIERARCHY pass (managing design hierarchy).

4.1. Analyzing design hierarchy..
Top module:  \gpio_control_block

4.2. Analyzing design hierarchy..
Top module:  \gpio_control_block
Removed 0 unused modules.

5. Executing SYNTH pass.

5.1. Executing HIERARCHY pass (managing design hierarchy).

5.1.1. Analyzing design hierarchy..
Top module:  \gpio_control_block

5.1.2. Analyzing design hierarchy..
Top module:  \gpio_control_block
Removed 0 unused modules.

5.2. Executing PROC pass (convert processes to netlists).

5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8 in module gpio_control_block.
Marked 1 switch rules as full_case in process $proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:142$6 in module gpio_control_block.
Removed a total of 0 dead cases.

5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 12 redundant assignments.
Promoted 0 assignments to connections.

5.2.4. Executing PROC_INIT pass (extract init attributes).

5.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \int_reset in `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
Found async reset \int_reset in `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:142$6'.

5.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
     1/11: $0\gpio_dm[2:0]
     2/11: $0\gpio_vtrip_sel[0:0]
     3/11: $0\gpio_slow_sel[0:0]
     4/11: $0\gpio_ana_pol[0:0]
     5/11: $0\gpio_ana_sel[0:0]
     6/11: $0\gpio_ana_en[0:0]
     7/11: $0\gpio_ib_mode_sel[0:0]
     8/11: $0\gpio_inenb[0:0]
     9/11: $0\gpio_holdover[0:0]
    10/11: $0\gpio_outenb[0:0]
    11/11: $0\mgmt_ena[0:0]
Creating decoders for process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:142$6'.
     1/1: $0\shift_register[12:0]

5.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

5.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\gpio_control_block.\mgmt_ena' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$24' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_holdover' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$25' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_slow_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$26' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_vtrip_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$27' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_inenb' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$28' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_ib_mode_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$29' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_outenb' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$30' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_dm' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$31' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_ana_en' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$32' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_ana_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$33' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_ana_pol' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
  created $adff cell `$procdff$34' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\shift_register' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:142$6'.
  created $adff cell `$procdff$35' with positive edge clock and positive level reset.

5.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:152$8'.
Removing empty process `gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:142$6'.
Cleaned up 0 empty switches.

5.3. Executing FLATTEN pass (flatten design).

5.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.


5.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 1 unused cells and 23 unused wires.


5.6. Executing CHECK pass (checking for obvious problems).
checking module gpio_control_block..
found and reported 0 problems.

5.7. Executing OPT pass (performing simple optimizations).

5.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

5.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.

Removed a total of 1 cells.

5.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


5.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.

5.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.7.6. Executing OPT_DFF pass (perform DFF optimizations).

5.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 0 unused cells and 1 unused wires.


5.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

5.7.9. Rerunning OPT passes. (Maybe there is more to do..)

5.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


5.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.

5.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.7.13. Executing OPT_DFF pass (perform DFF optimizations).

5.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..

5.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

5.7.16. Finished OPT passes. (There is nothing left to do.)

5.8. Executing FSM pass (extract and optimize FSM).

5.8.1. Executing FSM_DETECT pass (finding FSMs in design).

5.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

5.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

5.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..

5.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

5.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

5.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

5.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

5.9. Executing OPT pass (performing simple optimizations).

5.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

5.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


5.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.

5.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.9.6. Executing OPT_DFF pass (perform DFF optimizations).

5.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..

5.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

5.9.9. Finished OPT passes. (There is nothing left to do.)

5.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 1 bits (of 2) from port B of cell gpio_control_block.$eq$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:206$18 ($eq).

5.11. Executing PEEPOPT pass (run peephole optimizers).

5.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..

5.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module gpio_control_block:
  created 0 $alu and 0 $macc cells.

5.14. Executing SHARE pass (SAT-based resource sharing).

5.15. Executing OPT pass (performing simple optimizations).

5.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

5.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


5.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.

5.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.15.6. Executing OPT_DFF pass (perform DFF optimizations).

5.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..

5.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

5.15.9. Finished OPT passes. (There is nothing left to do.)

5.16. Executing MEMORY pass.

5.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

5.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

5.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..

5.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

5.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..

5.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

5.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..

5.18. Executing OPT pass (performing simple optimizations).

5.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.


5.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.18.3. Executing OPT_DFF pass (perform DFF optimizations).

5.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 0 unused cells and 1 unused wires.


5.18.5. Finished fast OPT passes.

5.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

5.20. Executing OPT pass (performing simple optimizations).

5.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

5.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


5.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.

5.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.20.6. Executing OPT_SHARE pass.

5.20.7. Executing OPT_DFF pass (perform DFF optimizations).

5.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..

5.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

5.20.10. Finished OPT passes. (There is nothing left to do.)

5.21. Executing TECHMAP pass (map to technology primitives).

5.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

5.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $adff.
No more expansions possible.


5.22. Executing OPT pass (performing simple optimizations).

5.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.


5.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.22.3. Executing OPT_DFF pass (perform DFF optimizations).

5.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 1 unused cells and 3 unused wires.


5.22.5. Finished fast OPT passes.

5.23. Executing ABC pass (technology mapping using ABC).

5.23.1. Extracting gate netlist of module `\gpio_control_block' to `/input.blif'..
Extracted 15 gates and 28 wires to a netlist network with 12 inputs and 6 outputs.

5.23.1.1. Executing ABC.
Running ABC command: /yosys-abc -s -f /abc.script 2>&1
ABC: ABC command line: "source /abc.script".
ABC: 
ABC: + read_blif /input.blif 
ABC: + read_library /stdcells.genlib 
ABC: Entered genlib library with 13 gates from file "/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif /output.blif 

5.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        2
ABC RESULTS:            ANDNOT cells:        1
ABC RESULTS:               MUX cells:        4
ABC RESULTS:               NOR cells:        1
ABC RESULTS:               NOT cells:        2
ABC RESULTS:             ORNOT cells:        2
ABC RESULTS:        internal signals:       10
ABC RESULTS:           input signals:       12
ABC RESULTS:          output signals:        6
Removing temp directory.

5.24. Executing OPT pass (performing simple optimizations).

5.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.


5.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

5.24.3. Executing OPT_DFF pass (perform DFF optimizations).

5.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 1 unused cells and 28 unused wires.


5.24.5. Finished fast OPT passes.

5.25. Executing HIERARCHY pass (managing design hierarchy).

5.25.1. Analyzing design hierarchy..
Top module:  \gpio_control_block

5.25.2. Analyzing design hierarchy..
Top module:  \gpio_control_block
Removed 0 unused modules.

5.26. Printing statistics.

=== gpio_control_block ===

   Number of wires:                 43
   Number of wire bits:             59
   Number of public wires:          37
   Number of public wire bits:      53
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 39
     $_ANDNOT_                       1
     $_AND_                          2
     $_DFF_PP0_                     23
     $_DFF_PP1_                      3
     $_MUX_                          4
     $_NOR_                          1
     $_NOT_                          1
     $_ORNOT_                        2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__einvp_8        1

5.27. Executing CHECK pass (checking for obvious problems).
checking module gpio_control_block..
found and reported 0 problems.

6. Executing SHARE pass (SAT-based resource sharing).

7. Executing OPT pass (performing simple optimizations).

7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.

7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.

7.6. Executing OPT_DFF pass (perform DFF optimizations).

7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..

7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.

7.9. Finished OPT passes. (There is nothing left to do.)

8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 0 unused cells and 9 unused wires.


9. Printing statistics.

=== gpio_control_block ===

   Number of wires:                 34
   Number of wire bits:             48
   Number of public wires:          28
   Number of public wire bits:      42
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 39
     $_ANDNOT_                       1
     $_AND_                          2
     $_DFF_PP0_                     23
     $_DFF_PP1_                      3
     $_MUX_                          4
     $_NOR_                          1
     $_NOT_                          1
     $_ORNOT_                        2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__einvp_8        1

10. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

10.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\gpio_control_block':
  mapped 23 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells.
  mapped 3 $_DFF_PN1_ cells to \sky130_fd_sc_hd__dfstp_4 cells.

11. Printing statistics.
[INFO]: ABC: WireLoad : S_2

=== gpio_control_block ===

   Number of wires:                 60
   Number of wire bits:             74
   Number of public wires:          28
   Number of public wire bits:      42
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 65
     $_ANDNOT_                       1
     $_AND_                          2
     $_MUX_                          4
     $_NOR_                          1
     $_NOT_                         27
     $_ORNOT_                        2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfrtp_4       23
     sky130_fd_sc_hd__dfstp_4        3
     sky130_fd_sc_hd__einvp_8        1

12. Executing ABC pass (technology mapping using ABC).

12.1. Extracting gate netlist of module `\gpio_control_block' to `/tmp/yosys-abc-Hcq5yP/input.blif'..
Extracted 37 gates and 49 wires to a netlist network with 12 inputs and 31 outputs.

12.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-Hcq5yP/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-Hcq5yP/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-Hcq5yP/input.blif 
ABC: + read_lib -w /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.06 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/gpio_control_block/runs/gpio_control_block/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.08 sec
ABC: Memory =    1.92 MB. Time =     0.08 sec
ABC: + read_constr -v /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/synthesis/yosys.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
ABC: Setting output load to be 17.650000.
ABC: + read_constr /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/synthesis/yosys.sdc 
ABC: + fx 
ABC: The network is unchanged by fast extract.
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 10000 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 10000 
ABC: + buffer -N 5 -S 1000.0 
ABC: + upsize -D 10000 
ABC: Current delay (745.80 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 10000 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =     43 ( 79.1 %)   Cap = 14.0 ff (  0.0 %)   Area =      261.50 (100.0 %)   Delay =   745.80 ps  (  9.3 %)               
ABC: Path  0 --       6 : 0    1 pi                      A =   0.00  Df =  21.9  -14.3 ps  S =  37.7 ps  Cin =  0.0 ff  Cout =  18.5 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --      77 : 1    1 sky130_fd_sc_hd__inv_8  A =  11.26  Df =  41.3   -9.1 ps  S =  14.8 ps  Cin = 17.7 ff  Cout =   2.5 ff  Cmax =1035.5 ff  G =   13  
ABC: Path  2 --      78 : 3    2 sky130_fd_sc_hd__and3_4 A =  11.26  Df = 213.4  -12.7 ps  S =  64.9 ps  Cin =  2.4 ff  Cout =  11.8 ff  Cmax = 532.8 ff  G =  462  
ABC: Path  3 --      79 : 2    1 sky130_fd_sc_hd__or2_4  A =   8.76  Df = 421.3  -99.2 ps  S =  46.2 ps  Cin =  2.4 ff  Cout =   4.5 ff  Cmax = 514.5 ff  G =  179  
ABC: Path  4 --      81 : 5    1 sky130_fd_sc_hd__a32o_4 A =  21.27  Df = 745.8 -205.1 ps  S =  83.1 ps  Cin =  4.3 ff  Cout =  17.6 ff  Cmax = 536.5 ff  G =  407  
ABC: Start-point = pi5 (\pad_gpio_dm [2]).  End-point = po26 (\pad_gpio_out).
ABC: + print_stats -m 
ABC: netlist                       : i/o =   12/   31  lat =    0  nd =    43  edge =     59  area =261.39  delay = 4.00  lev = 4
ABC: + write_blif /tmp/yosys-abc-Hcq5yP/output.blif 

12.1.2. Re-integrating ABC results.
ABC RESULTS:   sky130_fd_sc_hd__a32o_4 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__and2_4 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__and3_4 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__buf_1 cells:       31
ABC RESULTS:   sky130_fd_sc_hd__inv_8 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__nand2_4 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__or2_4 cells:        2
ABC RESULTS:        internal signals:        6
ABC RESULTS:           input signals:       12
ABC RESULTS:          output signals:       31
Removing temp directory.

13. Executing SETUNDEF pass (replace undef values with defined constants).

14. Executing HILOMAP pass (mapping to constant drivers).

15. Executing SPLITNETS pass (splitting up multi-bit signals).

16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 0 unused cells and 50 unused wires.


17. Executing INSBUF pass (insert buffer cells for connected wires).

18. Executing CHECK pass (checking for obvious problems).
checking module gpio_control_block..
found and reported 0 problems.

19. Printing statistics.

=== gpio_control_block ===

   Number of wires:                 77
   Number of wire bits:             79
   Number of public wires:          38
   Number of public wire bits:      40
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 71
     sky130_fd_sc_hd__a32o_4         2
     sky130_fd_sc_hd__and2_4         2
     sky130_fd_sc_hd__and3_4         1
     sky130_fd_sc_hd__buf_1         31
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfrtp_4       23
     sky130_fd_sc_hd__dfstp_4        3
     sky130_fd_sc_hd__einvp_8        1
     sky130_fd_sc_hd__inv_8          3
     sky130_fd_sc_hd__nand2_4        2
     sky130_fd_sc_hd__or2_4          2

   Area for cell type \sky130_fd_sc_hd__einvp_8 is unknown!

   Chip area for module '\gpio_control_block': 1017.225600

20. Executing Verilog backend.
Dumping module `\gpio_control_block'.

Warnings: 1 unique messages, 1 total
End of script. Logfile hash: bd299fc028, CPU: user 1.61s system 0.11s, MEM: 43.61 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 31% 2x abc (0 sec), 31% 2x read_liberty (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Info: Added 37 rows of 84 sites.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 38.959999999999994
[INFO]: Core area height: 103.24000000000001
[WARNING]: Current core area is too small for a power grid
[WARNING]: Minimizing the power grid!!!!
[INFO]: Changing layout from 0 to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/verilog2def_openroad.def
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 24 pins.
Notice 0:     Created 71 components and 353 component-terminals.
Notice 0:     Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/verilog2def_openroad.def
Top-level design name: gpio_control_block
Block boundaries: 0 0 50000 125000
Writing /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/verilog2def_openroad.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 24 pins.
Notice 0:     Created 71 components and 353 component-terminals.
Notice 0:     Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 0
[INFO] #Original rows: 37
[INFO] #Cut rows: 0
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 74
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 39
Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def to /project/openlane/gpio_control_block/runs/gpio_control_block/results/floorplan/gpio_control_block.floorplan.def
[INFO]: Running Placement...
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/floorplan/gpio_control_block.floorplan.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 24 pins.
Notice 0:     Created 184 components and 579 component-terminals.
Notice 0:     Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/floorplan/gpio_control_block.floorplan.def
[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (44160, 111520)
[INFO] NumInstances = 184
[INFO] NumPlaceInstances = 71
[INFO] NumFixedInstances = 113
[INFO] NumDummyInstances = 0
[INFO] NumNets = 79
[INFO] NumPins = 234
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (50000, 125000)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (44160, 111520)
[INFO] CoreArea = 3888729600
[INFO] NonPlaceInstsArea = 326563200
[INFO] PlaceInstsArea = 1039747200
[INFO] Util(%) = 29.188622
[INFO] StdInstsArea = 1039747200
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 1.05906e-07 HPWL: 2753880
[InitialPlace]  Iter: 2 CG Error: 1.14847e-07 HPWL: 2110888
[InitialPlace]  Iter: 3 CG Error: 7.01776e-08 HPWL: 2085756
[InitialPlace]  Iter: 4 CG Error: 7.54675e-08 HPWL: 2078520
[InitialPlace]  Iter: 5 CG Error: 1.13936e-07 HPWL: 2092488
[INFO] FillerInit: NumGCells = 98
[INFO] FillerInit: NumGNets = 79
[INFO] FillerInit: NumGPins = 234
[INFO] TargetDensity = 0.400000
[INFO] AveragePlaceInstArea = 14644326
[INFO] IdealBinArea = 36610816
[INFO] IdealBinCnt = 106
[INFO] TotalBinArea = 3888729600
[INFO] BinCnt = (8, 8)
[INFO] BinSize = (4830, 12580)
[INFO] NumBins = 64
[NesterovSolve] Iter: 1 overflow: 0.709908 HPWL: 1638919
[NesterovSolve] Iter: 10 overflow: 0.497771 HPWL: 1673566
[NesterovSolve] Iter: 20 overflow: 0.50846 HPWL: 1660355
[NesterovSolve] Iter: 30 overflow: 0.505602 HPWL: 1661709
[NesterovSolve] Iter: 40 overflow: 0.506297 HPWL: 1661040
[NesterovSolve] Iter: 50 overflow: 0.50615 HPWL: 1661104
[NesterovSolve] Iter: 60 overflow: 0.506139 HPWL: 1661139
[NesterovSolve] Iter: 70 overflow: 0.506105 HPWL: 1661132
[NesterovSolve] Iter: 80 overflow: 0.506055 HPWL: 1661240
[NesterovSolve] Iter: 90 overflow: 0.505971 HPWL: 1661372
[NesterovSolve] Iter: 100 overflow: 0.505825 HPWL: 1661625
[NesterovSolve] Iter: 110 overflow: 0.505622 HPWL: 1661980
[NesterovSolve] Iter: 120 overflow: 0.505302 HPWL: 1662532
[NesterovSolve] Iter: 130 overflow: 0.504843 HPWL: 1663209
[NesterovSolve] Iter: 140 overflow: 0.504151 HPWL: 1663829
[NesterovSolve] Iter: 150 overflow: 0.503008 HPWL: 1664271
[NesterovSolve] Iter: 160 overflow: 0.501058 HPWL: 1665596
[NesterovSolve] Iter: 170 overflow: 0.497836 HPWL: 1667853
[NesterovSolve] Iter: 180 overflow: 0.492678 HPWL: 1671171
[NesterovSolve] Iter: 190 overflow: 0.484747 HPWL: 1676460
[NesterovSolve] Iter: 200 overflow: 0.472351 HPWL: 1683923
[NesterovSolve] Iter: 210 overflow: 0.460509 HPWL: 1694566
[NesterovSolve] Iter: 220 overflow: 0.446098 HPWL: 1706868
[NesterovSolve] Iter: 230 overflow: 0.429146 HPWL: 1722786
[NesterovSolve] Iter: 240 overflow: 0.407395 HPWL: 1738513
[NesterovSolve] Iter: 250 overflow: 0.373378 HPWL: 1751118
[NesterovSolve] Iter: 260 overflow: 0.327698 HPWL: 1761013
[NesterovSolve] Iter: 270 overflow: 0.269933 HPWL: 1773879
[NesterovSolve] Iter: 280 overflow: 0.228274 HPWL: 1787323
[NesterovSolve] Iter: 290 overflow: 0.203813 HPWL: 1796742
[NesterovSolve] Iter: 300 overflow: 0.178708 HPWL: 1809979
[NesterovSolve] Iter: 310 overflow: 0.159275 HPWL: 1816347
[NesterovSolve] Iter: 320 overflow: 0.141698 HPWL: 1821180
[NesterovSolve] Iter: 330 overflow: 0.123013 HPWL: 1827543
[NesterovSolve] Iter: 340 overflow: 0.104345 HPWL: 1833584
[NesterovSolve] Finished with Overflow: 0.0990607
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/results/floorplan/gpio_control_block.floorplan.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/replace.def
[INFO]: Running OpenPhySyn Timing Optimization...
[INFO]: Trimming Liberty...
[OpenPhySyn] [2020-11-20 15:15:47.938] [info] Loaded 6 transforms.
[OpenPhySyn] [2020-11-20 15:15:50.436] [info] OpenPhySyn: 1.8.1
Warning: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/replace.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 24 pins.
Notice 0:     Created 184 components and 579 component-terminals.
Notice 0:     Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/replace.def
[INFO]: Setting output delay to: 2.0
[INFO]: Setting input delay to: 2.0
[INFO]: Setting load to: 0.01765
=============== Initial Reports =============
Startpoint: resetn (input port clocked by serial_clock)
Endpoint: _082_ (recovery check against rising-edge clock serial_clock)
Path Group: **async_default**
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock serial_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   2.00    2.00 ^ input external delay
   0.04    2.04 ^ resetn (in)
   0.19    2.23 ^ _039_/X (sky130_fd_sc_hd__or2_4)
   0.25    2.48 ^ _045_/X (sky130_fd_sc_hd__buf_1)
   0.33    2.80 ^ _064_/X (sky130_fd_sc_hd__buf_1)
   0.23    3.03 ^ _069_/X (sky130_fd_sc_hd__buf_1)
   0.00    3.03 ^ _082_/SET_B (sky130_fd_sc_hd__dfstp_4)
           3.03   data arrival time

  10.00   10.00   clock serial_clock (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ _082_/CLK (sky130_fd_sc_hd__dfstp_4)
   0.25   10.25   library recovery time
          10.25   data required time
---------------------------------------------------------
          10.25   data required time
          -3.03   data arrival time
---------------------------------------------------------
           7.21   slack (MET)


Startpoint: resetn (input port clocked by serial_clock)
Endpoint: _079_ (rising clock gating-check end-point clocked by serial_clock)
Path Group: **clock_gating_default**
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock serial_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   2.00    2.00 ^ input external delay
   0.04    2.04 ^ resetn (in)
   0.04    2.08 v _078_/Y (sky130_fd_sc_hd__inv_8)
   0.00    2.08 v _079_/B (sky130_fd_sc_hd__and2_4)
           2.08   data arrival time

  10.00   10.00   clock serial_clock (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ _079_/A (sky130_fd_sc_hd__and2_4)
   0.00   10.00   clock gating setup time
          10.00   data required time
---------------------------------------------------------
          10.00   data required time
          -2.08   data arrival time
---------------------------------------------------------
           7.92   slack (MET)


Startpoint: mgmt_gpio_oeb (input port clocked by serial_clock)
Endpoint: pad_gpio_out (output port clocked by serial_clock)
Path Group: serial_clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock serial_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   2.00    2.00 v input external delay
   0.01    2.01 v mgmt_gpio_oeb (in)
   0.26    2.26 v _073_/X (sky130_fd_sc_hd__and3_4)
   0.43    2.69 v _074_/X (sky130_fd_sc_hd__or2_4)
   0.57    3.26 v _076_/X (sky130_fd_sc_hd__a32o_4)
   0.00    3.26 v pad_gpio_out (out)
           3.26   data arrival time

  10.00   10.00   clock serial_clock (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -2.00    8.00   output external delay
           8.00   data required time
---------------------------------------------------------
           8.00   data required time
          -3.26   data arrival time
---------------------------------------------------------
           4.74   slack (MET)


Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Initial area: 13663 um2
OpenPhySyn timing repair:
[OpenPhySyn] [2020-11-20 15:17:00.923] [info] Invoking repair_timing transform
[OpenPhySyn] [2020-11-20 15:17:00.943] [info] Buffer library: sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_1
[OpenPhySyn] [2020-11-20 15:17:00.943] [info] Inverter library: None
[OpenPhySyn] [2020-11-20 15:17:00.943] [info] Buffering: enabled
[OpenPhySyn] [2020-11-20 15:17:00.943] [info] Driver sizing: enabled
[OpenPhySyn] [2020-11-20 15:17:00.943] [info] Pin-swapping: enabled
[OpenPhySyn] [2020-11-20 15:17:00.943] [info] Mode: Timing-Driven
[OpenPhySyn] [2020-11-20 15:17:00.943] [info] Iteration 1
[OpenPhySyn] [2020-11-20 15:17:00.991] [info] No more violations or cannot find more optimal buffer
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Runtime: 0s
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Buffers: 0
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Resize up: 0
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Resize down: 0
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Pin Swap: 0
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Buffered nets: 0
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Fanout violations: 0
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Transition violations: 0
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Capacitance violations: 0
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Slack gain: 0.0
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Initial area: 1366
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] New area: 1366
[OpenPhySyn] [2020-11-20 15:17:00.992] [info] Finished repair_timing transform (0)
Added/updated 0 cells
=============== Final Reports =============
Startpoint: resetn (input port clocked by serial_clock)
Endpoint: _082_ (recovery check against rising-edge clock serial_clock)
Path Group: **async_default**
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock serial_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   2.00    2.00 ^ input external delay
   0.04    2.04 ^ resetn (in)
   0.19    2.23 ^ _039_/X (sky130_fd_sc_hd__or2_4)
   0.25    2.47 ^ _045_/X (sky130_fd_sc_hd__buf_1)
   0.31    2.79 ^ _064_/X (sky130_fd_sc_hd__buf_1)
   0.22    3.00 ^ _069_/X (sky130_fd_sc_hd__buf_1)
   0.00    3.00 ^ _082_/SET_B (sky130_fd_sc_hd__dfstp_4)
           3.00   data arrival time

  10.00   10.00   clock serial_clock (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ _082_/CLK (sky130_fd_sc_hd__dfstp_4)
   0.25   10.25   library recovery time
          10.25   data required time
---------------------------------------------------------
          10.25   data required time
          -3.00   data arrival time
---------------------------------------------------------
           7.24   slack (MET)


Startpoint: resetn (input port clocked by serial_clock)
Endpoint: _079_ (rising clock gating-check end-point clocked by serial_clock)
Path Group: **clock_gating_default**
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock serial_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   2.00    2.00 ^ input external delay
   0.04    2.04 ^ resetn (in)
   0.04    2.08 v _078_/Y (sky130_fd_sc_hd__inv_8)
   0.00    2.08 v _079_/B (sky130_fd_sc_hd__and2_4)
           2.08   data arrival time

  10.00   10.00   clock serial_clock (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ _079_/A (sky130_fd_sc_hd__and2_4)
   0.00   10.00   clock gating setup time
          10.00   data required time
---------------------------------------------------------
          10.00   data required time
          -2.08   data arrival time
---------------------------------------------------------
           7.92   slack (MET)


Startpoint: mgmt_gpio_oeb (input port clocked by serial_clock)
Endpoint: pad_gpio_out (output port clocked by serial_clock)
Path Group: serial_clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock serial_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   2.00    2.00 v input external delay
   0.01    2.01 v mgmt_gpio_oeb (in)
   0.26    2.26 v _073_/X (sky130_fd_sc_hd__and3_4)
   0.43    2.69 v _074_/X (sky130_fd_sc_hd__or2_4)
   0.57    3.26 v _076_/X (sky130_fd_sc_hd__a32o_4)
   0.00    3.26 v pad_gpio_out (out)
           3.26   data arrival time

  10.00   10.00   clock serial_clock (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -2.00    8.00   output external delay
           8.00   data required time
---------------------------------------------------------
           8.00   data required time
          -3.26   data arrival time
---------------------------------------------------------
           4.74   slack (MET)


Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Final area: 13663 um2
Export optimized design
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/replace.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 24 pins.
Notice 0:     Created 184 components and 579 component-terminals.
Notice 0:     Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def
[INFO]: Changing netlist from /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis.v to /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_optimized.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_optimized.v, line 330 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found.  Creating black box for PHY_74.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Running Detailed Placement...
===========================================================================
   Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 >    
   Developers : SangGi Do, Mingyu Woo                                      
===========================================================================
Parsed 10000 number of lines!!
Parsed 20000 number of lines!!
Parsed 30000 number of lines!!
Parsed 40000 number of lines!!
Parsed 50000 number of lines!!
Parsed 60000 number of lines!!
Reading /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef is Done

-------------------- INPUT FILES ----------------------------------
 benchmark name    : placement
 directory         : /project/openlane/gpio_control_block/runs/gpio_control_block/tmp
 lef               : /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
 def               : /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def
-------------------------------------------------------------------
CoreArea: 
5520.000000 : 10880.000000 - 44160.000000 : 111520.000000
DieArea: 
0.000000 : 0.000000 - 38640.000000 : 100640.000000
Reading /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def is Done
-------------------- DESIGN ANALYSIS ------------------------------
  total cells              : 184
  multi cells              : 0
  fixed cells              : 113
  total nets               : 79
  design area              : 3.88873e+09
  total f_area             : 3.26563e+08
  total m_area             : 1.75043e+09
  design util              : 49.1394
  num rows                 : 37
  row height               : 2720
-------------------------------------------------------------------
 non_group_cell_region_assign done ..
 - - - - - - - - - - - - - - - - - - - - - - - - 
 non_group_cell_placement done .. 
 - - - - - - - - - - - - - - - - - - - - - - - - 
Reading /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def is Done
 DEF file write success !! 
 location : /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def
-------------------------------------------------------------------
 tasks                          Wtime      Ctime
 Parser                         0.175      0.160
 resgin assign                  0.175      0.160
 pre-placement                  0.175      0.160
 non Group cell placement       0.175      0.170
 All                            0.176      0.170
 - - - - - EVALUATION - - - - - 
 AVG_displacement : 1900.9
 SUM_displacement : 349766
 MAX_displacement : 18870
 - - - - - - - - - - - - - - - - 
 GP HPWL          : 1849.19
 HPWL             : 2153.75
 avg_Disp_site    : 4.1324
 avg_Disp_row     : 0.698861
 delta_HPWL       : 16.4702
 ==== CHECK LEGALITY ==== 
 row_check ==>> PASS 
 site_check ==>> PASS 
 power_check ==>> PASS 
 edge_check ==>> PASS 
 placed_check ==>> PASS 
 overlap_check ==>> PASS 
 - - - - - < Program END > - - - - - 
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/placement/openphysyn.def to /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def
[INFO]: Running TritonCTS...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 24 pins.
Notice 0:     Created 184 components and 579 component-terminals.
Notice 0:     Created 79 nets and 210 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def
[INFO]: Setting output delay to: 2.0
[INFO]: Setting input delay to: 2.0
[INFO]: Setting load to: 0.01765
[INFO]: Configuring cts characterization...
[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s): serial_clock
 *****************
 * TritonCTS 2.0 *
 *****************
 *****************************
 *  Create characterization  *
 *****************************
Number of created patterns = 50000.
Number of created patterns = 100000.
Number of created patterns = 150000.
Number of created patterns = 200000.
Number of created patterns = 250000.
Number of created patterns = 300000.
Number of created patterns = 313632.
 Compiling LUT
    Min. len    Max. len    Min. cap    Max. cap   Min. slew   Max. slew
           2           8           1          39           1         199
    [WARNING] 6336 wires are pure wire and no slew degration.
    TritonCTS forced slew degradation on these wires.
    Num wire segments: 216048
    Num keys in characterization LUT: 1887
    Actual min input cap: 2
 **********************
 *  Find clock roots  *
 **********************
 Running TritonCTS with user-specified clock roots: serial_clock
 ************************
 *  Populate TritonCTS  *
 ************************
 Initializing clock nets
 Looking for clock nets in the design
 Net "serial_clock" found
 Initializing clock net for : "serial_clock"
 Clock net "serial_clock" has 15 sinks
 TritonCTS found 1 clock nets.
 ****************************
 *  Check characterization  *
 ****************************
    The chacterization used 4 buffer(s) types. All of them are in the loaded DB.
 ***********************
 *  Build clock trees  *
 ***********************
 Generating H-Tree topology for net serial_clock...
    Tot. number of sinks: 15
    Number of static layers: 0
 Wire segment unit: 13000 dbu (13 um)
 Original sink region: [(7165, 23175), (24972, 99340)]
 Normalized sink region: [(0.551154, 1.78269), (1.92092, 7.64154)]
    Width:  1.36977
    Height: 5.85885
 [WARNING] Creating fake entries in the LUT.
 Level 1
    Direction: Vertical
    # sinks per sub-region: 8
    Sub-region size: 1.36977 X 2.92942
    Segment length (rounded): 1
    Key: 216280 outSlew: 11 load: 1 length: 1 isBuffered: 1
 Stop criterion found. Max number of sinks is (15)
 Building clock sub nets...
 Number of sinks covered: 15
 Clock topology of net "serial_clock" done.
 ****************
 * Post CTS opt *
 ****************
 Avg. source sink dist: 18924.3 dbu.
 Num outlier sinks: 0
 ********************
 * Write data to DB *
 ********************
 Writing clock net "serial_clock" to DB
    Created 3 clock buffers.
    Minimum number of buffers in the clock path: 2.
    Maximum number of buffers in the clock path: 2.
    Created 3 clock nets.
    Fanout distribution for the current clock = 6:1, 9:1.
    Max level of the clock tree: 1.
 ... End of TritonCTS execution.
[INFO]: Legalizing...
Warning: could not find power special net
Design Stats
--------------------------------
total instances           187
multi row instances         0
fixed instances           113
nets                       82
design area            3888.7 u^2
fixed area              326.6 u^2
movable area           1072.3 u^2
utilization                30 %
utilization padded         31 %
rows                       37
row height                2.7 u

Placement Analysis
--------------------------------
total displacement       17.8 u
average displacement      0.1 u
max displacement          9.3 u
original HPWL          2268.7 u
legalized HPWL         2276.0 u
delta HPWL                  0 %

[INFO]: Clock Tree Synthesis was successful
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def to /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 24 pins.
Notice 0:     Created 187 components and 591 component-terminals.
Notice 0:     Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def
[INFO]: Changing netlist from /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_optimized.v to /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_cts.v
[INFO]: Generating PDN...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 24 pins.
Notice 0:     Created 187 components and 591 component-terminals.
Notice 0:     Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is gpio_control_block
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
    Stdcell Rails
      Layer: met1 -  width: 0.480  pitch: 2.720  offset: 0.000 
    Straps
      Layer: met4 -  width: 1.600  pitch: 12.987  offset: 6.493 
      Layer: met5 -  width: 1.600  pitch: 34.413  offset: 17.207 
    Connect: {met1 met4} {met4 met5}
Type: macro, macro_1
    Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
    Straps
    Connect:  
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/results/cts/gpio_control_block.cts.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/pdn.def
[INFO]: Routing...
[INFO]: Running Global Routing...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/pdn.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 26 pins.
Notice 0:     Created 187 components and 591 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/pdn.def
[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 6
[PARAMS] Global adjustment: 0
[PARAMS] Unidirectional routing: 1
[PARAMS] Grid origin: (-1, -1)
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 5881
[INFO] #DB Macros: 0
[INFO] Found 0 clock nets
[INFO] Minimum degree: 2
[INFO] Maximum degree: 14
[INFO] Processing 3763 obstacles in layer 1
[INFO] Processing 935 obstacles in layer 2
[INFO] Processing 5 obstacles in layer 5
[INFO] Processing 5 obstacles in layer 6
[INFO] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 287, WIRELEN1 : 0
[INFO] NumSeg  : 161
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 287, WIRELEN1 : 287
[INFO] NumSeg  : 157
[INFO] NumShift: 4
[Overflow Report] Total hCap    : 3060
[Overflow Report] Total vCap    : 2594
[Overflow Report] Total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Second L Route
[Overflow Report] Total hCap    : 3060
[Overflow Report] Total vCap    : 2594
[Overflow Report] Total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

First Z Route
[Overflow Report] Total hCap    : 3060
[Overflow Report] Total vCap    : 2594
[Overflow Report] Total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 0, enlarge 10 
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 1, enlarge 15 
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 2, enlarge 20 
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Usage checked
Maze routing finished
[INFO] P3 runtime: 0.000000 sec
[INFO] Final 2D results: 
[Overflow Report] total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 60.540001 sec
Post Processing Begins 
Post Processsing finished
 Starting via filling
[INFO] Via related to pin nodes 327
[INFO] Via related stiner nodes 20
Via filling finished

Final usage/overflow report: 
[INFO] Usage per layer: 
    Layer 1 usage: 0
    Layer 2 usage: 110
    Layer 3 usage: 179
    Layer 4 usage: 0
    Layer 5 usage: 0
    Layer 6 usage: 0

[INFO] Capacity per layer: 
    Layer 1 capacity: 0
    Layer 2 capacity: 1770
    Layer 3 capacity: 1819
    Layer 4 capacity: 1080
    Layer 5 capacity: 775
    Layer 6 capacity: 210

[INFO] Use percentage per layer: 
    Layer 1 use percentage: 0.0%
    Layer 2 use percentage: 6.21%
    Layer 3 use percentage: 9.84%
    Layer 4 use percentage: 0.00%
    Layer 5 use percentage: 0.00%
    Layer 6 use percentage: 0.00%

[INFO] Overflow per layer: 
    Layer 1 overflow: 0
    Layer 2 overflow: 0
    Layer 3 overflow: 0
    Layer 4 overflow: 0
    Layer 5 overflow: 0
    Layer 6 overflow: 0

[Overflow Report] Total Usage   : 289
[Overflow Report] Total Capacity: 5654
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] Final usage          : 289
[INFO] Final number of vias : 384
[INFO] Final usage 3D       : 1441
[INFO] Total wirelength: 3850 um
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Repairing antennas...
[WARNING]No OR_DEFAULT vias defined
[INFO] #Antenna violations: 0
[INFO] Num routed nets: 82
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/pdn.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 26 pins.
Notice 0:     Created 187 components and 591 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 6
[PARAMS] Global adjustment: 0
[PARAMS] Unidirectional routing: 1
[PARAMS] Grid origin: (-1, -1)
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 5881
[INFO] #DB Macros: 0
[INFO] Found 0 clock nets
[INFO] Minimum degree: 2
[INFO] Maximum degree: 14
[INFO] Processing 3763 obstacles in layer 1
[INFO] Processing 935 obstacles in layer 2
[INFO] Processing 5 obstacles in layer 5
[INFO] Processing 5 obstacles in layer 6
[INFO] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 287, WIRELEN1 : 0
[INFO] NumSeg  : 161
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 287, WIRELEN1 : 287
[INFO] NumSeg  : 157
[INFO] NumShift: 4
[Overflow Report] Total hCap    : 3060
[Overflow Report] Total vCap    : 2594
[Overflow Report] Total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Second L Route
[Overflow Report] Total hCap    : 3060
[Overflow Report] Total vCap    : 2594
[Overflow Report] Total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

First Z Route
[Overflow Report] Total hCap    : 3060
[Overflow Report] Total vCap    : 2594
[Overflow Report] Total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 0, enlarge 10 
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 1, enlarge 15 
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 2, enlarge 20 
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Usage checked
Maze routing finished
[INFO] P3 runtime: 0.000000 sec
[INFO] Final 2D results: 
[Overflow Report] total Usage   : 287
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 65.010002 sec
Post Processing Begins 
Post Processsing finished
 Starting via filling
[INFO] Via related to pin nodes 327
[INFO] Via related stiner nodes 20
Via filling finished

Final usage/overflow report: 
[INFO] Usage per layer: 
    Layer 1 usage: 0
    Layer 2 usage: 110
    Layer 3 usage: 179
    Layer 4 usage: 0
    Layer 5 usage: 0
    Layer 6 usage: 0

[INFO] Capacity per layer: 
    Layer 1 capacity: 0
    Layer 2 capacity: 1770
    Layer 3 capacity: 1819
    Layer 4 capacity: 1080
    Layer 5 capacity: 775
    Layer 6 capacity: 210

[INFO] Use percentage per layer: 
    Layer 1 use percentage: 0.0%
    Layer 2 use percentage: 6.21%
    Layer 3 use percentage: 9.84%
    Layer 4 use percentage: 0.00%
    Layer 5 use percentage: 0.00%
    Layer 6 use percentage: 0.00%

[INFO] Overflow per layer: 
    Layer 1 overflow: 0
    Layer 2 overflow: 0
    Layer 3 overflow: 0
    Layer 4 overflow: 0
    Layer 5 overflow: 0
    Layer 6 overflow: 0

[Overflow Report] Total Usage   : 289
[Overflow Report] Total Capacity: 5654
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] Final usage          : 289
[INFO] Final number of vias : 384
[INFO] Final usage 3D       : 1441
[INFO] Total wirelength: 3850 um
[INFO] Num routed nets: 82
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
[INFO]: Current Def is /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
[INFO]: Running Fill Insertion...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 26 pins.
Notice 0:     Created 187 components and 591 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def
Placed 276 filler instances.
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/fastroute.def to /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/addspacers.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/addspacers.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 26 pins.
Notice 0:     Created 463 components and 1143 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/addspacers.def
[INFO]: Changing netlist from /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_cts.v to /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_preroute.v
[INFO]: Running Detailed Routing...

reading lef ...

units:       1000
#layers:     13
#macros:     437
#vias:       25
#viarulegen: 25

reading def ...

design:      gpio_control_block
die area:    ( 0 0 ) ( 50000 125000 )
trackPts:    12
defvias:     4
#components: 463
#terminals:  26
#snets:      2
#nets:       82

reading guide ...

#guides:     578
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
#unique instances = 37

init region query ...
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 5159
mcon shape region query size = 6447
met1 shape region query size = 1582
via shape region query size = 380
met2 shape region query size = 190
via2 shape region query size = 380
met3 shape region query size = 214
via3 shape region query size = 380
met4 shape region query size = 113
via4 shape region query size = 13
met5 shape region query size = 20


start pin access
Error: no ap for PIN/VGND
Error: no ap for PIN/VPWR
  complete 56 pins
  complete 31 unique inst patterns
  complete 73 groups
Expt1 runtime (pin-level access point gen): 1.33315
Expt2 runtime (design-level access pattern gen): 0.131903
#scanned instances     = 463
#unique  instances     = 37
#stdCellGenAp          = 600
#stdCellValidPlanarAp  = 28
#stdCellValidViaAp     = 283
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 216
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0

complete pin access
cpu time = 00:00:01, elapsed time = 00:00:01, memory = 13.24 (MB), peak = 13.57 (MB)

post process guides ...
GCELLGRID X -1 DO 18 STEP 6900 ;
GCELLGRID Y -1 DO 7 STEP 6900 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 179
mcon guide region query size = 0
met1 guide region query size = 169
via guide region query size = 0
met2 guide region query size = 112
via2 guide region query size = 0
met3 guide region query size = 24
via3 guide region query size = 0
met4 guide region query size = 0
via4 guide region query size = 0
met5 guide region query size = 0

init gr pin query ...


start track assignment
Done with 291 vertical wires in 1 frboxes and 193 horizontal wires in 1 frboxes.
Done with 33 vertical wires in 1 frboxes and 48 horizontal wires in 1 frboxes.

complete track assignment
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.35 (MB), peak = 15.82 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.49 (MB), peak = 15.82 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 28.19 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 25.18 (MB)
    completing 30% with 29 violations
    elapsed time = 00:00:01, memory = 30.17 (MB)
  number of violations = 8
cpu time = 00:00:02, elapsed time = 00:00:02, memory = 20.77 (MB), peak = 381.67 (MB)
total wire length = 2421 um
total wire length on LAYER li1 = 3 um
total wire length on LAYER met1 = 820 um
total wire length on LAYER met2 = 1244 um
total wire length on LAYER met3 = 352 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 449
up-via summary (total 449):

----------------------
 FR_MASTERSLICE      0
            li1    194
           met1    231
           met2     24
           met3      0
           met4      0
----------------------
                   449


start 1st optimization iteration ...
    completing 10% with 8 violations
    elapsed time = 00:00:00, memory = 31.38 (MB)
    completing 20% with 8 violations
    elapsed time = 00:00:00, memory = 31.52 (MB)
    completing 30% with 3 violations
    elapsed time = 00:00:00, memory = 37.67 (MB)
    completing 40% with 3 violations
    elapsed time = 00:00:01, memory = 22.01 (MB)
    completing 50% with 3 violations
    elapsed time = 00:00:01, memory = 22.07 (MB)
    completing 60% with 3 violations
    elapsed time = 00:00:01, memory = 23.10 (MB)
  number of violations = 3
cpu time = 00:00:02, elapsed time = 00:00:02, memory = 22.07 (MB), peak = 383.02 (MB)
total wire length = 2427 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 818 um
total wire length on LAYER met2 = 1249 um
total wire length on LAYER met3 = 359 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 449
up-via summary (total 449):

----------------------
 FR_MASTERSLICE      0
            li1    190
           met1    235
           met2     24
           met3      0
           met4      0
----------------------
                   449


start 2nd optimization iteration ...
    completing 10% with 3 violations
    elapsed time = 00:00:00, memory = 22.07 (MB)
    completing 20% with 3 violations
    elapsed time = 00:00:00, memory = 24.18 (MB)
    completing 30% with 3 violations
    elapsed time = 00:00:00, memory = 22.73 (MB)
    completing 40% with 3 violations
    elapsed time = 00:00:00, memory = 24.60 (MB)
    completing 50% with 3 violations
    elapsed time = 00:00:00, memory = 26.66 (MB)
    completing 60% with 3 violations
    elapsed time = 00:00:00, memory = 34.65 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 21.05 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 26.71 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:01, memory = 26.71 (MB), peak = 387.64 (MB)
total wire length = 2415 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 816 um
total wire length on LAYER met2 = 1236 um
total wire length on LAYER met3 = 363 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 450
up-via summary (total 450):

----------------------
 FR_MASTERSLICE      0
            li1    190
           met1    236
           met2     24
           met3      0
           met4      0
----------------------
                   450


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 28.61 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 29.49 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 28.38 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 26.71 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 26.72 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 27.75 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 27.94 (MB), peak = 387.64 (MB)
total wire length = 2415 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 816 um
total wire length on LAYER met2 = 1236 um
total wire length on LAYER met3 = 363 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 450
up-via summary (total 450):

----------------------
 FR_MASTERSLICE      0
            li1    190
           met1    236
           met2     24
           met3      0
           met4      0
----------------------
                   450


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 24.71 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 25.09 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 25.81 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 26.14 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 24.75 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 27.33 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 29.05 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 29.26 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 29.26 (MB), peak = 387.64 (MB)
total wire length = 2415 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 816 um
total wire length on LAYER met2 = 1236 um
total wire length on LAYER met3 = 363 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 450
up-via summary (total 450):

----------------------
 FR_MASTERSLICE      0
            li1    190
           met1    236
           met2     24
           met3      0
           met4      0
----------------------
                   450


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 29.26 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 22.60 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 23.66 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 23.13 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 22.60 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 23.48 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 22.96 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 23.48 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 27.14 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 26.83 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 26.83 (MB), peak = 387.64 (MB)
total wire length = 2415 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 816 um
total wire length on LAYER met2 = 1236 um
total wire length on LAYER met3 = 363 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 450
up-via summary (total 450):

----------------------
 FR_MASTERSLICE      0
            li1    190
           met1    236
           met2     24
           met3      0
           met4      0
----------------------
                   450


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 24.35 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 24.36 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 26.17 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 23.38 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 21.80 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 22.68 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 22.68 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 24.04 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 25.95 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 26.21 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 26.21 (MB), peak = 387.64 (MB)
total wire length = 2415 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 816 um
total wire length on LAYER met2 = 1236 um
total wire length on LAYER met3 = 363 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 450
up-via summary (total 450):

----------------------
 FR_MASTERSLICE      0
            li1    190
           met1    236
           met2     24
           met3      0
           met4      0
----------------------
                   450


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 21.83 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 22.61 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 23.58 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 24.81 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 24.81 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 25.06 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 24.36 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 24.36 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 26.39 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 26.39 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 26.39 (MB), peak = 387.64 (MB)
total wire length = 2415 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 816 um
total wire length on LAYER met2 = 1236 um
total wire length on LAYER met3 = 363 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 450
up-via summary (total 450):

----------------------
 FR_MASTERSLICE      0
            li1    190
           met1    236
           met2     24
           met3      0
           met4      0
----------------------
                   450


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 26.39 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 23.55 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 23.65 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 23.57 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 23.57 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 23.57 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 22.76 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 24.78 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 27.16 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 26.90 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 26.90 (MB), peak = 387.64 (MB)
total wire length = 2415 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 816 um
total wire length on LAYER met2 = 1236 um
total wire length on LAYER met3 = 363 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 450
up-via summary (total 450):

----------------------
 FR_MASTERSLICE      0
            li1    190
           met1    236
           met2     24
           met3      0
           met4      0
----------------------
                   450


complete detail routing
total wire length = 2415 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 816 um
total wire length on LAYER met2 = 1236 um
total wire length on LAYER met3 = 363 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 450
up-via summary (total 450):

----------------------
 FR_MASTERSLICE      0
            li1    190
           met1    236
           met2     24
           met3      0
           met4      0
----------------------
                   450

cpu time = 00:00:07, elapsed time = 00:00:08, memory = 26.90 (MB), peak = 387.64 (MB)

post processing ...

Runtime taken (hrt): 11.8858
[INFO]: Changing layout from /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/addspacers.def to /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def
[INFO]: Running SPEF Extraction...
Start parsing LEF file...
Parsing LEF file done.
Start parsing DEF file...
Parsing DEF file done.

Parameters Used:
Edge Capacitance Factor: 1.0
Wire model: L 

RC Extraction is done
Start writing SPEF file
Writing SPEF is done
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_preroute.v, line 334 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found.  Creating black box for PHY_74.
Warning: /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_preroute.v, line 389 module sky130_fd_sc_hd__fill_1 not found.  Creating black box for FILLER_1_21.
Warning: /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_preroute.v, line 402 module sky130_fd_sc_hd__fill_2 not found.  Creating black box for FILLER_2_79.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Routing completed for gpio_control_block/20-11_15-13 in 0h9m55s
[INFO]: Writing Powered Verilog...
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 26 pins.
Notice 0:     Created 463 components and 1143 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def
Top-level design name: gpio_control_block
Found port VPWR of type SIGNAL
Found port VGND of type SIGNAL
Power net:  VPWR
Ground net: VGND
Modified power connections of 463 cells (Remaining: 0 ).
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/gpio_control_block.powered.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 26 pins.
Notice 0:     Created 463 components and 1143 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 84 nets and 1142 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/routing/gpio_control_block.powered.def
[INFO]: Rewriting /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.powered.v into /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.powered.v
[INFO]: Changing netlist from /project/openlane/gpio_control_block/runs/gpio_control_block/results/synthesis/gpio_control_block.synthesis_preroute.v to /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.powered.v
[INFO]: Running Magic...
[INFO]: Streaming out GDS II...

Magic 8.3 revision 64 - Compiled on Fri Oct  9 12:13:18 UTC 2020.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130: scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
This action cannot be undone.
LEF read, Line 61 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 62 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 95 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 96 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 102 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 103 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 104 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 142 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 143 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 145 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 146 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 147 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 183 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 184 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 186 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 187 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 188 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 224 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 225 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 227 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 228 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 229 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 265 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 266 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 772 lines.
Reading DEF data from file /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def.
This action cannot be undone.
  Processed 6 vias total.
  Processed 463 subcell instances total.
  Processed 26 pins total.
  Processed 2 special nets total.
  Processed 82 nets total.
DEF read: Processed 2147 lines.
[INFO]: Zeroizing Origin
[INFO]: Current Box Values: 0 0 10000 23376
[INFO]: Saving .mag view With BBox Values: 0 0 10000 23376
[INFO]: GDS Write Complete
Generating LEF output /project/openlane/gpio_control_block/runs/gpio_control_block/results/magic/gpio_control_block.lef for cell gpio_control_block:
Diagnostic:  Write LEF header for cell gpio_control_block
Diagnostic:  Writing LEF output for cell gpio_control_block
Diagnostic:  Scale value is 0.005000
[INFO]: LEF Write Complete
[INFO]: MAGIC TAPEOUT STEP DONE
[INFO]: Running Magic Spice Export...

Magic 8.3 revision 64 - Compiled on Fri Oct  9 12:13:18 UTC 2020.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130: scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/project/openlane/gpio_control_block/runs/gpio_control_block/tmp/magic_spice.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
This action cannot be undone.
LEF read, Line 61 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 62 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 95 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 96 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 102 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 103 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 104 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 142 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 143 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 145 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 146 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 147 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 183 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 184 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 186 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 187 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 188 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 224 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 225 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 227 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 228 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 229 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 265 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 266 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 772 lines.
Reading DEF data from file /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def.
This action cannot be undone.
  Processed 6 vias total.
  Processed 463 subcell instances total.
  Processed 26 pins total.
  Processed 2 special nets total.
  Processed 82 nets total.
DEF read: Processed 2147 lines.
Extracting sky130_fd_sc_hd__and3_4 into sky130_fd_sc_hd__and3_4.ext:
Extracting sky130_fd_sc_hd__or2_4 into sky130_fd_sc_hd__or2_4.ext:
Extracting sky130_fd_sc_hd__a32o_4 into sky130_fd_sc_hd__a32o_4.ext:
Extracting sky130_fd_sc_hd__nand2_4 into sky130_fd_sc_hd__nand2_4.ext:
Extracting sky130_fd_sc_hd__inv_8 into sky130_fd_sc_hd__inv_8.ext:
Extracting sky130_fd_sc_hd__and2_4 into sky130_fd_sc_hd__and2_4.ext:
Extracting sky130_fd_sc_hd__buf_1 into sky130_fd_sc_hd__buf_1.ext:
Extracting sky130_fd_sc_hd__dfstp_4 into sky130_fd_sc_hd__dfstp_4.ext:
Extracting sky130_fd_sc_hd__dfrtp_4 into sky130_fd_sc_hd__dfrtp_4.ext:
Extracting sky130_fd_sc_hd__einvp_8 into sky130_fd_sc_hd__einvp_8.ext:
Extracting sky130_fd_sc_hd__conb_1 into sky130_fd_sc_hd__conb_1.ext:
Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:
Extracting sky130_fd_sc_hd__clkbuf_16 into sky130_fd_sc_hd__clkbuf_16.ext:
Extracting sky130_fd_sc_hd__clkbuf_1 into sky130_fd_sc_hd__clkbuf_1.ext:
Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext:
Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext:
Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:
Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext:
Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:
Extracting sky130_fd_sc_hd__decap_12 into sky130_fd_sc_hd__decap_12.ext:
Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext:
Extracting gpio_control_block into gpio_control_block.ext:
exttospice finished.
Using technology "sky130A", version 20200508
[INFO]: Saving Magic Views in /project
[INFO]: Running Magic DRC...

Magic 8.3 revision 64 - Compiled on Fri Oct  9 12:13:18 UTC 2020.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130: scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic_drc.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
This action cannot be undone.
LEF read, Line 61 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 62 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 95 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 96 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 102 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 103 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 104 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 142 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 143 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 145 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 146 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 147 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 183 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 184 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 186 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 187 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 188 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 224 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 225 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 227 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 228 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 229 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 265 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 266 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 772 lines.
Reading DEF data from file /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def.
This action cannot be undone.
  Processed 6 vias total.
  Processed 463 subcell instances total.
  Processed 26 pins total.
  Processed 2 special nets total.
  Processed 82 nets total.
DEF read: Processed 2147 lines.
[INFO]: Loading gpio_control_block

DRC style is now "drc(full)"
Loading DRC CIF style.
No errors found.
[INFO]: COUNT: 0
[INFO]: Should be divided by 3 or 4
[INFO]: DRC Checking DONE (/project/openlane/gpio_control_block/runs/gpio_control_block/logs/magic/magic.drc)
[INFO]: Saving mag view with DRC errors(/project/openlane/gpio_control_block/runs/gpio_control_block/results/magic/gpio_control_block.drc.mag)
[INFO]: Saved
[INFO]: Running LVS...
[INFO]: /project/openlane/gpio_control_block/runs/gpio_control_block/results/magic/gpio_control_block.spice against /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.powered.v
Netgen 1.5.157 compiled on Fri Oct  9 13:50:13 UTC 2020
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Generating JSON file result
Reading netlist file /project/openlane/gpio_control_block/runs/gpio_control_block/results/magic/gpio_control_block.spice
Reading netlist file /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.powered.v
Warning:  A case-insensitive file has been read and so the	verilog file must be treated case-insensitive to match.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_12.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_6.
Creating placeholder cell definition for module sky130_fd_sc_hd__fill_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_8.
Creating placeholder cell definition for module sky130_fd_sc_hd__fill_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_3.
Creating placeholder cell definition for module sky130_fd_sc_hd__tapvpwrvgnd_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__or2_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__buf_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__inv_8.
Creating placeholder cell definition for module sky130_fd_sc_hd__a32o_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__and3_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__nand2_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__and2_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__dfstp_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__dfrtp_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_16.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__einvp_8.
Creating placeholder cell definition for module sky130_fd_sc_hd__conb_1.
Reading setup file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/netgen/sky130A_setup.tcl
Comparison output logged to file /project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.log
Logging to file "/project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.log" enabled
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_1'
Circuit sky130_fd_sc_hd__buf_1 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_1'
Circuit sky130_fd_sc_hd__buf_1 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__buf_1 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__dfrtp_4'
Circuit sky130_fd_sc_hd__dfrtp_4 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__dfrtp_4'
Circuit sky130_fd_sc_hd__dfrtp_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__dfrtp_4 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1'
Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances.
Circuit contains 0 nets, and 2 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1'
Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and2_4'
Circuit sky130_fd_sc_hd__and2_4 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and2_4'
Circuit sky130_fd_sc_hd__and2_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__and2_4 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__inv_8'
Circuit sky130_fd_sc_hd__inv_8 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__inv_8'
Circuit sky130_fd_sc_hd__inv_8 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__inv_8 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand2_4'
Circuit sky130_fd_sc_hd__nand2_4 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand2_4'
Circuit sky130_fd_sc_hd__nand2_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__nand2_4 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a32o_4'
Circuit sky130_fd_sc_hd__a32o_4 contains 0 device instances.
Circuit contains 0 nets, and 8 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a32o_4'
Circuit sky130_fd_sc_hd__a32o_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__a32o_4 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__einvp_8'
Circuit sky130_fd_sc_hd__einvp_8 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__einvp_8'
Circuit sky130_fd_sc_hd__einvp_8 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__einvp_8 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__or2_4'
Circuit sky130_fd_sc_hd__or2_4 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__or2_4'
Circuit sky130_fd_sc_hd__or2_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__or2_4 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and3_4'
Circuit sky130_fd_sc_hd__and3_4 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and3_4'
Circuit sky130_fd_sc_hd__and3_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__and3_4 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_1'
Circuit sky130_fd_sc_hd__clkbuf_1 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_1'
Circuit sky130_fd_sc_hd__clkbuf_1 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__clkbuf_1 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__conb_1'
Circuit sky130_fd_sc_hd__conb_1 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__conb_1'
Circuit sky130_fd_sc_hd__conb_1 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__conb_1 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__dfstp_4'
Circuit sky130_fd_sc_hd__dfstp_4 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__dfstp_4'
Circuit sky130_fd_sc_hd__dfstp_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__dfstp_4 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_16'
Circuit sky130_fd_sc_hd__clkbuf_16 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_16'
Circuit sky130_fd_sc_hd__clkbuf_16 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__clkbuf_16 contains no devices.
Contents of circuit 1:  Circuit: 'gpio_control_block'
Circuit gpio_control_block contains 113 device instances.
  Class: sky130_fd_sc_hd__clkbuf_16 instances:   1
  Class: sky130_fd_sc_hd__buf_1 instances:  31
  Class: sky130_fd_sc_hd__dfstp_4 instances:   3
  Class: sky130_fd_sc_hd__dfrtp_4 instances:  23
  Class: sky130_fd_sc_hd__inv_8 instances:   3
  Class: sky130_fd_sc_hd__clkbuf_1 instances:   2
  Class: sky130_fd_sc_hd__conb_1 instances:   1
  Class: sky130_fd_sc_hd__and3_4 instances:   1
  Class: sky130_fd_sc_hd__or2_4 instances:   2
  Class: sky130_fd_sc_hd__einvp_8 instances:   1
  Class: sky130_fd_sc_hd__nand2_4 instances:   2
  Class: sky130_fd_sc_hd__and2_4 instances:   2
  Class: sky130_fd_sc_hd__a32o_4 instances:   2
  Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances:  39
Circuit contains 85 nets.
Contents of circuit 2:  Circuit: 'gpio_control_block'
Circuit gpio_control_block contains 113 device instances.
  Class: sky130_fd_sc_hd__clkbuf_16 instances:   1
  Class: sky130_fd_sc_hd__buf_1 instances:  31
  Class: sky130_fd_sc_hd__dfstp_4 instances:   3
  Class: sky130_fd_sc_hd__dfrtp_4 instances:  23
  Class: sky130_fd_sc_hd__inv_8 instances:   3
  Class: sky130_fd_sc_hd__clkbuf_1 instances:   2
  Class: sky130_fd_sc_hd__conb_1 instances:   1
  Class: sky130_fd_sc_hd__and3_4 instances:   1
  Class: sky130_fd_sc_hd__or2_4 instances:   2
  Class: sky130_fd_sc_hd__einvp_8 instances:   1
  Class: sky130_fd_sc_hd__nand2_4 instances:   2
  Class: sky130_fd_sc_hd__and2_4 instances:   2
  Class: sky130_fd_sc_hd__a32o_4 instances:   2
  Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances:  39
Circuit contains 84 nets.

Circuit 1 contains 113 devices, Circuit 2 contains 113 devices.
Circuit 1 contains 84 nets,    Circuit 2 contains 84 nets.

Circuits match with 1 symmetry.
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match with 1 symmetry.
Circuits match correctly.
Result: Circuits match uniquely.
Logging to file "/project/openlane/gpio_control_block/runs/gpio_control_block/results/lvs/gpio_control_block.lvs.log" disabled
LVS Done.
LVS reports no net, device, pin, or property mismatches.

Total errors = 0
[INFO]: Running Antenna Checks...
[INFO]: Running OpenROAD Antenna Rule Checker...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 26 pins.
Notice 0:     Created 463 components and 1143 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 82 nets and 216 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def
Notice 0: Split top of 24 T shapes.
Number of pins violated: 0
Number of nets violated: 0
Total number of nets: 82
[INFO]: Generating Final Summary Report...
[SUCCESS]: Flow Completed Without Fatal Errors.

Submodule: mgmt_core

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/mgmt_core/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/mgmt_core/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/mgmt_core/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/mgmt_core/runs/mgmt_core
[WARNING]: Removing exisiting run /project/openlane/mgmt_core/runs/mgmt_core
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
mergeLef.py : Merging LEFs
DFFRAM.lef: SITEs matched found: 0
DFFRAM.lef: MACROs matched found: 1
digital_pll.lef: SITEs matched found: 0
digital_pll.lef: MACROs matched found: 1
mergeLef.py : Merging LEFs complete
[INFO]: Merging the following extra LEFs:  /project/openlane/mgmt_core/../../lef/DFFRAM.lef
	/project/openlane/mgmt_core/../../lef/digital_pll.lef
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 3.68
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/DFFRAM.v
Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/DFFRAM.v' to AST representation.
Generating RTLIL representation for module `\DFFRAM'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/digital_pll.v
Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/digital_pll.v' to AST representation.
Generating RTLIL representation for module `\digital_pll_controller'.
Generating RTLIL representation for module `\delay_stage'.
Generating RTLIL representation for module `\start_stage'.
Generating RTLIL representation for module `\ring_osc2x13'.
Generating RTLIL representation for module `\digital_pll'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v
Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v' to AST representation.
Generating RTLIL representation for module `\storage_bridge_wb'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/clock_div.v
Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v' to AST representation.
Generating RTLIL representation for module `\clock_div'.
Generating RTLIL representation for module `\odd'.
Generating RTLIL representation for module `\even'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v
Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v' to AST representation.
Generating RTLIL representation for module `\caravel_clocking'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v
Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v' to AST representation.
Generating RTLIL representation for module `\mgmt_core'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v
Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:192)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:193)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:198)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:162)
Generating RTLIL representation for module `\picorv32'.
Generating RTLIL representation for module `\picorv32_regs'.
Generating RTLIL representation for module `\picorv32_pcpi_mul'.
Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'.
Generating RTLIL representation for module `\picorv32_pcpi_div'.
Generating RTLIL representation for module `\picorv32_axi'.
Generating RTLIL representation for module `\picorv32_axi_adapter'.
Generating RTLIL representation for module `\picorv32_wb'.
Generating RTLIL representation for module `\spimemio_wb'.
Generating RTLIL representation for module `\spimemio'.
Generating RTLIL representation for module `\spimemio_xfer'.
Generating RTLIL representation for module `\simpleuart_wb'.
Generating RTLIL representation for module `\simpleuart'.
Generating RTLIL representation for module `\simple_spi_master_wb'.
Generating RTLIL representation for module `\simple_spi_master'.
Generating RTLIL representation for module `\counter_timer_high_wb'.
Generating RTLIL representation for module `\counter_timer_high'.
Generating RTLIL representation for module `\counter_timer_low_wb'.
Generating RTLIL representation for module `\counter_timer_low'.
Generating RTLIL representation for module `\wb_intercon'.
Generating RTLIL representation for module `\mem_wb'.
Generating RTLIL representation for module `\soc_mem'.
Generating RTLIL representation for module `\gpio_wb'.
Generating RTLIL representation for module `\gpio'.
Generating RTLIL representation for module `\sysctrl_wb'.
Generating RTLIL representation for module `\sysctrl'.
Generating RTLIL representation for module `\la_wb'.
Generating RTLIL representation for module `\la'.
Generating RTLIL representation for module `\mprj_ctrl_wb'.
Generating RTLIL representation for module `\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270
Generating RTLIL representation for module `\convert_gpio_sigs'.
Generating RTLIL representation for module `\mgmt_soc'.
Generating RTLIL representation for module `\mgmt_soc_regs'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v
Parsing Verilog input from `/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:129)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:130)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:131)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:133)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:134)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:135)
Generating RTLIL representation for module `\housekeeping_spi'.
Generating RTLIL representation for module `\housekeeping_spi_slave'.
Successfully finished Verilog frontend.

11. Executing HIERARCHY pass (managing design hierarchy).

11.1. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         \wb_intercon
Used module:         \storage_bridge_wb
Used module:         \mem_wb
Used module:             \soc_mem
Used module:         \mprj_ctrl_wb
Used module:             \mprj_ctrl
Used module:         \la_wb
Used module:             \la
Used module:         \sysctrl_wb
Used module:             \sysctrl
Used module:         \gpio_wb
Used module:             \gpio
Used module:         \counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         \counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         \simple_spi_master_wb
Used module:             \simple_spi_master
Used module:         \simpleuart_wb
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         \picorv32_wb
Used module:             \picorv32
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         \clock_div
Used module:             \odd
Used module:             \even
Parameter \SIZE = 3

11.2. Executing AST frontend in derive mode using pre-parsed AST for module `\clock_div'.
Parameter \SIZE = 3
Generating RTLIL representation for module `$paramod\clock_div\SIZE=3'.
Parameter \SIZE = 3
Found cached RTLIL representation for module `$paramod\clock_div\SIZE=3'.
Parameter \DW = 32
Parameter \AW = 32
Parameter \NS = 14
Parameter \ADR_MASK = 448'1111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000
Parameter \SLAVE_ADR = 448'0010111100000000000000000000000000101101000000000000000000000000001100000000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000

11.3. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_intercon'.
Parameter \DW = 32
Parameter \AW = 32
Parameter \NS = 14
Parameter \ADR_MASK = 448'1111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000
Parameter \SLAVE_ADR = 448'0010111100000000000000000000000000101101000000000000000000000000001100000000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
Generating RTLIL representation for module `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon'.
Parameter \RW_BLOCKS_ADR = 48'000100000000000000000000000000000000000000000000
Parameter \RO_BLOCKS_ADR = 24'000000000000000000000000

11.4. Executing AST frontend in derive mode using pre-parsed AST for module `\storage_bridge_wb'.
Parameter \RW_BLOCKS_ADR = 48'000100000000000000000000000000000000000000000000
Parameter \RO_BLOCKS_ADR = 24'000000000000000000000000
Generating RTLIL representation for module `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb'.
Parameter \BASE_ADR = 637534208

11.5. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl_wb'.
Parameter \BASE_ADR = 637534208
Generating RTLIL representation for module `$paramod\mprj_ctrl_wb\BASE_ADR=637534208'.
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100

11.6. Executing AST frontend in derive mode using pre-parsed AST for module `\la_wb'.
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
Generating RTLIL representation for module `$paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100

11.7. Executing AST frontend in derive mode using pre-parsed AST for module `\sysctrl_wb'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
Generating RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100

11.8. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio_wb'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
Generating RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb'.
Parameter \BASE_ADR = 587202560
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000

11.9. Executing AST frontend in derive mode using pre-parsed AST for module `\counter_timer_high_wb'.
Parameter \BASE_ADR = 587202560
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000
Generating RTLIL representation for module `$paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb'.
Parameter \BASE_ADR = 570425344
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000

11.10. Executing AST frontend in derive mode using pre-parsed AST for module `\counter_timer_low_wb'.
Parameter \BASE_ADR = 570425344
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000
Generating RTLIL representation for module `$paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb'.
Parameter \BASE_ADR = 603979776
Parameter \CONFIG = 8'00000000
Parameter \DATA = 8'00000100

11.11. Executing AST frontend in derive mode using pre-parsed AST for module `\simple_spi_master_wb'.
Parameter \BASE_ADR = 603979776
Parameter \CONFIG = 8'00000000
Parameter \DATA = 8'00000100
Generating RTLIL representation for module `$paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100'.
Parameter \BASE_ADR = 536870912
Parameter \CLK_DIV = 8'00000000
Parameter \DATA = 8'00000100

11.12. Executing AST frontend in derive mode using pre-parsed AST for module `\simpleuart_wb'.
Parameter \BASE_ADR = 536870912
Parameter \CLK_DIV = 8'00000000
Parameter \DATA = 8'00000100
Generating RTLIL representation for module `$paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100'.
Parameter \BARREL_SHIFTER = 1
Parameter \COMPRESSED_ISA = 1
Parameter \ENABLE_MUL = 1
Parameter \ENABLE_DIV = 1
Parameter \ENABLE_IRQ = 1
Parameter \ENABLE_IRQ_QREGS = 0
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024

11.13. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32_wb'.
Parameter \BARREL_SHIFTER = 1
Parameter \COMPRESSED_ISA = 1
Parameter \ENABLE_MUL = 1
Parameter \ENABLE_DIV = 1
Parameter \ENABLE_IRQ = 1
Parameter \ENABLE_IRQ_QREGS = 0
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024
Generating RTLIL representation for module `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'0
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'0
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'0
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'0
Parameter \ENABLE_IRQ = 1'0
Parameter \ENABLE_IRQ_QREGS = 1'1
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 0
Parameter \PROGADDR_IRQ = 16
Parameter \STACKADDR = 32'11111111111111111111111111111111

11.14. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'0
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'0
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'0
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'0
Parameter \ENABLE_IRQ = 1'0
Parameter \ENABLE_IRQ_QREGS = 1'1
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 0
Parameter \PROGADDR_IRQ = 16
Parameter \STACKADDR = 32'11111111111111111111111111111111
Generating RTLIL representation for module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'.
Parameter \WORDS = 256
Parameter \ADR_WIDTH = 8

11.15. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_mem'.
Parameter \WORDS = 256
Parameter \ADR_WIDTH = 8
Generating RTLIL representation for module `$paramod\soc_mem\WORDS=256\ADR_WIDTH=8'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100

11.16. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
Generating RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100

11.17. Executing AST frontend in derive mode using pre-parsed AST for module `\sysctrl'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
Generating RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl'.
Parameter \BASE_ADR = 570425344
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100

11.18. Executing AST frontend in derive mode using pre-parsed AST for module `\la'.
Parameter \BASE_ADR = 570425344
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
Generating RTLIL representation for module `$paramod$499b0a1c054fbe1b70d6dc28b15376e5cd987bff\la'.
Parameter \BASE_ADR = 587202560
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000

11.19. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl'.
Parameter \BASE_ADR = 587202560
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000
Generating RTLIL representation for module `$paramod$ed88d8bd975b89882ecfbd510fe3c5e6ac127a6b\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270

11.20. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module:         $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module:         \mem_wb
Used module:             $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module:         $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module:             \mprj_ctrl
Used module:         $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module:             \la
Used module:         $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module:             \sysctrl
Used module:         $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module:             \gpio
Used module:         $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module:             \simple_spi_master
Used module:         $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module:             \picorv32
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         $paramod\clock_div\SIZE=3
Used module:             \odd
Used module:             \even
Parameter \BASE_ADR = 637534208
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000

11.21. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl'.
Parameter \BASE_ADR = 637534208
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000
Generating RTLIL representation for module `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100

11.22. Executing AST frontend in derive mode using pre-parsed AST for module `\la'.
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
Generating RTLIL representation for module `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
Found cached RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
Found cached RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'1
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'1
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'1
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'1
Parameter \ENABLE_IRQ = 1'1
Parameter \ENABLE_IRQ_QREGS = 1'0
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024

11.23. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'1
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'1
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'1
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'1
Parameter \ENABLE_IRQ = 1'1
Parameter \ENABLE_IRQ_QREGS = 1'0
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024
Generating RTLIL representation for module `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32'.

11.24. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module:         $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module:         \mem_wb
Used module:             $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module:         $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module:             $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module:         $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module:             $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module:         $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module:             $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module:         $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module:             $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module:         $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module:             \simple_spi_master
Used module:         $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module:             $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module:                 \picorv32_pcpi_div
Used module:                 \picorv32_pcpi_mul
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         $paramod\clock_div\SIZE=3
Used module:             \odd
Used module:             \even

11.25. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module:         $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module:         \mem_wb
Used module:             $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module:         $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module:             $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module:         $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module:             $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module:         $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module:             $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module:         $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module:             $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module:         $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module:             \simple_spi_master
Used module:         $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module:             $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module:                 \picorv32_pcpi_div
Used module:                 \picorv32_pcpi_mul
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         $paramod\clock_div\SIZE=3
Used module:             \odd
Used module:             \even
Removing unused module `$paramod$ed88d8bd975b89882ecfbd510fe3c5e6ac127a6b\mprj_ctrl'.
Removing unused module `$paramod$499b0a1c054fbe1b70d6dc28b15376e5cd987bff\la'.
Removing unused module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'.
Removing unused module `\mprj_ctrl'.
Removing unused module `\mprj_ctrl_wb'.
Removing unused module `\la'.
Removing unused module `\la_wb'.
Removing unused module `\sysctrl'.
Removing unused module `\sysctrl_wb'.
Removing unused module `\gpio'.
Removing unused module `\gpio_wb'.
Removing unused module `\soc_mem'.
Removing unused module `\wb_intercon'.
Removing unused module `\counter_timer_low_wb'.
Removing unused module `\counter_timer_high_wb'.
Removing unused module `\simple_spi_master_wb'.
Removing unused module `\simpleuart_wb'.
Removing unused module `\picorv32_wb'.
Removing unused module `\picorv32_axi_adapter'.
Removing unused module `\picorv32_axi'.
Removing unused module `\picorv32_pcpi_fast_mul'.
Removing unused module `\picorv32_regs'.
Removing unused module `\picorv32'.
Removing unused module `\clock_div'.
Removing unused module `\storage_bridge_wb'.
Removed 25 unused modules.
Mapping positional arguments of cell $paramod\clock_div\SIZE=3.odd_0 (odd).
Mapping positional arguments of cell $paramod\clock_div\SIZE=3.even_0 (even).

12. Executing SYNTH pass.

12.1. Executing HIERARCHY pass (managing design hierarchy).

12.1.1. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module:         $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module:         \mem_wb
Used module:             $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module:         $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module:             $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module:         $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module:             $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module:         $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module:             $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module:         $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module:             $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module:         $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module:             \simple_spi_master
Used module:         $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module:             $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module:                 \picorv32_pcpi_div
Used module:                 \picorv32_pcpi_mul
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         $paramod\clock_div\SIZE=3
Used module:             \odd
Used module:             \even

12.1.2. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module:         $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module:         \mem_wb
Used module:             $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module:         $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module:             $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module:         $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module:             $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module:         $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module:             $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module:         $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module:             $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module:         $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module:             \simple_spi_master
Used module:         $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module:             $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module:                 \picorv32_pcpi_div
Used module:                 \picorv32_pcpi_mul
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         $paramod\clock_div\SIZE=3
Used module:             \odd
Used module:             \even
Removed 0 unused modules.

12.2. Executing PROC pass (convert processes to netlists).

12.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 16 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
Found and cleaned up 1 empty switch in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
Found and cleaned up 6 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:546$6993'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:546$6993'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
Found and cleaned up 1 empty switch in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
Cleaned up 62 empty switches.

12.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 41 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 8 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 47 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Removed 2 dead cases from process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 8 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855 in module $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443 in module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433 in module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 11 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 43 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757 in module $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156 in module mem_wb.
Marked 22 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519 in module counter_timer_low.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509 in module counter_timer_low.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507 in module counter_timer_low.
Marked 17 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458 in module counter_timer_high.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450 in module counter_timer_high.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448 in module counter_timer_high.
Marked 5 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413 in module simple_spi_master.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407 in module simple_spi_master.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401 in module simple_spi_master.
Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390 in module simple_spi_master.
Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373 in module simple_spi_master.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371 in module simple_spi_master.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326 in module simpleuart.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316 in module simpleuart.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314 in module simpleuart.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268 in module spimemio_xfer.
Marked 5 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244 in module spimemio_xfer.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214 in module spimemio.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146 in module spimemio.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506 in module $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066 in module picorv32_pcpi_div.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045 in module $paramod\clock_div\SIZE=3.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023 in module picorv32_pcpi_mul.
Marked 16 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011 in module housekeeping_spi_slave.
Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001 in module housekeeping_spi_slave.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994 in module housekeeping_spi.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263 in module caravel_clocking.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258 in module caravel_clocking.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252 in module even.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244 in module odd.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236 in module odd.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230 in module odd.
Removed a total of 2 dead cases.

12.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 24 redundant assignments.
Promoted 263 assignments to connections.

12.2.4. Executing PROC_INIT pass (extract init attributes).

12.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \resetn in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
Found async reset \resetb in `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
Found async reset \csb_reset in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
Found async reset \csb_reset in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
Found async reset \RSTB in `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
Found async reset \resetb in `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
Found async reset \resetb in `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
Found async reset \resetb in `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.

12.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
     1/86: $23\next_irq_pending[2:2]
     2/86: $22\next_irq_pending[2:2]
     3/86: $21\next_irq_pending[2:2]
     4/86: $20\next_irq_pending[2:2]
     5/86: $19\next_irq_pending[2:2]
     6/86: $18\next_irq_pending[2:2]
     7/86: $17\next_irq_pending[2:2]
     8/86: $16\next_irq_pending[0:0]
     9/86: $15\next_irq_pending[0:0]
    10/86: $14\next_irq_pending[31:0] [0]
    11/86: $14\next_irq_pending[31:0] [31:1]
    12/86: $2\next_irq_pending[31:0] [31:2]
    13/86: $3\set_mem_do_rdata[0:0]
    14/86: $2\next_irq_pending[31:0] [1]
    15/86: $3\set_mem_do_wdata[0:0]
    16/86: $2\next_irq_pending[31:0] [0]
    17/86: $4\set_mem_do_rinst[0:0]
    18/86: $3\set_mem_do_rinst[0:0]
    19/86: $4\set_mem_do_wdata[0:0]
    20/86: $12\next_irq_pending[1:1]
    21/86: $11\next_irq_pending[1:1]
    22/86: $10\next_irq_pending[1:1]
    23/86: $4\set_mem_do_rdata[0:0]
    24/86: $8\next_irq_pending[1:1]
    25/86: $7\next_irq_pending[1:1]
    26/86: $6\next_irq_pending[1:1]
    27/86: $5\next_irq_pending[1:1]
    28/86: $4\next_irq_pending[1:1]
    29/86: $13\next_irq_pending[1:1]
    30/86: $5\set_mem_do_rinst[0:0]
    31/86: $9\next_irq_pending[1:1]
    32/86: $3\next_irq_pending[31:0]
    33/86: $3\current_pc[31:0]
    34/86: $2\current_pc[31:0]
    35/86: $2\set_mem_do_wdata[0:0]
    36/86: $2\set_mem_do_rdata[0:0]
    37/86: $2\set_mem_do_rinst[0:0]
    38/86: $1\next_irq_pending[31:0]
    39/86: $1\current_pc[31:0]
    40/86: $1\set_mem_do_wdata[0:0]
    41/86: $1\set_mem_do_rdata[0:0]
    42/86: $1\set_mem_do_rinst[0:0]
    43/86: $0\trace_data[35:0]
    44/86: $0\count_cycle[63:0]
    45/86: $0\pcpi_timeout[0:0]
    46/86: $0\trace_valid[0:0]
    47/86: $0\do_waitirq[0:0]
    48/86: $0\decoder_pseudo_trigger[0:0]
    49/86: $0\decoder_trigger[0:0]
    50/86: $0\alu_wait_2[0:0]
    51/86: $0\alu_wait[0:0]
    52/86: $0\reg_out[31:0]
    53/86: $0\reg_sh[4:0]
    54/86: $0\trap[0:0]
    55/86: $0\pcpi_timeout_counter[3:0]
    56/86: $0\latched_rd[4:0]
    57/86: $0\latched_is_lb[0:0]
    58/86: $0\latched_is_lh[0:0]
    59/86: $0\latched_is_lu[0:0]
    60/86: $0\latched_trace[0:0]
    61/86: $0\latched_compr[0:0]
    62/86: $0\latched_branch[0:0]
    63/86: $0\latched_stalu[0:0]
    64/86: $0\latched_store[0:0]
    65/86: $0\irq_state[1:0]
    66/86: $0\cpu_state[7:0]
    67/86: $0\dbg_rs2val_valid[0:0]
    68/86: $0\dbg_rs1val_valid[0:0]
    69/86: $0\dbg_rs2val[31:0]
    70/86: $0\dbg_rs1val[31:0]
    71/86: $0\mem_do_wdata[0:0]
    72/86: $0\mem_do_rdata[0:0]
    73/86: $0\mem_do_rinst[0:0]
    74/86: $0\mem_do_prefetch[0:0]
    75/86: $0\mem_wordsize[1:0]
    76/86: $0\timer[31:0]
    77/86: $0\irq_mask[31:0]
    78/86: $0\irq_active[0:0]
    79/86: $0\irq_delay[0:0]
    80/86: $0\reg_op2[31:0]
    81/86: $0\reg_op1[31:0]
    82/86: $0\reg_next_pc[31:0]
    83/86: $0\reg_pc[31:0]
    84/86: $0\count_instr[63:0]
    85/86: $0\eoi[31:0]
    86/86: $0\pcpi_valid[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
     1/4: $2\cpuregs_write[0:0]
     2/4: $2\cpuregs_wrdata[31:0]
     3/4: $1\cpuregs_wrdata[31:0]
     4/4: $1\cpuregs_write[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
     1/2: $2\clear_prefetched_high_word[0:0]
     2/2: $1\clear_prefetched_high_word[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'.
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
     1/2: $1\alu_out[31:0]
     2/2: $1\alu_out_0[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
     1/8: $8\dbg_ascii_state[127:0]
     2/8: $7\dbg_ascii_state[127:0]
     3/8: $6\dbg_ascii_state[127:0]
     4/8: $5\dbg_ascii_state[127:0]
     5/8: $4\dbg_ascii_state[127:0]
     6/8: $3\dbg_ascii_state[127:0]
     7/8: $2\dbg_ascii_state[127:0]
     8/8: $1\dbg_ascii_state[127:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
     1/76: $0\decoded_rs1[4:0] [4]
     2/76: $0\decoded_imm_j[31:0] [10]
     3/76: $0\decoded_imm_j[31:0] [7]
     4/76: $0\decoded_imm_j[31:0] [6]
     5/76: $0\decoded_imm_j[31:0] [3:1]
     6/76: $0\decoded_imm_j[31:0] [5]
     7/76: $0\decoded_imm_j[31:0] [9:8]
     8/76: $0\decoded_imm_j[31:0] [31:20]
     9/76: $0\decoded_imm_j[31:0] [4]
    10/76: $0\decoded_imm_j[31:0] [11]
    11/76: $0\decoded_imm_j[31:0] [0]
    12/76: $0\decoded_rs1[4:0] [3:0]
    13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0]
    14/76: $0\is_alu_reg_reg[0:0]
    15/76: $0\is_alu_reg_imm[0:0]
    16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0]
    17/76: $0\is_sll_srl_sra[0:0]
    18/76: $0\is_sb_sh_sw[0:0]
    19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0]
    20/76: $0\is_slli_srli_srai[0:0]
    21/76: $0\is_lb_lh_lw_lbu_lhu[0:0]
    22/76: $0\compressed_instr[0:0]
    23/76: $0\is_compare[0:0]
    24/76: $0\decoded_imm[31:0]
    25/76: $0\decoded_rs2[4:0]
    26/76: $0\decoded_imm_j[31:0] [19:12]
    27/76: $0\decoded_rd[4:0]
    28/76: $0\instr_timer[0:0]
    29/76: $0\instr_waitirq[0:0]
    30/76: $0\instr_maskirq[0:0]
    31/76: $0\instr_retirq[0:0]
    32/76: $0\instr_setq[0:0]
    33/76: $0\instr_getq[0:0]
    34/76: $0\instr_ecall_ebreak[0:0]
    35/76: $0\instr_rdinstrh[0:0]
    36/76: $0\instr_rdinstr[0:0]
    37/76: $0\instr_rdcycleh[0:0]
    38/76: $0\instr_rdcycle[0:0]
    39/76: $0\instr_and[0:0]
    40/76: $0\instr_or[0:0]
    41/76: $0\instr_sra[0:0]
    42/76: $0\instr_srl[0:0]
    43/76: $0\instr_xor[0:0]
    44/76: $0\instr_sltu[0:0]
    45/76: $0\instr_slt[0:0]
    46/76: $0\instr_sll[0:0]
    47/76: $0\instr_sub[0:0]
    48/76: $0\instr_add[0:0]
    49/76: $0\instr_srai[0:0]
    50/76: $0\instr_srli[0:0]
    51/76: $0\instr_slli[0:0]
    52/76: $0\instr_andi[0:0]
    53/76: $0\instr_ori[0:0]
    54/76: $0\instr_xori[0:0]
    55/76: $0\instr_sltiu[0:0]
    56/76: $0\instr_slti[0:0]
    57/76: $0\instr_addi[0:0]
    58/76: $0\instr_sw[0:0]
    59/76: $0\instr_sh[0:0]
    60/76: $0\instr_sb[0:0]
    61/76: $0\instr_lhu[0:0]
    62/76: $0\instr_lbu[0:0]
    63/76: $0\instr_lw[0:0]
    64/76: $0\instr_lh[0:0]
    65/76: $0\instr_lb[0:0]
    66/76: $0\instr_bgeu[0:0]
    67/76: $0\instr_bltu[0:0]
    68/76: $0\instr_bge[0:0]
    69/76: $0\instr_blt[0:0]
    70/76: $0\instr_bne[0:0]
    71/76: $0\instr_beq[0:0]
    72/76: $0\instr_jalr[0:0]
    73/76: $0\instr_jal[0:0]
    74/76: $0\instr_auipc[0:0]
    75/76: $0\instr_lui[0:0]
    76/76: $0\pcpi_insn[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
     1/13: $3\dbg_insn_opcode[31:0]
     2/13: $2\dbg_insn_rd[4:0]
     3/13: $2\dbg_insn_rs2[4:0]
     4/13: $2\dbg_insn_rs1[4:0]
     5/13: $2\dbg_insn_opcode[31:0]
     6/13: $2\dbg_insn_imm[31:0]
     7/13: $2\dbg_ascii_instr[63:0]
     8/13: $1\dbg_insn_rd[4:0]
     9/13: $1\dbg_insn_rs2[4:0]
    10/13: $1\dbg_insn_rs1[4:0]
    11/13: $1\dbg_insn_imm[31:0]
    12/13: $1\dbg_ascii_instr[63:0]
    13/13: $1\dbg_insn_opcode[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
     1/8: $0\cached_insn_rd[4:0]
     2/8: $0\cached_insn_rs2[4:0]
     3/8: $0\cached_insn_rs1[4:0]
     4/8: $0\cached_insn_opcode[31:0]
     5/8: $0\cached_insn_imm[31:0]
     6/8: $0\cached_ascii_instr[63:0]
     7/8: $0\dbg_valid_insn[0:0]
     8/8: $0\dbg_insn_addr[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
     1/47: $47\new_ascii_instr[63:0]
     2/47: $46\new_ascii_instr[63:0]
     3/47: $45\new_ascii_instr[63:0]
     4/47: $44\new_ascii_instr[63:0]
     5/47: $43\new_ascii_instr[63:0]
     6/47: $42\new_ascii_instr[63:0]
     7/47: $41\new_ascii_instr[63:0]
     8/47: $40\new_ascii_instr[63:0]
     9/47: $39\new_ascii_instr[63:0]
    10/47: $38\new_ascii_instr[63:0]
    11/47: $37\new_ascii_instr[63:0]
    12/47: $36\new_ascii_instr[63:0]
    13/47: $35\new_ascii_instr[63:0]
    14/47: $34\new_ascii_instr[63:0]
    15/47: $33\new_ascii_instr[63:0]
    16/47: $32\new_ascii_instr[63:0]
    17/47: $31\new_ascii_instr[63:0]
    18/47: $30\new_ascii_instr[63:0]
    19/47: $29\new_ascii_instr[63:0]
    20/47: $28\new_ascii_instr[63:0]
    21/47: $27\new_ascii_instr[63:0]
    22/47: $26\new_ascii_instr[63:0]
    23/47: $25\new_ascii_instr[63:0]
    24/47: $24\new_ascii_instr[63:0]
    25/47: $23\new_ascii_instr[63:0]
    26/47: $22\new_ascii_instr[63:0]
    27/47: $21\new_ascii_instr[63:0]
    28/47: $20\new_ascii_instr[63:0]
    29/47: $19\new_ascii_instr[63:0]
    30/47: $18\new_ascii_instr[63:0]
    31/47: $17\new_ascii_instr[63:0]
    32/47: $16\new_ascii_instr[63:0]
    33/47: $15\new_ascii_instr[63:0]
    34/47: $14\new_ascii_instr[63:0]
    35/47: $13\new_ascii_instr[63:0]
    36/47: $12\new_ascii_instr[63:0]
    37/47: $11\new_ascii_instr[63:0]
    38/47: $10\new_ascii_instr[63:0]
    39/47: $9\new_ascii_instr[63:0]
    40/47: $8\new_ascii_instr[63:0]
    41/47: $7\new_ascii_instr[63:0]
    42/47: $6\new_ascii_instr[63:0]
    43/47: $5\new_ascii_instr[63:0]
    44/47: $4\new_ascii_instr[63:0]
    45/47: $3\new_ascii_instr[63:0]
    46/47: $2\new_ascii_instr[63:0]
    47/47: $1\new_ascii_instr[63:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
     1/9: $0\mem_16bit_buffer[15:0]
     2/9: $0\prefetched_high_word[0:0]
     3/9: $0\mem_la_secondword[0:0]
     4/9: $0\mem_state[1:0]
     5/9: $0\mem_wstrb[3:0]
     6/9: $0\mem_wdata[31:0]
     7/9: $0\mem_addr[31:0]
     8/9: $0\mem_instr[0:0]
     9/9: $0\mem_valid[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
     1/9: $0\mem_rdata_q[31:0] [31]
     2/9: $0\mem_rdata_q[31:0] [7]
     3/9: $0\mem_rdata_q[31:0] [24:20]
     4/9: $0\mem_rdata_q[31:0] [19:15]
     5/9: $0\mem_rdata_q[31:0] [6:0]
     6/9: $0\mem_rdata_q[31:0] [14:12]
     7/9: $0\mem_rdata_q[31:0] [11:8]
     8/9: $0\mem_rdata_q[31:0] [30:25]
     9/9: $0\next_insn_opcode[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
     1/5: $3\mem_rdata_word[31:0]
     2/5: $2\mem_rdata_word[31:0]
     3/5: $1\mem_rdata_word[31:0]
     4/5: $1\mem_la_wstrb[3:0]
     5/5: $1\mem_la_wdata[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
     1/2: $0\last_mem_valid[0:0]
     2/2: $0\mem_la_firstword_reg[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
     1/2: $1\pcpi_int_rd[31:0]
     2/2: $1\pcpi_int_wr[0:0]
Creating decoders for process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
     1/34: $0\la_ena_3[31:0] [31:24]
     2/34: $0\la_ena_3[31:0] [23:16]
     3/34: $0\la_ena_3[31:0] [15:8]
     4/34: $0\la_ena_3[31:0] [7:0]
     5/34: $0\la_ena_2[31:0] [23:16]
     6/34: $0\la_ena_2[31:0] [15:8]
     7/34: $0\la_ena_2[31:0] [7:0]
     8/34: $0\la_ena_1[31:0] [23:16]
     9/34: $0\la_ena_1[31:0] [15:8]
    10/34: $0\la_ena_1[31:0] [7:0]
    11/34: $0\la_ena_0[31:0] [23:16]
    12/34: $0\la_ena_0[31:0] [15:8]
    13/34: $0\la_ena_0[31:0] [7:0]
    14/34: $0\la_data_3[31:0] [23:16]
    15/34: $0\la_data_3[31:0] [15:8]
    16/34: $0\la_data_3[31:0] [7:0]
    17/34: $0\la_data_2[31:0] [23:16]
    18/34: $0\la_data_2[31:0] [15:8]
    19/34: $0\la_data_2[31:0] [7:0]
    20/34: $0\la_data_1[31:0] [23:16]
    21/34: $0\la_data_1[31:0] [15:8]
    22/34: $0\la_data_1[31:0] [7:0]
    23/34: $0\la_data_0[31:0] [23:16]
    24/34: $0\la_data_0[31:0] [15:8]
    25/34: $0\la_data_0[31:0] [7:0]
    26/34: $0\la_ena_1[31:0] [31:24]
    27/34: $0\la_ena_0[31:0] [31:24]
    28/34: $0\la_data_3[31:0] [31:24]
    29/34: $0\la_data_2[31:0] [31:24]
    30/34: $0\la_data_1[31:0] [31:24]
    31/34: $0\la_data_0[31:0] [31:24]
    32/34: $0\la_ena_2[31:0] [31:24]
    33/34: $0\iomem_ready[0:0]
    34/34: $0\iomem_rdata[31:0]
Creating decoders for process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
     1/7: $0\irq_8_inputsrc[0:0]
     2/7: $0\irq_7_inputsrc[0:0]
     3/7: $0\trap_output_dest[0:0]
     4/7: $0\clk2_output_dest[0:0]
     5/7: $0\clk1_output_dest[0:0]
     6/7: $0\iomem_ready[0:0]
     7/7: $0\iomem_rdata[31:0]
Creating decoders for process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
     1/6: $0\iomem_ready[0:0]
     2/6: $0\iomem_rdata[31:0]
     3/6: $0\gpio_pd[0:0]
     4/6: $0\gpio_pu[0:0]
     5/6: $0\gpio_oeb[0:0]
     6/6: $0\gpio[0:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
     1/1: $0\io_ctrl[37][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
     1/1: $0\io_ctrl[36][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
     1/1: $0\io_ctrl[35][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
     1/1: $0\io_ctrl[34][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
     1/1: $0\io_ctrl[33][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
     1/1: $0\io_ctrl[32][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
     1/1: $0\io_ctrl[31][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
     1/1: $0\io_ctrl[30][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
     1/1: $0\io_ctrl[29][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
     1/1: $0\io_ctrl[28][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
     1/1: $0\io_ctrl[27][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
     1/1: $0\io_ctrl[26][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
     1/1: $0\io_ctrl[25][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
     1/1: $0\io_ctrl[24][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
     1/1: $0\io_ctrl[23][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
     1/1: $0\io_ctrl[22][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
     1/1: $0\io_ctrl[21][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
     1/1: $0\io_ctrl[20][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
     1/1: $0\io_ctrl[19][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
     1/1: $0\io_ctrl[18][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
     1/1: $0\io_ctrl[17][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
     1/1: $0\io_ctrl[16][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
     1/1: $0\io_ctrl[15][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
     1/1: $0\io_ctrl[14][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
     1/1: $0\io_ctrl[13][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
     1/1: $0\io_ctrl[12][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
     1/1: $0\io_ctrl[11][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
     1/1: $0\io_ctrl[10][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
     1/1: $0\io_ctrl[9][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
     1/1: $0\io_ctrl[8][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
     1/1: $0\io_ctrl[7][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
     1/1: $0\io_ctrl[6][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
     1/1: $0\io_ctrl[5][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
     1/1: $0\io_ctrl[4][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
     1/1: $0\io_ctrl[3][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
     1/1: $0\io_ctrl[2][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
     1/1: $0\io_ctrl[1][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
     1/1: $0\io_ctrl[0][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
     1/1: $0\mgmt_gpio_outr[37:32]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
     1/1: $0\mgmt_gpio_outr[31:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
     1/13: $4$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6397
     2/13: $3$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6394
     3/13: $3$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6393
     4/13: $2$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6390
     5/13: $2$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6389
     6/13: $1$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6387
     7/13: $1$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6386
     8/13: $0\serial_data_staging[12:0]
     9/13: $0\xfer_state[1:0]
    10/13: $0\pad_count[5:0]
    11/13: $0\xfer_count[3:0]
    12/13: $0\serial_resetn[0:0]
    13/13: $0\serial_clock[0:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
     1/2: $0\xfer_ctrl[0:0]
     2/2: $0\pwr_ctrl_out[3:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
     1/2: $0\iomem_ready[0:0]
     2/2: $0\iomem_rdata[31:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
     1/46: $43\iomem_rdata_pre[31:0]
     2/46: $42\iomem_rdata_pre[31:0]
     3/46: $41\iomem_rdata_pre[31:0]
     4/46: $40\iomem_rdata_pre[31:0]
     5/46: $39\iomem_rdata_pre[31:0]
     6/46: $38\iomem_rdata_pre[31:0]
     7/46: $37\iomem_rdata_pre[31:0]
     8/46: $36\iomem_rdata_pre[31:0]
     9/46: $35\iomem_rdata_pre[31:0]
    10/46: $34\iomem_rdata_pre[31:0]
    11/46: $33\iomem_rdata_pre[31:0]
    12/46: $32\iomem_rdata_pre[31:0]
    13/46: $31\iomem_rdata_pre[31:0]
    14/46: $30\iomem_rdata_pre[31:0]
    15/46: $29\iomem_rdata_pre[31:0]
    16/46: $28\iomem_rdata_pre[31:0]
    17/46: $27\iomem_rdata_pre[31:0]
    18/46: $26\iomem_rdata_pre[31:0]
    19/46: $25\iomem_rdata_pre[31:0]
    20/46: $24\iomem_rdata_pre[31:0]
    21/46: $23\iomem_rdata_pre[31:0]
    22/46: $22\iomem_rdata_pre[31:0]
    23/46: $21\iomem_rdata_pre[31:0]
    24/46: $20\iomem_rdata_pre[31:0]
    25/46: $19\iomem_rdata_pre[31:0]
    26/46: $18\iomem_rdata_pre[31:0]
    27/46: $17\iomem_rdata_pre[31:0]
    28/46: $16\iomem_rdata_pre[31:0]
    29/46: $15\iomem_rdata_pre[31:0]
    30/46: $14\iomem_rdata_pre[31:0]
    31/46: $13\iomem_rdata_pre[31:0]
    32/46: $12\iomem_rdata_pre[31:0]
    33/46: $11\iomem_rdata_pre[31:0]
    34/46: $10\iomem_rdata_pre[31:0]
    35/46: $9\iomem_rdata_pre[31:0]
    36/46: $8\iomem_rdata_pre[31:0]
    37/46: $7\iomem_rdata_pre[31:0]
    38/46: $6\iomem_rdata_pre[31:0]
    39/46: $5\iomem_rdata_pre[31:0]
    40/46: $4\iomem_rdata_pre[31:0]
    41/46: $3\j[31:0]
    42/46: $3\iomem_rdata_pre[31:0]
    43/46: $2\iomem_rdata_pre[31:0]
    44/46: $2\j[31:0]
    45/46: $1\iomem_rdata_pre[31:0]
    46/46: $1\j[31:0]
Creating decoders for process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
     1/9: $0\state[1:0]
     2/9: $0\wbm_cyc_o[0:0]
     3/9: $0\wbm_stb_o[0:0]
     4/9: $0\wbm_sel_o[3:0]
     5/9: $0\wbm_we_o[0:0]
     6/9: $0\wbm_dat_o[31:0]
     7/9: $0\wbm_adr_o[31:0]
     8/9: $0\mem_rdata[31:0]
     9/9: $0\mem_ready[0:0]
Creating decoders for process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
     1/2: $0\wb_ack_o[0:0]
     2/2: $0\wb_ack_read[0:0]
Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
     1/8: $0\value_cur[31:0] [31:24]
     2/8: $0\value_cur[31:0] [7:0]
     3/8: $0\value_cur[31:0] [15:8]
     4/8: $0\value_cur[31:0] [23:16]
     5/8: $0\lastenable[0:0]
     6/8: $0\stop_out[0:0]
     7/8: $0\strobe[0:0]
     8/8: $0\irq_out[0:0]
Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
     1/4: $0\value_reset[31:0] [15:8]
     2/4: $0\value_reset[31:0] [7:0]
     3/4: $0\value_reset[31:0] [23:16]
     4/4: $0\value_reset[31:0] [31:24]
Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
     1/5: $0\chain[0:0]
     2/5: $0\irq_ena[0:0]
     3/5: $0\updown[0:0]
     4/5: $0\oneshot[0:0]
     5/5: $0\enable[0:0]
Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
     1/7: $0\value_cur[31:0] [31:24]
     2/7: $0\value_cur[31:0] [23:16]
     3/7: $0\value_cur[31:0] [7:0]
     4/7: $0\value_cur[31:0] [15:8]
     5/7: $0\lastenable[0:0]
     6/7: $0\stop_out[0:0]
     7/7: $0\irq_out[0:0]
Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
     1/4: $0\value_reset[31:0] [15:8]
     2/4: $0\value_reset[31:0] [7:0]
     3/4: $0\value_reset[31:0] [23:16]
     4/4: $0\value_reset[31:0] [31:24]
Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
     1/5: $0\chain[0:0]
     2/5: $0\irq_ena[0:0]
     3/5: $0\updown[0:0]
     4/5: $0\oneshot[0:0]
     5/5: $0\enable[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
     1/3: $0\rreg[7:0]
     2/3: $0\treg[7:0]
     3/3: $0\isdo[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
     1/1: $0\isck[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
     1/2: $0\count[7:0]
     2/2: $0\hsck[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
     1/4: $0\nbit[2:0]
     2/4: $0\icsb[0:0]
     3/4: $0\done[0:0]
     4/4: $0\state[1:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
     1/4: $0\r_latched[0:0]
     2/4: $0\w_latched[0:0]
     3/4: $0\d_latched[7:0]
     4/4: $0\err_out[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
     1/9: $0\hkconn[0:0]
     2/9: $0\mode[0:0]
     3/9: $0\stream[0:0]
     4/9: $0\irqena[0:0]
     5/9: $0\mlb[0:0]
     6/9: $0\invcsb[0:0]
     7/9: $0\invsck[0:0]
     8/9: $0\prescaler[7:0]
     9/9: $0\enable[0:0]
Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
     1/4: $0\send_divcnt[31:0]
     2/4: $0\send_dummy[0:0]
     3/4: $0\send_bitcnt[3:0]
     4/4: $0\send_pattern[9:0]
Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
     1/5: $0\recv_divcnt[31:0]
     2/5: $0\recv_buf_valid[0:0]
     3/5: $0\recv_buf_data[7:0]
     4/5: $0\recv_pattern[7:0]
     5/5: $0\recv_state[3:0]
Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
     1/5: $0\cfg_divider[31:0] [31:24]
     2/5: $0\cfg_divider[31:0] [23:16]
     3/5: $0\cfg_divider[31:0] [15:8]
     4/5: $0\cfg_divider[31:0] [7:0]
     5/5: $0\enabled[0:0]
Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
     1/14: $0\last_fetch[0:0]
     2/14: $0\fetch[0:0]
     3/14: $0\xfer_tag[3:0]
     4/14: $0\xfer_rd[0:0]
     5/14: $0\xfer_qspi[0:0]
     6/14: $0\xfer_cont[0:0]
     7/14: $0\dummy_count[3:0]
     8/14: $0\count[3:0]
     9/14: $0\ibuffer[7:0]
    10/14: $0\obuffer[7:0]
    11/14: $0\xfer_ddr[0:0]
    12/14: $0\xfer_dspi[0:0]
    13/14: $0\flash_clk[0:0]
    14/14: $0\flash_csb[0:0]
Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
     1/33: $5\next_count[3:0]
     2/33: $5\next_obuffer[7:0]
     3/33: $5\next_ibuffer[7:0]
     4/33: $4\next_count[3:0]
     5/33: $4\next_obuffer[7:0]
     6/33: $4\next_ibuffer[7:0]
     7/33: $3\next_count[3:0]
     8/33: $3\next_obuffer[7:0]
     9/33: $3\next_ibuffer[7:0]
    10/33: $2\next_fetch[0:0]
    11/33: $2\next_count[3:0]
    12/33: $2\next_ibuffer[7:0]
    13/33: $2\next_obuffer[7:0]
    14/33: $2\flash_io0_do[0:0]
    15/33: $2\flash_io0_oe[0:0]
    16/33: $2\flash_io3_oe[0:0]
    17/33: $2\flash_io2_oe[0:0]
    18/33: $2\flash_io1_oe[0:0]
    19/33: $2\flash_io3_do[0:0]
    20/33: $2\flash_io2_do[0:0]
    21/33: $2\flash_io1_do[0:0]
    22/33: $1\next_fetch[0:0]
    23/33: $1\next_count[3:0]
    24/33: $1\next_ibuffer[7:0]
    25/33: $1\next_obuffer[7:0]
    26/33: $1\flash_io3_oe[0:0]
    27/33: $1\flash_io2_oe[0:0]
    28/33: $1\flash_io1_oe[0:0]
    29/33: $1\flash_io0_oe[0:0]
    30/33: $1\flash_io3_do[0:0]
    31/33: $1\flash_io2_do[0:0]
    32/33: $1\flash_io1_do[0:0]
    33/33: $1\flash_io0_do[0:0]
Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
     1/17: $0\buffer[23:0] [23:16]
     2/17: $0\buffer[23:0] [15:8]
     3/17: $0\buffer[23:0] [7:0]
     4/17: $0\xfer_resetn[0:0]
     5/17: $0\rd_inc[0:0]
     6/17: $0\rd_wait[0:0]
     7/17: $0\rd_valid[0:0]
     8/17: $0\rd_addr[23:0]
     9/17: $0\din_valid[0:0]
    10/17: $0\din_rd[0:0]
    11/17: $0\din_ddr[0:0]
    12/17: $0\din_qspi[0:0]
    13/17: $0\din_cont[0:0]
    14/17: $0\din_tag[3:0]
    15/17: $0\din_data[7:0]
    16/17: $0\rdata[31:0]
    17/17: $0\state[3:0]
Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
     1/10: $0\softreset[0:0]
     2/10: $0\config_do[3:0]
     3/10: $0\config_clk[0:0]
     4/10: $0\config_csb[0:0]
     5/10: $0\config_oe[3:0]
     6/10: $0\config_dummy[3:0]
     7/10: $0\config_cont[0:0]
     8/10: $0\config_qspi[0:0]
     9/10: $0\config_ddr[0:0]
    10/10: $0\config_en[0:0]
Creating decoders for process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
Creating decoders for process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
     1/2: $0\wb_ack_o[1:0]
     2/2: $0\wb_ack_read[1:0]
Creating decoders for process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
Creating decoders for process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
     1/9: $0\pcpi_rd[31:0]
     2/9: $0\pcpi_wr[0:0]
     3/9: $0\pcpi_ready[0:0]
     4/9: $0\outsign[0:0]
     5/9: $0\running[0:0]
     6/9: $0\quotient_msk[31:0]
     7/9: $0\quotient[31:0]
     8/9: $0\divisor[62:0]
     9/9: $0\dividend[31:0]
Creating decoders for process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
     1/4: $0\instr_remu[0:0]
     2/4: $0\instr_rem[0:0]
     3/4: $0\instr_divu[0:0]
     4/4: $0\instr_div[0:0]
Creating decoders for process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
     1/2: $0\syncN[2:0]
     2/2: $0\syncNp[2:0]
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
     1/3: $0\pcpi_ready[0:0]
     2/3: $0\pcpi_wr[0:0]
     3/3: $0\pcpi_rd[31:0]
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
     1/7: $0\mul_finish[0:0]
     2/7: $0\mul_waiting[0:0]
     3/7: $0\mul_counter[6:0]
     4/7: $0\rdx[63:0]
     5/7: $0\rd[63:0]
     6/7: $0\rs2[63:0]
     7/7: $0\rs1[63:0]
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
     1/4: $0\instr_mulhu[0:0]
     2/4: $0\instr_mulhsu[0:0]
     3/4: $0\instr_mulh[0:0]
     4/4: $0\instr_mul[0:0]
Creating decoders for process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
     1/14: $1\pass_thru_user[0:0]
     2/14: $0\pre_pass_thru_user[0:0]
     3/14: $0\pre_pass_thru_mgmt[0:0]
     4/14: $0\predata[6:0]
     5/14: $0\fixed[2:0]
     6/14: $0\readmode[0:0]
     7/14: $0\writemode[0:0]
     8/14: $0\pass_thru_user_delay[0:0]
     9/14: $0\pass_thru_mgmt_delay[0:0]
    10/14: $0\rdstb[0:0]
    11/14: $0\count[2:0]
    12/14: $0\addr[7:0]
    13/14: $0\state[2:0]
    14/14: $0\pass_thru_mgmt[0:0]
Creating decoders for process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
     1/3: $0\sdoenb[0:0]
     2/3: $0\ldata[7:0]
     3/3: $0\wrstb[0:0]
Creating decoders for process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
     1/12: $0\pll_trim[25:0] [25:24]
     2/12: $0\pll_trim[25:0] [23:16]
     3/12: $0\pll_trim[25:0] [15:8]
     4/12: $0\pll_trim[25:0] [7:0]
     5/12: $0\irq[0:0]
     6/12: $0\pll_bypass[0:0]
     7/12: $0\reset_reg[0:0]
     8/12: $0\pll_ena[0:0]
     9/12: $0\pll_div[4:0]
    10/12: $0\pll90_sel[2:0]
    11/12: $0\pll_sel[2:0]
    12/12: $0\pll_dco_ena[0:0]
Creating decoders for process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
     1/1: $0\reset_delay[2:0]
Creating decoders for process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
     1/4: $0\ext_clk_syncd[0:0]
     2/4: $0\use_pll_second[0:0]
     3/4: $0\use_pll_first[0:0]
     4/4: $0\ext_clk_syncd_pre[0:0]
Creating decoders for process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
     1/2: $0\out_counter[0:0]
     2/2: $0\counter[2:0]
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'.
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
     1/1: $0\rst_pulse[0:0]
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
     1/3: $0\initial_begin[2:0]
     2/3: $0\out_counter2[0:0]
     3/3: $0\counter2[2:0]
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
     1/2: $0\out_counter[0:0]
     2/2: $0\counter[2:0]
Creating decoders for process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
     1/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936
     2/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_DATA[31:0]$2935
     3/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_ADDR[4:0]$2934
Creating decoders for process `\mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'.

12.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_rs1' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_rs2' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_write' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_wrdata' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\clear_prefetched_high_word' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_0' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_ascii_state' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_opcode' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_ascii_instr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_imm' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rs1' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rs2' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rd' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\new_ascii_instr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_add_sub' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_shl' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_shr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_eq' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_ltu' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_lts' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_wdata' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_wstrb' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_rdata_word' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_wr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_rd' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_wait' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_ready' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_data_arr[0]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_data_arr[1]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[0]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[1]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[2]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[3]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[4]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[5]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[6]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[7]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[8]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[9]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[10]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[11]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[12]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[13]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[14]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[15]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[16]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[17]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[18]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[19]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[20]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[21]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[22]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[23]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[24]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[25]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[26]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[27]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[28]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[29]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[30]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[31]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[32]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[33]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[34]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[35]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[36]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[37]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6238' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6236' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6234' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6232' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6230' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6228' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6226' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6224' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6222' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6220' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6218' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6216' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6214' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6212' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6210' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6208' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6206' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6204' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6202' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6200' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6198' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6196' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6194' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6192' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6190' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6188' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6186' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6184' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6182' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6180' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6178' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6176' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6174' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6172' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6170' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6168' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6166' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6164' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:141$6160' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:140$6159' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_rdata_pre' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
Latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\j' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367': $auto$proc_dlatch.cc:430:proc_dlatch$14650
No latch inferred for signal `\spimemio_xfer.\flash_io0_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io1_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io2_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io3_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io0_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io1_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io2_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io3_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_obuffer' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_ibuffer' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_count' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_fetch' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_rw_dat_o' from process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
No latch inferred for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\i' from process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
No latch inferred for signal `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.\i' from process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
No latch inferred for signal `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.\wbm_dat_o' from process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
No latch inferred for signal `\picorv32_pcpi_mul.\i' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rs1' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rs2' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\this_rs2' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rd' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rdx' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rdt' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\j' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\mgmt_soc.\irq' from process `\mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'.

12.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trap' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14651' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14652' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\eoi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14653' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trace_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14654' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trace_data' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14655' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\count_cycle' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14656' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\count_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14657' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14658' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_next_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14659' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_op1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14660' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_op2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14661' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_out' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14662' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_sh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14663' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_delay' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14664' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_active' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14665' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_mask' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14666' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_pending' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14667' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\timer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14668' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wordsize' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14669' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_prefetch' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14670' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_rinst' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14671' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_rdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14672' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14673' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_trigger' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14674' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_trigger_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14675' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_pseudo_trigger' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14676' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14677' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs1val' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14678' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs2val' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14679' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs1val_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14680' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs2val_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14681' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpu_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14682' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14683' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_rinst' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14684' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_rdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14685' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14686' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_store' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14687' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_stalu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14688' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_branch' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14689' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_compr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14690' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_trace' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14691' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14692' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14693' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14694' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14695' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\current_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14696' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_timeout_counter' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14697' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_timeout' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14698' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\next_irq_pending' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14699' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\do_waitirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14700' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14701' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_0_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14702' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_wait' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14703' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_wait_2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14704' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\clear_prefetched_high_word_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'.
  created $dff cell `$procdff$14705' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_insn' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14706' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lui' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14707' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_auipc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14708' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_jal' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14709' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_jalr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14710' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_beq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14711' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bne' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14712' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_blt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14713' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bge' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14714' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14715' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bgeu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14716' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14717' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14718' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14719' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lbu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14720' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lhu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14721' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14722' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14723' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14724' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_addi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14725' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slti' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14726' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sltiu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14727' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_xori' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14728' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_ori' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14729' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_andi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14730' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slli' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14731' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srli' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14732' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srai' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14733' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_add' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14734' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sub' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14735' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sll' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14736' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14737' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14738' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_xor' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14739' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srl' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14740' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sra' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14741' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_or' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14742' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_and' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14743' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdcycle' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14744' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdcycleh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14745' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdinstr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14746' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdinstrh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14747' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_ecall_ebreak' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14748' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_getq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14749' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_setq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14750' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_retirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14751' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_maskirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14752' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_waitirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14753' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_timer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14754' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14755' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14756' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14757' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14758' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_imm_j' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14759' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\compressed_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14760' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lui_auipc_jal' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14761' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14762' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_slli_srli_srai' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14763' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14764' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sb_sh_sw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14765' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sll_srl_sra' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14766' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14767' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_slti_blt_slt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14768' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14769' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14770' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lbu_lhu_lw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14771' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_alu_reg_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14772' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_alu_reg_reg' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14773' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_compare' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14774' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_addr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14775' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_ascii_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14776' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14777' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14778' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14779' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14780' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14781' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_next' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14782' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_valid_insn' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14783' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_ascii_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14784' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14785' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14786' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14787' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14788' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14789' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14790' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14791' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_addr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14792' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14793' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wstrb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14794' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14795' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_secondword' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14796' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\prefetched_high_word' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14797' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_16bit_buffer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14798' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\next_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
  created $dff cell `$procdff$14799' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_rdata_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
  created $dff cell `$procdff$14800' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_firstword_reg' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
  created $dff cell `$procdff$14801' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\last_mem_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
  created $dff cell `$procdff$14802' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\iomem_rdata' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14803' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\iomem_ready' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14804' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_0' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14805' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_1' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14806' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_2' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14807' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_3' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14808' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_0' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14809' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_1' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14810' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_2' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14811' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_3' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14812' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\iomem_rdata' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14813' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\iomem_ready' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14814' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\clk1_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14815' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\clk2_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14816' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\trap_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14817' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\irq_7_inputsrc' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14818' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\irq_8_inputsrc' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14819' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14820' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_oeb' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14821' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_pu' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14822' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_pd' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14823' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\iomem_rdata' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14824' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\iomem_ready' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14825' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[37]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
  created $dff cell `$procdff$14826' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[36]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
  created $dff cell `$procdff$14827' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[35]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
  created $dff cell `$procdff$14828' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[34]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
  created $dff cell `$procdff$14829' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[33]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
  created $dff cell `$procdff$14830' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[32]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
  created $dff cell `$procdff$14831' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[31]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
  created $dff cell `$procdff$14832' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[30]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
  created $dff cell `$procdff$14833' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[29]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
  created $dff cell `$procdff$14834' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[28]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
  created $dff cell `$procdff$14835' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[27]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
  created $dff cell `$procdff$14836' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[26]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
  created $dff cell `$procdff$14837' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[25]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
  created $dff cell `$procdff$14838' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[24]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
  created $dff cell `$procdff$14839' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[23]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
  created $dff cell `$procdff$14840' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[22]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
  created $dff cell `$procdff$14841' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[21]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
  created $dff cell `$procdff$14842' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[20]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
  created $dff cell `$procdff$14843' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[19]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
  created $dff cell `$procdff$14844' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[18]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
  created $dff cell `$procdff$14845' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[17]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
  created $dff cell `$procdff$14846' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[16]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
  created $dff cell `$procdff$14847' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[15]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
  created $dff cell `$procdff$14848' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[14]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
  created $dff cell `$procdff$14849' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[13]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
  created $dff cell `$procdff$14850' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[12]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
  created $dff cell `$procdff$14851' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[11]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
  created $dff cell `$procdff$14852' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[10]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
  created $dff cell `$procdff$14853' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[9]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
  created $dff cell `$procdff$14854' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[8]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
  created $dff cell `$procdff$14855' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[7]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
  created $dff cell `$procdff$14856' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[6]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
  created $dff cell `$procdff$14857' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[5]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
  created $dff cell `$procdff$14858' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[4]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
  created $dff cell `$procdff$14859' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[3]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
  created $dff cell `$procdff$14860' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[2]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
  created $dff cell `$procdff$14861' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[1]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
  created $dff cell `$procdff$14862' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[0]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
  created $dff cell `$procdff$14863' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\mgmt_gpio_outr [37:32]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
  created $dff cell `$procdff$14864' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\mgmt_gpio_outr [31:0]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
  created $dff cell `$procdff$14865' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_clock' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14866' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_resetn' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14867' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_count' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14868' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\pad_count' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14869' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_state' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14870' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_data_staging' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $dff cell `$procdff$14871' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14872' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14873' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\pwr_ctrl_out' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
  created $dff cell `$procdff$14874' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_ctrl' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
  created $dff cell `$procdff$14875' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_rdata' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
  created $dff cell `$procdff$14876' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_ready' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
  created $dff cell `$procdff$14877' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\mem_ready' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14878' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\mem_rdata' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14879' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_adr_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14880' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_dat_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14881' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_we_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14882' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_sel_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14883' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_stb_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14884' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_cyc_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14885' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\state' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14886' with positive edge clock.
Creating register for signal `\mem_wb.\wb_ack_o' using process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
  created $dff cell `$procdff$14887' with positive edge clock.
Creating register for signal `\mem_wb.\wb_ack_read' using process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
  created $dff cell `$procdff$14888' with positive edge clock.
Creating register for signal `\counter_timer_low.\irq_out' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
  created $adff cell `$procdff$14889' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\strobe' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
  created $adff cell `$procdff$14890' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\stop_out' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
  created $adff cell `$procdff$14891' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\value_cur' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
  created $adff cell `$procdff$14892' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\lastenable' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
  created $adff cell `$procdff$14893' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\value_reset' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
  created $adff cell `$procdff$14894' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\enable' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
  created $adff cell `$procdff$14895' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\oneshot' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
  created $adff cell `$procdff$14896' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\updown' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
  created $adff cell `$procdff$14897' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\irq_ena' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
  created $adff cell `$procdff$14898' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\chain' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
  created $adff cell `$procdff$14899' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\irq_out' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
  created $adff cell `$procdff$14900' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\stop_out' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
  created $adff cell `$procdff$14901' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\value_cur' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
  created $adff cell `$procdff$14902' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\lastenable' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
  created $adff cell `$procdff$14903' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\value_reset' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
  created $adff cell `$procdff$14904' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\enable' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
  created $adff cell `$procdff$14905' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\oneshot' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
  created $adff cell `$procdff$14906' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\updown' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
  created $adff cell `$procdff$14907' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\irq_ena' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
  created $adff cell `$procdff$14908' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\chain' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
  created $adff cell `$procdff$14909' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\isdo' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
  created $adff cell `$procdff$14910' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\treg' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
  created $adff cell `$procdff$14911' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\rreg' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
  created $adff cell `$procdff$14912' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\isck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
  created $adff cell `$procdff$14913' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\count' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
  created $adff cell `$procdff$14914' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\hsck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
  created $adff cell `$procdff$14915' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\state' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
  created $adff cell `$procdff$14916' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\done' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
  created $adff cell `$procdff$14917' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\icsb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
  created $adff cell `$procdff$14918' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\nbit' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
  created $adff cell `$procdff$14919' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\err_out' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
  created $adff cell `$procdff$14920' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\d_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
  created $adff cell `$procdff$14921' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\w_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
  created $adff cell `$procdff$14922' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\r_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
  created $adff cell `$procdff$14923' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\enable' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14924' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\prescaler' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14925' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\invsck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14926' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\invcsb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14927' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\mlb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14928' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\irqena' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14929' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\stream' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14930' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\mode' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14931' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\hkconn' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14932' with positive edge clock and negative level reset.
Creating register for signal `\simpleuart.\send_pattern' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
  created $dff cell `$procdff$14933' with positive edge clock.
Creating register for signal `\simpleuart.\send_bitcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
  created $dff cell `$procdff$14934' with positive edge clock.
Creating register for signal `\simpleuart.\send_divcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
  created $dff cell `$procdff$14935' with positive edge clock.
Creating register for signal `\simpleuart.\send_dummy' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
  created $dff cell `$procdff$14936' with positive edge clock.
Creating register for signal `\simpleuart.\recv_state' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
  created $dff cell `$procdff$14937' with positive edge clock.
Creating register for signal `\simpleuart.\recv_divcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
  created $dff cell `$procdff$14938' with positive edge clock.
Creating register for signal `\simpleuart.\recv_pattern' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
  created $dff cell `$procdff$14939' with positive edge clock.
Creating register for signal `\simpleuart.\recv_buf_data' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
  created $dff cell `$procdff$14940' with positive edge clock.
Creating register for signal `\simpleuart.\recv_buf_valid' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
  created $dff cell `$procdff$14941' with positive edge clock.
Creating register for signal `\simpleuart.\enabled' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
  created $dff cell `$procdff$14942' with positive edge clock.
Creating register for signal `\simpleuart.\cfg_divider' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
  created $dff cell `$procdff$14943' with positive edge clock.
Creating register for signal `\spimemio_xfer.\flash_csb' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14944' with positive edge clock.
Creating register for signal `\spimemio_xfer.\flash_clk' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14945' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_dspi' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14946' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_ddr' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14947' with positive edge clock.
Creating register for signal `\spimemio_xfer.\obuffer' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14948' with positive edge clock.
Creating register for signal `\spimemio_xfer.\ibuffer' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14949' with positive edge clock.
Creating register for signal `\spimemio_xfer.\count' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14950' with positive edge clock.
Creating register for signal `\spimemio_xfer.\dummy_count' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14951' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_cont' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14952' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_qspi' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14953' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_rd' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14954' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_tag' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14955' with positive edge clock.
Creating register for signal `\spimemio_xfer.\fetch' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14956' with positive edge clock.
Creating register for signal `\spimemio_xfer.\last_fetch' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14957' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_ddr_q' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
  created $dff cell `$procdff$14958' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_tag_q' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
  created $dff cell `$procdff$14959' with positive edge clock.
Creating register for signal `\spimemio.\state' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14960' with positive edge clock.
Creating register for signal `\spimemio.\rdata' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14961' with positive edge clock.
Creating register for signal `\spimemio.\xfer_resetn' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14962' with positive edge clock.
Creating register for signal `\spimemio.\din_valid' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14963' with positive edge clock.
Creating register for signal `\spimemio.\din_data' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14964' with positive edge clock.
Creating register for signal `\spimemio.\din_tag' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14965' with positive edge clock.
Creating register for signal `\spimemio.\din_cont' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14966' with positive edge clock.
Creating register for signal `\spimemio.\din_qspi' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14967' with positive edge clock.
Creating register for signal `\spimemio.\din_ddr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14968' with positive edge clock.
Creating register for signal `\spimemio.\din_rd' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14969' with positive edge clock.
Creating register for signal `\spimemio.\buffer' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14970' with positive edge clock.
Creating register for signal `\spimemio.\rd_addr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14971' with positive edge clock.
Creating register for signal `\spimemio.\rd_valid' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14972' with positive edge clock.
Creating register for signal `\spimemio.\rd_wait' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14973' with positive edge clock.
Creating register for signal `\spimemio.\rd_inc' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14974' with positive edge clock.
Creating register for signal `\spimemio.\xfer_io0_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
  created $dff cell `$procdff$14975' with negative edge clock.
Creating register for signal `\spimemio.\xfer_io1_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
  created $dff cell `$procdff$14976' with negative edge clock.
Creating register for signal `\spimemio.\xfer_io2_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
  created $dff cell `$procdff$14977' with negative edge clock.
Creating register for signal `\spimemio.\xfer_io3_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
  created $dff cell `$procdff$14978' with negative edge clock.
Creating register for signal `\spimemio.\softreset' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14979' with positive edge clock.
Creating register for signal `\spimemio.\config_en' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14980' with positive edge clock.
Creating register for signal `\spimemio.\config_ddr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14981' with positive edge clock.
Creating register for signal `\spimemio.\config_qspi' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14982' with positive edge clock.
Creating register for signal `\spimemio.\config_cont' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14983' with positive edge clock.
Creating register for signal `\spimemio.\config_dummy' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14984' with positive edge clock.
Creating register for signal `\spimemio.\config_oe' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14985' with positive edge clock.
Creating register for signal `\spimemio.\config_csb' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14986' with positive edge clock.
Creating register for signal `\spimemio.\config_clk' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14987' with positive edge clock.
Creating register for signal `\spimemio.\config_do' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14988' with positive edge clock.
Creating register for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_ack_o' using process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
  created $dff cell `$procdff$14989' with positive edge clock.
Creating register for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_ack_read' using process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
  created $dff cell `$procdff$14990' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_wr' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14991' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_rd' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14992' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_ready' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14993' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\dividend' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14994' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\divisor' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14995' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\quotient' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14996' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\quotient_msk' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14997' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\running' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14998' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\outsign' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14999' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_wait' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15000' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_wait_q' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15001' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_div' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15002' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_divu' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15003' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_rem' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15004' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_remu' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15005' with positive edge clock.
Creating register for signal `$paramod\clock_div\SIZE=3.\syncN' using process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
  created $adff cell `$procdff$15006' with positive edge clock and negative level reset.
Creating register for signal `$paramod\clock_div\SIZE=3.\syncNp' using process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
  created $adff cell `$procdff$15007' with positive edge clock and negative level reset.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_wr' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
  created $dff cell `$procdff$15008' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_rd' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
  created $dff cell `$procdff$15009' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_ready' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
  created $dff cell `$procdff$15010' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rs1' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15011' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rs2' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15012' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rd' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15013' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rdx' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15014' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\mul_counter' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15015' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\mul_waiting' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15016' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\mul_finish' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15017' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_wait' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15018' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mul' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15019' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mulh' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15020' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mulhsu' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15021' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mulhu' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15022' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_wait_q' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15023' with positive edge clock.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_mgmt' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15024' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\state' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15025' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\addr' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15026' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\count' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15027' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\rdstb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15028' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_mgmt_delay' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15029' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_user' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15030' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_user_delay' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15031' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\writemode' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15032' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\readmode' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15033' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\fixed' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15034' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\predata' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15035' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pre_pass_thru_mgmt' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15036' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pre_pass_thru_user' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15037' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\sdoenb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
  created $adff cell `$procdff$15038' with negative edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\wrstb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
  created $adff cell `$procdff$15039' with negative edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\ldata' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
  created $adff cell `$procdff$15040' with negative edge clock and positive level reset.
Creating register for signal `\housekeeping_spi.\pll_dco_ena' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15041' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_sel' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15042' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll90_sel' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15043' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_div' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15044' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_ena' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15045' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_trim' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15046' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_bypass' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15047' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\irq' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15048' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\reset_reg' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15049' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\reset_delay' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
  created $adff cell `$procdff$15050' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\use_pll_first' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
  created $adff cell `$procdff$15051' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\use_pll_second' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
  created $adff cell `$procdff$15052' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\ext_clk_syncd_pre' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
  created $dff cell `$procdff$15053' with positive edge clock.
Creating register for signal `\caravel_clocking.\ext_clk_syncd' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
  created $adff cell `$procdff$15054' with positive edge clock and negative level reset.
Creating register for signal `\even.\counter' using process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
  created $adff cell `$procdff$15055' with positive edge clock and negative level reset.
Creating register for signal `\even.\out_counter' using process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
  created $adff cell `$procdff$15056' with positive edge clock and negative level reset.
Creating register for signal `\odd.\old_N' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'.
  created $dff cell `$procdff$15057' with positive edge clock.
Creating register for signal `\odd.\rst_pulse' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
  created $adff cell `$procdff$15058' with positive edge clock and negative level reset.
Creating register for signal `\odd.\counter2' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Warning: Async reset value `\N' is not constant!
  created $dffsr cell `$procdff$15059' with negative edge clock and negative level non-const reset.
Creating register for signal `\odd.\out_counter2' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
  created $adff cell `$procdff$15066' with negative edge clock and negative level reset.
Creating register for signal `\odd.\initial_begin' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Warning: Async reset value `$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235_Y [3:1]' is not constant!
  created $dffsr cell `$procdff$15067' with negative edge clock and negative level non-const reset.
Creating register for signal `\odd.\counter' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
Warning: Async reset value `\N' is not constant!
  created $dffsr cell `$procdff$15074' with positive edge clock and negative level non-const reset.
Creating register for signal `\odd.\out_counter' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
  created $adff cell `$procdff$15081' with positive edge clock and negative level reset.
Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_ADDR' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
  created $dff cell `$procdff$15082' with positive edge clock.
Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_DATA' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
  created $dff cell `$procdff$15083' with positive edge clock.
Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
  created $dff cell `$procdff$15084' with positive edge clock.

12.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 61 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
Found and cleaned up 8 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
Found and cleaned up 22 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
Found and cleaned up 3 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
Found and cleaned up 5 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
Found and cleaned up 47 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
Found and cleaned up 16 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
Found and cleaned up 19 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
Found and cleaned up 3 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
Found and cleaned up 1 empty switch in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
Found and cleaned up 42 empty switches in `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
Removing empty process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
Found and cleaned up 9 empty switches in `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
Removing empty process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
Found and cleaned up 10 empty switches in `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
Removing empty process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'.
Found and cleaned up 13 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
Found and cleaned up 6 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
Found and cleaned up 3 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
Found and cleaned up 43 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
Found and cleaned up 4 empty switches in `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
Removing empty process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
Found and cleaned up 1 empty switch in `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
Removing empty process `mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
Found and cleaned up 25 empty switches in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
Found and cleaned up 4 empty switches in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
Found and cleaned up 1 empty switch in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
Found and cleaned up 26 empty switches in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
Found and cleaned up 4 empty switches in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
Found and cleaned up 1 empty switch in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
Found and cleaned up 1 empty switch in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
Found and cleaned up 9 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
Found and cleaned up 5 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
Found and cleaned up 7 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
Found and cleaned up 6 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
Found and cleaned up 4 empty switches in `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
Found and cleaned up 5 empty switches in `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
Found and cleaned up 25 empty switches in `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
Found and cleaned up 5 empty switches in `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
Removing empty process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
Found and cleaned up 1 empty switch in `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
Removing empty process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
Removing empty process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
Found and cleaned up 5 empty switches in `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
Removing empty process `picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
Found and cleaned up 2 empty switches in `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
Removing empty process `picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
Removing empty process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
Found and cleaned up 1 empty switch in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
Found and cleaned up 5 empty switches in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
Found and cleaned up 2 empty switches in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
Found and cleaned up 18 empty switches in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
Removing empty process `housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
Found and cleaned up 6 empty switches in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
Removing empty process `housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
Found and cleaned up 2 empty switches in `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
Removing empty process `housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
Removing empty process `caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
Removing empty process `caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
Found and cleaned up 2 empty switches in `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
Removing empty process `even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'.
Found and cleaned up 2 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
Found and cleaned up 4 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Found and cleaned up 3 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
Found and cleaned up 1 empty switch in `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
Removing empty process `mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
Removing empty process `mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'.
Cleaned up 682 empty switches.

12.3. Executing FLATTEN pass (flatten design).
Deleting now unused module convert_gpio_sigs.
Deleting now unused module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Deleting now unused module $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.
Deleting now unused module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.
Deleting now unused module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.
Deleting now unused module $paramod\soc_mem\WORDS=256\ADR_WIDTH=8.
Deleting now unused module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Deleting now unused module $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.
Deleting now unused module $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100.
Deleting now unused module $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100.
Deleting now unused module mem_wb.
Deleting now unused module $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb.
Deleting now unused module counter_timer_low.
Deleting now unused module $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb.
Deleting now unused module counter_timer_high.
Deleting now unused module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb.
Deleting now unused module simple_spi_master.
Deleting now unused module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb.
Deleting now unused module simpleuart.
Deleting now unused module $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb.
Deleting now unused module spimemio_xfer.
Deleting now unused module spimemio.
Deleting now unused module spimemio_wb.
Deleting now unused module $paramod\mprj_ctrl_wb\BASE_ADR=637534208.
Deleting now unused module $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.
Deleting now unused module $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.
Deleting now unused module picorv32_pcpi_div.
Deleting now unused module $paramod\clock_div\SIZE=3.
Deleting now unused module picorv32_pcpi_mul.
Deleting now unused module housekeeping_spi_slave.
Deleting now unused module housekeeping_spi.
Deleting now unused module caravel_clocking.
Deleting now unused module even.
Deleting now unused module odd.
Deleting now unused module mgmt_soc_regs.
Deleting now unused module mgmt_soc.


12.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 395 unused cells and 4411 unused wires.


12.6. Executing CHECK pass (checking for obvious problems).
checking module mgmt_core..
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.sck:
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6440 ($mux)
    port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:193$1362 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.csb:
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6435 ($mux)
    port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:192$1358 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.sdo:
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6430 ($mux)
    port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:198$1364 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_sdi:
    port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:135$2951 ($mux)
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6470 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_sck:
    port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:134$2949 ($mux)
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6465 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_csb:
    port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:133$2947 ($mux)
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6460 ($mux)
Warning: Wire mgmt_core.\pwr_ctrl_out [3] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [2] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [1] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [0] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [31] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [30] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [29] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [28] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [27] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [26] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [25] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [24] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [23] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [22] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [21] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [20] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [19] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [18] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [17] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [16] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [15] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [14] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [13] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [12] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [11] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [10] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [9] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [8] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [7] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [6] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [5] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [4] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [3] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [2] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [1] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [0] is used but has no driver.
Warning: Wire mgmt_core.\soc.intercon.wbs_dat_i [387] is used but has no driver.
Warning: Wire mgmt_core.\soc.intercon.wbs_dat_i [386] is used but has no driver.
Warning: Wire mgmt_core.\soc.cpu.picorv32_core.irq [4] is used but has no driver.
found and reported 45 problems.

12.7. Executing OPT pass (performing simple optimizations).

12.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 805 cells.

12.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port A of cell $flatten\housekeeping.\U1.$procmux$14195: \housekeeping.U1.pre_pass_thru_user -> 1'0
      Replacing known input bits on port A of cell $flatten\housekeeping.\U1.$procmux$14221: \housekeeping.U1.pre_pass_thru_mgmt -> 1'0
      Replacing known input bits on port A of cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14113: \soc.cpu.picorv32_core.pcpi_mul.mul_waiting -> 1'0
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10354.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10361.
    dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10387.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7556.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7566.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7568.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7574.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7581.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7583.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7589.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7598.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7618.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7624.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7627.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7640.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7647.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7650.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7663.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7675.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7678.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7687.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7690.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7698.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7700.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7703.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7717.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7719.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7721.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7724.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7737.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7739.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7742.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7754.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7757.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7764.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7766.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7769.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7792.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7794.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7796.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7799.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7821.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7823.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7826.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7845.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7847.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7850.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7869.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7871.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7874.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7895.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7898.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7912.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7915.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7917.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7919.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7922.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7932.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7937.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7940.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7963.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7966.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7968.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7970.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7973.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7985.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7988.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8031.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8044.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8057.
    dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8287.
    dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8287.
    dead port 2/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8330.
    dead port 7/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8330.
    dead port 8/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8330.
    dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8537.
    dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8537.
    dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8605.
    dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8620.
    dead port 2/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8624.
    dead port 7/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8624.
    dead port 8/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8624.
    dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808.
    dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8820.
    dead port 2/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8824.
    dead port 7/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8824.
    dead port 8/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8824.
    dead port 2/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9008.
    dead port 7/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9008.
    dead port 8/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9008.
    dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9058.
    dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9058.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9199.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9208.
    dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11658.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11661.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11833.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11836.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11839.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11845.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11848.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11851.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11857.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11860.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11863.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11869.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11872.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11875.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11881.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11884.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11887.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11893.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11896.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11899.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11905.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11908.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11911.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11917.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11920.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11923.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11929.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11932.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11935.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11941.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11944.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11947.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11953.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11956.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11959.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11965.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11968.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11971.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11977.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11980.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11983.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11989.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11992.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11995.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12001.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12004.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12007.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12013.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12016.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12019.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12025.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12028.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12031.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12037.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12040.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12043.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12049.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12052.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12055.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12061.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12064.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12067.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12073.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12076.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12079.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12085.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12088.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12091.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12097.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12100.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12103.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12109.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12112.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12115.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12121.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12124.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12127.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12133.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12136.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12139.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12145.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12148.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12151.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12157.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12160.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12163.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12169.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12172.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12175.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12181.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12184.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12187.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12193.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12196.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12199.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12205.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12208.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12211.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12217.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12220.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12223.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12229.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12232.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12235.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12241.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12244.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12247.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12253.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12256.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12259.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12265.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12268.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12271.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12277.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12280.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12283.
    dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12289.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12292.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12295.
    dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12301.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12304.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12307.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12322.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12325.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12331.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13432.
    dead port 1/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13434.
    dead port 2/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13434.
    dead port 3/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13434.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13438.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13445.
    dead port 1/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13447.
    dead port 2/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13447.
    dead port 3/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13447.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13451.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13471.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13473.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13482.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13484.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13506.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13508.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13518.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13520.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13530.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13540.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13550.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13560.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13570.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13580.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13588.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13596.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13606.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13632.
Removed 247 multiplexer ports.


12.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    New input vector for $reduce_or cell $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:329$6890: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_ready \soc.cpu.picorv32_core.pcpi_div.pcpi_ready }
    New input vector for $reduce_or cell $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:328$6886: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_wait \soc.cpu.picorv32_core.pcpi_div.pcpi_wait }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10133: { $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15086 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10148: { $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15088 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10166: $auto$opt_reduce.cc:134:opt_mux$15090
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10179: $auto$opt_reduce.cc:134:opt_mux$15092
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10204: { $auto$opt_reduce.cc:134:opt_mux$15094 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10239: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15096 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10254: { $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15098 $flatten\soc.\cpu.\picorv32_core.$procmux$10149_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10281: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $auto$opt_reduce.cc:134:opt_mux$15100 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10294: $auto$opt_reduce.cc:134:opt_mux$15102
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10320: { $auto$opt_reduce.cc:134:opt_mux$15106 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15104 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10339: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $auto$opt_reduce.cc:134:opt_mux$15108 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7608: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $auto$opt_reduce.cc:134:opt_mux$15110 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7630: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $auto$opt_reduce.cc:134:opt_mux$15112 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7653: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $auto$opt_reduce.cc:134:opt_mux$15114 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8021: { $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP $auto$opt_reduce.cc:134:opt_mux$15116 }
    New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$14195: { }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8034: { $auto$opt_reduce.cc:134:opt_mux$15118 $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP }
    New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$14221: { }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8047: { $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $auto$opt_reduce.cc:134:opt_mux$15120 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8330: $auto$opt_reduce.cc:134:opt_mux$15122
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8374: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8514: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $auto$opt_reduce.cc:134:opt_mux$15124 }
    New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$14360: { }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8537: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$15126 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8624: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$15130 $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y $auto$opt_reduce.cc:134:opt_mux$15128 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8798: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8824: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$15134 $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y $auto$opt_reduce.cc:134:opt_mux$15132 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9008: { \soc.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$15136 $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9058: { \soc.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$15138 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9194: $auto$opt_reduce.cc:134:opt_mux$15140
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9284: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15142 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9302: $auto$opt_reduce.cc:134:opt_mux$15144
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9370: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15146 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9388: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $auto$opt_reduce.cc:134:opt_mux$15148 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9436: { $auto$opt_reduce.cc:134:opt_mux$15150 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9457: $auto$opt_reduce.cc:134:opt_mux$15152
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9578: { $flatten\soc.\cpu.\picorv32_core.$procmux$9586_CMP $auto$opt_reduce.cc:134:opt_mux$15154 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9590: $auto$opt_reduce.cc:134:opt_mux$15156
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9746: $auto$opt_reduce.cc:134:opt_mux$15158
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\cpuregs.$procmux$14616:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936
      New ports: A=1'0, B=1'1, Y=$flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0]
      New connections: $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [31:1] = { $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] }
    New ctrl vector for $pmux cell $flatten\soc.\simpleuart.\simpleuart.$procmux$13279: $auto$opt_reduce.cc:134:opt_mux$15160
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13839: { $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP $auto$opt_reduce.cc:134:opt_mux$15162 $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13421: $auto$opt_reduce.cc:134:opt_mux$15164
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13566: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15166 }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13576: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15168 }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13585: $auto$opt_reduce.cc:134:opt_mux$15170
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13593: $auto$opt_reduce.cc:134:opt_mux$15172
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13602: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15174 }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13628: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15176 }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15121: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15125: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15127: { \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15129: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15131: { \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15133: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15135: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15137: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer }
  Optimizing cells in module \mgmt_core.
Performed a total of 59 changes.

12.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 104 cells.

12.7.6. Executing OPT_DFF pass (perform DFF optimizations).

12.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 1142 unused wires.


12.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.7.9. Rerunning OPT passes. (Maybe there is more to do..)

12.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $flatten\soc.\cpu.\picorv32_core.$procmux$10392: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_wr \soc.cpu.picorv32_core.pcpi_div.pcpi_wr } -> 2'11
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10177: { $flatten\soc.\cpu.\picorv32_core.$procmux$10165_CMP $auto$opt_reduce.cc:134:opt_mux$15178 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10392: $auto$opt_reduce.cc:134:opt_mux$15180
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7630: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $auto$opt_reduce.cc:134:opt_mux$15182 $auto$opt_reduce.cc:134:opt_mux$15112 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8138: $auto$opt_reduce.cc:134:opt_mux$15184
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8155: { $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $auto$opt_reduce.cc:134:opt_mux$15186 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8583: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP $auto$opt_reduce.cc:134:opt_mux$15188 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9167: $auto$opt_reduce.cc:134:opt_mux$15190
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9472: $auto$opt_reduce.cc:134:opt_mux$15192
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13696: $auto$opt_reduce.cc:134:opt_mux$15194
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13746: { $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP $auto$opt_reduce.cc:134:opt_mux$15196 $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP }
  Optimizing cells in module \mgmt_core.
Performed a total of 10 changes.

12.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 5 cells.

12.7.13. Executing OPT_DFF pass (perform DFF optimizations).

12.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 5 unused wires.


12.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.7.16. Rerunning OPT passes. (Maybe there is more to do..)

12.7.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10392.
Removed 1 multiplexer ports.


12.7.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

12.7.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.7.20. Executing OPT_DFF pass (perform DFF optimizations).

12.7.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

12.7.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.7.23. Rerunning OPT passes. (Maybe there is more to do..)

12.7.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.7.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

12.7.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.7.27. Executing OPT_DFF pass (perform DFF optimizations).

12.7.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

12.7.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.7.30. Finished OPT passes. (There is nothing left to do.)

12.8. Executing FSM pass (extract and optimize FSM).

12.8.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register mgmt_core.housekeeping.U1.state.
Found FSM state register mgmt_core.soc.cpu.picorv32_core.cpu_state.
Not marking mgmt_core.soc.cpu.picorv32_core.irq_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking mgmt_core.soc.cpu.picorv32_core.mem_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register mgmt_core.soc.cpu.picorv32_core.mem_wordsize.
Found FSM state register mgmt_core.soc.cpu.state.
Not marking mgmt_core.soc.mprj_ctrl.mprj_ctrl.xfer_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register mgmt_core.soc.simple_spi_master_inst.spi_master.state.
Not marking mgmt_core.soc.spimemio.spimemio.din_tag as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register mgmt_core.soc.spimemio.spimemio.state.

12.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\housekeeping.U1.state' from module `\mgmt_core'.
  found $adff cell for state register: $flatten\housekeeping.\U1.$procdff$15025
  root of input selection tree: $flatten\housekeeping.\U1.$0\state[2:0]
  found reset state: 3'000 (from async reset)
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:382$3006_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030_Y
  found state code: 3'010
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:369$3005_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016_Y
  found ctrl input: $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:429$3019_Y
  found ctrl input: \housekeeping.U1.pre_pass_thru_mgmt
  found ctrl input: \housekeeping.U1.pre_pass_thru_user
  found state code: 3'001
  found state code: 3'100
  found state code: 3'101
  found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y
  found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3008_Y
  found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3009_Y
  found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y
  found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y
  ctrl inputs: { $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030_Y \housekeeping.U1.pre_pass_thru_mgmt \housekeeping.U1.pre_pass_thru_user $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:369$3005_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:382$3006_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016_Y $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:429$3019_Y }
  ctrl outputs: { $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3008_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3009_Y $flatten\housekeeping.\U1.$0\state[2:0] $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y }
  transition:      3'000 9'---000000 ->      3'000 8'00000001
  transition:      3'000 9'-00010000 ->      3'001 8'00000011
  transition:      3'000 9'-01010000 ->      3'100 8'00001001
  transition:      3'000 9'-1-010000 ->      3'101 8'00001011
  transition:      3'000 9'---0-0001 ->      3'000 8'00000001
  transition:      3'000 9'---0-001- ->      3'000 8'00000001
  transition:      3'000 9'---0-01-- ->      3'000 8'00000001
  transition:      3'000 9'---0-1--- ->      3'000 8'00000001
  transition:      3'000 9'---1----- ->      3'000 8'00000001
  transition:      3'100 9'--------- ->      3'100 8'00011000
  transition:      3'010 9'----0---- ->      3'010 8'01000100
  transition:      3'010 9'0---1---- ->      3'010 8'01000100
  transition:      3'010 9'1---1---- ->      3'000 8'01000000
  transition:      3'001 9'----0---- ->      3'001 8'10000010
  transition:      3'001 9'----1---- ->      3'010 8'10000100
  transition:      3'101 9'--------- ->      3'101 8'00101010
Extracting FSM `\soc.cpu.picorv32_core.cpu_state' from module `\mgmt_core'.
  found $dff cell for state register: $flatten\soc.\cpu.\picorv32_core.$procdff$14682
  root of input selection tree: $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0]
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$7529_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$7512_Y
  found ctrl input: \soc.cpu.wb_rst_i
  found ctrl input: $auto$opt_reduce.cc:134:opt_mux$15184
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$7497_Y
  found state code: 8'01000000
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$7475_Y
  found ctrl input: \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu
  found ctrl input: \soc.cpu.picorv32_core.mem_done
  found ctrl input: \soc.cpu.picorv32_core.is_sb_sh_sw
  found ctrl input: \soc.cpu.picorv32_core.instr_trap
  found state code: 8'00001000
  found state code: 8'00000010
  found ctrl input: \soc.cpu.picorv32_core.pcpi_int_ready
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$7429_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$7433_Y
  found state code: 8'10000000
  found ctrl input: $auto$opt_reduce.cc:134:opt_mux$15128
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y
  found ctrl input: $auto$opt_reduce.cc:134:opt_mux$15126
  found state code: 8'00000001
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$7408_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$7416_Y
  found ctrl input: \soc.cpu.picorv32_core.decoder_trigger
  found ctrl input: \soc.cpu.picorv32_core.instr_jal
  found state code: 8'00100000
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7522_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7515_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$7519_Y
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7616_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y
  ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$15128 $auto$opt_reduce.cc:134:opt_mux$15126 $auto$opt_reduce.cc:134:opt_mux$15184 \soc.cpu.picorv32_core.pcpi_int_ready \soc.cpu.picorv32_core.mem_done \soc.cpu.picorv32_core.instr_jal \soc.cpu.picorv32_core.instr_trap \soc.cpu.picorv32_core.decoder_trigger \soc.cpu.picorv32_core.is_sb_sh_sw \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$7408_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$7416_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$7429_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$7433_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$7475_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$7497_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$7512_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7515_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$7519_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7522_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$7529_Y \soc.cpu.wb_rst_i }
  ctrl outputs: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7616_CMP }
  transition: 8'10000000 24'------------------0---00 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------0---01 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------10-000 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------10-001 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------11000- -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------111000 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------111001 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------1-010- -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------101100 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------101101 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------111100 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------111101 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'--------------------0-1- -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------0-1-10 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------0-1-11 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------101010 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------101011 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------111010 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------111011 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------101110 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------101111 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------111110 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------111111 -> 8'01000000 16'0010000000000001
  transition: 8'01000000 24'-------0--00------0---00 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------0---00 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------0---00 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------0---00 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------0---00 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------0---01 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------10-000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------10-000 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------10-000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------10-000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------10-000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------10-001 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------11000- -> 8'10000000 16'1100000000000000
  transition: 8'01000000 24'-------0--00------111000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------111000 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------111000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------111000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------111000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------111001 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------1-010- -> 8'10000000 16'1100000000000000
  transition: 8'01000000 24'-------0--00------101100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------101100 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------101100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------101100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------101100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------101101 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------111100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------111100 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------111100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------111100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------111100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------111101 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'--------------------0-1- -> 8'10000000 16'1100000000000000
  transition: 8'01000000 24'-------0--00------0-1-10 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------0-1-10 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------0-1-10 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------0-1-10 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------0-1-10 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------0-1-11 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------101010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------101010 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------101010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------101010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------101010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------101011 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------111010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------111010 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------111010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------111010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------111010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------111011 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------101110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------101110 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------101110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------101110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------101110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------101111 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------111110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------111110 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------111110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------111110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------111110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------111111 -> 8'01000000 16'1010000000000000
  transition: 8'00100000 24'00----0-0-----0---0---00 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---0---00 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----0---00 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----0---00 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----0---00 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------0---00 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------0---00 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---0---00 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------0---00 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------0---01 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---10-000 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---10-000 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----10-000 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----10-000 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----10-000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------10-000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------10-000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---10-000 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------10-000 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------10-001 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'------------------11000- -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'00----0-0-----0---111000 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---111000 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----111000 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----111000 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----111000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------111000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------111000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---111000 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------111000 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------111001 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'------------------1-010- -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'00----0-0-----0---101100 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---101100 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----101100 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----101100 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----101100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------101100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------101100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---101100 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------101100 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------101101 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---111100 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---111100 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----111100 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----111100 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----111100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------111100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------111100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---111100 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------111100 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------111101 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------------0-1- -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'00----0-0-----0---0-1-10 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---0-1-10 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----0-1-10 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----0-1-10 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----0-1-10 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------0-1-10 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------0-1-10 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---0-1-10 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------0-1-10 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------0-1-11 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---101010 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---101010 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----101010 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----101010 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----101010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------101010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------101010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---101010 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------101010 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------101011 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---111010 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---111010 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----111010 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----111010 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----111010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------111010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------111010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---111010 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------111010 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------111011 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---101110 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---101110 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----101110 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----101110 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----101110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------101110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------101110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---101110 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------101110 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------101111 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---111110 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---111110 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----111110 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----111110 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----111110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------111110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------111110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---111110 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------111110 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------111111 -> 8'01000000 16'0010000000000010
  transition: 8'00001000 24'---------0--------0---00 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------0---00 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------0---00 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------0---01 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------10-000 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------10-000 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------10-000 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------10-001 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------11000- -> 8'10000000 16'0100000000001000
  transition: 8'00001000 24'---------0--------111000 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------111000 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------111000 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------111001 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------1-010- -> 8'10000000 16'0100000000001000
  transition: 8'00001000 24'---------0--------101100 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------101100 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------101100 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------101101 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------111100 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------111100 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------111100 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------111101 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'--------------------0-1- -> 8'10000000 16'0100000000001000
  transition: 8'00001000 24'---------0--------0-1-10 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------0-1-10 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------0-1-10 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------0-1-11 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------101010 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------101010 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------101010 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------101011 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------111010 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------111010 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------111010 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------111011 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------101110 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------101110 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------101110 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------101111 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------111110 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------111110 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------111110 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------111111 -> 8'01000000 16'0010000000001000
  transition: 8'00000010 24'----------------0-0---00 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------100---00 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------110---00 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------0---01 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-10-000 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------1010-000 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------1110-000 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------10-001 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------11000- -> 8'10000000 16'0100000000100000
  transition: 8'00000010 24'----------------0-111000 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10111000 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11111000 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------111001 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------1-010- -> 8'10000000 16'0100000000100000
  transition: 8'00000010 24'----------------0-101100 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10101100 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11101100 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------101101 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-111100 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10111100 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11111100 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------111101 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'--------------------0-1- -> 8'10000000 16'0100000000100000
  transition: 8'00000010 24'----------------0-0-1-10 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------100-1-10 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------110-1-10 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------0-1-11 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-101010 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10101010 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11101010 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------101011 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-111010 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10111010 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11111010 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------111011 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-101110 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10101110 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11101110 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------101111 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-111110 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10111110 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11111110 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------111111 -> 8'01000000 16'0010000000100000
  transition: 8'00000001 24'----------------0-0---00 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------100---00 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------110---00 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------0---01 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-10-000 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------1010-000 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------1110-000 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------10-001 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------11000- -> 8'10000000 16'0100000001000000
  transition: 8'00000001 24'----------------0-111000 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10111000 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11111000 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------111001 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------1-010- -> 8'10000000 16'0100000001000000
  transition: 8'00000001 24'----------------0-101100 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10101100 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11101100 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------101101 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-111100 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10111100 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11111100 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------111101 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'--------------------0-1- -> 8'10000000 16'0100000001000000
  transition: 8'00000001 24'----------------0-0-1-10 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------100-1-10 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------110-1-10 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------0-1-11 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-101010 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10101010 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11101010 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------101011 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-111010 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10111010 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11111010 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------111011 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-101110 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10101110 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11101110 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------101111 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-111110 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10111110 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11111110 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------111111 -> 8'01000000 16'0010000001000000
Extracting FSM `\soc.cpu.picorv32_core.mem_wordsize' from module `\mgmt_core'.
  found $dff cell for state register: $flatten\soc.\cpu.\picorv32_core.$procdff$14669
  root of input selection tree: $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0]
  found ctrl input: \soc.cpu.wb_rst_i
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y
  found ctrl input: \soc.cpu.picorv32_core.mem_do_rdata
  found ctrl input: \soc.cpu.picorv32_core.instr_lw
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$7502_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$7501_Y
  found state code: 2'00
  found state code: 2'01
  found state code: 2'10
  found ctrl input: \soc.cpu.picorv32_core.mem_do_wdata
  found ctrl input: \soc.cpu.picorv32_core.instr_sw
  found ctrl input: \soc.cpu.picorv32_core.instr_sh
  found ctrl input: \soc.cpu.picorv32_core.instr_sb
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$10355_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7520_Y
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7513_Y
  ctrl inputs: { \soc.cpu.picorv32_core.mem_do_rdata \soc.cpu.picorv32_core.mem_do_wdata \soc.cpu.picorv32_core.instr_lw \soc.cpu.picorv32_core.instr_sb \soc.cpu.picorv32_core.instr_sh \soc.cpu.picorv32_core.instr_sw $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$7501_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$7502_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP \soc.cpu.wb_rst_i }
  ctrl outputs: { $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7513_Y $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7520_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10355_CMP }
  transition:       2'00 13'------0---000 ->       2'00 5'00100
  transition:       2'00 13'------1-----0 ->       2'00 5'00100
  transition:       2'00 13'-------0---10 ->       2'00 5'00100
  transition:       2'00 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx100  
  transition:       2'00 13'-0-1---1---10 ->       2'10 5'10100
  transition:       2'00 13'-0--1--1---10 ->       2'01 5'01100
  transition:       2'00 13'-0---1-1---10 ->       2'00 5'00100
  transition:       2'00 13'-1-----1---10 ->       2'00 5'00100
  transition:       2'00 13'-------0--1-0 ->       2'00 5'00100
  transition:       2'00 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx100  
  transition:       2'00 13'0------11-1-0 ->       2'10 5'10100
  transition:       2'00 13'0------1-11-0 ->       2'01 5'01100
  transition:       2'00 13'0-1----1--1-0 ->       2'00 5'00100
  transition:       2'00 13'1------1--1-0 ->       2'00 5'00100
  transition:       2'00 13'------------1 ->       2'00 5'00100
  transition:       2'10 13'------0---000 ->       2'10 5'10001
  transition:       2'10 13'------1-----0 ->       2'00 5'00001
  transition:       2'10 13'-------0---10 ->       2'10 5'10001
  transition:       2'10 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx001  
  transition:       2'10 13'-0-1---1---10 ->       2'10 5'10001
  transition:       2'10 13'-0--1--1---10 ->       2'01 5'01001
  transition:       2'10 13'-0---1-1---10 ->       2'00 5'00001
  transition:       2'10 13'-1-----1---10 ->       2'10 5'10001
  transition:       2'10 13'-------0--1-0 ->       2'10 5'10001
  transition:       2'10 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx001  
  transition:       2'10 13'0------11-1-0 ->       2'10 5'10001
  transition:       2'10 13'0------1-11-0 ->       2'01 5'01001
  transition:       2'10 13'0-1----1--1-0 ->       2'00 5'00001
  transition:       2'10 13'1------1--1-0 ->       2'10 5'10001
  transition:       2'10 13'------------1 ->       2'10 5'10001
  transition:       2'01 13'------0---000 ->       2'01 5'01010
  transition:       2'01 13'------1-----0 ->       2'00 5'00010
  transition:       2'01 13'-------0---10 ->       2'01 5'01010
  transition:       2'01 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx010  
  transition:       2'01 13'-0-1---1---10 ->       2'10 5'10010
  transition:       2'01 13'-0--1--1---10 ->       2'01 5'01010
  transition:       2'01 13'-0---1-1---10 ->       2'00 5'00010
  transition:       2'01 13'-1-----1---10 ->       2'01 5'01010
  transition:       2'01 13'-------0--1-0 ->       2'01 5'01010
  transition:       2'01 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx010  
  transition:       2'01 13'0------11-1-0 ->       2'10 5'10010
  transition:       2'01 13'0------1-11-0 ->       2'01 5'01010
  transition:       2'01 13'0-1----1--1-0 ->       2'00 5'00010
  transition:       2'01 13'1------1--1-0 ->       2'01 5'01010
  transition:       2'01 13'------------1 ->       2'01 5'01010
Extracting FSM `\soc.cpu.state' from module `\mgmt_core'.
  found $dff cell for state register: $flatten\soc.\cpu.$procdff$14886
  root of input selection tree: $flatten\soc.\cpu.$0\state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \soc.cpu.wb_rst_i
  found ctrl input: $flatten\soc.\cpu.$procmux$12350_CMP
  found ctrl input: $flatten\soc.\cpu.$procmux$12354_CMP
  found state code: 2'00
  found ctrl input: \soc.cpu.wbm_ack_i
  found state code: 2'10
  found ctrl input: \soc.cpu.picorv32_core.mem_valid
  found state code: 2'01
  found ctrl output: $flatten\soc.\cpu.$procmux$12350_CMP
  found ctrl output: $flatten\soc.\cpu.$procmux$12354_CMP
  found ctrl output: $flatten\soc.\cpu.$procmux$12441_CMP
  ctrl inputs: { \soc.cpu.picorv32_core.mem_valid \soc.cpu.wbm_ack_i \soc.cpu.wb_rst_i }
  ctrl outputs: { $flatten\soc.\cpu.$procmux$12441_CMP $flatten\soc.\cpu.$procmux$12354_CMP $flatten\soc.\cpu.$procmux$12350_CMP $flatten\soc.\cpu.$0\state[1:0] }
  transition:       2'00 3'0-0 ->       2'00 5'01000
  transition:       2'00 3'1-0 ->       2'01 5'01001
  transition:       2'00 3'--1 ->       2'00 5'01000
  transition:       2'10 3'--0 ->       2'00 5'10000
  transition:       2'10 3'--1 ->       2'00 5'10000
  transition:       2'01 3'-00 ->       2'01 5'00101
  transition:       2'01 3'-10 ->       2'10 5'00110
  transition:       2'01 3'--1 ->       2'00 5'00100
Extracting FSM `\soc.simple_spi_master_inst.spi_master.state' from module `\mgmt_core'.
  found $adff cell for state register: $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14916
  root of input selection tree: $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0]
  found reset state: 2'00 (from async reset)
  found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y
  found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y
  found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y
  found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y
  found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:305$1398_Y
  found state code: 2'01
  found state code: 2'11
  found state code: 2'10
  found ctrl input: \soc.simple_spi_master_inst.spi_master.w_latched
  found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y
  found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y
  found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y
  found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y
  ctrl inputs: { \soc.simple_spi_master_inst.spi_master.w_latched $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:305$1398_Y }
  ctrl outputs: { $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y }
  transition:       2'00 2'0- ->       2'00 6'000010
  transition:       2'00 2'1- ->       2'01 6'000110
  transition:       2'10 2'-0 ->       2'01 6'010100
  transition:       2'10 2'-1 ->       2'11 6'011100
  transition:       2'01 2'-- ->       2'10 6'101000
  transition:       2'11 2'-- ->       2'00 6'000001
Extracting FSM `\soc.spimemio.spimemio.state' from module `\mgmt_core'.
  found $dff cell for state register: $flatten\soc.\spimemio.\spimemio.$procdff$14960
  root of input selection tree: $flatten\soc.\spimemio.\spimemio.$0\state[3:0]
  found reset state: 4'0000 (guessed from mux tree)
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:373$1216_Y
  found ctrl input: \soc.spimemio.spimemio.jump
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:512$1234_Y
  found ctrl input: \soc.spimemio.spimemio.xfer.din_ready
  found state code: 4'1001
  found state code: 4'1100
  found state code: 4'1011
  found state code: 4'1010
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:472$1230_Y
  found state code: 4'1000
  found state code: 4'0111
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1137_Y
  found state code: 4'0110
  found state code: 4'0101
  found ctrl input: \soc.spimemio.spimemio.dout_valid
  found state code: 4'0100
  found state code: 4'0011
  found state code: 4'0010
  found state code: 4'0001
  found ctrl input: \soc.spimemio.spimemio.config_cont
  found state code: 4'0000
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP
  ctrl inputs: { \soc.spimemio.spimemio.dout_valid \soc.spimemio.spimemio.jump \soc.spimemio.spimemio.config_cont $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1137_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:373$1216_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:472$1230_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:512$1234_Y \soc.spimemio.spimemio.xfer.din_ready }
  ctrl outputs: { $flatten\soc.\spimemio.\spimemio.$0\state[3:0] $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP }
  transition:     4'0000 8'-0--0--0 ->     4'0000 17'00000000000000001
  transition:     4'0000 8'-0--0--1 ->     4'0001 17'00010000000000001
  transition:     4'0000 8'-10-0--- ->     4'0100 17'01000000000000001
  transition:     4'0000 8'-11-0--- ->     4'0101 17'01010000000000001
  transition:     4'0000 8'----1--- ->     4'0000 17'00000000000000001
  transition:     4'1000 8'-0--0--0 ->     4'1000 17'10000000000100000
  transition:     4'1000 8'-0--0--1 ->     4'1001 17'10010000000100000
  transition:     4'1000 8'-10-0--- ->     4'0100 17'01000000000100000
  transition:     4'1000 8'-11-0--- ->     4'0101 17'01010000000100000
  transition:     4'1000 8'----1--- ->     4'0000 17'00000000000100000
  transition:     4'0100 8'-0--0--0 ->     4'0100 17'01000010000000000
  transition:     4'0100 8'-0--0--1 ->     4'0101 17'01010010000000000
  transition:     4'0100 8'-10-0--- ->     4'0100 17'01000010000000000
  transition:     4'0100 8'-11-0--- ->     4'0101 17'01010010000000000
  transition:     4'0100 8'----1--- ->     4'0000 17'00000010000000000
  transition:     4'1100 8'-0--0-0- ->     4'1100 17'11000001000000000
  transition:     4'1100 8'-0--0-10 ->     4'1100 17'11000001000000000
  transition:     4'1100 8'-0--0-11 ->     4'1001 17'10010001000000000
  transition:     4'1100 8'-10-0--- ->     4'0100 17'01000001000000000
  transition:     4'1100 8'-11-0--- ->     4'0101 17'01010001000000000
  transition:     4'1100 8'----1--- ->     4'0000 17'00000001000000000
  transition:     4'0010 8'-0--0--0 ->     4'0010 17'00100000000000010
  transition:     4'0010 8'-0--0--1 ->     4'0011 17'00110000000000010
  transition:     4'0010 8'-10-0--- ->     4'0100 17'01000000000000010
  transition:     4'0010 8'-11-0--- ->     4'0101 17'01010000000000010
  transition:     4'0010 8'----1--- ->     4'0000 17'00000000000000010
  transition:     4'1010 8'-0--0--0 ->     4'1010 17'10100000010000000
  transition:     4'1010 8'-0--0--1 ->     4'1011 17'10110000010000000
  transition:     4'1010 8'-10-0--- ->     4'0100 17'01000000010000000
  transition:     4'1010 8'-11-0--- ->     4'0101 17'01010000010000000
  transition:     4'1010 8'----1--- ->     4'0000 17'00000000010000000
  transition:     4'0110 8'-0--0--0 ->     4'0110 17'01100000000001000
  transition:     4'0110 8'-0--0--1 ->     4'0111 17'01110000000001000
  transition:     4'0110 8'-10-0--- ->     4'0100 17'01000000000001000
  transition:     4'0110 8'-11-0--- ->     4'0101 17'01010000000001000
  transition:     4'0110 8'----1--- ->     4'0000 17'00000000000001000
  transition:     4'0001 8'00--0--- ->     4'0001 17'00010100000000000
  transition:     4'0001 8'10--0--- ->     4'0010 17'00100100000000000
  transition:     4'0001 8'-10-0--- ->     4'0100 17'01000100000000000
  transition:     4'0001 8'-11-0--- ->     4'0101 17'01010100000000000
  transition:     4'0001 8'----1--- ->     4'0000 17'00000100000000000
  transition:     4'1001 8'-0--0--0 ->     4'1001 17'10010000001000000
  transition:     4'1001 8'-0--0--1 ->     4'1010 17'10100000001000000
  transition:     4'1001 8'-10-0--- ->     4'0100 17'01000000001000000
  transition:     4'1001 8'-11-0--- ->     4'0101 17'01010000001000000
  transition:     4'1001 8'----1--- ->     4'0000 17'00000000001000000
  transition:     4'0101 8'-0-00--- ->     4'0101 17'01010000000000100
  transition:     4'0101 8'-0-10--0 ->     4'0101 17'01010000000000100
  transition:     4'0101 8'-0-10--1 ->     4'0110 17'01100000000000100
  transition:     4'0101 8'-10-0--- ->     4'0100 17'01000000000000100
  transition:     4'0101 8'-11-0--- ->     4'0101 17'01010000000000100
  transition:     4'0101 8'----1--- ->     4'0000 17'00000000000000100
  transition:     4'0011 8'00--0--- ->     4'0011 17'00111000000000000
  transition:     4'0011 8'10--0--- ->     4'0100 17'01001000000000000
  transition:     4'0011 8'-10-0--- ->     4'0100 17'01001000000000000
  transition:     4'0011 8'-11-0--- ->     4'0101 17'01011000000000000
  transition:     4'0011 8'----1--- ->     4'0000 17'00001000000000000
  transition:     4'1011 8'-0--0--0 ->     4'1011 17'10110000100000000
  transition:     4'1011 8'-0--0--1 ->     4'1100 17'11000000100000000
  transition:     4'1011 8'-10-0--- ->     4'0100 17'01000000100000000
  transition:     4'1011 8'-11-0--- ->     4'0101 17'01010000100000000
  transition:     4'1011 8'----1--- ->     4'0000 17'00000000100000000
  transition:     4'0111 8'-0--0--0 ->     4'0111 17'01110000000010000
  transition:     4'0111 8'-0--00-1 ->     4'1001 17'10010000000010000
  transition:     4'0111 8'-0--01-1 ->     4'1000 17'10000000000010000
  transition:     4'0111 8'-10-0--- ->     4'0100 17'01000000000010000
  transition:     4'0111 8'-11-0--- ->     4'0101 17'01010000000010000
  transition:     4'0111 8'----1--- ->     4'0000 17'00000000000010000

12.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core'.
Optimizing FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core'.
Optimizing FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core'.
  Merging pattern 3'--0 and 3'--1 from group (1 0 5'10000).
  Merging pattern 3'--1 and 3'--0 from group (1 0 5'10000).
Optimizing FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core'.
Optimizing FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core'.
  Merging pattern 24'------------------111000 and 24'------------------111010 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------101100 and 24'------------------101110 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------111100 and 24'------------------111110 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------111010 and 24'------------------111000 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------101110 and 24'------------------101100 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------111110 and 24'------------------111100 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------1110-0 and 24'------------------1111-0 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------1111-0 and 24'------------------1110-0 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (0 1 16'0010000000000001).
  Merging pattern 24'-------0--00------111000 and 24'-------0--00------111010 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------111000 and 24'-----1-1--00------111010 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------111000 and 24'----------01------111010 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------111000 and 24'----------1-------111010 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------101100 and 24'-------0--00------101110 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------101100 and 24'-----1-1--00------101110 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------101100 and 24'----------01------101110 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------101100 and 24'----------1-------101110 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------111100 and 24'-------0--00------111110 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------111100 and 24'-----1-1--00------111110 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------111100 and 24'----------01------111110 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------111100 and 24'----------1-------111110 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------111010 and 24'-------0--00------111000 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------111010 and 24'-----1-1--00------111000 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------111010 and 24'----------01------111000 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------111010 and 24'----------1-------111000 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------101110 and 24'-------0--00------101100 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------101110 and 24'-----1-1--00------101100 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------101110 and 24'----------01------101100 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------101110 and 24'----------1-------101100 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------111110 and 24'-------0--00------111100 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------111110 and 24'-----1-1--00------111100 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------111110 and 24'----------01------111100 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------111110 and 24'----------1-------111100 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------1110-0 and 24'-------0--00------1111-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------1110-0 and 24'-----1-1--00------1111-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------1110-0 and 24'----------01------1111-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------1110-0 and 24'----------1-------1111-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------1111-0 and 24'-------0--00------1110-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------1111-0 and 24'-----1-1--00------1110-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------1111-0 and 24'----------01------1110-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------1111-0 and 24'----------1-------1110-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----0-1--00------111000 and 24'-----0-1--00------111010 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------101100 and 24'-----0-1--00------101110 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------111100 and 24'-----0-1--00------111110 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------111010 and 24'-----0-1--00------111000 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------101110 and 24'-----0-1--00------101100 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------111110 and 24'-----0-1--00------111100 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------1110-0 and 24'-----0-1--00------1111-0 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------1111-0 and 24'-----0-1--00------1110-0 from group (1 2 16'1001000000000000).
  Merging pattern 24'---0--1-----10----111000 and 24'---0--1-----10----111010 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----101100 and 24'---0--1-----10----101110 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----111100 and 24'---0--1-----10----111110 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----111010 and 24'---0--1-----10----111000 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----101110 and 24'---0--1-----10----101100 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----111110 and 24'---0--1-----10----111100 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----1110-0 and 24'---0--1-----10----1111-0 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----1111-0 and 24'---0--1-----10----1110-0 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----11----111000 and 24'---0--1-----11----111010 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------111000 and 24'---1--1-----------111010 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------111000 and 24'-1----------------111010 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----101100 and 24'---0--1-----11----101110 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------101100 and 24'---1--1-----------101110 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------101100 and 24'-1----------------101110 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----111100 and 24'---0--1-----11----111110 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------111100 and 24'---1--1-----------111110 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------111100 and 24'-1----------------111110 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----111010 and 24'---0--1-----11----111000 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------111010 and 24'---1--1-----------111000 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------111010 and 24'-1----------------111000 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----101110 and 24'---0--1-----11----101100 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------101110 and 24'---1--1-----------101100 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------101110 and 24'-1----------------101100 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----111110 and 24'---0--1-----11----111100 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------111110 and 24'---1--1-----------111100 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------111110 and 24'-1----------------111100 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----1110-0 and 24'---0--1-----11----1111-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------1110-0 and 24'---1--1-----------1111-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------1110-0 and 24'-1----------------1111-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----1111-0 and 24'---0--1-----11----1110-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------1111-0 and 24'---1--1-----------1110-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------1111-0 and 24'-1----------------1110-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----0-----111000 and 24'---0--1-----0-----111010 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----101100 and 24'---0--1-----0-----101110 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----111100 and 24'---0--1-----0-----111110 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----111010 and 24'---0--1-----0-----111000 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----101110 and 24'---0--1-----0-----101100 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----111110 and 24'---0--1-----0-----111100 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----1110-0 and 24'---0--1-----0-----1111-0 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----1111-0 and 24'---0--1-----0-----1110-0 from group (2 2 16'0001000000000010).
  Merging pattern 24'00----0-0-----0---111000 and 24'00----0-0-----0---111010 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------111000 and 24'1-----------------111010 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---101100 and 24'00----0-0-----0---101110 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------101100 and 24'1-----------------101110 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---111100 and 24'00----0-0-----0---111110 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------111100 and 24'1-----------------111110 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---111010 and 24'00----0-0-----0---111000 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------111010 and 24'1-----------------111000 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---101110 and 24'00----0-0-----0---101100 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------101110 and 24'1-----------------101100 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---111110 and 24'00----0-0-----0---111100 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------111110 and 24'1-----------------111100 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---1110-0 and 24'00----0-0-----0---1111-0 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------1110-0 and 24'1-----------------1111-0 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---1111-0 and 24'00----0-0-----0---1110-0 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------1111-0 and 24'1-----------------1110-0 from group (2 3 16'0000010000000010).
  Merging pattern 24'00------1-----0---111000 and 24'00------1-----0---111010 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---101100 and 24'00------1-----0---101110 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---111100 and 24'00------1-----0---111110 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---111010 and 24'00------1-----0---111000 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---101110 and 24'00------1-----0---101100 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---111110 and 24'00------1-----0---111100 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---1110-0 and 24'00------1-----0---1111-0 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---1111-0 and 24'00------1-----0---1110-0 from group (2 4 16'0000000100000010).
  Merging pattern 24'--------------1---111000 and 24'--------------1---111010 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---101100 and 24'--------------1---101110 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---111100 and 24'--------------1---111110 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---111010 and 24'--------------1---111000 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---101110 and 24'--------------1---101100 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---111110 and 24'--------------1---111100 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---1110-0 and 24'--------------1---1111-0 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---1111-0 and 24'--------------1---1110-0 from group (2 5 16'0000000010000010).
  Merging pattern 24'---------0--------111000 and 24'---------0--------111010 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------111000 and 24'----1----1--------111010 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------101100 and 24'---------0--------101110 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------101100 and 24'----1----1--------101110 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------111100 and 24'---------0--------111110 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------111100 and 24'----1----1--------111110 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------111010 and 24'---------0--------111000 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------111010 and 24'----1----1--------111000 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------101110 and 24'---------0--------101100 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------101110 and 24'----1----1--------101100 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------111110 and 24'---------0--------111100 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------111110 and 24'----1----1--------111100 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------1110-0 and 24'---------0--------1111-0 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------1110-0 and 24'----1----1--------1111-0 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------1111-0 and 24'---------0--------1110-0 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------1111-0 and 24'----1----1--------1110-0 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (3 1 16'0010000000001000).
  Merging pattern 24'----0----1--------111000 and 24'----0----1--------111010 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------101100 and 24'----0----1--------101110 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------111100 and 24'----0----1--------111110 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------111010 and 24'----0----1--------111000 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------101110 and 24'----0----1--------101100 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------111110 and 24'----0----1--------111100 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------1110-0 and 24'----0----1--------1111-0 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------1111-0 and 24'----0----1--------1110-0 from group (3 3 16'0000010000001000).
  Merging pattern 24'----------------11111000 and 24'----------------11111010 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------11101100 and 24'----------------11101110 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------11111100 and 24'----------------11111110 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------11111010 and 24'----------------11111000 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------11101110 and 24'----------------11101100 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------11111110 and 24'----------------11111100 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------111110-0 and 24'----------------111111-0 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------111111-0 and 24'----------------111110-0 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------10111000 and 24'----------------10111010 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-111000 and 24'----------------0-111010 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------10101100 and 24'----------------10101110 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-101100 and 24'----------------0-101110 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------10111100 and 24'----------------10111110 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-111100 and 24'----------------0-111110 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------10111010 and 24'----------------10111000 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-111010 and 24'----------------0-111000 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------10101110 and 24'----------------10101100 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-101110 and 24'----------------0-101100 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------10111110 and 24'----------------10111100 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-111110 and 24'----------------0-111100 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------101110-0 and 24'----------------101111-0 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-1110-0 and 24'----------------0-1111-0 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------101111-0 and 24'----------------101110-0 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-1111-0 and 24'----------------0-1110-0 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------11111000 and 24'----------------11111010 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------11101100 and 24'----------------11101110 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------11111100 and 24'----------------11111110 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------11111010 and 24'----------------11111000 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------11101110 and 24'----------------11101100 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------11111110 and 24'----------------11111100 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------111110-0 and 24'----------------111111-0 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------111111-0 and 24'----------------111110-0 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------10111000 and 24'----------------10111010 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-111000 and 24'----------------0-111010 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------10101100 and 24'----------------10101110 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-101100 and 24'----------------0-101110 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------10111100 and 24'----------------10111110 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-111100 and 24'----------------0-111110 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------10111010 and 24'----------------10111000 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-111010 and 24'----------------0-111000 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------10101110 and 24'----------------10101100 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-101110 and 24'----------------0-101100 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------10111110 and 24'----------------10111100 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-111110 and 24'----------------0-111100 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------101110-0 and 24'----------------101111-0 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-1110-0 and 24'----------------0-1111-0 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------101111-0 and 24'----------------101110-0 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-1111-0 and 24'----------------0-1110-0 from group (5 5 16'0000000011000000).
  Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$15184.
  Removing unused input signal $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$7475_Y.
Optimizing FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core'.

12.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 117 unused cells and 117 unused wires.


12.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core'.
  Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [0].
  Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [1].
  Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [2].
Optimizing FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core'.
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [0].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [1].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [2].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [3].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [4].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [5].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [6].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [7].
Optimizing FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core'.
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [0].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [1].
Optimizing FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core'.
  Removing unused output signal $flatten\soc.\cpu.$0\state[1:0] [0].
  Removing unused output signal $flatten\soc.\cpu.$0\state[1:0] [1].
Optimizing FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core'.
  Removing unused output signal $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] [0].
  Removing unused output signal $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] [1].
Optimizing FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core'.
  Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [0].
  Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [1].
  Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [2].
  Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [3].

12.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ----1
  100 -> ---1-
  010 -> --1--
  001 -> -1---
  101 -> 1----
Recoding FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  10000000 -> -----1
  01000000 -> ----1-
  00100000 -> ---1--
  00001000 -> --1---
  00000010 -> -1----
  00000001 -> 1-----
Recoding FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> --1
  10 -> -1-
  01 -> 1--
Recoding FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> --1
  10 -> -1-
  01 -> 1--
Recoding FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---
Recoding FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  0000 -> ------------1
  1000 -> -----------1-
  0100 -> ----------1--
  1100 -> ---------1---
  0010 -> --------1----
  1010 -> -------1-----
  0110 -> ------1------
  0001 -> -----1-------
  1001 -> ----1--------
  0101 -> ---1---------
  0011 -> --1----------
  1011 -> -1-----------
  0111 -> 1------------

12.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\housekeeping.U1.state$15197' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\housekeeping.U1.state$15197 (\housekeeping.U1.state):

  Number of input signals:    9
  Number of output signals:   5
  Number of state bits:       5

  Input signals:
    0: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:429$3019_Y
    1: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018_Y
    2: $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017_Y
    3: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016_Y
    4: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:382$3006_Y
    5: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:369$3005_Y
    6: \housekeeping.U1.pre_pass_thru_user
    7: \housekeeping.U1.pre_pass_thru_mgmt
    8: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030_Y

  Output signals:
    0: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y
    1: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3009_Y
    2: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3008_Y
    3: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y
    4: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y

  State encoding:
    0:    5'----1  
    1:    5'---1-
    2:    5'--1--
    3:    5'-1---
    4:    5'1----

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 9'---000000   ->     0 5'00001
      1:     0 9'---0-0001   ->     0 5'00001
      2:     0 9'---0-001-   ->     0 5'00001
      3:     0 9'---0-01--   ->     0 5'00001
      4:     0 9'---0-1---   ->     0 5'00001
      5:     0 9'---1-----   ->     0 5'00001
      6:     0 9'-01010000   ->     1 5'00001
      7:     0 9'-00010000   ->     3 5'00001
      8:     0 9'-1-010000   ->     4 5'00001
      9:     1 9'---------   ->     1 5'00010
     10:     2 9'1---1----   ->     0 5'01000
     11:     2 9'----0----   ->     2 5'01000
     12:     2 9'0---1----   ->     2 5'01000
     13:     3 9'----1----   ->     2 5'10000
     14:     3 9'----0----   ->     3 5'10000
     15:     4 9'---------   ->     4 5'00100

-------------------------------------

FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\soc.cpu.picorv32_core.cpu_state$15204 (\soc.cpu.picorv32_core.cpu_state):

  Number of input signals:   22
  Number of output signals:   8
  Number of state bits:       6

  Input signals:
    0: \soc.cpu.wb_rst_i
    1: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$7529_Y
    2: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7522_Y
    3: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$7519_Y
    4: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7515_Y
    5: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$7512_Y
    6: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$7497_Y
    7: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y
    8: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y
    9: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$7433_Y
   10: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$7429_Y
   11: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$7416_Y
   12: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$7408_Y
   13: \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu
   14: \soc.cpu.picorv32_core.is_sb_sh_sw
   15: \soc.cpu.picorv32_core.decoder_trigger
   16: \soc.cpu.picorv32_core.instr_trap
   17: \soc.cpu.picorv32_core.instr_jal
   18: \soc.cpu.picorv32_core.mem_done
   19: \soc.cpu.picorv32_core.pcpi_int_ready
   20: $auto$opt_reduce.cc:134:opt_mux$15126
   21: $auto$opt_reduce.cc:134:opt_mux$15128

  Output signals:
    0: $flatten\soc.\cpu.\picorv32_core.$procmux$7616_CMP
    1: $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP
    2: $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP
    3: $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP
    4: $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP
    5: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP
    6: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP
    7: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y

  State encoding:
    0:   6'-----1
    1:   6'----1-
    2:   6'---1--
    3:   6'--1---
    4:   6'-1----
    5:   6'1-----

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 22'----------------10-000   ->     0 8'00000001
      1:     0 22'----------------0---00   ->     0 8'00000001
      2:     0 22'----------------101010   ->     0 8'00000001
      3:     0 22'----------------0-1-10   ->     0 8'00000001
      4:     0 22'----------------1011-0   ->     0 8'00000001
      5:     0 22'----------------111--0   ->     0 8'00000001
      6:     0 22'----------------11000-   ->     0 8'00000001
      7:     0 22'----------------1-010-   ->     0 8'00000001
      8:     0 22'------------------0-1-   ->     0 8'00000001
      9:     0 22'----------------10-001   ->     1 8'00000001
     10:     0 22'----------------0---01   ->     1 8'00000001
     11:     0 22'----------------101011   ->     1 8'00000001
     12:     0 22'----------------0-1-11   ->     1 8'00000001
     13:     0 22'----------------1011-1   ->     1 8'00000001
     14:     0 22'----------------111--1   ->     1 8'00000001
     15:     1 22'----------------11000-   ->     0 8'10000000
     16:     1 22'----------------1-010-   ->     0 8'10000000
     17:     1 22'------------------0-1-   ->     0 8'10000000
     18:     1 22'------0--00-----10-000   ->     1 8'10000000
     19:     1 22'----1-1--00-----10-000   ->     1 8'10000000
     20:     1 22'---------01-----10-000   ->     1 8'10000000
     21:     1 22'---------1------10-000   ->     1 8'10000000
     22:     1 22'------0--00-----0---00   ->     1 8'10000000
     23:     1 22'----1-1--00-----0---00   ->     1 8'10000000
     24:     1 22'---------01-----0---00   ->     1 8'10000000
     25:     1 22'---------1------0---00   ->     1 8'10000000
     26:     1 22'------0--00-----101010   ->     1 8'10000000
     27:     1 22'----1-1--00-----101010   ->     1 8'10000000
     28:     1 22'---------01-----101010   ->     1 8'10000000
     29:     1 22'---------1------101010   ->     1 8'10000000
     30:     1 22'------0--00-----0-1-10   ->     1 8'10000000
     31:     1 22'----1-1--00-----0-1-10   ->     1 8'10000000
     32:     1 22'---------01-----0-1-10   ->     1 8'10000000
     33:     1 22'---------1------0-1-10   ->     1 8'10000000
     34:     1 22'------0--00-----1011-0   ->     1 8'10000000
     35:     1 22'----1-1--00-----1011-0   ->     1 8'10000000
     36:     1 22'---------01-----1011-0   ->     1 8'10000000
     37:     1 22'---------1------1011-0   ->     1 8'10000000
     38:     1 22'------0--00-----111--0   ->     1 8'10000000
     39:     1 22'----1-1--00-----111--0   ->     1 8'10000000
     40:     1 22'---------01-----111--0   ->     1 8'10000000
     41:     1 22'---------1------111--0   ->     1 8'10000000
     42:     1 22'----------------10-001   ->     1 8'10000000
     43:     1 22'----------------0---01   ->     1 8'10000000
     44:     1 22'----------------101011   ->     1 8'10000000
     45:     1 22'----------------0-1-11   ->     1 8'10000000
     46:     1 22'----------------1011-1   ->     1 8'10000000
     47:     1 22'----------------111--1   ->     1 8'10000000
     48:     1 22'----0-1--00-----10-000   ->     2 8'10000000
     49:     1 22'----0-1--00-----0---00   ->     2 8'10000000
     50:     1 22'----0-1--00-----101010   ->     2 8'10000000
     51:     1 22'----0-1--00-----0-1-10   ->     2 8'10000000
     52:     1 22'----0-1--00-----1011-0   ->     2 8'10000000
     53:     1 22'----0-1--00-----111--0   ->     2 8'10000000
     54:     2 22'--0--1-----10---10-000   ->     0 8'00000010
     55:     2 22'--0--1-----10---0---00   ->     0 8'00000010
     56:     2 22'--0--1-----10---101010   ->     0 8'00000010
     57:     2 22'--0--1-----10---0-1-10   ->     0 8'00000010
     58:     2 22'--0--1-----10---1011-0   ->     0 8'00000010
     59:     2 22'--0--1-----10---111--0   ->     0 8'00000010
     60:     2 22'----------------11000-   ->     0 8'00000010
     61:     2 22'----------------1-010-   ->     0 8'00000010
     62:     2 22'------------------0-1-   ->     0 8'00000010
     63:     2 22'--0--1-----11---10-000   ->     1 8'00000010
     64:     2 22'--1--1----------10-000   ->     1 8'00000010
     65:     2 22'-1--------------10-000   ->     1 8'00000010
     66:     2 22'--0--1-----11---0---00   ->     1 8'00000010
     67:     2 22'--1--1----------0---00   ->     1 8'00000010
     68:     2 22'-1--------------0---00   ->     1 8'00000010
     69:     2 22'--0--1-----11---101010   ->     1 8'00000010
     70:     2 22'--1--1----------101010   ->     1 8'00000010
     71:     2 22'-1--------------101010   ->     1 8'00000010
     72:     2 22'--0--1-----11---0-1-10   ->     1 8'00000010
     73:     2 22'--1--1----------0-1-10   ->     1 8'00000010
     74:     2 22'-1--------------0-1-10   ->     1 8'00000010
     75:     2 22'--0--1-----11---1011-0   ->     1 8'00000010
     76:     2 22'--1--1----------1011-0   ->     1 8'00000010
     77:     2 22'-1--------------1011-0   ->     1 8'00000010
     78:     2 22'--0--1-----11---111--0   ->     1 8'00000010
     79:     2 22'--1--1----------111--0   ->     1 8'00000010
     80:     2 22'-1--------------111--0   ->     1 8'00000010
     81:     2 22'----------------10-001   ->     1 8'00000010
     82:     2 22'----------------0---01   ->     1 8'00000010
     83:     2 22'----------------101011   ->     1 8'00000010
     84:     2 22'----------------0-1-11   ->     1 8'00000010
     85:     2 22'----------------1011-1   ->     1 8'00000010
     86:     2 22'----------------111--1   ->     1 8'00000010
     87:     2 22'--0--1-----0----10-000   ->     2 8'00000010
     88:     2 22'--0--1-----0----0---00   ->     2 8'00000010
     89:     2 22'--0--1-----0----101010   ->     2 8'00000010
     90:     2 22'--0--1-----0----0-1-10   ->     2 8'00000010
     91:     2 22'--0--1-----0----1011-0   ->     2 8'00000010
     92:     2 22'--0--1-----0----111--0   ->     2 8'00000010
     93:     2 22'00---0-0-----0--10-000   ->     3 8'00000010
     94:     2 22'1---------------10-000   ->     3 8'00000010
     95:     2 22'00---0-0-----0--0---00   ->     3 8'00000010
     96:     2 22'1---------------0---00   ->     3 8'00000010
     97:     2 22'00---0-0-----0--101010   ->     3 8'00000010
     98:     2 22'1---------------101010   ->     3 8'00000010
     99:     2 22'00---0-0-----0--0-1-10   ->     3 8'00000010
    100:     2 22'1---------------0-1-10   ->     3 8'00000010
    101:     2 22'00---0-0-----0--1011-0   ->     3 8'00000010
    102:     2 22'1---------------1011-0   ->     3 8'00000010
    103:     2 22'00---0-0-----0--111--0   ->     3 8'00000010
    104:     2 22'1---------------111--0   ->     3 8'00000010
    105:     2 22'00-----1-----0--10-000   ->     4 8'00000010
    106:     2 22'00-----1-----0--0---00   ->     4 8'00000010
    107:     2 22'00-----1-----0--101010   ->     4 8'00000010
    108:     2 22'00-----1-----0--0-1-10   ->     4 8'00000010
    109:     2 22'00-----1-----0--1011-0   ->     4 8'00000010
    110:     2 22'00-----1-----0--111--0   ->     4 8'00000010
    111:     2 22'-------------1--10-000   ->     5 8'00000010
    112:     2 22'-------------1--0---00   ->     5 8'00000010
    113:     2 22'-------------1--101010   ->     5 8'00000010
    114:     2 22'-------------1--0-1-10   ->     5 8'00000010
    115:     2 22'-------------1--1011-0   ->     5 8'00000010
    116:     2 22'-------------1--111--0   ->     5 8'00000010
    117:     3 22'----------------11000-   ->     0 8'00001000
    118:     3 22'----------------1-010-   ->     0 8'00001000
    119:     3 22'------------------0-1-   ->     0 8'00001000
    120:     3 22'--------0-------10-000   ->     1 8'00001000
    121:     3 22'---1----1-------10-000   ->     1 8'00001000
    122:     3 22'--------0-------0---00   ->     1 8'00001000
    123:     3 22'---1----1-------0---00   ->     1 8'00001000
    124:     3 22'--------0-------101010   ->     1 8'00001000
    125:     3 22'---1----1-------101010   ->     1 8'00001000
    126:     3 22'--------0-------0-1-10   ->     1 8'00001000
    127:     3 22'---1----1-------0-1-10   ->     1 8'00001000
    128:     3 22'--------0-------1011-0   ->     1 8'00001000
    129:     3 22'---1----1-------1011-0   ->     1 8'00001000
    130:     3 22'--------0-------111--0   ->     1 8'00001000
    131:     3 22'---1----1-------111--0   ->     1 8'00001000
    132:     3 22'----------------10-001   ->     1 8'00001000
    133:     3 22'----------------0---01   ->     1 8'00001000
    134:     3 22'----------------101011   ->     1 8'00001000
    135:     3 22'----------------0-1-11   ->     1 8'00001000
    136:     3 22'----------------1011-1   ->     1 8'00001000
    137:     3 22'----------------111--1   ->     1 8'00001000
    138:     3 22'---0----1-------10-000   ->     3 8'00001000
    139:     3 22'---0----1-------0---00   ->     3 8'00001000
    140:     3 22'---0----1-------101010   ->     3 8'00001000
    141:     3 22'---0----1-------0-1-10   ->     3 8'00001000
    142:     3 22'---0----1-------1011-0   ->     3 8'00001000
    143:     3 22'---0----1-------111--0   ->     3 8'00001000
    144:     4 22'----------------11000-   ->     0 8'00100000
    145:     4 22'----------------1-010-   ->     0 8'00100000
    146:     4 22'------------------0-1-   ->     0 8'00100000
    147:     4 22'--------------1110-000   ->     1 8'00100000
    148:     4 22'--------------110---00   ->     1 8'00100000
    149:     4 22'--------------11101010   ->     1 8'00100000
    150:     4 22'--------------110-1-10   ->     1 8'00100000
    151:     4 22'--------------111011-0   ->     1 8'00100000
    152:     4 22'--------------11111--0   ->     1 8'00100000
    153:     4 22'----------------10-001   ->     1 8'00100000
    154:     4 22'----------------0---01   ->     1 8'00100000
    155:     4 22'----------------101011   ->     1 8'00100000
    156:     4 22'----------------0-1-11   ->     1 8'00100000
    157:     4 22'----------------1011-1   ->     1 8'00100000
    158:     4 22'----------------111--1   ->     1 8'00100000
    159:     4 22'--------------1010-000   ->     4 8'00100000
    160:     4 22'--------------0-10-000   ->     4 8'00100000
    161:     4 22'--------------100---00   ->     4 8'00100000
    162:     4 22'--------------0-0---00   ->     4 8'00100000
    163:     4 22'--------------10101010   ->     4 8'00100000
    164:     4 22'--------------0-101010   ->     4 8'00100000
    165:     4 22'--------------100-1-10   ->     4 8'00100000
    166:     4 22'--------------0-0-1-10   ->     4 8'00100000
    167:     4 22'--------------101011-0   ->     4 8'00100000
    168:     4 22'--------------0-1011-0   ->     4 8'00100000
    169:     4 22'--------------10111--0   ->     4 8'00100000
    170:     4 22'--------------0-111--0   ->     4 8'00100000
    171:     5 22'----------------11000-   ->     0 8'01000000
    172:     5 22'----------------1-010-   ->     0 8'01000000
    173:     5 22'------------------0-1-   ->     0 8'01000000
    174:     5 22'--------------1110-000   ->     1 8'01000000
    175:     5 22'--------------110---00   ->     1 8'01000000
    176:     5 22'--------------11101010   ->     1 8'01000000
    177:     5 22'--------------110-1-10   ->     1 8'01000000
    178:     5 22'--------------111011-0   ->     1 8'01000000
    179:     5 22'--------------11111--0   ->     1 8'01000000
    180:     5 22'----------------10-001   ->     1 8'01000000
    181:     5 22'----------------0---01   ->     1 8'01000000
    182:     5 22'----------------101011   ->     1 8'01000000
    183:     5 22'----------------0-1-11   ->     1 8'01000000
    184:     5 22'----------------1011-1   ->     1 8'01000000
    185:     5 22'----------------111--1   ->     1 8'01000000
    186:     5 22'--------------1010-000   ->     5 8'01000000
    187:     5 22'--------------0-10-000   ->     5 8'01000000
    188:     5 22'--------------100---00   ->     5 8'01000000
    189:     5 22'--------------0-0---00   ->     5 8'01000000
    190:     5 22'--------------10101010   ->     5 8'01000000
    191:     5 22'--------------0-101010   ->     5 8'01000000
    192:     5 22'--------------100-1-10   ->     5 8'01000000
    193:     5 22'--------------0-0-1-10   ->     5 8'01000000
    194:     5 22'--------------101011-0   ->     5 8'01000000
    195:     5 22'--------------0-1011-0   ->     5 8'01000000
    196:     5 22'--------------10111--0   ->     5 8'01000000
    197:     5 22'--------------0-111--0   ->     5 8'01000000

-------------------------------------

FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\soc.cpu.picorv32_core.mem_wordsize$15214 (\soc.cpu.picorv32_core.mem_wordsize):

  Number of input signals:   13
  Number of output signals:   3
  Number of state bits:       3

  Input signals:
    0: \soc.cpu.wb_rst_i
    1: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP
    2: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP
    3: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$7502_Y
    4: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$7501_Y
    5: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y
    6: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y
    7: \soc.cpu.picorv32_core.instr_sw
    8: \soc.cpu.picorv32_core.instr_sh
    9: \soc.cpu.picorv32_core.instr_sb
   10: \soc.cpu.picorv32_core.instr_lw
   11: \soc.cpu.picorv32_core.mem_do_wdata
   12: \soc.cpu.picorv32_core.mem_do_rdata

  Output signals:
    0: $flatten\soc.\cpu.\picorv32_core.$procmux$10355_CMP
    1: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7520_Y
    2: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7513_Y

  State encoding:
    0:      3'--1
    1:      3'-1-
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 13'------0---000   ->     0 3'100
      1:     0 13'-------0---10   ->     0 3'100
      2:     0 13'-0---1-1---10   ->     0 3'100
      3:     0 13'-1-----1---10   ->     0 3'100
      4:     0 13'-------0--1-0   ->     0 3'100
      5:     0 13'0-1----1--1-0   ->     0 3'100
      6:     0 13'1------1--1-0   ->     0 3'100
      7:     0 13'------1-----0   ->     0 3'100
      8:     0 13'------------1   ->     0 3'100
      9:     0 13'-0-1---1---10   ->     1 3'100
     10:     0 13'0------11-1-0   ->     1 3'100
     11:     0 13'-0--1--1---10   ->     2 3'100
     12:     0 13'0------1-11-0   ->     2 3'100
     13:     1 13'-0---1-1---10   ->     0 3'001
     14:     1 13'0-1----1--1-0   ->     0 3'001
     15:     1 13'------1-----0   ->     0 3'001
     16:     1 13'------0---000   ->     1 3'001
     17:     1 13'-------0---10   ->     1 3'001
     18:     1 13'-0-1---1---10   ->     1 3'001
     19:     1 13'-1-----1---10   ->     1 3'001
     20:     1 13'0------11-1-0   ->     1 3'001
     21:     1 13'-------0--1-0   ->     1 3'001
     22:     1 13'1------1--1-0   ->     1 3'001
     23:     1 13'------------1   ->     1 3'001
     24:     1 13'-0--1--1---10   ->     2 3'001
     25:     1 13'0------1-11-0   ->     2 3'001
     26:     2 13'-0---1-1---10   ->     0 3'010
     27:     2 13'0-1----1--1-0   ->     0 3'010
     28:     2 13'------1-----0   ->     0 3'010
     29:     2 13'-0-1---1---10   ->     1 3'010
     30:     2 13'0------11-1-0   ->     1 3'010
     31:     2 13'------0---000   ->     2 3'010
     32:     2 13'-------0---10   ->     2 3'010
     33:     2 13'-0--1--1---10   ->     2 3'010
     34:     2 13'-1-----1---10   ->     2 3'010
     35:     2 13'0------1-11-0   ->     2 3'010
     36:     2 13'-------0--1-0   ->     2 3'010
     37:     2 13'1------1--1-0   ->     2 3'010
     38:     2 13'------------1   ->     2 3'010

-------------------------------------

FSM `$fsm$\soc.cpu.state$15219' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\soc.cpu.state$15219 (\soc.cpu.state):

  Number of input signals:    3
  Number of output signals:   3
  Number of state bits:       3

  Input signals:
    0: \soc.cpu.wb_rst_i
    1: \soc.cpu.wbm_ack_i
    2: \soc.cpu.picorv32_core.mem_valid

  Output signals:
    0: $flatten\soc.\cpu.$procmux$12350_CMP
    1: $flatten\soc.\cpu.$procmux$12354_CMP
    2: $flatten\soc.\cpu.$procmux$12441_CMP

  State encoding:
    0:      3'--1  
    1:      3'-1-
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 3'0-0   ->     0 3'010
      1:     0 3'--1   ->     0 3'010
      2:     0 3'1-0   ->     2 3'010
      3:     1 3'---   ->     0 3'100
      4:     2 3'--1   ->     0 3'001
      5:     2 3'-10   ->     1 3'001
      6:     2 3'-00   ->     2 3'001

-------------------------------------

FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\soc.simple_spi_master_inst.spi_master.state$15224 (\soc.simple_spi_master_inst.spi_master.state):

  Number of input signals:    2
  Number of output signals:   4
  Number of state bits:       4

  Input signals:
    0: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:305$1398_Y
    1: \soc.simple_spi_master_inst.spi_master.w_latched

  Output signals:
    0: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y
    1: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y
    2: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y
    3: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y

  State encoding:
    0:     4'---1  
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'0-   ->     0 4'0010
      1:     0 2'1-   ->     2 4'0010
      2:     1 2'-0   ->     2 4'0100
      3:     1 2'-1   ->     3 4'0100
      4:     2 2'--   ->     1 4'1000
      5:     3 2'--   ->     0 4'0001

-------------------------------------

FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\soc.spimemio.spimemio.state$15230 (\soc.spimemio.spimemio.state):

  Number of input signals:    8
  Number of output signals:  13
  Number of state bits:      13

  Input signals:
    0: \soc.spimemio.spimemio.xfer.din_ready
    1: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:512$1234_Y
    2: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:472$1230_Y
    3: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:373$1216_Y
    4: $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1137_Y
    5: \soc.spimemio.spimemio.config_cont
    6: \soc.spimemio.spimemio.jump
    7: \soc.spimemio.spimemio.dout_valid

  Output signals:
    0: $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP
    1: $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP
    2: $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP
    3: $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP
    4: $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP
    5: $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP
    6: $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP
    7: $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP
    8: $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP
    9: $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP
   10: $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP
   11: $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP
   12: $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP

  State encoding:
    0: 13'------------1  
    1: 13'-----------1-
    2: 13'----------1--
    3: 13'---------1---
    4: 13'--------1----
    5: 13'-------1-----
    6: 13'------1------
    7: 13'-----1-------
    8: 13'----1--------
    9: 13'---1---------
   10: 13'--1----------
   11: 13'-1-----------
   12: 13'1------------

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 8'-0--0--0   ->     0 13'0000000000001
      1:     0 8'----1---   ->     0 13'0000000000001
      2:     0 8'-10-0---   ->     2 13'0000000000001
      3:     0 8'-0--0--1   ->     7 13'0000000000001
      4:     0 8'-11-0---   ->     9 13'0000000000001
      5:     1 8'----1---   ->     0 13'0000000100000
      6:     1 8'-0--0--0   ->     1 13'0000000100000
      7:     1 8'-10-0---   ->     2 13'0000000100000
      8:     1 8'-0--0--1   ->     8 13'0000000100000
      9:     1 8'-11-0---   ->     9 13'0000000100000
     10:     2 8'----1---   ->     0 13'0010000000000
     11:     2 8'-0--0--0   ->     2 13'0010000000000
     12:     2 8'-10-0---   ->     2 13'0010000000000
     13:     2 8'-0--0--1   ->     9 13'0010000000000
     14:     2 8'-11-0---   ->     9 13'0010000000000
     15:     3 8'----1---   ->     0 13'0001000000000
     16:     3 8'-10-0---   ->     2 13'0001000000000
     17:     3 8'-0--0-10   ->     3 13'0001000000000
     18:     3 8'-0--0-0-   ->     3 13'0001000000000
     19:     3 8'-0--0-11   ->     8 13'0001000000000
     20:     3 8'-11-0---   ->     9 13'0001000000000
     21:     4 8'----1---   ->     0 13'0000000000010
     22:     4 8'-10-0---   ->     2 13'0000000000010
     23:     4 8'-0--0--0   ->     4 13'0000000000010
     24:     4 8'-11-0---   ->     9 13'0000000000010
     25:     4 8'-0--0--1   ->    10 13'0000000000010
     26:     5 8'----1---   ->     0 13'0000010000000
     27:     5 8'-10-0---   ->     2 13'0000010000000
     28:     5 8'-0--0--0   ->     5 13'0000010000000
     29:     5 8'-11-0---   ->     9 13'0000010000000
     30:     5 8'-0--0--1   ->    11 13'0000010000000
     31:     6 8'----1---   ->     0 13'0000000001000
     32:     6 8'-10-0---   ->     2 13'0000000001000
     33:     6 8'-0--0--0   ->     6 13'0000000001000
     34:     6 8'-11-0---   ->     9 13'0000000001000
     35:     6 8'-0--0--1   ->    12 13'0000000001000
     36:     7 8'----1---   ->     0 13'0100000000000
     37:     7 8'-10-0---   ->     2 13'0100000000000
     38:     7 8'10--0---   ->     4 13'0100000000000
     39:     7 8'00--0---   ->     7 13'0100000000000
     40:     7 8'-11-0---   ->     9 13'0100000000000
     41:     8 8'----1---   ->     0 13'0000001000000
     42:     8 8'-10-0---   ->     2 13'0000001000000
     43:     8 8'-0--0--1   ->     5 13'0000001000000
     44:     8 8'-0--0--0   ->     8 13'0000001000000
     45:     8 8'-11-0---   ->     9 13'0000001000000
     46:     9 8'----1---   ->     0 13'0000000000100
     47:     9 8'-10-0---   ->     2 13'0000000000100
     48:     9 8'-0-10--1   ->     6 13'0000000000100
     49:     9 8'-0-10--0   ->     9 13'0000000000100
     50:     9 8'-0-00---   ->     9 13'0000000000100
     51:     9 8'-11-0---   ->     9 13'0000000000100
     52:    10 8'----1---   ->     0 13'1000000000000
     53:    10 8'-10-0---   ->     2 13'1000000000000
     54:    10 8'10--0---   ->     2 13'1000000000000
     55:    10 8'-11-0---   ->     9 13'1000000000000
     56:    10 8'00--0---   ->    10 13'1000000000000
     57:    11 8'----1---   ->     0 13'0000100000000
     58:    11 8'-10-0---   ->     2 13'0000100000000
     59:    11 8'-0--0--1   ->     3 13'0000100000000
     60:    11 8'-11-0---   ->     9 13'0000100000000
     61:    11 8'-0--0--0   ->    11 13'0000100000000
     62:    12 8'----1---   ->     0 13'0000000010000
     63:    12 8'-0--01-1   ->     1 13'0000000010000
     64:    12 8'-10-0---   ->     2 13'0000000010000
     65:    12 8'-0--00-1   ->     8 13'0000000010000
     66:    12 8'-11-0---   ->     9 13'0000000010000
     67:    12 8'-0--0--0   ->    12 13'0000000010000

-------------------------------------

12.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core'.
Mapping FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core'.
Mapping FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core'.
Mapping FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core'.
Mapping FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core'.
Mapping FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core'.

12.9. Executing OPT pass (performing simple optimizations).

12.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 46 cells.

12.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/7 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8267.
    dead port 4/7 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8267.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8270.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8270.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8280.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8280.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8321.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8321.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8324.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8324.
    dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8326.
    dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8326.
    dead port 3/6 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8514.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8530.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8530.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8796.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8796.
    dead port 1/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8798.
    dead port 2/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8798.
    dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808.
    dead port 2/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808.
    dead port 3/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808.
    dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9005.
    dead port 3/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9030.
    dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039.
    dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039.
    dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039.
    dead port 4/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039.
    dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044.
    dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044.
    dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044.
    dead port 4/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9048.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9048.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9051.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9051.
Removed 36 multiplexer ports.


12.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15119: { \soc.cpu.picorv32_core.cpu_state [5:4] \soc.cpu.picorv32_core.cpu_state [2:0] }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15117: \soc.cpu.picorv32_core.cpu_state [4:0]
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15115: { \soc.cpu.picorv32_core.cpu_state [5] \soc.cpu.picorv32_core.cpu_state [3:0] }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15113: { \soc.cpu.picorv32_core.cpu_state [5:2] \soc.cpu.picorv32_core.cpu_state [0] }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15111: { \soc.cpu.picorv32_core.cpu_state [5:3] \soc.cpu.picorv32_core.cpu_state [0] }
  Optimizing cells in module \mgmt_core.
Performed a total of 5 changes.

12.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.9.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\soc.\wb_bridge.$procdff$14990 ($dff) from module mgmt_core (D = $flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:60$4514_Y, Q = \soc.wb_bridge.wb_ack_read, rval = 2'00).
Adding SRST signal on $flatten\soc.\wb_bridge.$procdff$14989 ($dff) from module mgmt_core (D = $flatten\soc.\wb_bridge.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:59$4510_Y, Q = \soc.wb_bridge.wb_ack_o, rval = 2'00).
Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14819 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11093_Y, Q = \soc.sysctrl.sysctrl.irq_8_inputsrc, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16182 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.sysctrl.sysctrl.irq_8_inputsrc).
Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14818 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11111_Y, Q = \soc.sysctrl.sysctrl.irq_7_inputsrc, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16192 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.irq_7_inputsrc).
Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14817 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11127_Y, Q = \soc.sysctrl.sysctrl.trap_output_dest, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16202 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.trap_output_dest).
Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14816 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11140_Y, Q = \soc.sysctrl.sysctrl.clk2_output_dest, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16210 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.sysctrl.sysctrl.clk2_output_dest).
Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14815 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11153_Y, Q = \soc.sysctrl.sysctrl.clk1_output_dest, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16216 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.clk1_output_dest).
Adding EN signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14814 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11158_Y, Q = \soc.sysctrl.sysctrl.iomem_ready).
Adding EN signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14813 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11172_Y, Q = \soc.sysctrl.sysctrl.iomem_rdata).
Adding SRST signal on $auto$opt_dff.cc:764:run$16229 ($dffe) from module mgmt_core (D = 28'xxxxxxxxxxxxxxxxxxxxxxxxxxxx, Q = \soc.sysctrl.sysctrl.iomem_rdata [31:4], rval = 28'0000000000000000000000000000).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14957 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.fetch, Q = \soc.spimemio.spimemio.xfer.last_fetch, rval = 1'1).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14956 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.next_fetch, Q = \soc.spimemio.spimemio.xfer.fetch, rval = 1'1).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14955 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13333_Y, Q = \soc.spimemio.spimemio.xfer.xfer_tag, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16239 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_tag, Q = \soc.spimemio.spimemio.xfer.xfer_tag).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14954 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13338_Y, Q = \soc.spimemio.spimemio.xfer.xfer_rd, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16241 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_rd, Q = \soc.spimemio.spimemio.xfer.xfer_rd).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14953 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13343_Y, Q = \soc.spimemio.spimemio.xfer.xfer_qspi, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16243 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_qspi, Q = \soc.spimemio.spimemio.xfer.xfer_qspi).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14951 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13356_Y, Q = \soc.spimemio.spimemio.xfer.dummy_count, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16245 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13356_Y, Q = \soc.spimemio.spimemio.xfer.dummy_count).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14950 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13366_Y [3], Q = \soc.spimemio.spimemio.xfer.count [3], rval = 1'0).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14950 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13364_Y [2:0], Q = \soc.spimemio.spimemio.xfer.count [2:0], rval = 3'000).
Adding EN signal on $auto$opt_dff.cc:702:run$16252 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$2\next_count[3:0] [2:0], Q = \soc.spimemio.spimemio.xfer.count [2:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16249 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13366_Y [3], Q = \soc.spimemio.spimemio.xfer.count [3]).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14949 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$2\next_ibuffer[7:0], Q = \soc.spimemio.spimemio.xfer.ibuffer).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14948 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13384_Y, Q = \soc.spimemio.spimemio.xfer.obuffer).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14947 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13389_Y, Q = \soc.spimemio.spimemio.xfer.xfer_ddr, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16305 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.din_ddr, Q = \soc.spimemio.spimemio.xfer.xfer_ddr).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14946 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13394_Y, Q = \soc.spimemio.spimemio.xfer.xfer_dspi, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16307 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.din_dspi, Q = \soc.spimemio.spimemio.xfer.xfer_dspi).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14945 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13402_Y, Q = \soc.spimemio.spimemio.xfer.flash_clk, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16311 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13402_Y, Q = \soc.spimemio.spimemio.xfer.flash_clk).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14944 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13409_Y, Q = \soc.spimemio.spimemio.xfer.flash_csb, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$16315 ($sdff) from module mgmt_core (D = 1'0, Q = \soc.spimemio.spimemio.xfer.flash_csb).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14988 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13941_Y, Q = \soc.spimemio.spimemio.config_do, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16317 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3:0], Q = \soc.spimemio.spimemio.config_do).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14987 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13946_Y, Q = \soc.spimemio.spimemio.config_clk, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16319 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [4], Q = \soc.spimemio.spimemio.config_clk).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14986 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13951_Y, Q = \soc.spimemio.spimemio.config_csb, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16321 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [5], Q = \soc.spimemio.spimemio.config_csb).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14985 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13956_Y, Q = \soc.spimemio.spimemio.config_oe, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16323 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [11:8], Q = \soc.spimemio.spimemio.config_oe).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14984 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13961_Y, Q = \soc.spimemio.spimemio.config_dummy, rval = 4'1000).
Adding EN signal on $auto$opt_dff.cc:702:run$16325 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [19:16], Q = \soc.spimemio.spimemio.config_dummy).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14983 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13966_Y, Q = \soc.spimemio.spimemio.config_cont, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16327 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [20], Q = \soc.spimemio.spimemio.config_cont).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14982 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13971_Y, Q = \soc.spimemio.spimemio.config_qspi, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16329 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [21], Q = \soc.spimemio.spimemio.config_qspi).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14981 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13976_Y, Q = \soc.spimemio.spimemio.config_ddr, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16331 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [22], Q = \soc.spimemio.spimemio.config_ddr).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14980 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13981_Y, Q = \soc.spimemio.spimemio.config_en, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$16333 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31], Q = \soc.spimemio.spimemio.config_en).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14979 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:244$1148_Y, Q = \soc.spimemio.spimemio.softreset, rval = 1'1).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14974 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13718_Y, Q = \soc.spimemio.spimemio.rd_inc).
Adding SRST signal on $auto$opt_dff.cc:764:run$16342 ($dffe) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13706_Y, Q = \soc.spimemio.spimemio.rd_inc, rval = 1'0).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14973 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13725_Y, Q = \soc.spimemio.spimemio.rd_wait).
Adding SRST signal on $auto$opt_dff.cc:764:run$16352 ($dffe) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13723_Y, Q = \soc.spimemio.spimemio.rd_wait, rval = 1'0).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14972 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13730_Y, Q = \soc.spimemio.spimemio.rd_valid, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16356 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.spimemio.spimemio.rd_valid).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14971 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:388$1227_Y [23:0], Q = \soc.spimemio.spimemio.rd_addr).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14970 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [23:16]).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14970 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [15:8]).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14970 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [7:0]).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14969 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13789_Y, Q = \soc.spimemio.spimemio.din_rd, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16380 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.spimemio.spimemio.din_rd).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14968 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13810_Y, Q = \soc.spimemio.spimemio.din_ddr, rval = 1'0).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14967 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13829_Y, Q = \soc.spimemio.spimemio.din_qspi, rval = 1'0).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14965 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13839_Y, Q = \soc.spimemio.spimemio.din_tag, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16386 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13839_Y, Q = \soc.spimemio.spimemio.din_tag).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14964 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858_Y, Q = \soc.spimemio.spimemio.din_data).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14963 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13746_Y, Q = \soc.spimemio.spimemio.din_valid, rval = 1'0).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14962 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13696_Y, Q = \soc.spimemio.spimemio.xfer_resetn, rval = 1'0).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14961 ($dff) from module mgmt_core (D = { \soc.spimemio.spimemio.xfer.ibuffer \soc.spimemio.spimemio.buffer }, Q = \soc.spimemio.spimemio.rdata).
Adding SRST signal on $flatten\soc.\soc_mem.$procdff$14888 ($dff) from module mgmt_core (D = $flatten\soc.\soc_mem.$and$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:49$2164_Y, Q = \soc.soc_mem.wb_ack_read, rval = 1'0).
Adding SRST signal on $flatten\soc.\soc_mem.$procdff$14887 ($dff) from module mgmt_core (D = $flatten\soc.\soc_mem.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:48$2160_Y, Q = \soc.soc_mem.wb_ack_o, rval = 1'0).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14943 ($dff) from module mgmt_core (D = { $flatten\soc.\simpleuart.\simpleuart.$procmux$13302_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$13307_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$13312_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$13317_Y }, Q = \soc.simpleuart.simpleuart.cfg_divider, rval = 1).
Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simpleuart.simpleuart.cfg_divider [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.simpleuart.simpleuart.cfg_divider [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.simpleuart.simpleuart.cfg_divider [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.simpleuart.simpleuart.cfg_divider [31:24]).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14942 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13322_Y, Q = \soc.simpleuart.simpleuart.enabled, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16421 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.simpleuart.simpleuart.enabled).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14941 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13263_Y, Q = \soc.simpleuart.simpleuart.recv_buf_valid, rval = 1'0).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14940 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13271_Y, Q = \soc.simpleuart.simpleuart.recv_buf_data, rval = 8'00000000).
Adding EN signal on $auto$opt_dff.cc:702:run$16424 ($sdff) from module mgmt_core (D = \soc.simpleuart.simpleuart.recv_pattern, Q = \soc.simpleuart.simpleuart.recv_buf_data).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14939 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13279_Y, Q = \soc.simpleuart.simpleuart.recv_pattern, rval = 8'00000000).
Adding EN signal on $auto$opt_dff.cc:702:run$16428 ($sdff) from module mgmt_core (D = { \mgmt_in_data [5] \soc.simpleuart.simpleuart.recv_pattern [7:1] }, Q = \soc.simpleuart.simpleuart.recv_pattern).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14938 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13249_Y, Q = \soc.simpleuart.simpleuart.recv_divcnt, rval = 0).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14937 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13291_Y, Q = \soc.simpleuart.simpleuart.recv_state, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16435 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13291_Y, Q = \soc.simpleuart.simpleuart.recv_state).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14936 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13219_Y, Q = \soc.simpleuart.simpleuart.send_dummy, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$16447 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13219_Y, Q = \soc.simpleuart.simpleuart.send_dummy).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14935 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328_Y, Q = \soc.simpleuart.simpleuart.send_divcnt, rval = 0).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14934 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13230_Y, Q = \soc.simpleuart.simpleuart.send_bitcnt, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16454 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13230_Y, Q = \soc.simpleuart.simpleuart.send_bitcnt).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14933 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13235_Y [9], Q = \soc.simpleuart.simpleuart.send_pattern [9], rval = 1'1).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14933 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13238_Y [8:0], Q = \soc.simpleuart.simpleuart.send_pattern [8:0], rval = 9'111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$16463 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13238_Y [8:0], Q = \soc.simpleuart.simpleuart.send_pattern [8:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16460 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.simpleuart.simpleuart.send_pattern [9]).
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$16467 ($sdffe) from module mgmt_core.
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14932 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15], Q = \soc.simple_spi_master_inst.spi_master.hkconn).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14931 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [11], Q = \soc.simple_spi_master_inst.spi_master.mode).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14930 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12], Q = \soc.simple_spi_master_inst.spi_master.stream).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14929 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [14], Q = \soc.simple_spi_master_inst.spi_master.irqena).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14928 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [8], Q = \soc.simple_spi_master_inst.spi_master.mlb).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14927 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [9], Q = \soc.simple_spi_master_inst.spi_master.invcsb).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14926 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [10], Q = \soc.simple_spi_master_inst.spi_master.invsck).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14925 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simple_spi_master_inst.spi_master.prescaler).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14924 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [13], Q = \soc.simple_spi_master_inst.spi_master.enable).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14922 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\w_latched[0:0], Q = \soc.simple_spi_master_inst.spi_master.w_latched).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14921 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simple_spi_master_inst.spi_master.d_latched).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14919 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\nbit[2:0], Q = \soc.simple_spi_master_inst.spi_master.nbit).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14918 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\icsb[0:0], Q = \soc.simple_spi_master_inst.spi_master.icsb).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14917 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\done[0:0], Q = \soc.simple_spi_master_inst.spi_master.done).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14915 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$not$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:331$1406_Y, Q = \soc.simple_spi_master_inst.spi_master.hsck).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14912 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13041_Y, Q = \soc.simple_spi_master_inst.spi_master.rreg).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14911 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\treg[7:0], Q = \soc.simple_spi_master_inst.spi_master.treg).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14910 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\isdo[0:0], Q = \soc.simple_spi_master_inst.spi_master.isdo).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14877 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11817_Y, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_ready, rval = 1'0).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14876 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11824_Y, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$16533 ($sdff) from module mgmt_core (D = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata_pre, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14875 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11797_Y, Q = \soc.mprj_ctrl.mprj_ctrl.xfer_ctrl, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16541 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.mprj_ctrl.mprj_ctrl.xfer_ctrl).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14874 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11812_Y, Q = \soc.mprj_ctrl.mprj_ctrl.pwr_ctrl_out, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16545 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3:0], Q = \soc.mprj_ctrl.mprj_ctrl.pwr_ctrl_out).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14871 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11688_Y, Q = \soc.mprj_ctrl.mprj_ctrl.serial_data_staging).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14870 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\xfer_state[1:0], Q = \soc.mprj_ctrl.mprj_ctrl.xfer_state).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14869 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\pad_count[5:0], Q = \soc.mprj_ctrl.mprj_ctrl.pad_count).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14868 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11744_Y, Q = \soc.mprj_ctrl.mprj_ctrl.xfer_count).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14867 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\serial_resetn[0:0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_resetn).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14866 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\serial_clock[0:0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_clock).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14865 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11612_Y, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [31:0], rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$16607 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [31:0]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14864 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11603_Y, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [37:32], rval = 6'000000).
Adding EN signal on $auto$opt_dff.cc:702:run$16611 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [5:0], Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [37:32]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14863 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11594_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[0], rval = 13'1100000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16615 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[0]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14862 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11585_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[1], rval = 13'1100000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16619 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[1]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14861 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11576_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[2], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16623 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[2]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14860 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11567_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[3], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16627 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[3]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14859 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11558_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[4], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16631 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[4]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14858 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11549_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[5], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16635 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[5]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14857 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11540_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[6], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16639 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[6]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14856 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11531_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[7], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16643 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[7]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14855 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11522_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[8], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16647 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[8]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14854 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11513_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[9], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16651 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[9]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14853 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11504_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[10], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16655 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[10]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14852 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11495_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[11], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16659 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[11]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14851 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11486_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[12], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16663 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[12]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14850 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11477_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[13], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16667 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[13]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14849 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11468_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[14], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16671 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[14]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14848 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11459_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[15], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16675 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[15]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14847 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11450_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[16], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16679 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[16]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14846 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11441_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[17], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16683 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[17]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14845 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11432_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[18], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16687 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[18]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14844 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11423_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[19], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16691 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[19]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14843 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11414_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[20], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16695 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[20]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14842 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11405_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[21], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16699 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[21]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14841 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11396_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[22], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16703 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[22]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14840 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11387_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[23], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16707 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[23]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14839 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11378_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[24], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16711 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[24]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14838 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11369_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[25], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16715 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[25]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14837 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11360_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[26], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16719 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[26]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14836 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11351_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[27], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16723 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[27]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14835 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11342_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[28], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16727 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[28]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14834 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11333_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[29], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16731 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[29]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14833 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11324_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[30], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16735 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[30]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14832 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11315_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[31], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16739 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[31]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14831 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11306_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[32], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16743 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[32]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14830 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11297_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[33], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16747 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[33]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14829 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11288_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[34], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16751 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[34]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14828 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11279_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[35], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16755 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[35]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14827 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11270_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[36], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16759 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[36]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14826 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11261_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[37], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16763 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[37]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14812 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10420_Y $flatten\soc.\la.\la_ctrl.$procmux$10450_Y $flatten\soc.\la.\la_ctrl.$procmux$10480_Y $flatten\soc.\la.\la_ctrl.$procmux$10510_Y }, Q = \soc.la.la_ctrl.la_ena_3, rval = 32'11111111111111111111111111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_3 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_3 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_3 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_3 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14811 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$11042_Y $flatten\soc.\la.\la_ctrl.$procmux$10538_Y $flatten\soc.\la.\la_ctrl.$procmux$10566_Y $flatten\soc.\la.\la_ctrl.$procmux$10594_Y }, Q = \soc.la.la_ctrl.la_ena_2, rval = 32'11111111111111111111111111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_2 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_2 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_2 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_2 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14810 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10934_Y $flatten\soc.\la.\la_ctrl.$procmux$10619_Y $flatten\soc.\la.\la_ctrl.$procmux$10644_Y $flatten\soc.\la.\la_ctrl.$procmux$10669_Y }, Q = \soc.la.la_ctrl.la_ena_1, rval = 32'11111111111111111111111111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_1 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_1 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_1 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_1 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14809 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10956_Y $flatten\soc.\la.\la_ctrl.$procmux$10691_Y $flatten\soc.\la.\la_ctrl.$procmux$10713_Y $flatten\soc.\la.\la_ctrl.$procmux$10735_Y }, Q = \soc.la.la_ctrl.la_ena_0, rval = 32'11111111111111111111111111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_0 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_0 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_0 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_0 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14808 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10975_Y $flatten\soc.\la.\la_ctrl.$procmux$10754_Y $flatten\soc.\la.\la_ctrl.$procmux$10773_Y $flatten\soc.\la.\la_ctrl.$procmux$10792_Y }, Q = \soc.la.la_ctrl.la_data_3, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_3 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_3 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_3 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_3 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14807 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10991_Y $flatten\soc.\la.\la_ctrl.$procmux$10808_Y $flatten\soc.\la.\la_ctrl.$procmux$10824_Y $flatten\soc.\la.\la_ctrl.$procmux$10840_Y }, Q = \soc.la.la_ctrl.la_data_2, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_2 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_2 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_2 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_2 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14806 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$11004_Y $flatten\soc.\la.\la_ctrl.$procmux$10853_Y $flatten\soc.\la.\la_ctrl.$procmux$10866_Y $flatten\soc.\la.\la_ctrl.$procmux$10879_Y }, Q = \soc.la.la_ctrl.la_data_1, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_1 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_1 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_1 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_1 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14805 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$11014_Y $flatten\soc.\la.\la_ctrl.$procmux$10889_Y $flatten\soc.\la.\la_ctrl.$procmux$10899_Y $flatten\soc.\la.\la_ctrl.$procmux$10909_Y }, Q = \soc.la.la_ctrl.la_data_0, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_0 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_0 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_0 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_0 [31:24]).
Adding EN signal on $flatten\soc.\la.\la_ctrl.$procdff$14804 ($dff) from module mgmt_core (D = $flatten\soc.\la.\la_ctrl.$procmux$11047_Y, Q = \soc.la.la_ctrl.iomem_ready).
Adding EN signal on $flatten\soc.\la.\la_ctrl.$procdff$14803 ($dff) from module mgmt_core (D = $flatten\soc.\la.\la_ctrl.$procmux$11073_Y, Q = \soc.la.la_ctrl.iomem_rdata).
Adding EN signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14825 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11179_Y, Q = \soc.gpio_wb.gpio_ctrl.iomem_ready).
Adding EN signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14824 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11193_Y, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata).
Adding SRST signal on $auto$opt_dff.cc:764:run$17110 ($dffe) from module mgmt_core (D = 30'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata [31:2], rval = 30'000000000000000000000000000000).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14823 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11213_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_pd, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17114 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_pd).
Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14822 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11229_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_pu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17124 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_pu).
Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14821 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11242_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_oeb, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$17132 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_oeb).
Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14820 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11252_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17138 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15022 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14157_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulhu, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15021 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14162_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulhsu, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15020 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14168_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulh, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15019 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14175_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mul, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15017 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14105_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_finish, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15016 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14116_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_waiting, rval = 1'1).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15015 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14122_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_counter).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15014 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14128_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rdx).
Adding SRST signal on $auto$opt_dff.cc:764:run$17151 ($dffe) from module mgmt_core (D = { \soc.cpu.picorv32_core.pcpi_mul.next_rdx [60] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [56] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [52] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [48] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [44] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [40] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [36] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [32] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [28] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [24] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [20] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [16] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [12] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [8] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [4] }, Q = { \soc.cpu.picorv32_core.pcpi_mul.rdx [60] \soc.cpu.picorv32_core.pcpi_mul.rdx [56] \soc.cpu.picorv32_core.pcpi_mul.rdx [52] \soc.cpu.picorv32_core.pcpi_mul.rdx [48] \soc.cpu.picorv32_core.pcpi_mul.rdx [44] \soc.cpu.picorv32_core.pcpi_mul.rdx [40] \soc.cpu.picorv32_core.pcpi_mul.rdx [36] \soc.cpu.picorv32_core.pcpi_mul.rdx [32] \soc.cpu.picorv32_core.pcpi_mul.rdx [28] \soc.cpu.picorv32_core.pcpi_mul.rdx [24] \soc.cpu.picorv32_core.pcpi_mul.rdx [20] \soc.cpu.picorv32_core.pcpi_mul.rdx [16] \soc.cpu.picorv32_core.pcpi_mul.rdx [12] \soc.cpu.picorv32_core.pcpi_mul.rdx [8] \soc.cpu.picorv32_core.pcpi_mul.rdx [4] }, rval = 15'000000000000000).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15013 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14134_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rd).
Adding SRST signal on $auto$opt_dff.cc:764:run$17153 ($dffe) from module mgmt_core (D = \soc.cpu.picorv32_core.pcpi_mul.next_rd, Q = \soc.cpu.picorv32_core.pcpi_mul.rd, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15012 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14143_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rs2).
Adding SRST signal on $auto$opt_dff.cc:764:run$17155 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [0], Q = \soc.cpu.picorv32_core.pcpi_mul.rs2 [0], rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15011 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14152_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rs1).
Adding SRST signal on $auto$opt_dff.cc:764:run$17157 ($dffe) from module mgmt_core (D = \soc.cpu.picorv32_core.reg_op1 [31], Q = \soc.cpu.picorv32_core.pcpi_mul.rs1 [63], rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15009 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2308$1031_Y [31:0], Q = \soc.cpu.picorv32_core.pcpi_mul.pcpi_rd).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15005 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14077_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_remu, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15004 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14082_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_rem, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15003 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14088_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_divu, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15002 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14095_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_div, rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14999 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2471$1084_Y, Q = \soc.cpu.picorv32_core.pcpi_div.outsign).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14998 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14032_Y, Q = \soc.cpu.picorv32_core.pcpi_div.running, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17171 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14032_Y, Q = \soc.cpu.picorv32_core.pcpi_div.running).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14997 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14041_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient_msk).
Adding SRST signal on $auto$opt_dff.cc:764:run$17181 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14038_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient_msk, rval = 32'10000000000000000000000000000000).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14996 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14052_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient).
Adding SRST signal on $auto$opt_dff.cc:764:run$17191 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14049_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient, rval = 0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14995 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14061_Y, Q = \soc.cpu.picorv32_core.pcpi_div.divisor).
Adding SRST signal on $auto$opt_dff.cc:764:run$17199 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14058_Y [30:0], Q = \soc.cpu.picorv32_core.pcpi_div.divisor [30:0], rval = 31'0000000000000000000000000000000).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14994 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14072_Y, Q = \soc.cpu.picorv32_core.pcpi_div.dividend).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14991 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14005_Y, Q = \soc.cpu.picorv32_core.pcpi_div.pcpi_wr, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14802 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:397$6960_Y, Q = \soc.cpu.picorv32_core.last_mem_valid, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14801 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10381_Y, Q = \soc.cpu.picorv32_core.mem_la_firstword_reg, rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14800 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_rdata_latched [6:0], Q = \soc.cpu.picorv32_core.mem_rdata_q [6:0]).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14798 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10013_Y, Q = \soc.cpu.picorv32_core.mem_16bit_buffer).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14797 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10034_Y, Q = \soc.cpu.picorv32_core.prefetched_high_word, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17229 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10025_Y, Q = \soc.cpu.picorv32_core.prefetched_high_word).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14796 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10048_Y, Q = \soc.cpu.picorv32_core.mem_la_secondword, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17237 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10044_Y, Q = \soc.cpu.picorv32_core.mem_la_secondword).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14795 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$0\mem_state[1:0], Q = \soc.cpu.picorv32_core.mem_state).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14794 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10083_Y, Q = \soc.cpu.picorv32_core.mem_wstrb).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14793 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_la_wdata, Q = \soc.cpu.picorv32_core.mem_wdata).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14792 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_la_addr, Q = \soc.cpu.picorv32_core.mem_addr).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14790 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$0\mem_valid[0:0], Q = \soc.cpu.picorv32_core.mem_valid).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14774 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:862$7039_Y, Q = \soc.cpu.picorv32_core.is_compare, rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14773 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9416_Y, Q = \soc.cpu.picorv32_core.is_alu_reg_reg).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14772 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9452_Y, Q = \soc.cpu.picorv32_core.is_alu_reg_imm).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14770 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9464_Y, Q = \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17287 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9462_Y, Q = \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14767 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:858$7035_Y, Q = \soc.cpu.picorv32_core.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14765 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9477_Y, Q = \soc.cpu.picorv32_core.is_sb_sh_sw).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14764 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1098$7277_Y, Q = \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14763 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1092$7268_Y, Q = \soc.cpu.picorv32_core.is_slli_srli_srai).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14762 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9497_Y, Q = \soc.cpu.picorv32_core.is_lb_lh_lw_lbu_lhu).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14760 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9501_Y, Q = \soc.cpu.picorv32_core.compressed_instr).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14759 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9547_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9342_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9310_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9330_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9314_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9318_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9326_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9338_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9322_Y 1'0 }, Q = \soc.cpu.picorv32_core.decoded_imm_j).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17295 ($dffe) from module mgmt_core.
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14758 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510_Y, Q = \soc.cpu.picorv32_core.decoded_imm).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14757 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9543_Y, Q = \soc.cpu.picorv32_core.decoded_rs2).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14756 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$procmux$9306_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9393_Y }, Q = \soc.cpu.picorv32_core.decoded_rs1).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14755 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9594_Y, Q = \soc.cpu.picorv32_core.decoded_rd).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14754 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1090$7255_Y, Q = \soc.cpu.picorv32_core.instr_timer).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14753 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:870$7053_Y, Q = \soc.cpu.picorv32_core.instr_waitirq).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14752 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1089$7251_Y, Q = \soc.cpu.picorv32_core.instr_maskirq).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14751 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:869$7049_Y, Q = \soc.cpu.picorv32_core.instr_retirq).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14750 ($dff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.instr_setq).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17304 ($dffe) from module mgmt_core.
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14749 ($dff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.instr_getq).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17305 ($dffe) from module mgmt_core.
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14748 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1084$7238_Y, Q = \soc.cpu.picorv32_core.instr_ecall_ebreak).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14747 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1082$7228_Y, Q = \soc.cpu.picorv32_core.instr_rdinstrh).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14746 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1081$7224_Y, Q = \soc.cpu.picorv32_core.instr_rdinstr).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14745 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1079$7220_Y, Q = \soc.cpu.picorv32_core.instr_rdcycleh).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14744 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1077$7212_Y, Q = \soc.cpu.picorv32_core.instr_rdcycle).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14743 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9620_Y, Q = \soc.cpu.picorv32_core.instr_and, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17311 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1075$7204_Y, Q = \soc.cpu.picorv32_core.instr_and).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14742 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9624_Y, Q = \soc.cpu.picorv32_core.instr_or, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17313 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1074$7200_Y, Q = \soc.cpu.picorv32_core.instr_or).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14741 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9628_Y, Q = \soc.cpu.picorv32_core.instr_sra, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17315 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1073$7196_Y, Q = \soc.cpu.picorv32_core.instr_sra).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14740 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9632_Y, Q = \soc.cpu.picorv32_core.instr_srl, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17317 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1072$7192_Y, Q = \soc.cpu.picorv32_core.instr_srl).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14739 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9636_Y, Q = \soc.cpu.picorv32_core.instr_xor, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17319 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1071$7188_Y, Q = \soc.cpu.picorv32_core.instr_xor).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14738 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9640_Y, Q = \soc.cpu.picorv32_core.instr_sltu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17321 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1070$7184_Y, Q = \soc.cpu.picorv32_core.instr_sltu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14737 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9644_Y, Q = \soc.cpu.picorv32_core.instr_slt, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17323 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1069$7180_Y, Q = \soc.cpu.picorv32_core.instr_slt).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14736 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9648_Y, Q = \soc.cpu.picorv32_core.instr_sll, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17325 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1068$7176_Y, Q = \soc.cpu.picorv32_core.instr_sll).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14735 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9652_Y, Q = \soc.cpu.picorv32_core.instr_sub, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17327 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1067$7172_Y, Q = \soc.cpu.picorv32_core.instr_sub).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14734 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9656_Y, Q = \soc.cpu.picorv32_core.instr_add, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17329 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1066$7168_Y, Q = \soc.cpu.picorv32_core.instr_add).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14733 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1064$7164_Y, Q = \soc.cpu.picorv32_core.instr_srai).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14732 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1063$7160_Y, Q = \soc.cpu.picorv32_core.instr_srli).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14731 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1062$7156_Y, Q = \soc.cpu.picorv32_core.instr_slli).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14730 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9666_Y, Q = \soc.cpu.picorv32_core.instr_andi, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17334 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1060$7152_Y, Q = \soc.cpu.picorv32_core.instr_andi).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14729 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9670_Y, Q = \soc.cpu.picorv32_core.instr_ori, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17336 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1059$7150_Y, Q = \soc.cpu.picorv32_core.instr_ori).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14728 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9674_Y, Q = \soc.cpu.picorv32_core.instr_xori, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17338 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1058$7148_Y, Q = \soc.cpu.picorv32_core.instr_xori).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14727 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9678_Y, Q = \soc.cpu.picorv32_core.instr_sltiu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17340 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1057$7146_Y, Q = \soc.cpu.picorv32_core.instr_sltiu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14726 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9682_Y, Q = \soc.cpu.picorv32_core.instr_slti, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17342 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1056$7144_Y, Q = \soc.cpu.picorv32_core.instr_slti).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14725 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9686_Y, Q = \soc.cpu.picorv32_core.instr_addi, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17344 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1055$7142_Y, Q = \soc.cpu.picorv32_core.instr_addi).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14724 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1053$7140_Y, Q = \soc.cpu.picorv32_core.instr_sw).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14723 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1052$7138_Y, Q = \soc.cpu.picorv32_core.instr_sh).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14722 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1051$7136_Y, Q = \soc.cpu.picorv32_core.instr_sb).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14721 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1049$7134_Y, Q = \soc.cpu.picorv32_core.instr_lhu).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14720 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1048$7132_Y, Q = \soc.cpu.picorv32_core.instr_lbu).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14719 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1047$7130_Y, Q = \soc.cpu.picorv32_core.instr_lw).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14718 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1046$7128_Y, Q = \soc.cpu.picorv32_core.instr_lh).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14717 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1045$7126_Y, Q = \soc.cpu.picorv32_core.instr_lb).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14716 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9706_Y, Q = \soc.cpu.picorv32_core.instr_bgeu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17354 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1043$7124_Y, Q = \soc.cpu.picorv32_core.instr_bgeu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14715 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9710_Y, Q = \soc.cpu.picorv32_core.instr_bltu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17356 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1042$7122_Y, Q = \soc.cpu.picorv32_core.instr_bltu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14714 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9714_Y, Q = \soc.cpu.picorv32_core.instr_bge, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17358 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1041$7120_Y, Q = \soc.cpu.picorv32_core.instr_bge).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14713 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9718_Y, Q = \soc.cpu.picorv32_core.instr_blt, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17360 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1040$7118_Y, Q = \soc.cpu.picorv32_core.instr_blt).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14712 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9722_Y, Q = \soc.cpu.picorv32_core.instr_bne, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17362 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1039$7116_Y, Q = \soc.cpu.picorv32_core.instr_bne).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14711 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9726_Y, Q = \soc.cpu.picorv32_core.instr_beq, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17364 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1038$7114_Y, Q = \soc.cpu.picorv32_core.instr_beq).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14710 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9739_Y, Q = \soc.cpu.picorv32_core.instr_jalr).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14709 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9751_Y, Q = \soc.cpu.picorv32_core.instr_jal).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14708 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:866$7042_Y, Q = \soc.cpu.picorv32_core.instr_auipc).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14707 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9771_Y, Q = \soc.cpu.picorv32_core.instr_lui).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14706 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_rdata_q, Q = \soc.cpu.picorv32_core.pcpi_insn).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14700 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8120_Y, Q = \soc.cpu.picorv32_core.do_waitirq, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14698 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_not$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1424$7367_Y, Q = \soc.cpu.picorv32_core.pcpi_timeout, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14697 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8359_Y, Q = \soc.cpu.picorv32_core.pcpi_timeout_counter, rval = 4'1111).
Adding EN signal on $auto$opt_dff.cc:702:run$17379 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366_Y [3:0], Q = \soc.cpu.picorv32_core.pcpi_timeout_counter).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14695 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8374_Y, Q = \soc.cpu.picorv32_core.latched_rd, rval = 5'00010).
Adding EN signal on $auto$opt_dff.cc:702:run$17381 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8374_Y, Q = \soc.cpu.picorv32_core.latched_rd).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14694 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8400_Y, Q = \soc.cpu.picorv32_core.latched_is_lb, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17389 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8400_Y, Q = \soc.cpu.picorv32_core.latched_is_lb).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14693 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8413_Y, Q = \soc.cpu.picorv32_core.latched_is_lh, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17399 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8413_Y, Q = \soc.cpu.picorv32_core.latched_is_lh).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14692 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8426_Y, Q = \soc.cpu.picorv32_core.latched_is_lu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17409 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8426_Y, Q = \soc.cpu.picorv32_core.latched_is_lu).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14690 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.compressed_instr, Q = \soc.cpu.picorv32_core.latched_compr).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14689 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8471_Y, Q = \soc.cpu.picorv32_core.latched_branch, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17426 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8471_Y, Q = \soc.cpu.picorv32_core.latched_branch).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14688 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8507_Y, Q = \soc.cpu.picorv32_core.latched_stalu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17434 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8507_Y, Q = \soc.cpu.picorv32_core.latched_stalu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14687 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8514_Y, Q = \soc.cpu.picorv32_core.latched_store, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$17442 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8514_Y, Q = \soc.cpu.picorv32_core.latched_store).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14683 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8572_Y, Q = \soc.cpu.picorv32_core.irq_state, rval = 2'00).
Adding EN signal on $auto$opt_dff.cc:702:run$17452 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1535$7412_Y, Q = \soc.cpu.picorv32_core.irq_state).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14676 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8134_Y, Q = \soc.cpu.picorv32_core.decoder_pseudo_trigger, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14673 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8784_Y, Q = \soc.cpu.picorv32_core.mem_do_wdata, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$17463 ($sdff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.mem_do_wdata).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14672 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8788_Y, Q = \soc.cpu.picorv32_core.mem_do_rdata, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$17465 ($sdff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.mem_do_rdata).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14671 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8862_Y, Q = \soc.cpu.picorv32_core.mem_do_rinst, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$17467 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8862_Y, Q = \soc.cpu.picorv32_core.mem_do_rinst).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14670 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8887_Y, Q = \soc.cpu.picorv32_core.mem_do_prefetch, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17479 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1568$7426_Y, Q = \soc.cpu.picorv32_core.mem_do_prefetch).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14668 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8933_Y, Q = \soc.cpu.picorv32_core.timer, rval = 0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14666 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8951_Y, Q = \soc.cpu.picorv32_core.irq_mask, rval = 32'11111111111111111111111111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$17492 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs_rs1, Q = \soc.cpu.picorv32_core.irq_mask).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14665 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8970_Y, Q = \soc.cpu.picorv32_core.irq_active, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17496 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8970_Y, Q = \soc.cpu.picorv32_core.irq_active).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14664 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8995_Y, Q = \soc.cpu.picorv32_core.irq_delay, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17506 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.irq_active, Q = \soc.cpu.picorv32_core.irq_delay).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14662 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8267_Y, Q = \soc.cpu.picorv32_core.reg_out, rval = 1024).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14661 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9008_Y, Q = \soc.cpu.picorv32_core.reg_op2).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14660 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9030_Y, Q = \soc.cpu.picorv32_core.reg_op1).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14659 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9091_Y, Q = \soc.cpu.picorv32_core.reg_next_pc, rval = 268435456).
Adding EN signal on $auto$opt_dff.cc:702:run$17535 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9089_Y, Q = \soc.cpu.picorv32_core.reg_next_pc).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14658 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9103_Y, Q = \soc.cpu.picorv32_core.reg_pc, rval = 268435456).
Adding EN signal on $auto$opt_dff.cc:702:run$17537 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0], Q = \soc.cpu.picorv32_core.reg_pc).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14657 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9123_Y, Q = \soc.cpu.picorv32_core.count_instr, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$opt_dff.cc:702:run$17539 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$7422_Y, Q = \soc.cpu.picorv32_core.count_instr).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14656 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$7368_Y, Q = \soc.cpu.picorv32_core.count_cycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14652 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9167_Y, Q = \soc.cpu.picorv32_core.pcpi_valid, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17548 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9163_Y, Q = \soc.cpu.picorv32_core.pcpi_valid).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14651 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8353_Y, Q = \soc.cpu.picorv32_core.trap, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14885 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12362_Y, Q = \soc.cpu.wbm_cyc_o, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17553 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12362_Y, Q = \soc.cpu.wbm_cyc_o).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14884 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12375_Y, Q = \soc.cpu.wbm_stb_o, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17561 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12375_Y, Q = \soc.cpu.wbm_stb_o).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14883 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12390_Y, Q = \soc.cpu.wbm_sel_o, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$17569 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_wstrb, Q = \soc.cpu.wbm_sel_o).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14882 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12399_Y, Q = \soc.cpu.wbm_we_o, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17573 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12399_Y, Q = \soc.cpu.wbm_we_o).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14881 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12414_Y, Q = \soc.cpu.wbm_dat_o, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$17581 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_wdata, Q = \soc.cpu.wbm_dat_o).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14880 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12425_Y, Q = \soc.cpu.wbm_adr_o, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$17585 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_addr, Q = \soc.cpu.wbm_adr_o).
Adding EN signal on $flatten\soc.\cpu.$procdff$14879 ($dff) from module mgmt_core (D = \soc.cpu.wbm_dat_i, Q = \soc.cpu.mem_rdata).
Adding EN signal on $flatten\soc.\cpu.$procdff$14878 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12440_Y, Q = \soc.cpu.mem_ready).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14909 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3], Q = \soc.counter_timer_1.counter_timer_high_inst.chain).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14908 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [4], Q = \soc.counter_timer_1.counter_timer_high_inst.irq_ena).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14907 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [2], Q = \soc.counter_timer_1.counter_timer_high_inst.updown).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14906 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.counter_timer_1.counter_timer_high_inst.oneshot).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14905 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.counter_timer_1.counter_timer_high_inst.enable).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14904 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [7:0]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14904 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [15:8]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14904 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [23:16]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14904 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [31:24]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14902 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [7:0], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [7:0]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14902 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [15:8], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [15:8]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14902 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [23:16], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [23:16]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14902 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [31:24], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [31:24]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14901 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$13011_Y, Q = \soc.counter_timer_1.counter_timer_high_inst.stop_out).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14900 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:197$1466_Y, Q = \soc.counter_timer_1.counter_timer_high_inst.irq_out).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14899 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3], Q = \soc.counter_timer_0.counter_timer_low_inst.chain).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14898 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [4], Q = \soc.counter_timer_0.counter_timer_low_inst.irq_ena).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14897 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [2], Q = \soc.counter_timer_0.counter_timer_low_inst.updown).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14896 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.counter_timer_0.counter_timer_low_inst.oneshot).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14895 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.counter_timer_0.counter_timer_low_inst.enable).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14894 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [7:0]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14894 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [15:8]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14894 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [23:16]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14894 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [31:24]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14892 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [7:0], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [7:0]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14892 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [15:8], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [15:8]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14892 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [23:16], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [23:16]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14892 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [31:24], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [31:24]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14891 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12696_Y, Q = \soc.counter_timer_0.counter_timer_low_inst.stop_out).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14890 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12725_Y, Q = \soc.counter_timer_0.counter_timer_low_inst.strobe).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14889 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:205$1527_Y, Q = \soc.counter_timer_0.counter_timer_low_inst.irq_out).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15040 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$14440_Y, Q = \housekeeping.U1.ldata).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15039 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$0\wrstb[0:0], Q = \housekeeping.U1.wrstb).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15037 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$14203_Y, Q = \housekeeping.U1.pre_pass_thru_user).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15036 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$14229_Y, Q = \housekeeping.U1.pre_pass_thru_mgmt).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15035 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [5:0] \housekeeping.SDI }, Q = \housekeeping.U1.predata).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15034 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$0\fixed[2:0], Q = \housekeeping.U1.fixed).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15033 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.U1.readmode).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15032 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.U1.writemode).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15031 ($adff) from module mgmt_core (D = \housekeeping.U1.pre_pass_thru_user, Q = \housekeeping.U1.pass_thru_user_delay).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15030 ($adff) from module mgmt_core (D = 1'1, Q = \housekeeping.U1.pass_thru_user).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15029 ($adff) from module mgmt_core (D = \housekeeping.U1.pre_pass_thru_mgmt, Q = \housekeeping.U1.pass_thru_mgmt_delay).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15027 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$0\count[2:0], Q = \housekeeping.U1.count).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15026 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$14370_Y, Q = \housekeeping.U1.addr).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15024 ($adff) from module mgmt_core (D = 1'1, Q = \housekeeping.U1.pass_thru_mgmt).
Adding EN signal on $flatten\housekeeping.$procdff$15049 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.reset_reg).
Adding EN signal on $flatten\housekeeping.$procdff$15048 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.irq).
Adding EN signal on $flatten\housekeeping.$procdff$15047 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.pll_bypass).
Adding EN signal on $flatten\housekeeping.$procdff$15046 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [0] \housekeeping.SDI }, Q = \housekeeping.pll_trim [25:24]).
Adding EN signal on $flatten\housekeeping.$procdff$15046 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata \housekeeping.SDI }, Q = \housekeeping.pll_trim [23:16]).
Adding EN signal on $flatten\housekeeping.$procdff$15046 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata \housekeeping.SDI }, Q = \housekeeping.pll_trim [15:8]).
Adding EN signal on $flatten\housekeeping.$procdff$15046 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata \housekeeping.SDI }, Q = \housekeeping.pll_trim [7:0]).
Adding EN signal on $flatten\housekeeping.$procdff$15045 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.pll_ena).
Adding EN signal on $flatten\housekeeping.$procdff$15044 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [3:0] \housekeeping.SDI }, Q = \housekeeping.pll_div).
Adding EN signal on $flatten\housekeeping.$procdff$15043 ($adff) from module mgmt_core (D = \housekeeping.U1.predata [4:2], Q = \housekeeping.pll90_sel).
Adding EN signal on $flatten\housekeeping.$procdff$15042 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [1:0] \housekeeping.SDI }, Q = \housekeeping.pll_sel).
Adding EN signal on $flatten\housekeeping.$procdff$15041 ($adff) from module mgmt_core (D = \housekeeping.U1.predata [0], Q = \housekeeping.pll_dco_ena).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15081 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\out_counter[0:0], Q = \clocking.divider2.odd_0.out_counter).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15074 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\counter[2:0], Q = \clocking.divider2.odd_0.counter).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15067 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\initial_begin[2:0], Q = \clocking.divider2.odd_0.initial_begin).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15066 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\out_counter2[0:0], Q = \clocking.divider2.odd_0.out_counter2).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15059 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\counter2[2:0], Q = \clocking.divider2.odd_0.counter2).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15058 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$procmux$14570_Y, Q = \clocking.divider2.odd_0.rst_pulse).
Adding EN signal on $flatten\clocking.\divider2.\even_0.$procdff$15056 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\even_0.$not$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:188$255_Y, Q = \clocking.divider2.even_0.out_counter).
Adding EN signal on $flatten\clocking.\divider2.\even_0.$procdff$15055 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\even_0.$procmux$14565_Y, Q = \clocking.divider2.even_0.counter).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15081 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\out_counter[0:0], Q = \clocking.divider.odd_0.out_counter).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15074 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\counter[2:0], Q = \clocking.divider.odd_0.counter).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15067 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\initial_begin[2:0], Q = \clocking.divider.odd_0.initial_begin).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15066 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\out_counter2[0:0], Q = \clocking.divider.odd_0.out_counter2).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15059 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\counter2[2:0], Q = \clocking.divider.odd_0.counter2).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15058 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$procmux$14570_Y, Q = \clocking.divider.odd_0.rst_pulse).
Adding EN signal on $flatten\clocking.\divider.\even_0.$procdff$15056 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\even_0.$not$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:188$255_Y, Q = \clocking.divider.even_0.out_counter).
Adding EN signal on $flatten\clocking.\divider.\even_0.$procdff$15055 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\even_0.$procmux$14565_Y, Q = \clocking.divider.even_0.counter).

12.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 933 unused cells and 1005 unused wires.


12.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.9.9. Rerunning OPT passes. (Maybe there is more to do..)

12.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

12.9.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 257 cells.

12.9.13. Executing OPT_DFF pass (perform DFF optimizations).

12.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 372 unused wires.


12.9.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.9.16. Rerunning OPT passes. (Maybe there is more to do..)

12.9.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.9.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

12.9.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.9.20. Executing OPT_DFF pass (perform DFF optimizations).

12.9.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

12.9.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.9.23. Finished OPT passes. (There is nothing left to do.)

12.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 4 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15254 ($eq).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15258 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider2.\even_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:184$254 ($eq).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14611 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14603 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14601 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14595 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14586 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14584 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14577 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14574 ($mux).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:110$240 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238 ($le).
Removed top 1 bits (of 4) from port A of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235 ($add).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:80$232 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider.\even_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:184$254 ($eq).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14611 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14603 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14601 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14595 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14586 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14584 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14577 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14574 ($mux).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:110$240 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238 ($le).
Removed top 1 bits (of 4) from port A of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235 ($add).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:80$232 ($eq).
Removed top 3 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16571 ($ne).
Removed top 3 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16567 ($ne).
Removed top 3 bits (of 6) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16565 ($ne).
Removed top 3 bits (of 7) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16563 ($ne).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16561 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16554 ($ne).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16505 ($ne).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16480 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16443 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16441 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16439 ($ne).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16130 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16126 ($eq).
Removed top 3 bits (of 9) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16287 ($ne).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16261 ($ne).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16108 ($eq).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16154 ($eq).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16139 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15514 ($eq).
Removed top 2 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15522 ($eq).
Removed top 4 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15506 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15502 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16585 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16575 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15262 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15347 ($eq).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15343 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15339 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15355 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15266 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16073 ($eq).
Removed top 2 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15765 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15748 ($eq).
Removed top 5 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15744 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15736 ($eq).
Removed top 5 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15732 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15724 ($eq).
Removed top 6 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15720 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15712 ($eq).
Removed top 5 bits (of 11) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15708 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15700 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15688 ($eq).
Removed top 5 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15684 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15679 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16057 ($eq).
Removed top 3 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16272 ($ne).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15983 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15981 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15975 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15971 ($eq).
Removed top 1 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15331 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15952 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15323 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15946 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15315 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15925 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15915 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15894 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15882 ($eq).
Removed top 2 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15870 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15858 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15834 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15825 ($eq).
Removed top 2 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15813 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15801 ($eq).
Removed top 2 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15789 ($eq).
Removed top 2 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15777 ($eq).
Removed top 1 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15655 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15639 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15635 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15651 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15663 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15659 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15544 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15606 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15598 ($eq).
Removed top 3 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15590 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15586 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15564 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15556 ($eq).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15628 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15548 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15647 ($eq).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15624 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15671 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15643 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15675 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15667 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15279 ($eq).
Removed top 7 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4412 ($eq).
Removed top 6 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4414 ($eq).
Removed top 3 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4416 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17632 ($ne).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4418 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4420 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4422 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4424 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4426 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4428 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4430 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4432 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4434 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4436 ($eq).
Removed top 4 bits (of 8) from port Y of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:49$4505 ($and).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:49$4505 ($and).
Removed top 3 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$eq$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:72$4654 ($eq).
Removed top 2 bits (of 7) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17617 ($ne).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12274 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12262 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12250 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12238 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12226 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12214 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12202 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12190 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12178 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12166 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12154 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12142 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12130 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12118 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12106 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12094 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12082 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12070 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12058 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12046 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12034 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12022 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12010 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11998 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11986 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11974 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11962 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11950 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11938 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11926 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11914 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11902 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11890 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11878 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11866 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11854 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11842 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11830 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11782 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11771 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11760 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11749 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11739 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11737 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11732 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11727 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11722 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11714 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11712 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11704 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11702 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11699 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11696 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11693 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11685 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11683 ($mux).
Removed top 5 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11656_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11655_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11654_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11653_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11652_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11651_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11650_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11649_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11648_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11647_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11646_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11645_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11644_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11643_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11642_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11641_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11640_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11639_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11638_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11637_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11636_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11635_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11634_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11633_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11632_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11631_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11630_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11629_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11628_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11627_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11626_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6531 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6526 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6521 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6516 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6511 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6506 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6501 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6496 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6491 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6486 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6481 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6476 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6471 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6466 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6461 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6456 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6451 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6446 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6441 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6436 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6431 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6426 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6421 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6416 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:359$6409 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:356$6408 ($eq).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:353$6407 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:337$6403 ($add).
Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:337$6403 ($add).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$6395 ($sub).
Removed top 26 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$6395 ($sub).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:319$6392 ($eq).
Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:213$6373 ($eq).
Removed cell mgmt_core.$flatten\soc.\la.\la_ctrl.$procmux$11052 ($mux).
Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:138$6859 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:119$6854 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:120$6853 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:121$6852 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:122$6851 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17621 ($ne).
Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11172 ($mux).
Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11169 ($mux).
Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11166 ($mux).
Removed cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11163 ($mux).
Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:133$5447 ($eq).
Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11193 ($mux).
Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11190 ($mux).
Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11187 ($mux).
Removed cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11184 ($mux).
Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:115$5437 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:105$5432 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:104$5431 ($eq).
Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:103$5430 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:39$4669 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:40$4671 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:41$4673 ($eq).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12958 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12955 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12918 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12906 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12903 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12866 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12854 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12851 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12814 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12802 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12799 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12777 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12762 ($mux).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:168$1453 ($sub).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$1452 ($add).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:40$4691 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:41$4693 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:42$4695 ($eq).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12718 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12708 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12642 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12639 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12595 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12592 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12548 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12545 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12501 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12498 ($mux).
Removed top 30 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:262$1544 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:171$1512 ($sub).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:170$1511 ($add).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:99$4713 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:100$4715 ($eq).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13156 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13153 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13151 ($mux).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15472 ($eq).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13116 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13112 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13109 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13106 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13098 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13095 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13092 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13088 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13084 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13081 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13059 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13048 ($mux).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404 ($add).
Removed top 24 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404 ($add).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17475 ($ne).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:304$1397 ($add).
Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:304$1397 ($add).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:52$4731 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:53$4733 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:54$4735 ($eq).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13296 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13293 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13289 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13286 ($mux).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13253_CMP0 ($eq).
Removed top 1 bits (of 10) from mux cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13238 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13235 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13224 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13216 ($mux).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:217$1336 ($sub).
Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:217$1336 ($sub).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328 ($add).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:184$1325 ($add).
Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:184$1325 ($add).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:159$1318 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:633$1247 ($sub).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254 ($sub).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266 ($sub).
Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:729$1285 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13354 ($mux).
Removed top 1 bits (of 4) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13361 ($mux).
Removed top 1 bits (of 4) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13364 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13379 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13382 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13399 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13402 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13419 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13421 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13423_CMP0 ($eq).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13425 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13430 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13443 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13460 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13462 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13469 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13480 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13494 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13496 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13504 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13516 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13534 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13544 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13554 ($mux).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17254 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17250 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17248 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17246 ($ne).
Removed top 1 bits (of 4) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13638 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13644 ($mux).
Removed top 2 bits (of 4) from FF cell mgmt_core.$auto$opt_dff.cc:764:run$16318 ($sdffe).
Removed top 3 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15464 ($eq).
Removed top 1 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15460 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13873_CMP0 ($eq).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13867 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13847 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13837 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13723 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13706 ($mux).
Removed top 1 bits (of 8) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:478$1232 ($mux).
Removed top 8 bits (of 32) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:388$1227 ($mux).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:386$1223 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:385$1221 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:384$1219 ($eq).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:383$1217 ($eq).
Removed top 29 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138 ($add).
Removed top 7 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138 ($add).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15430 ($eq).
Removed cell mgmt_core.$flatten\soc.\cpu.$procmux$12360 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.$procmux$12442 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.$procmux$12446 ($mux).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2439$1060 ($eq).
Removed top 6 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2439$1062 ($eq).
Removed top 31 bits (of 63) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075 ($neg).
Removed top 31 bits (of 63) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1077 ($mux).
Removed top 31 bits (of 63) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1093 ($sub).
Removed top 31 bits (of 63) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1093 ($sub).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$13996 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$13999 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14002 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14029 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14038 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14046 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14049 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14058 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14066 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14069 ($mux).
Removed top 1 bits (of 5) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019 ($add).
Removed top 1 bits (of 5) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019 ($add).
Removed top 26 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2286$1025 ($mux).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027 ($sub).
Removed top 25 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027 ($sub).
Removed top 32 bits (of 64) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2308$1031 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14128 ($mux).
Removed top 1 bits (of 64) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14152 ($mux).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14158_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14163_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14169_CMP0 ($eq).
Removed cell mgmt_core.$auto$opt_dff.cc:764:run$17151 ($dffe).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$procmux$14618 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$procmux$14620 ($mux).
Removed top 31 bits (of 32) from FF cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$procdff$15084 ($dff).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17895 ($ne).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17900 ($ne).
Removed top 16 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10358 ($pmux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10352_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10349 ($pmux).
Removed top 2 bits (of 6) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10333 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17929 ($ne).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17934 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10165_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10144_CMP0 ($eq).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10127 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10121 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10118 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10111 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10072 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10066 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10063 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10061 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10057 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10053 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10018_CMP0 ($eq).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10011 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10008 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10006 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17654 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9586_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17676 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17683 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17690 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17697 ($ne).
Removed top 2 bits (of 4) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9362 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9211 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17744 ($ne).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9036 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9034 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9028 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9026 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8974 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8968 ($mux).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15418 ($eq).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8860 ($mux).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17766 ($ne).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17768 ($ne).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17770 ($ne).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15396 ($eq).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8528 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8502 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8479 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8424 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8422 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8411 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8409 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8398 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8396 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8369 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8311 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8308 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8306 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8278 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8265 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8263 ($mux).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17827 ($ne).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17829 ($ne).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8005 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8002 ($mux).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15388 ($eq).
Removed top 1 bits (of 33) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sshr$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1240$7551 ($sshr).
Removed top 20 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1911$7506 ($or).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$7422 ($add).
Removed top 29 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7418 ($mux).
Removed top 29 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1541$7413 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$7410 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$7373 ($sub).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$7368 ($add).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366 ($sub).
Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366 ($sub).
Removed top 29 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7335 ($mux).
Removed top 4 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1090$7254 ($eq).
Removed top 5 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1089$7250 ($eq).
Removed top 3 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1089$7249 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1064$7163 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1057$7145 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1047$7129 ($eq).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1039$7115 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17643 ($ne).
Removed top 28 bits (of 32) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073 ($add).
Removed top 27 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073 ($add).
Removed top 28 bits (of 32) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072 ($add).
Removed top 27 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072 ($add).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:876$7059 ($eq).
Removed top 2 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:875$7058 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:874$7057 ($eq).
Removed top 5 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:873$7056 ($eq).
Removed top 4 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:870$7052 ($eq).
Removed top 5 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:869$7048 ($eq).
Removed top 3 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:869$7047 ($eq).
Removed top 2 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:866$7042 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:865$7041 ($eq).
Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:617$7022 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17221 ($ne).
Removed top 1 bits (of 7) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:491$6978 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:488$6974 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:486$6972 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:478$6970 ($eq).
Removed top 3 bits (of 5) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:465$6968 ($eq).
Removed top 3 bits (of 4) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$shl$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:419$6963 ($shl).
Removed top 16 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:386$6955 ($mux).
Removed top 16 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:388$6953 ($mux).
Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:25$2911 ($mux).
Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:24$2913 ($mux).
Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:28$2918 ($mux).
Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:27$2919 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15288 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15297 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15480 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15380 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:420$3014 ($add).
Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:420$3014 ($add).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016 ($eq).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3032 ($sub).
Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3032 ($sub).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:463$3033 ($add).
Removed top 24 bits (of 32) from port Y of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:463$3033 ($add).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14198 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14200 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14223 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14226 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14254 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14257 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14259 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14261 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14264 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14268 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14271 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14274 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14349 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14352 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14355 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14363 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14365 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14367 ($mux).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15376 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15367 ($eq).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14450 ($mux).
Removed top 3 bits (of 8) from mux cell mgmt_core.$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:193$2975 ($mux).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:193$2974 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2973 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$2972 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:190$2971 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:189$2970 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:188$2969 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:187$2968 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:186$2967 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:185$2966 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:184$2965 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:183$2964 ($eq).
Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:181$2963 ($eq).
Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:180$2962 ($eq).
Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:179$2961 ($eq).
Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:178$2960 ($eq).
Removed top 6 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:177$2959 ($eq).
Removed top 6 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:176$2958 ($eq).
Removed top 7 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:175$2957 ($eq).
Removed top 1 bits (of 2) from port Y of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:48$4504 ($and).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:48$4504 ($and).
Removed top 7 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$ne$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1139 ($ne).
Removed top 31 bits (of 63) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075 ($neg).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1004 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1006 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1008 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1010 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1012 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1014 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1016 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1018 ($add).
Removed top 1 bits (of 5) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1018 ($add).
Removed top 1 bits (of 64) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14150 ($mux).
Removed top 29 bits (of 32) from wire mgmt_core.$flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256_Y.
Removed top 29 bits (of 32) from wire mgmt_core.$flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256_Y.
Removed top 3 bits (of 8) from wire mgmt_core.$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:193$2975_Y.
Removed top 31 bits (of 32) from wire mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:25$2911_Y.
Removed top 31 bits (of 32) from wire mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:28$2918_Y.
Removed top 16 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$2\mem_rdata_word[31:0].
Removed top 24 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$3\mem_rdata_word[31:0].
Removed top 27 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072_Y.
Removed top 27 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073_Y.
Removed top 2 bits (of 4) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9362_Y.
Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366_Y.
Removed top 29 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7335_Y.
Removed top 29 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1541$7413_Y.
Removed top 29 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7418_Y.
Removed top 1 bits (of 7) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:491$6978_Y.
Removed top 31 bits (of 63) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075_Y.
Removed top 1 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14038_Y.
Removed top 1 bits (of 63) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14058_Y.
Removed top 1 bits (of 5) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1018_Y.
Removed top 1 bits (of 64) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14150_Y.
Removed top 1 bits (of 64) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14152_Y.
Removed top 25 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027_Y.
Removed top 26 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2286$1025_Y.
Removed top 32 bits (of 64) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2308$1031_Y.
Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11187_Y.
Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11190_Y.
Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11193_Y.
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$10\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$11\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$12\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$13\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$14\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$15\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$16\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$17\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$18\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$19\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$20\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$21\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$22\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$23\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$24\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$25\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$26\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$27\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$28\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$29\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$30\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$31\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$32\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$33\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$34\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$35\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$36\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$37\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$38\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$39\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$40\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$41\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$42\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$43\iomem_rdata_pre[31:0].
Removed top 24 bits (of 32) from wire mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404_Y.
Removed top 2 bits (of 10) from wire mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13235_Y.
Removed top 1 bits (of 10) from wire mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13238_Y.
Removed top 7 bits (of 32) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138_Y.
Removed top 8 bits (of 32) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:388$1227_Y.
Removed top 1 bits (of 8) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:478$1232_Y.
Removed top 3 bits (of 4) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:633$1246_Y.
Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:729$1285_Y.
Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11163_Y.
Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11166_Y.
Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11169_Y.
Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11172_Y.

12.11. Executing PEEPOPT pass (run peephole optimizers).

12.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 1 unused cells and 261 unused wires.


12.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module mgmt_core:
  creating $macc model for $flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
  creating $macc model for $flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235 ($add).
  creating $macc model for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242 ($sub).
  creating $macc model for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243 ($sub).
  creating $macc model for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234 ($sub).
  creating $macc model for $flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
  creating $macc model for $flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235 ($add).
  creating $macc model for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242 ($sub).
  creating $macc model for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243 ($sub).
  creating $macc model for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234 ($sub).
  creating $macc model for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:420$3014 ($add).
  creating $macc model for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:463$3033 ($add).
  creating $macc model for $flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3032 ($sub).
  creating $macc model for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:170$1511 ($add).
  creating $macc model for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:171$1512 ($sub).
  creating $macc model for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$1452 ($add).
  creating $macc model for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:168$1453 ($sub).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7543 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7336 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$7368 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$7422 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$7423 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1801$7470 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1864$7495 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6946 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7542 ($sub).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366 ($sub).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$7373 ($sub).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2469$1070 ($neg).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075 ($neg).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2488$1088 ($neg).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2490$1090 ($neg).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1093 ($sub).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1000 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1001 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1002 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1003 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1004 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1005 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1006 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1007 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1008 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1009 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1010 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1011 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1012 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1013 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1014 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1015 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1016 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1017 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1018 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$988 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$989 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$990 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$991 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$992 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$993 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$994 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$995 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$996 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$997 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$998 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$999 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027 ($sub).
  creating $macc model for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:337$6403 ($add).
  creating $macc model for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$6395 ($sub).
  creating $macc model for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:304$1397 ($add).
  creating $macc model for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404 ($add).
  creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:159$1318 ($add).
  creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:184$1325 ($add).
  creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328 ($add).
  creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:217$1336 ($sub).
  creating $macc model for $flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138 ($add).
  creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:633$1247 ($sub).
  creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254 ($sub).
  creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266 ($sub).
  creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:716$1278 ($sub).
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$998 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$999.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$996 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$997.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$994 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$995.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$992 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$993.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$990 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$991.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$988 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$989.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1018 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1016 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1017.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1014 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1015.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1012 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1013.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1010 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1011.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1008 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1009.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1006 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1007.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1004 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1005.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1002 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1003.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1000 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1001.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027.
  creating $alu model for $macc $flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:337$6403.
  creating $alu model for $macc $flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$6395.
  creating $alu model for $macc $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:304$1397.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019.
  creating $alu model for $macc $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1017.
  creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:159$1318.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1015.
  creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:184$1325.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1013.
  creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1011.
  creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:217$1336.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1009.
  creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1007.
  creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:633$1247.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1005.
  creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254.
  creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266.
  creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:716$1278.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1093.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2490$1090.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2488$1088.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2469$1070.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$7373.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7542.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6946.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1864$7495.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1801$7470.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$7423.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$7422.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$7368.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7336.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7543.
  creating $alu model for $macc $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:168$1453.
  creating $alu model for $macc $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$1452.
  creating $alu model for $macc $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:171$1512.
  creating $alu model for $macc $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:170$1511.
  creating $alu model for $macc $flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3032.
  creating $alu model for $macc $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:463$3033.
  creating $alu model for $macc $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:420$3014.
  creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234.
  creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243.
  creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242.
  creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235.
  creating $alu model for $macc $flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256.
  creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234.
  creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243.
  creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242.
  creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235.
  creating $alu model for $macc $flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256.
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1003: $auto$alumacc.cc:365:replace_macc$18023
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$991: $auto$alumacc.cc:365:replace_macc$18024
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1001: $auto$alumacc.cc:365:replace_macc$18025
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$993: $auto$alumacc.cc:365:replace_macc$18026
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$989: $auto$alumacc.cc:365:replace_macc$18027
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$995: $auto$alumacc.cc:365:replace_macc$18028
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$999: $auto$alumacc.cc:365:replace_macc$18029
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$997: $auto$alumacc.cc:365:replace_macc$18030
  creating $alu model for $flatten\clocking.\divider.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238 ($le): new $alu
  creating $alu model for $flatten\clocking.\divider2.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238 ($le): new $alu
  creating $alu model for $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017 ($lt): new $alu
  creating $alu model for $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1237$7546 ($lt): new $alu
  creating $alu model for $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1238$7547 ($lt): merged with $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7542.
  creating $alu model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$le$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2493$1092 ($le): new $alu
  creating $alu model for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:169$1322 ($gt): new $alu
  creating $alu model for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:175$1323 ($gt): new $alu
  creating $alu model for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:215$1334 ($gt): new $alu
  creating $alu model for $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018 ($eq): merged with $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017.
  creating $alu model for $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1236$7545 ($eq): merged with $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7542.
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:215$1334: $auto$alumacc.cc:485:replace_alu$18039
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:175$1323: $auto$alumacc.cc:485:replace_alu$18050
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:169$1322: $auto$alumacc.cc:485:replace_alu$18055
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$le$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2493$1092: $auto$alumacc.cc:485:replace_alu$18060
  creating $alu cell for $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017, $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018: $auto$alumacc.cc:485:replace_alu$18073
  creating $alu cell for $flatten\clocking.\divider2.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238: $auto$alumacc.cc:485:replace_alu$18080
  creating $alu cell for $flatten\clocking.\divider.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238: $auto$alumacc.cc:485:replace_alu$18093
  creating $alu cell for $flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256: $auto$alumacc.cc:485:replace_alu$18106
  creating $alu cell for $flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235: $auto$alumacc.cc:485:replace_alu$18109
  creating $alu cell for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242: $auto$alumacc.cc:485:replace_alu$18112
  creating $alu cell for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243: $auto$alumacc.cc:485:replace_alu$18115
  creating $alu cell for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234: $auto$alumacc.cc:485:replace_alu$18118
  creating $alu cell for $flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256: $auto$alumacc.cc:485:replace_alu$18121
  creating $alu cell for $flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235: $auto$alumacc.cc:485:replace_alu$18124
  creating $alu cell for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242: $auto$alumacc.cc:485:replace_alu$18127
  creating $alu cell for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243: $auto$alumacc.cc:485:replace_alu$18130
  creating $alu cell for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234: $auto$alumacc.cc:485:replace_alu$18133
  creating $alu cell for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:420$3014: $auto$alumacc.cc:485:replace_alu$18136
  creating $alu cell for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:463$3033: $auto$alumacc.cc:485:replace_alu$18139
  creating $alu cell for $flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3032: $auto$alumacc.cc:485:replace_alu$18142
  creating $alu cell for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:170$1511: $auto$alumacc.cc:485:replace_alu$18145
  creating $alu cell for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:171$1512: $auto$alumacc.cc:485:replace_alu$18148
  creating $alu cell for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$1452: $auto$alumacc.cc:485:replace_alu$18151
  creating $alu cell for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:168$1453: $auto$alumacc.cc:485:replace_alu$18154
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7336: $auto$alumacc.cc:485:replace_alu$18157
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$7368: $auto$alumacc.cc:485:replace_alu$18160
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419: $auto$alumacc.cc:485:replace_alu$18163
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$7422: $auto$alumacc.cc:485:replace_alu$18166
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$7423: $auto$alumacc.cc:485:replace_alu$18169
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1801$7470: $auto$alumacc.cc:485:replace_alu$18172
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1864$7495: $auto$alumacc.cc:485:replace_alu$18175
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6946: $auto$alumacc.cc:485:replace_alu$18178
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072: $auto$alumacc.cc:485:replace_alu$18181
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073: $auto$alumacc.cc:485:replace_alu$18184
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1237$7546: $auto$alumacc.cc:485:replace_alu$18187
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7543: $auto$alumacc.cc:485:replace_alu$18194
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7542, $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1238$7547, $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1236$7545: $auto$alumacc.cc:485:replace_alu$18197
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366: $auto$alumacc.cc:485:replace_alu$18204
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$7373: $auto$alumacc.cc:485:replace_alu$18207
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2469$1070: $auto$alumacc.cc:485:replace_alu$18210
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075: $auto$alumacc.cc:485:replace_alu$18213
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2488$1088: $auto$alumacc.cc:485:replace_alu$18216
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2490$1090: $auto$alumacc.cc:485:replace_alu$18219
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1093: $auto$alumacc.cc:485:replace_alu$18222
  creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:716$1278: $auto$alumacc.cc:485:replace_alu$18225
  creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266: $auto$alumacc.cc:485:replace_alu$18228
  creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254: $auto$alumacc.cc:485:replace_alu$18231
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1005: $auto$alumacc.cc:485:replace_alu$18234
  creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:633$1247: $auto$alumacc.cc:485:replace_alu$18237
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1007: $auto$alumacc.cc:485:replace_alu$18240
  creating $alu cell for $flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138: $auto$alumacc.cc:485:replace_alu$18243
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1009: $auto$alumacc.cc:485:replace_alu$18246
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:217$1336: $auto$alumacc.cc:485:replace_alu$18249
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1011: $auto$alumacc.cc:485:replace_alu$18252
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328: $auto$alumacc.cc:485:replace_alu$18255
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1013: $auto$alumacc.cc:485:replace_alu$18258
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:184$1325: $auto$alumacc.cc:485:replace_alu$18261
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1015: $auto$alumacc.cc:485:replace_alu$18264
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:159$1318: $auto$alumacc.cc:485:replace_alu$18267
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1017: $auto$alumacc.cc:485:replace_alu$18270
  creating $alu cell for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404: $auto$alumacc.cc:485:replace_alu$18273
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019: $auto$alumacc.cc:485:replace_alu$18276
  creating $alu cell for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:304$1397: $auto$alumacc.cc:485:replace_alu$18279
  creating $alu cell for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$6395: $auto$alumacc.cc:485:replace_alu$18282
  creating $alu cell for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:337$6403: $auto$alumacc.cc:485:replace_alu$18285
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027: $auto$alumacc.cc:485:replace_alu$18288
  created 66 $alu and 8 $macc cells.

12.14. Executing SHARE pass (SAT-based resource sharing).
Found 4 cells in module mgmt_core that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:851$2938 ($memrd):
    Found 1 activation_patterns using ctrl signal { $auto$opt_reduce.cc:134:opt_mux$15136 \soc.cpu.picorv32_core.is_lui_auipc_jal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1386$7350_Y $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL }.
    Found 1 candidates: $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937
    Analyzing resource sharing with $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937 ($memrd):
      Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$7348_Y.
      Activation pattern for cell $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:851$2938: { $auto$opt_reduce.cc:134:opt_mux$15136 \soc.cpu.picorv32_core.is_lui_auipc_jal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1386$7350_Y $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL } = 4'0010
      Activation pattern for cell $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937: $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$7348_Y = 1'1
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_timer vs. \soc.cpu.picorv32_core.instr_maskirq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_timer vs. \soc.cpu.picorv32_core.instr_retirq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_maskirq vs. \soc.cpu.picorv32_core.instr_retirq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_trap vs. \soc.cpu.picorv32_core.instr_timer
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_trap vs. \soc.cpu.picorv32_core.instr_maskirq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_trap vs. \soc.cpu.picorv32_core.instr_retirq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstrh vs. \soc.cpu.picorv32_core.instr_rdinstr
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstrh vs. \soc.cpu.picorv32_core.instr_rdcycleh
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstrh vs. \soc.cpu.picorv32_core.instr_rdcycle
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstr vs. \soc.cpu.picorv32_core.instr_rdcycleh
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstr vs. \soc.cpu.picorv32_core.instr_rdcycle
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdcycleh vs. \soc.cpu.picorv32_core.instr_rdcycle
      Adding exclusive control bits: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y vs. \soc.cpu.picorv32_core.instr_trap
      Adding exclusive control bits: $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL vs. $auto$opt_reduce.cc:134:opt_mux$15136
      Adding exclusive control bits: $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL vs. \soc.cpu.picorv32_core.is_lui_auipc_jal
      Adding exclusive control bits: \soc.cpu.picorv32_core.is_lui_auipc_jal vs. $auto$opt_reduce.cc:134:opt_mux$15136
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bgeu vs. \soc.cpu.picorv32_core.instr_bge
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bgeu vs. \soc.cpu.picorv32_core.instr_bne
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bgeu vs. \soc.cpu.picorv32_core.instr_beq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bge vs. \soc.cpu.picorv32_core.instr_bne
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bge vs. \soc.cpu.picorv32_core.instr_beq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bne vs. \soc.cpu.picorv32_core.instr_beq
      Size of SAT problem: 7 cells, 133 variables, 287 clauses
      According to the SAT solver this pair of cells can not be shared.
      Model from SAT solver: { $auto$opt_reduce.cc:134:opt_mux$15136 \soc.cpu.picorv32_core.is_lui_auipc_jal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$7348_Y $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1386$7350_Y $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL } = 5'00110
  Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937 ($memrd):
    Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$7348_Y.
    No candidates found.
  Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.$sshr$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1240$7551 ($sshr):
    Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1277$7326_Y.
    No candidates found.
  Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.$shl$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1239$7548 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1275$7322_Y.
    No candidates found.

12.15. Executing OPT pass (performing simple optimizations).

12.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 1 cells.

12.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    New ctrl vector for $pmux cell $flatten\soc.\cpu.$procmux$12440: { \soc.cpu.state [2] $auto$opt_reduce.cc:134:opt_mux$18292 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10055: { $flatten\soc.\cpu.\picorv32_core.$logic_not$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:379$6926_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10018_CMP $auto$opt_reduce.cc:134:opt_mux$18294 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8537: $auto$opt_reduce.cc:134:opt_mux$18296
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8824: { $auto$opt_reduce.cc:134:opt_mux$15126 $auto$opt_reduce.cc:134:opt_mux$18298 $auto$opt_reduce.cc:134:opt_mux$15128 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9030: { \soc.cpu.picorv32_core.cpu_state [2] $auto$opt_reduce.cc:134:opt_mux$18300 }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13839: { $auto$opt_reduce.cc:134:opt_mux$18302 \soc.spimemio.spimemio.state [8] \soc.spimemio.spimemio.state [5] \soc.spimemio.spimemio.state [11] \soc.spimemio.spimemio.state [3] }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13546: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$18304 }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13556: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$18306 }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$18295: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer \soc.cpu.picorv32_core.instr_trap }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$18301: { \soc.spimemio.spimemio.state [12] \soc.spimemio.spimemio.state [9] \soc.spimemio.spimemio.state [6] \soc.spimemio.spimemio.state [4] \soc.spimemio.spimemio.state [2:0] }
  Optimizing cells in module \mgmt_core.
Performed a total of 10 changes.

12.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 3 cells.

12.15.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$opt_dff.cc:764:run$17281 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10113_Y, Q = \soc.cpu.picorv32_core.mem_valid, rval = 1'0).
Adding SRST signal on $auto$opt_dff.cc:764:run$17257 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10055_Y, Q = \soc.cpu.picorv32_core.mem_state, rval = 2'00).
Adding SRST signal on $auto$opt_dff.cc:764:run$17199 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$shl$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1078_Y [62], Q = \soc.cpu.picorv32_core.pcpi_div.divisor [62], rval = 1'0).
Adding SRST signal on $auto$opt_dff.cc:764:run$17150 ($dffe) from module mgmt_core (D = $auto$wreduce.cc:454:run$17971 [6], Q = \soc.cpu.picorv32_core.pcpi_mul.mul_counter [6], rval = 1'0).
Adding SRST signal on $auto$opt_dff.cc:764:run$16559 ($dffe) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$4$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6397 [0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_data_staging [0], rval = 1'0).

12.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 17 unused cells and 38 unused wires.


12.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.15.9. Rerunning OPT passes. (Maybe there is more to do..)

12.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

12.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.15.13. Executing OPT_DFF pass (perform DFF optimizations).

12.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

12.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.15.16. Finished OPT passes. (There is nothing left to do.)

12.16. Executing MEMORY pass.

12.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

12.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
Checking cell `$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:0$2939' in module `\mgmt_core': merged $dff to cell.
Checking cell `$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937' in module `\mgmt_core': merged address $dff to cell.
Checking cell `$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:851$2938' in module `\mgmt_core': merged address $dff to cell.

12.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 3 unused cells and 3 unused wires.


12.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

12.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

12.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
Collecting $memrd, $memwr and $meminit for memory `\soc.cpu.picorv32_core.cpuregs.regs' in module `\mgmt_core':
  $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:0$2939 ($memwr)
  $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:851$2938 ($memrd)
  $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937 ($memrd)

12.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

12.18. Executing OPT pass (performing simple optimizations).

12.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 3 cells.

12.18.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $auto$opt_dff.cc:764:run$16362 ($dffe) from module mgmt_core (D = $auto$wreduce.cc:454:run$18015 [1:0], Q = \soc.spimemio.spimemio.rd_addr [1:0]).

12.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 19 unused cells and 111 unused wires.


12.18.5. Rerunning OPT passes. (Removed registers in this run.)

12.18.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.18.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.18.8. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 1-bit at position 4 on $flatten\soc.\cpu.\picorv32_core.$procdff$14667 ($dff) from module mgmt_core.
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14667 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [31:12] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [8] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [5] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [3] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [1] }, Q = { \soc.cpu.picorv32_core.irq_pending [31:12] \soc.cpu.picorv32_core.irq_pending [8] \soc.cpu.picorv32_core.irq_pending [5] \soc.cpu.picorv32_core.irq_pending [3] \soc.cpu.picorv32_core.irq_pending [1] }, rval = 24'000000000000000000000000).

12.18.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 1 unused wires.


12.18.10. Rerunning OPT passes. (Removed registers in this run.)

12.18.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.18.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.18.13. Executing OPT_DFF pass (perform DFF optimizations).

12.18.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 11 unused wires.


12.18.15. Finished fast OPT passes.

12.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
Mapping memory cell \soc.cpu.picorv32_core.cpuregs.regs in module \mgmt_core:
  created 32 $dff cells and 0 static cells of width 32.
  read interface: 2 $dff and 62 $mux cells.
  write interface: 32 write mux blocks.

12.20. Executing OPT pass (performing simple optimizations).

12.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    New input vector for $reduce_and cell $auto$opt_dff.cc:243:make_patterns_logic$18374: { $auto$opt_dff.cc:217:make_patterns_logic$18371 $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:386$1224_Y $auto$rtlil.cc:2121:Not$16339 }
    Consolidated identical input bits for $mux cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976:
      Old ports: A={ 3'000 $auto$wreduce.cc:454:run$17952 [4:0] }, B={ 2'00 \housekeeping.pll90_sel \housekeeping.pll_sel }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976_Y
      New ports: A={ 1'0 $auto$wreduce.cc:454:run$17952 [4:0] }, B={ \housekeeping.pll90_sel \housekeeping.pll_sel }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976_Y [5:0]
      New connections: $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976_Y [7:6] = 2'00
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10207:
      Old ports: A={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \soc.cpu.picorv32_core.mem_rdata_latched [6] 4'0000 }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y
      New ports: A={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \soc.cpu.picorv32_core.mem_rdata_latched [6] 1'0 }, Y={ $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [4] $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [0] }
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [3:1] = { $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [0] }
    Consolidated identical input bits for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10374:
      Old ports: A=\soc.cpu.picorv32_core.reg_op2, B={ \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] }, Y=\soc.cpu.picorv32_core.mem_la_wdata
      New ports: A=\soc.cpu.picorv32_core.reg_op2 [31:8], B={ \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] }, Y=\soc.cpu.picorv32_core.mem_la_wdata [31:8]
      New connections: \soc.cpu.picorv32_core.mem_la_wdata [7:0] = \soc.cpu.picorv32_core.reg_op2 [7:0]
    Consolidated identical input bits for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8259:
      Old ports: A=\soc.cpu.picorv32_core.mem_rdata_word, B={ \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15:0] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7:0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$8259_Y
      New ports: A=\soc.cpu.picorv32_core.mem_rdata_word [31:8], B={ \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15:7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$8259_Y [31:8]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$8259_Y [7:0] = \soc.cpu.picorv32_core.mem_rdata_word [7:0]
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8514: { \soc.cpu.picorv32_core.cpu_state [3] $auto$opt_reduce.cc:134:opt_mux$18885 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9282: { $flatten\soc.\cpu.\picorv32_core.$procmux$10165_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10147_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9284: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP }
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9334:
      Old ports: A={ \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] }, B={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y
      New ports: A=\soc.cpu.picorv32_core.mem_rdata_latched [31], B=\soc.cpu.picorv32_core.mem_rdata_latched [12], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [11:1] = { $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9362:
      Old ports: A=2'00, B=2'10, Y=$auto$wreduce.cc:454:run$17959 [1:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$17959 [1]
      New connections: $auto$wreduce.cc:454:run$17959 [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9540:
      Old ports: A=5'00000, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9540_Y
      New ports: A=4'0000, B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9540_Y [3:0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9540_Y [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9547:
      Old ports: A=\soc.cpu.picorv32_core.mem_rdata_latched [19:12], B={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9547_Y
      New ports: A=\soc.cpu.picorv32_core.mem_rdata_latched [19:13], B={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9547_Y [7:1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9547_Y [0] = \soc.cpu.picorv32_core.mem_rdata_latched [12]
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9572:
      Old ports: A=5'00000, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9572_Y
      New ports: A=4'0000, B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9572_Y [3:0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9572_Y [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9590:
      Old ports: A=5'00000, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9590_Y
      New ports: A=4'0000, B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9590_Y [3:0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9590_Y [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7335:
      Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$17961 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$17961 [2:1]
      New connections: $auto$wreduce.cc:454:run$17961 [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$7411:
      Old ports: A=2'00, B=2'10, Y=$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$7411_Y
      New ports: A=1'0, B=1'1, Y=$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$7411_Y [1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$7411_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1541$7413:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:454:run$17962 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$17962 [2] $auto$wreduce.cc:454:run$17962 [0] }
      New connections: $auto$wreduce.cc:454:run$17962 [1] = $auto$wreduce.cc:454:run$17962 [0]
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7418:
      Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$17963 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$17963 [2:1]
      New connections: $auto$wreduce.cc:454:run$17963 [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6947:
      Old ports: A={ \soc.cpu.picorv32_core.reg_op1 [31:2] 2'00 }, B={ $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6946_Y 2'00 }, Y=\soc.cpu.picorv32_core.mem_la_addr
      New ports: A=\soc.cpu.picorv32_core.reg_op1 [31:2], B=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6946_Y, Y=\soc.cpu.picorv32_core.mem_la_addr [31:2]
      New connections: \soc.cpu.picorv32_core.mem_la_addr [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962:
      Old ports: A=4'0011, B=4'1100, Y=$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y
      New ports: A=2'01, B=2'10, Y={ $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [2] $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [0] }
      New connections: { $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [3] $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [1] } = { $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [2] $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:491$6978:
      Old ports: A=6'000000, B=6'100000, Y=$auto$wreduce.cc:454:run$17964 [5:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$17964 [5]
      New connections: $auto$wreduce.cc:454:run$17964 [4:0] = 5'00000
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:617$7022:
      Old ports: A=2'11, B=2'00, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10061_Y
      New ports: A=1'1, B=1'0, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10061_Y [0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10061_Y [1] = $flatten\soc.\cpu.\picorv32_core.$procmux$10061_Y [0]
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141:
      Old ports: A={ 32'00000000000000000000000000000000 \soc.cpu.picorv32_core.reg_op2 }, B={ \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 }, Y=$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y
      New ports: A=1'0, B=\soc.cpu.picorv32_core.reg_op2 [31], Y=$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32]
      New connections: { $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [63:33] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [31:0] } = { $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] \soc.cpu.picorv32_core.reg_op2 }
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14150:
      Old ports: A={ 31'0000000000000000000000000000000 \soc.cpu.picorv32_core.reg_op1 }, B={ \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 }, Y=$auto$wreduce.cc:454:run$17969 [62:0]
      New ports: A=1'0, B=\soc.cpu.picorv32_core.reg_op1 [31], Y=$auto$wreduce.cc:454:run$17969 [32]
      New connections: { $auto$wreduce.cc:454:run$17969 [62:33] $auto$wreduce.cc:454:run$17969 [31:0] } = { $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] \soc.cpu.picorv32_core.reg_op1 }
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2286$1025:
      Old ports: A=6'011110, B=6'111110, Y=$auto$wreduce.cc:454:run$17972 [5:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$17972 [5]
      New connections: $auto$wreduce.cc:454:run$17972 [4:0] = 5'11110
    Consolidated identical input bits for $mux cell $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11187:
      Old ports: A={ 1'0 \soc.gpio_wb.gpio_ctrl.gpio_pd }, B={ 1'0 \soc.gpio_wb.gpio_ctrl.gpio_pu }, Y=$auto$wreduce.cc:454:run$17974 [1:0]
      New ports: A=\soc.gpio_wb.gpio_ctrl.gpio_pd, B=\soc.gpio_wb.gpio_ctrl.gpio_pu, Y=$auto$wreduce.cc:454:run$17974 [0]
      New connections: $auto$wreduce.cc:454:run$17974 [1] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11710:
      Old ports: A=2'01, B=2'11, Y=$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11710_Y
      New ports: A=1'0, B=1'1, Y=$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11710_Y [1]
      New connections: $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11710_Y [0] = 1'1
    Consolidated identical input bits for $mux cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:207$1370:
      Old ports: A=32'11111111111111111111111111111111, B={ 24'000000000000000000000000 \soc.simple_spi_master_inst.spi_master.rreg }, Y=\soc.simple_spi_master_inst.simple_spi_master_reg_dat_do
      New ports: A=9'111111111, B={ 1'0 \soc.simple_spi_master_inst.spi_master.rreg }, Y=\soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8:0]
      New connections: \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [31:9] = { \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] }
    Consolidated identical input bits for $mux cell $flatten\soc.\simpleuart.\simpleuart.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:136$1313:
      Old ports: A=32'11111111111111111111111111111111, B={ 24'000000000000000000000000 \soc.simpleuart.simpleuart.recv_buf_data }, Y=\soc.simpleuart.simpleuart_reg_dat_do
      New ports: A=9'111111111, B={ 1'0 \soc.simpleuart.simpleuart.recv_buf_data }, Y=\soc.simpleuart.simpleuart_reg_dat_do [8:0]
      New connections: \soc.simpleuart.simpleuart_reg_dat_do [31:9] = { \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] }
    Consolidated identical input bits for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13839:
      Old ports: A=4'0000, B=16'0001001000110100, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13839_Y
      New ports: A=3'000, B=12'001010011100, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13839_Y [2:0]
      New connections: $flatten\soc.\spimemio.\spimemio.$procmux$13839_Y [3] = 1'0
    Consolidated identical input bits for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13870:
      Old ports: A=8'11101101, B=24'111010111011101100000011, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13870_Y
      New ports: A=5'10110, B=15'101010110100001, Y={ $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [6] $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [4:1] }
      New connections: { $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [7] $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [5] $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [0] } = { $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [3] $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [3] 1'1 }
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:478$1232:
      Old ports: A=7'1111111, B=7'0100101, Y=$auto$wreduce.cc:454:run$18016 [6:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$18016 [1]
      New connections: { $auto$wreduce.cc:454:run$18016 [6:2] $auto$wreduce.cc:454:run$18016 [0] } = { $auto$wreduce.cc:454:run$18016 [1] 1'1 $auto$wreduce.cc:454:run$18016 [1] $auto$wreduce.cc:454:run$18016 [1] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13417:
      Old ports: A=\soc.spimemio.spimemio.xfer.count, B={ $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266_Y [3:1] \soc.spimemio.spimemio.xfer.count [0] }, Y=$flatten\soc.\spimemio.\spimemio.\xfer.$5\next_count[3:0]
      New ports: A=\soc.spimemio.spimemio.xfer.count [3:1], B=$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266_Y [3:1], Y=$flatten\soc.\spimemio.\spimemio.\xfer.$5\next_count[3:0] [3:1]
      New connections: $flatten\soc.\spimemio.\spimemio.\xfer.$5\next_count[3:0] [0] = \soc.spimemio.spimemio.xfer.count [0]
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13458:
      Old ports: A=\soc.spimemio.spimemio.xfer.count, B={ $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254_Y [3:2] \soc.spimemio.spimemio.xfer.count [1:0] }, Y=$flatten\soc.\spimemio.\spimemio.\xfer.$4\next_count[3:0]
      New ports: A=\soc.spimemio.spimemio.xfer.count [3:2], B=$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254_Y [3:2], Y=$flatten\soc.\spimemio.\spimemio.\xfer.$4\next_count[3:0] [3:2]
      New connections: $flatten\soc.\spimemio.\spimemio.\xfer.$4\next_count[3:0] [1:0] = \soc.spimemio.spimemio.xfer.count [1:0]
    Consolidated identical input bits for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13556:
      Old ports: A={ \soc.spimemio.spimemio.xfer.obuffer [5:0] 2'00 }, B={ \soc.spimemio.spimemio.xfer.obuffer [6:0] 1'0 \soc.spimemio.spimemio.xfer.obuffer [3:0] 4'0000 }, Y=\soc.spimemio.spimemio.xfer.next_obuffer
      New ports: A={ \soc.spimemio.spimemio.xfer.obuffer [5:0] 1'0 }, B={ \soc.spimemio.spimemio.xfer.obuffer [6:0] \soc.spimemio.spimemio.xfer.obuffer [3:0] 3'000 }, Y=\soc.spimemio.spimemio.xfer.next_obuffer [7:1]
      New connections: \soc.spimemio.spimemio.xfer.next_obuffer [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\sysctrl.\sysctrl.$procmux$11166:
      Old ports: A={ 2'00 \soc.sysctrl.sysctrl.irq_8_inputsrc \soc.sysctrl.sysctrl.irq_7_inputsrc }, B={ 3'000 \soc.sysctrl.sysctrl.trap_output_dest }, Y=$auto$wreduce.cc:454:run$18020 [3:0]
      New ports: A={ \soc.sysctrl.sysctrl.irq_8_inputsrc \soc.sysctrl.sysctrl.irq_7_inputsrc }, B={ 1'0 \soc.sysctrl.sysctrl.trap_output_dest }, Y=$auto$wreduce.cc:454:run$18020 [1:0]
      New connections: $auto$wreduce.cc:454:run$18020 [3:2] = 2'00
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$2977:
      Old ports: A=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976_Y, B={ 6'000000 \housekeeping.pll_trim [25:24] }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$2977_Y
      New ports: A=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976_Y [5:0], B={ 4'0000 \housekeeping.pll_trim [25:24] }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$2977_Y [5:0]
      New connections: $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$2977_Y [7:6] = 2'00
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9574:
      Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9572_Y, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9574_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9572_Y [3:0], B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9574_Y [3:0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9574_Y [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11190:
      Old ports: A=$auto$wreduce.cc:454:run$17974 [1:0], B={ 1'0 \soc.gpio_wb.gpio_ctrl.gpio_oeb }, Y=$auto$wreduce.cc:454:run$17975 [1:0]
      New ports: A=$auto$wreduce.cc:454:run$17974 [0], B=\soc.gpio_wb.gpio_ctrl.gpio_oeb, Y=$auto$wreduce.cc:454:run$17975 [0]
      New connections: $auto$wreduce.cc:454:run$17975 [1] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\simple_spi_master_inst.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:110$4725:
      Old ports: A=\soc.simple_spi_master_inst.simple_spi_master_reg_dat_do, B={ 16'0000000000000000 \soc.simple_spi_master_inst.spi_master.hkconn \soc.simple_spi_master_inst.spi_master.irqena \soc.simple_spi_master_inst.spi_master.enable \soc.simple_spi_master_inst.spi_master.stream \soc.simple_spi_master_inst.spi_master.mode \soc.simple_spi_master_inst.spi_master.invsck \soc.simple_spi_master_inst.spi_master.invcsb \soc.simple_spi_master_inst.spi_master.mlb \soc.simple_spi_master_inst.spi_master.prescaler }, Y=\soc.simple_spi_master_inst.wb_dat_o
      New ports: A={ \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8:0] }, B={ 1'0 \soc.simple_spi_master_inst.spi_master.hkconn \soc.simple_spi_master_inst.spi_master.irqena \soc.simple_spi_master_inst.spi_master.enable \soc.simple_spi_master_inst.spi_master.stream \soc.simple_spi_master_inst.spi_master.mode \soc.simple_spi_master_inst.spi_master.invsck \soc.simple_spi_master_inst.spi_master.invcsb \soc.simple_spi_master_inst.spi_master.mlb \soc.simple_spi_master_inst.spi_master.prescaler }, Y=\soc.simple_spi_master_inst.wb_dat_o [16:0]
      New connections: \soc.simple_spi_master_inst.wb_dat_o [31:17] = { \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] }
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$procmux$13860:
      Old ports: A={ 1'1 $auto$wreduce.cc:454:run$18016 [6:0] }, B={ 4'0000 \soc.spimemio.spimemio.config_dummy }, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13860_Y
      New ports: A={ 1'1 $auto$wreduce.cc:454:run$18016 [1] $auto$wreduce.cc:454:run$18016 [1] 1'1 $auto$wreduce.cc:454:run$18016 [1] 1'1 }, B={ 2'00 \soc.spimemio.spimemio.config_dummy }, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13860_Y [5:0]
      New connections: $flatten\soc.\spimemio.\spimemio.$procmux$13860_Y [7:6] = $flatten\soc.\spimemio.\spimemio.$procmux$13860_Y [5:4]
    Consolidated identical input bits for $mux cell $flatten\soc.\sysctrl.\sysctrl.$procmux$11169:
      Old ports: A=$auto$wreduce.cc:454:run$18020 [3:0], B={ 2'00 \soc.sysctrl.sysctrl.clk2_output_dest \soc.sysctrl.sysctrl.clk1_output_dest }, Y=$auto$wreduce.cc:454:run$18021 [3:0]
      New ports: A=$auto$wreduce.cc:454:run$18020 [1:0], B={ \soc.sysctrl.sysctrl.clk2_output_dest \soc.sysctrl.sysctrl.clk1_output_dest }, Y=$auto$wreduce.cc:454:run$18021 [1:0]
      New connections: $auto$wreduce.cc:454:run$18021 [3:2] = 2'00
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9576:
      Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9574_Y, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9576_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9574_Y [3:0], B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9576_Y [3:0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9576_Y [4] = 1'0
  Optimizing cells in module \mgmt_core.
Performed a total of 43 changes.

12.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 18 cells.

12.20.6. Executing OPT_SHARE pass.
    Found cells that share an operand and can be merged by moving the $mux $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12696 in front of them:
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12694
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12669

    Found cells that share an operand and can be merged by moving the $mux $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12723 in front of them:
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12721
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12711

    Found cells that share an operand and can be merged by moving the $mux $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$13009 in front of them:
        $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$13007
        $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12983

    Found cells that share an operand and can be merged by moving the $pmux $flatten\soc.\spimemio.\spimemio.$procmux$13746 in front of them:
        $flatten\soc.\spimemio.\spimemio.$procmux$13744
        $flatten\soc.\spimemio.\spimemio.$procmux$13768

12.20.7. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$opt_dff.cc:764:run$17150 ($dffe) from module mgmt_core (D = $auto$wreduce.cc:454:run$17971 [4:0], Q = \soc.cpu.picorv32_core.pcpi_mul.mul_counter [4:0], rval = 5'11110).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$17377 ($sdff) from module mgmt_core.

12.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 2 unused cells and 129 unused wires.


12.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.20.10. Rerunning OPT passes. (Maybe there is more to do..)

12.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9078:
      Old ports: A=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419_Y, B={ $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$7423_Y [31:1] $auto$alumacc.cc:501:replace_alu$18170 [0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9078_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419_Y [31:1], B=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$7423_Y [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9078_Y [31:1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9078_Y [0] = $auto$alumacc.cc:501:replace_alu$18170 [0]
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13746: { $auto$opt_reduce.cc:134:opt_mux$15196 $auto$opt_reduce.cc:134:opt_mux$18900 }
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9080:
      Old ports: A={ $flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$18170 [0] }, B=$flatten\soc.\cpu.\picorv32_core.$procmux$9078_Y, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9080_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], B=$flatten\soc.\cpu.\picorv32_core.$procmux$9078_Y [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9080_Y [31:1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9080_Y [0] = $auto$alumacc.cc:501:replace_alu$18170 [0]
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9086:
      Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9080_Y, B={ $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419_Y [31:1] $auto$alumacc.cc:501:replace_alu$18170 [0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9086_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9080_Y [31:1], B=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419_Y [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9086_Y [31:1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9086_Y [0] = $auto$alumacc.cc:501:replace_alu$18170 [0]
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9089:
      Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9086_Y, B={ $flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$18170 [0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9089_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9086_Y [31:1], B=$flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9089_Y [31:1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9089_Y [0] = $auto$alumacc.cc:501:replace_alu$18170 [0]
  Optimizing cells in module \mgmt_core.
Performed a total of 5 changes.

12.20.13. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.20.14. Executing OPT_SHARE pass.
    Found cells that share an operand and can be merged by moving the $mux $auto$opt_share.cc:241:merge_operators$18890 in front of them:
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:214$1531
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:262$1544

12.20.15. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[9]$18404 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[9]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[8]$18402 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[8]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[7]$18400 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[7]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[6]$18398 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[6]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[5]$18396 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[5]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[4]$18394 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[4]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[3]$18392 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[3]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[31]$18448 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[31]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[30]$18446 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[30]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[2]$18390 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[2]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[29]$18444 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[29]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[28]$18442 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[28]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[27]$18440 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[27]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[26]$18438 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[26]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[25]$18436 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[25]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[24]$18434 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[24]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[23]$18432 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[23]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[22]$18430 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[22]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[21]$18428 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[21]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[20]$18426 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[20]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[1]$18388 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[1]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[19]$18424 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[19]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[18]$18422 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[18]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[17]$18420 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[17]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[16]$18418 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[16]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[15]$18416 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[15]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[14]$18414 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[14]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[13]$18412 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[13]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[12]$18410 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[12]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[11]$18408 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[11]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[10]$18406 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[10]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[0]$18386 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[0]).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17268 ($dffe) from module mgmt_core.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$17268 ($dffe) from module mgmt_core.
Adding SRST signal on $auto$opt_dff.cc:764:run$17110 ($dffe) from module mgmt_core (D = \soc.gpio_wb.gpio_ctrl.gpio, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata [1], rval = 1'0).
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$16395 ($sdffe) from module mgmt_core.
Adding SRST signal on $auto$opt_dff.cc:764:run$16304 ($dffe) from module mgmt_core (D = \soc.spimemio.spimemio.din_data [0], Q = \soc.spimemio.spimemio.xfer.obuffer [0], rval = 1'0).
Adding SRST signal on $auto$opt_dff.cc:764:run$16229 ($dffe) from module mgmt_core (D = { \mprj2_vdd_pwrgood \mprj_vdd_pwrgood }, Q = \soc.sysctrl.sysctrl.iomem_rdata [3:2], rval = 2'00).

12.20.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 32 unused cells and 45 unused wires.


12.20.17. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.20.18. Rerunning OPT passes. (Maybe there is more to do..)

12.20.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.20.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $auto$opt_share.cc:241:merge_operators$18902:
      Old ports: A=2, B=32'11111111111111111111111111111111, Y=$auto$rtlil.cc:2218:Mux$18903
      New ports: A=1'0, B=1'1, Y=$auto$rtlil.cc:2218:Mux$18903 [0]
      New connections: $auto$rtlil.cc:2218:Mux$18903 [31:1] = { $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] 1'1 }
  Optimizing cells in module \mgmt_core.
Performed a total of 1 changes.

12.20.21. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.20.22. Executing OPT_SHARE pass.

12.20.23. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17588 ($sdffe) from module mgmt_core.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$17588 ($sdffe) from module mgmt_core.
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$16240 ($sdffe) from module mgmt_core.

12.20.24. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 1 unused wires.


12.20.25. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.20.26. Rerunning OPT passes. (Maybe there is more to do..)

12.20.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.20.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$procmux$13863:
      Old ports: A={ \soc.cpu.wbm_adr_o [7:2] 2'00 }, B=8'00000000, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13863_Y
      New ports: A=\soc.cpu.wbm_adr_o [7:2], B=6'000000, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13863_Y [7:2]
      New connections: $flatten\soc.\spimemio.\spimemio.$procmux$13863_Y [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:388$1227:
      Old ports: A={ \soc.cpu.wbm_adr_o [23:2] 2'00 }, B={ $auto$wreduce.cc:454:run$18014 [23:2] 2'xx }, Y=$auto$wreduce.cc:454:run$18015 [23:0]
      New ports: A={ \soc.cpu.wbm_adr_o [23:2] 1'0 }, B={ $auto$wreduce.cc:454:run$18014 [23:2] 1'x }, Y={ $auto$wreduce.cc:454:run$18015 [23:2] $auto$wreduce.cc:454:run$18015 [0] }
      New connections: $auto$wreduce.cc:454:run$18015 [1] = $auto$wreduce.cc:454:run$18015 [0]
  Optimizing cells in module \mgmt_core.
Performed a total of 2 changes.

12.20.29. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.20.30. Executing OPT_SHARE pass.

12.20.31. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 3 on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14959 ($dff) from module mgmt_core.

12.20.32. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 1 unused wires.


12.20.33. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.20.34. Rerunning OPT passes. (Maybe there is more to do..)

12.20.35. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.


12.20.36. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

12.20.37. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.20.38. Executing OPT_SHARE pass.

12.20.39. Executing OPT_DFF pass (perform DFF optimizations).

12.20.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

12.20.41. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

12.20.42. Finished OPT passes. (There is nothing left to do.)

12.21. Executing TECHMAP pass (map to technology primitives).

12.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

12.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $ne.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $adff.
Using extmapper simplemap for cells of type $adffe.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=3\Y_WIDTH=4 for cells of type $alu.
Using extmapper simplemap for cells of type $dff.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=0\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper maccmap for cells of type $macc.
  add \soc.cpu.picorv32_core.pcpi_mul.rd [31:28] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [31:28] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [28] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
Using template $paramod\_90_pmux\WIDTH=13\S_WIDTH=37 for cells of type $pmux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=1\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=63\Y_WIDTH=63 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=7\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=7 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=0\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu.
  add \soc.cpu.picorv32_core.pcpi_mul.rd [15:12] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [15:12] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [12] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \soc.cpu.picorv32_core.pcpi_mul.rd [27:24] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [27:24] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [24] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \soc.cpu.picorv32_core.pcpi_mul.rd [3:0] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [3:0] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rd [23:20] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [23:20] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [20] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \soc.cpu.picorv32_core.pcpi_mul.rd [19:16] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [19:16] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [16] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \soc.cpu.picorv32_core.pcpi_mul.rd [11:8] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [11:8] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [8] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \soc.cpu.picorv32_core.pcpi_mul.rd [7:4] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [7:4] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [4] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=22\Y_WIDTH=23 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux.
Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux.
Using extmapper simplemap for cells of type $dffsre.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux.
Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$88abf4b792300efa328894e6936be740fdc22f6d\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$887c9fe2c55be14c90171bd2ff359c086a0858d7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=6 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=8 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=31 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=3 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=64 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=4 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=23 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=5 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=63 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=30 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=6 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=7 for cells of type $lcu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
No more expansions possible.


12.22. Executing OPT pass (performing simple optimizations).

12.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 3849 cells.

12.22.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39409 ($_DFFE_PP_) from module mgmt_core (D = 1'x, Q = \soc.spimemio.spimemio.rd_addr [0], rval = 1'0).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$66014 ($_SDFFCE_PN0P_) from module mgmt_core.

12.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 972 unused cells and 9378 unused wires.


12.22.5. Rerunning OPT passes. (Removed registers in this run.)

12.22.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.22.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

12.22.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$38143 ($_SDFFE_PP0P_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$7999.B_AND_S [32], Q = \soc.cpu.picorv32_core.reg_pc [0]).
Adding EN signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$20331 ($_SDFFE_PP0P_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13536.Y_B [0], Q = \soc.spimemio.spimemio.xfer.count [0]).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35611 ($_SDFF_PP0_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13746.Y_B, Q = \soc.spimemio.spimemio.din_valid, rval = 1'0).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34763 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [30], Q = \soc.cpu.picorv32_core.irq_pending [31]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34762 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [29], Q = \soc.cpu.picorv32_core.irq_pending [30]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34761 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [28], Q = \soc.cpu.picorv32_core.irq_pending [29]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34760 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [27], Q = \soc.cpu.picorv32_core.irq_pending [28]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34759 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [26], Q = \soc.cpu.picorv32_core.irq_pending [27]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34758 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [25], Q = \soc.cpu.picorv32_core.irq_pending [26]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34757 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [24], Q = \soc.cpu.picorv32_core.irq_pending [25]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34756 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [23], Q = \soc.cpu.picorv32_core.irq_pending [24]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34755 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [22], Q = \soc.cpu.picorv32_core.irq_pending [23]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34754 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [21], Q = \soc.cpu.picorv32_core.irq_pending [22]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34753 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [20], Q = \soc.cpu.picorv32_core.irq_pending [21]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34752 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [19], Q = \soc.cpu.picorv32_core.irq_pending [20]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34751 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [18], Q = \soc.cpu.picorv32_core.irq_pending [19]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34750 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [17], Q = \soc.cpu.picorv32_core.irq_pending [18]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34749 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [16], Q = \soc.cpu.picorv32_core.irq_pending [17]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34748 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [15], Q = \soc.cpu.picorv32_core.irq_pending [16]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34747 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [14], Q = \soc.cpu.picorv32_core.irq_pending [15]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34746 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [13], Q = \soc.cpu.picorv32_core.irq_pending [14]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34745 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [12], Q = \soc.cpu.picorv32_core.irq_pending [13]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34744 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [11], Q = \soc.cpu.picorv32_core.irq_pending [12]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34743 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [7], Q = \soc.cpu.picorv32_core.irq_pending [8]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34742 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [4], Q = \soc.cpu.picorv32_core.irq_pending [5]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34741 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [3], Q = \soc.cpu.picorv32_core.irq_pending [3]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34740 ($_SDFF_PP0_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$7630.Y, Q = \soc.cpu.picorv32_core.irq_pending [1]).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37838 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [31], Q = \soc.cpu.picorv32_core.decoded_imm [31], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37837 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [30], Q = \soc.cpu.picorv32_core.decoded_imm [30], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37836 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [29], Q = \soc.cpu.picorv32_core.decoded_imm [29], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37835 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [28], Q = \soc.cpu.picorv32_core.decoded_imm [28], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37834 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [27], Q = \soc.cpu.picorv32_core.decoded_imm [27], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37833 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [26], Q = \soc.cpu.picorv32_core.decoded_imm [26], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37832 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [25], Q = \soc.cpu.picorv32_core.decoded_imm [25], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37831 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [24], Q = \soc.cpu.picorv32_core.decoded_imm [24], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37830 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [23], Q = \soc.cpu.picorv32_core.decoded_imm [23], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37829 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [22], Q = \soc.cpu.picorv32_core.decoded_imm [22], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37828 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [21], Q = \soc.cpu.picorv32_core.decoded_imm [21], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37827 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [20], Q = \soc.cpu.picorv32_core.decoded_imm [20], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37826 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [19], Q = \soc.cpu.picorv32_core.decoded_imm [19], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37825 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [18], Q = \soc.cpu.picorv32_core.decoded_imm [18], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37824 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [17], Q = \soc.cpu.picorv32_core.decoded_imm [17], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37823 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [16], Q = \soc.cpu.picorv32_core.decoded_imm [16], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37822 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [15], Q = \soc.cpu.picorv32_core.decoded_imm [15], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37821 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [14], Q = \soc.cpu.picorv32_core.decoded_imm [14], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37820 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [13], Q = \soc.cpu.picorv32_core.decoded_imm [13], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37819 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [12], Q = \soc.cpu.picorv32_core.decoded_imm [12], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37818 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [11], Q = \soc.cpu.picorv32_core.decoded_imm [11], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37817 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [10], Q = \soc.cpu.picorv32_core.decoded_imm [10], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37816 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [9], Q = \soc.cpu.picorv32_core.decoded_imm [9], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37815 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [8], Q = \soc.cpu.picorv32_core.decoded_imm [8], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37814 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [7], Q = \soc.cpu.picorv32_core.decoded_imm [7], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37813 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [6], Q = \soc.cpu.picorv32_core.decoded_imm [6], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37812 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [5], Q = \soc.cpu.picorv32_core.decoded_imm [5], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37811 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [4], Q = \soc.cpu.picorv32_core.decoded_imm [4], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37810 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [3], Q = \soc.cpu.picorv32_core.decoded_imm [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37809 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [2], Q = \soc.cpu.picorv32_core.decoded_imm [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37808 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [1], Q = \soc.cpu.picorv32_core.decoded_imm [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19989 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [7], Q = \soc.spimemio.spimemio.din_data [7], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19988 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [6], Q = \soc.spimemio.spimemio.din_data [6], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19987 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [5], Q = \soc.spimemio.spimemio.din_data [5], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19986 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [4], Q = \soc.spimemio.spimemio.din_data [4], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19985 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [3], Q = \soc.spimemio.spimemio.din_data [3], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19984 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [2], Q = \soc.spimemio.spimemio.din_data [2], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19983 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [1], Q = \soc.spimemio.spimemio.din_data [1], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19982 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [0], Q = \soc.spimemio.spimemio.din_data [0], rval = 1'1).

12.22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 88 unused cells and 30 unused wires.


12.22.10. Rerunning OPT passes. (Removed registers in this run.)

12.22.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.22.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 44 cells.

12.22.13. Executing OPT_DFF pass (perform DFF optimizations).

12.22.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 45 unused wires.


12.22.15. Finished fast OPT passes.

12.23. Executing ABC pass (technology mapping using ABC).

12.23.1. Extracting gate netlist of module `\mgmt_core' to `/input.blif'..
Extracted 20080 gates and 24166 wires to a netlist network with 4083 inputs and 1936 outputs.

12.23.1.1. Executing ABC.
Running ABC command: /yosys-abc -s -f /abc.script 2>&1
ABC: ABC command line: "source /abc.script".
ABC: 
ABC: + read_blif /input.blif 
ABC: + read_library /stdcells.genlib 
ABC: Entered genlib library with 13 gates from file "/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif /output.blif 

12.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:      971
ABC RESULTS:            ANDNOT cells:     4247
ABC RESULTS:               MUX cells:     5751
ABC RESULTS:              NAND cells:      771
ABC RESULTS:               NOR cells:      824
ABC RESULTS:               NOT cells:     1114
ABC RESULTS:                OR cells:     4001
ABC RESULTS:             ORNOT cells:      558
ABC RESULTS:              XNOR cells:      282
ABC RESULTS:               XOR cells:     1160
ABC RESULTS:        internal signals:    18147
ABC RESULTS:           input signals:     4083
ABC RESULTS:          output signals:     1936
Removing temp directory.

12.24. Executing OPT pass (performing simple optimizations).

12.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.


12.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.

Removed a total of 76 cells.

12.24.3. Executing OPT_DFF pass (perform DFF optimizations).

12.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 27 unused cells and 11570 unused wires.


12.24.5. Finished fast OPT passes.

12.25. Executing HIERARCHY pass (managing design hierarchy).

12.25.1. Analyzing design hierarchy..
Top module:  \mgmt_core

12.25.2. Analyzing design hierarchy..
Top module:  \mgmt_core
Removed 0 unused modules.

12.26. Printing statistics.

=== mgmt_core ===

   Number of wires:              20026
   Number of wire bits:          33346
   Number of public wires:        1160
   Number of public wire bits:   13867
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              23444
     $_ANDNOT_                    4240
     $_AND_                        971
     $_DFFE_NN0P_                   12
     $_DFFE_NN1P_                   32
     $_DFFE_NP0N_                    3
     $_DFFE_NP0P_                   26
     $_DFFE_PN0N_                    7
     $_DFFE_PN0P_                  182
     $_DFFE_PN1N_                    5
     $_DFFE_PN1P_                   23
     $_DFFE_PN_                      7
     $_DFFE_PP0P_                    9
     $_DFFE_PP_                   1654
     $_DFFSRE_NPPP_                 12
     $_DFFSRE_PPPP_                  6
     $_DFF_NP0_                      4
     $_DFF_NP1_                      1
     $_DFF_N_                        2
     $_DFF_PN0_                     25
     $_DFF_PN1_                      8
     $_DFF_PP1_                      1
     $_DFF_P_                      152
     $_MUX_                       5744
     $_NAND_                       767
     $_NOR_                        773
     $_NOT_                       1087
     $_ORNOT_                      556
     $_OR_                        3998
     $_SDFFCE_PN0P_                 42
     $_SDFFCE_PN1P_                  8
     $_SDFFCE_PP0P_                177
     $_SDFFCE_PP1P_                  5
     $_SDFFE_PN0N_                   1
     $_SDFFE_PN0P_                 916
     $_SDFFE_PN1N_                   4
     $_SDFFE_PN1P_                 285
     $_SDFFE_PP0P_                  20
     $_SDFFE_PP1N_                   2
     $_SDFFE_PP1P_                  11
     $_SDFF_PN0_                   181
     $_SDFF_PN1_                     3
     $_SDFF_PP0_                    38
     $_SDFF_PP1_                     2
     $_XNOR_                       281
     $_XOR_                       1159
     DFFRAM                          1
     digital_pll                     1

12.27. Executing CHECK pass (checking for obvious problems).
checking module mgmt_core..
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.spi_master.isdo:
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$19703 ($_DFFE_PN0P_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22058 ($_SDFFE_PN0P_)
Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [9]:
    port Y[0] of cell $abc$66242$auto$blifparse.cc:377:parse_blif$85027 ($_ANDNOT_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22065 ($_SDFFE_PN0P_)
Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [10]:
    port Y[0] of cell $abc$66242$auto$blifparse.cc:377:parse_blif$85026 ($_AND_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22066 ($_SDFFE_PN0P_)
Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [8]:
    port Y[0] of cell $abc$66242$auto$blifparse.cc:377:parse_blif$83360 ($_NOT_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22064 ($_SDFFE_PN0P_)
Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [3]:
    port Y[0] of cell $abc$66242$auto$blifparse.cc:377:parse_blif$70033 ($_XOR_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22059 ($_SDFFE_PN0P_)
Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [4]:
    port Y[0] of cell $abc$66242$auto$blifparse.cc:377:parse_blif$70029 ($_NOT_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22060 ($_SDFFE_PN0P_)
found and reported 6 problems.

13. Executing SHARE pass (SAT-based resource sharing).

14. Executing OPT pass (performing simple optimizations).

14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

14.6. Executing OPT_DFF pass (perform DFF optimizations).

14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

14.9. Finished OPT passes. (There is nothing left to do.)

15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 665 unused wires.


16. Printing statistics.

=== mgmt_core ===

   Number of wires:              19361
   Number of wire bits:          24892
   Number of public wires:         495
   Number of public wire bits:    5413
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              23444
     $_ANDNOT_                    4240
     $_AND_                        971
     $_DFFE_NN0P_                   12
     $_DFFE_NN1P_                   32
     $_DFFE_NP0N_                    3
     $_DFFE_NP0P_                   26
     $_DFFE_PN0N_                    7
     $_DFFE_PN0P_                  182
     $_DFFE_PN1N_                    5
     $_DFFE_PN1P_                   23
     $_DFFE_PN_                      7
     $_DFFE_PP0P_                    9
     $_DFFE_PP_                   1654
     $_DFFSRE_NPPP_                 12
     $_DFFSRE_PPPP_                  6
     $_DFF_NP0_                      4
     $_DFF_NP1_                      1
     $_DFF_N_                        2
     $_DFF_PN0_                     25
     $_DFF_PN1_                      8
     $_DFF_PP1_                      1
     $_DFF_P_                      152
     $_MUX_                       5744
     $_NAND_                       767
     $_NOR_                        773
     $_NOT_                       1087
     $_ORNOT_                      556
     $_OR_                        3998
     $_SDFFCE_PN0P_                 42
     $_SDFFCE_PN1P_                  8
     $_SDFFCE_PP0P_                177
     $_SDFFCE_PP1P_                  5
     $_SDFFE_PN0N_                   1
     $_SDFFE_PN0P_                 916
     $_SDFFE_PN1N_                   4
     $_SDFFE_PN1P_                 285
     $_SDFFE_PP0P_                  20
     $_SDFFE_PP1N_                   2
     $_SDFFE_PP1P_                  11
     $_SDFF_PN0_                   181
     $_SDFF_PN1_                     3
     $_SDFF_PP0_                    38
     $_SDFF_PP1_                     2
     $_XNOR_                       281
     $_XOR_                       1159
     DFFRAM                          1
     digital_pll                     1

17. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

17.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\mgmt_core':
  mapped 18 $_DFFSR_NNN_ cells to \sky130_fd_sc_hd__dfbbn_2 cells.
  mapped 268 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells.
  mapped 70 $_DFF_PN1_ cells to \sky130_fd_sc_hd__dfstp_4 cells.
  mapped 3510 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_4 cells.

18. Printing statistics.
[INFO]: ABC: WireLoad : S_2

=== mgmt_core ===

   Number of wires:              24695
   Number of wire bits:          30226
   Number of public wires:         495
   Number of public wire bits:    5413
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              28754
     $_ANDNOT_                    4240
     $_AND_                        971
     $_MUX_                      10888
     $_NAND_                       767
     $_NOR_                        773
     $_NOT_                       1253
     $_ORNOT_                      556
     $_OR_                        3998
     $_XNOR_                       281
     $_XOR_                       1159
     DFFRAM                          1
     digital_pll                     1
     sky130_fd_sc_hd__dfbbn_2       18
     sky130_fd_sc_hd__dfrtp_4      268
     sky130_fd_sc_hd__dfstp_4       70
     sky130_fd_sc_hd__dfxtp_4     3510

19. Executing ABC pass (technology mapping using ABC).

19.1. Extracting gate netlist of module `\mgmt_core' to `/tmp/yosys-abc-PAFRQ6/input.blif'..
Extracted 24886 gates and 29115 wires to a netlist network with 4227 inputs and 4046 outputs.

19.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-PAFRQ6/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-PAFRQ6/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-PAFRQ6/input.blif 
ABC: + read_lib -w /project/openlane/mgmt_core/runs/mgmt_core/tmp/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.05 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/mgmt_core/runs/mgmt_core/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.08 sec
ABC: Memory =    1.92 MB. Time =     0.08 sec
ABC: + read_constr -v /project/openlane/mgmt_core/runs/mgmt_core/tmp/synthesis/yosys.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
ABC: Setting output load to be 17.650000.
ABC: + read_constr /project/openlane/mgmt_core/runs/mgmt_core/tmp/synthesis/yosys.sdc 
ABC: + fx 
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 50000 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 50000 
ABC: + buffer -N 4 -S 5000.0 
ABC: Node 9771 has dup fanin 9768.
ABC: Node 9771 has dup fanin 9768.
ABC: Node 9795 has dup fanin 209.
ABC: Node 9795 has dup fanin 209.
ABC: Node 9801 has dup fanin 9800.
ABC: Node 9801 has dup fanin 9800.
ABC: Node 9802 has dup fanin 9800.
ABC: Node 9802 has dup fanin 9800.
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ABC: Node 9816 has dup fanin 9810.
ABC: Node 9817 has dup fanin 9791.
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ABC: Node 9830 has dup fanin 9822.
ABC: Node 9830 has dup fanin 9822.
ABC: Node 9860 has dup fanin 9859.
ABC: Node 9860 has dup fanin 9859.
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ABC: Node 9867 has dup fanin 9858.
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ABC: Node 9925 has dup fanin 9924.
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ABC: Node 9929 has dup fanin 9924.
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ABC: Node 9930 has dup fanin 9924.
ABC: Node 9932 has dup fanin 9923.
ABC: Node 9932 has dup fanin 9923.
ABC: Node 9987 has dup fanin 9985.
ABC: Node 9987 has dup fanin 9985.
ABC: Node 10078 has dup fanin 691.
ABC: Node 10078 has dup fanin 1723.
ABC: Node 10078 has dup fanin 691.
ABC: Node 10078 has dup fanin 1723.
ABC: Node 10102 has dup fanin 10100.
ABC: Node 10102 has dup fanin 10101.
ABC: Node 10102 has dup fanin 10100.
ABC: Node 10102 has dup fanin 10101.
ABC: Node 10121 has dup fanin 10119.
ABC: Node 10121 has dup fanin 10120.
ABC: Node 10121 has dup fanin 10119.
ABC: Node 10121 has dup fanin 10120.
ABC: Node 10146 has dup fanin 10145.
ABC: Node 10146 has dup fanin 10145.
ABC: Node 10152 has dup fanin 10151.
ABC: Node 10152 has dup fanin 10151.
ABC: Node 10165 has dup fanin 10163.
ABC: Node 10165 has dup fanin 10164.
ABC: Node 10165 has dup fanin 10163.
ABC: Node 10165 has dup fanin 10164.
ABC: Node 10200 has dup fanin 10186.
ABC: Node 10200 has dup fanin 10186.
ABC: Node 10405 has dup fanin 8341.
ABC: Node 10405 has dup fanin 281.
ABC: Node 10405 has dup fanin 8341.
ABC: Node 10405 has dup fanin 281.
ABC: Node 10411 has dup fanin 8361.
ABC: Node 10411 has dup fanin 301.
ABC: Node 10411 has dup fanin 8361.
ABC: Node 10411 has dup fanin 301.
ABC: Node 10433 has dup fanin 263.
ABC: Node 10433 has dup fanin 8387.
ABC: Node 10433 has dup fanin 263.
ABC: Node 10433 has dup fanin 8387.
ABC: Node 10439 has dup fanin 8340.
ABC: Node 10439 has dup fanin 280.
ABC: Node 10439 has dup fanin 8340.
ABC: Node 10439 has dup fanin 280.
ABC: Node 10489 has dup fanin 8372.
ABC: Node 10489 has dup fanin 10488.
ABC: Node 10489 has dup fanin 8372.
ABC: Node 10489 has dup fanin 10488.
ABC: Node 10492 has dup fanin 282.
ABC: Node 10492 has dup fanin 10491.
ABC: Node 10492 has dup fanin 282.
ABC: Node 10492 has dup fanin 10491.
ABC: Node 10495 has dup fanin 284.
ABC: Node 10495 has dup fanin 10494.
ABC: Node 10495 has dup fanin 284.
ABC: Node 10495 has dup fanin 10494.
ABC: Node 10504 has dup fanin 10428.
ABC: Node 10504 has dup fanin 10477.
ABC: Node 10504 has dup fanin 10428.
ABC: Node 10504 has dup fanin 10477.
ABC: Node 10522 has dup fanin 10411.
ABC: Node 10522 has dup fanin 10465.
ABC: Node 10522 has dup fanin 10411.
ABC: Node 10522 has dup fanin 10465.
ABC: Node 10529 has dup fanin 710.
ABC: Node 10529 has dup fanin 10528.
ABC: Node 10529 has dup fanin 710.
ABC: Node 10529 has dup fanin 10528.
ABC: Node 10552 has dup fanin 300.
ABC: Node 10552 has dup fanin 10551.
ABC: Node 10552 has dup fanin 300.
ABC: Node 10552 has dup fanin 10551.
ABC: Node 10572 has dup fanin 10405.
ABC: Node 10572 has dup fanin 10485.
ABC: Node 10572 has dup fanin 10405.
ABC: Node 10572 has dup fanin 10485.
ABC: Node 10629 has dup fanin 10598.
ABC: Node 10629 has dup fanin 10598.
ABC: Node 10643 has dup fanin 10598.
ABC: Node 10643 has dup fanin 10598.
ABC: Node 10644 has dup fanin 250.
ABC: Node 10644 has dup fanin 10630.
ABC: Node 10644 has dup fanin 250.
ABC: Node 10644 has dup fanin 10630.
ABC: Node 10653 has dup fanin 10598.
ABC: Node 10653 has dup fanin 10598.
ABC: Node 10665 has dup fanin 10598.
ABC: Node 10665 has dup fanin 10598.
ABC: Node 10678 has dup fanin 10598.
ABC: Node 10678 has dup fanin 10598.
ABC: Node 10679 has dup fanin 253.
ABC: Node 10679 has dup fanin 10668.
ABC: Node 10679 has dup fanin 253.
ABC: Node 10679 has dup fanin 10668.
ABC: Node 10689 has dup fanin 10598.
ABC: Node 10689 has dup fanin 10598.
ABC: Node 10700 has dup fanin 10598.
ABC: Node 10700 has dup fanin 10598.
ABC: Node 10712 has dup fanin 10598.
ABC: Node 10712 has dup fanin 10598.
ABC: Node 10726 has dup fanin 10713.
ABC: Node 10726 has dup fanin 10713.
ABC: Node 10730 has dup fanin 257.
ABC: Node 10730 has dup fanin 10718.
ABC: Node 10730 has dup fanin 257.
ABC: Node 10730 has dup fanin 10718.
ABC: Node 10737 has dup fanin 10713.
ABC: Node 10737 has dup fanin 10713.
ABC: Node 10748 has dup fanin 10713.
ABC: Node 10748 has dup fanin 10713.
ABC: Node 10759 has dup fanin 10713.
ABC: Node 10759 has dup fanin 10713.
ABC: Node 10770 has dup fanin 10713.
ABC: Node 10770 has dup fanin 10713.
ABC: Node 10783 has dup fanin 10713.
ABC: Node 10783 has dup fanin 10713.
ABC: Node 10794 has dup fanin 10713.
ABC: Node 10794 has dup fanin 10713.
ABC: Node 10805 has dup fanin 10713.
ABC: Node 10805 has dup fanin 10713.
ABC: Node 10819 has dup fanin 10806.
ABC: Node 10819 has dup fanin 10806.
ABC: Node 10823 has dup fanin 265.
ABC: Node 10823 has dup fanin 10807.
ABC: Node 10823 has dup fanin 265.
ABC: Node 10823 has dup fanin 10807.
ABC: Node 10831 has dup fanin 10806.
ABC: Node 10831 has dup fanin 10806.
ABC: Node 10842 has dup fanin 10806.
ABC: Node 10842 has dup fanin 10806.
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ABC: Node 10911 has dup fanin 10899.
ABC: Node 10911 has dup fanin 10899.
ABC: Node 10921 has dup fanin 10899.
ABC: Node 10921 has dup fanin 10899.
ABC: Node 10930 has dup fanin 10899.
ABC: Node 10930 has dup fanin 10899.
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ABC: Node 10941 has dup fanin 10899.
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ABC: Node 10991 has dup fanin 10987.
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ABC: Node 10992 has dup fanin 10987.
ABC: Node 10993 has dup fanin 10987.
ABC: Node 10993 has dup fanin 10987.
ABC: Node 10994 has dup fanin 10987.
ABC: Node 10994 has dup fanin 10987.
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ABC: Node 10995 has dup fanin 10987.
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ABC: Node 11000 has dup fanin 10996.
ABC: Node 11001 has dup fanin 10996.
ABC: Node 11001 has dup fanin 10996.
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ABC: Node 11002 has dup fanin 10996.
ABC: Node 11003 has dup fanin 10996.
ABC: Node 11003 has dup fanin 10996.
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ABC: Node 11011 has dup fanin 11005.
ABC: Node 11012 has dup fanin 11005.
ABC: Node 11012 has dup fanin 11005.
ABC: Node 11013 has dup fanin 11005.
ABC: Node 11013 has dup fanin 11005.
ABC: Node 11061 has dup fanin 319.
ABC: Node 11061 has dup fanin 8667.
ABC: Node 11061 has dup fanin 319.
ABC: Node 11061 has dup fanin 8667.
ABC: Node 11181 has dup fanin 11083.
ABC: Node 11181 has dup fanin 11083.
ABC: Node 11201 has dup fanin 11083.
ABC: Node 11201 has dup fanin 11083.
ABC: Node 11295 has dup fanin 733.
ABC: Node 11295 has dup fanin 733.
ABC: Node 11672 has dup fanin 9055.
ABC: Node 11672 has dup fanin 11470.
ABC: Node 11672 has dup fanin 9055.
ABC: Node 11672 has dup fanin 11470.
ABC: Node 11676 has dup fanin 9055.
ABC: Node 11676 has dup fanin 11500.
ABC: Node 11676 has dup fanin 9055.
ABC: Node 11676 has dup fanin 11500.
ABC: Node 11684 has dup fanin 9057.
ABC: Node 11684 has dup fanin 11531.
ABC: Node 11684 has dup fanin 9057.
ABC: Node 11684 has dup fanin 11531.
ABC: Node 11707 has dup fanin 9069.
ABC: Node 11707 has dup fanin 11625.
ABC: Node 11707 has dup fanin 9069.
ABC: Node 11707 has dup fanin 11625.
ABC: Node 11714 has dup fanin 9073.
ABC: Node 11714 has dup fanin 11655.
ABC: Node 11714 has dup fanin 9073.
ABC: Node 11714 has dup fanin 11655.
ABC: Node 11857 has dup fanin 2067.
ABC: Node 11857 has dup fanin 11440.
ABC: Node 11857 has dup fanin 2067.
ABC: Node 11857 has dup fanin 11440.
ABC: Node 11908 has dup fanin 11675.
ABC: Node 11908 has dup fanin 11759.
ABC: Node 11908 has dup fanin 11675.
ABC: Node 11908 has dup fanin 11759.
ABC: Node 11944 has dup fanin 11679.
ABC: Node 11944 has dup fanin 11747.
ABC: Node 11944 has dup fanin 11679.
ABC: Node 11944 has dup fanin 11747.
ABC: Node 12291 has dup fanin 12151.
ABC: Node 12291 has dup fanin 12151.
ABC: Node 12318 has dup fanin 12151.
ABC: Node 12318 has dup fanin 12151.
ABC: Node 12323 has dup fanin 12151.
ABC: Node 12323 has dup fanin 12151.
ABC: Node 12328 has dup fanin 12151.
ABC: Node 12328 has dup fanin 12151.
ABC: Node 12341 has dup fanin 8502.
ABC: Node 12341 has dup fanin 12340.
ABC: Node 12341 has dup fanin 8502.
ABC: Node 12341 has dup fanin 12340.
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ABC: Node 22194 has dup fanin 22022.
ABC: Node 22194 has dup fanin 22022.
ABC: Node 22200 has dup fanin 22022.
ABC: Node 22200 has dup fanin 22022.
ABC: Node 22206 has dup fanin 22022.
ABC: Node 22206 has dup fanin 22022.
ABC: Node 22212 has dup fanin 22022.
ABC: Node 22212 has dup fanin 22022.
ABC: Node 22218 has dup fanin 22022.
ABC: Node 22218 has dup fanin 22022.
ABC: Node 22224 has dup fanin 22022.
ABC: Node 22224 has dup fanin 22022.
ABC: Node 22230 has dup fanin 22022.
ABC: Node 22230 has dup fanin 22022.
ABC: Node 22236 has dup fanin 22022.
ABC: Node 22236 has dup fanin 22022.
ABC: Node 22241 has dup fanin 22022.
ABC: Node 22241 has dup fanin 22022.
ABC: Node 22248 has dup fanin 22022.
ABC: Node 22248 has dup fanin 22022.
ABC: Node 22250 has dup fanin 22249.
ABC: Node 22250 has dup fanin 22249.
ABC: Node 22251 has dup fanin 22249.
ABC: Node 22251 has dup fanin 22249.
ABC: Node 22252 has dup fanin 22249.
ABC: Node 22252 has dup fanin 22249.
ABC: Node 22253 has dup fanin 22249.
ABC: Node 22253 has dup fanin 22249.
ABC: Node 22254 has dup fanin 22249.
ABC: Node 22254 has dup fanin 22249.
ABC: Node 22255 has dup fanin 22249.
ABC: Node 22255 has dup fanin 22249.
ABC: Node 22256 has dup fanin 22249.
ABC: Node 22256 has dup fanin 22249.
ABC: Node 22257 has dup fanin 22249.
ABC: Node 22257 has dup fanin 22249.
ABC: Node 22258 has dup fanin 22249.
ABC: Node 22258 has dup fanin 22249.
ABC: Node 22259 has dup fanin 22249.
ABC: Node 22259 has dup fanin 22249.
ABC: Node 22260 has dup fanin 22249.
ABC: Node 22260 has dup fanin 22249.
ABC: Node 22261 has dup fanin 22249.
ABC: Node 22261 has dup fanin 22249.
ABC: Node 22262 has dup fanin 22249.
ABC: Node 22262 has dup fanin 22249.
ABC: Node 22263 has dup fanin 22249.
ABC: Node 22263 has dup fanin 22249.
ABC: Node 22264 has dup fanin 22249.
ABC: Node 22264 has dup fanin 22249.
ABC: Node 22265 has dup fanin 22249.
ABC: Node 22265 has dup fanin 22249.
ABC: Node 22266 has dup fanin 22249.
ABC: Node 22266 has dup fanin 22249.
ABC: Node 22267 has dup fanin 22249.
ABC: Node 22267 has dup fanin 22249.
ABC: Node 22268 has dup fanin 22249.
ABC: Node 22268 has dup fanin 22249.
ABC: Node 22269 has dup fanin 22249.
ABC: Node 22269 has dup fanin 22249.
ABC: Node 22270 has dup fanin 22249.
ABC: Node 22270 has dup fanin 22249.
ABC: Node 22271 has dup fanin 22249.
ABC: Node 22271 has dup fanin 22249.
ABC: Node 22272 has dup fanin 22249.
ABC: Node 22272 has dup fanin 22249.
ABC: Node 22273 has dup fanin 22249.
ABC: Node 22273 has dup fanin 22249.
ABC: Node 22274 has dup fanin 22249.
ABC: Node 22274 has dup fanin 22249.
ABC: Node 22275 has dup fanin 22249.
ABC: Node 22275 has dup fanin 22249.
ABC: Node 22276 has dup fanin 22249.
ABC: Node 22276 has dup fanin 22249.
ABC: Node 22277 has dup fanin 22249.
ABC: Node 22277 has dup fanin 22249.
ABC: Node 22278 has dup fanin 22249.
ABC: Node 22278 has dup fanin 22249.
ABC: Node 22279 has dup fanin 22249.
ABC: Node 22279 has dup fanin 22249.
ABC: Node 22280 has dup fanin 22249.
ABC: Node 22280 has dup fanin 22249.
ABC: Node 22281 has dup fanin 22249.
ABC: Node 22281 has dup fanin 22249.
ABC: Node 22283 has dup fanin 22282.
ABC: Node 22283 has dup fanin 22282.
ABC: Node 22284 has dup fanin 22282.
ABC: Node 22284 has dup fanin 22282.
ABC: Node 22285 has dup fanin 22282.
ABC: Node 22285 has dup fanin 22282.
ABC: Node 22286 has dup fanin 22282.
ABC: Node 22286 has dup fanin 22282.
ABC: Node 22287 has dup fanin 22282.
ABC: Node 22287 has dup fanin 22282.
ABC: Node 22288 has dup fanin 22282.
ABC: Node 22288 has dup fanin 22282.
ABC: Node 22289 has dup fanin 22282.
ABC: Node 22289 has dup fanin 22282.
ABC: Node 22290 has dup fanin 22282.
ABC: Node 22290 has dup fanin 22282.
ABC: Node 22291 has dup fanin 22282.
ABC: Node 22291 has dup fanin 22282.
ABC: Node 22292 has dup fanin 22282.
ABC: Node 22292 has dup fanin 22282.
ABC: Node 22293 has dup fanin 22282.
ABC: Node 22293 has dup fanin 22282.
ABC: Node 22294 has dup fanin 22282.
ABC: Node 22294 has dup fanin 22282.
ABC: Node 22295 has dup fanin 22282.
ABC: Node 22295 has dup fanin 22282.
ABC: Node 22296 has dup fanin 22282.
ABC: Node 22296 has dup fanin 22282.
ABC: Node 22297 has dup fanin 22282.
ABC: Node 22297 has dup fanin 22282.
ABC: Node 22298 has dup fanin 22282.
ABC: Node 22298 has dup fanin 22282.
ABC: Node 22299 has dup fanin 22282.
ABC: Node 22299 has dup fanin 22282.
ABC: Node 22300 has dup fanin 22282.
ABC: Node 22300 has dup fanin 22282.
ABC: Node 22301 has dup fanin 22282.
ABC: Node 22301 has dup fanin 22282.
ABC: Node 22302 has dup fanin 22282.
ABC: Node 22302 has dup fanin 22282.
ABC: Node 22303 has dup fanin 22282.
ABC: Node 22303 has dup fanin 22282.
ABC: Node 22304 has dup fanin 22282.
ABC: Node 22304 has dup fanin 22282.
ABC: Node 22305 has dup fanin 22282.
ABC: Node 22305 has dup fanin 22282.
ABC: Node 22306 has dup fanin 22282.
ABC: Node 22306 has dup fanin 22282.
ABC: Node 22307 has dup fanin 22282.
ABC: Node 22307 has dup fanin 22282.
ABC: Node 22308 has dup fanin 22282.
ABC: Node 22308 has dup fanin 22282.
ABC: Node 22309 has dup fanin 22282.
ABC: Node 22309 has dup fanin 22282.
ABC: Node 22310 has dup fanin 22282.
ABC: Node 22310 has dup fanin 22282.
ABC: Node 22311 has dup fanin 22282.
ABC: Node 22311 has dup fanin 22282.
ABC: Node 22312 has dup fanin 22282.
ABC: Node 22312 has dup fanin 22282.
ABC: Node 22313 has dup fanin 22282.
ABC: Node 22313 has dup fanin 22282.
ABC: Node 22314 has dup fanin 22282.
ABC: Node 22314 has dup fanin 22282.
ABC: Node 22317 has dup fanin 22316.
ABC: Node 22317 has dup fanin 22316.
ABC: Node 22318 has dup fanin 22316.
ABC: Node 22318 has dup fanin 22316.
ABC: Node 22319 has dup fanin 22316.
ABC: Node 22319 has dup fanin 22316.
ABC: Node 22320 has dup fanin 22316.
ABC: Node 22320 has dup fanin 22316.
ABC: Node 22321 has dup fanin 22316.
ABC: Node 22321 has dup fanin 22316.
ABC: Node 22322 has dup fanin 22316.
ABC: Node 22322 has dup fanin 22316.
ABC: Node 22323 has dup fanin 22316.
ABC: Node 22323 has dup fanin 22316.
ABC: Node 22324 has dup fanin 22316.
ABC: Node 22324 has dup fanin 22316.
ABC: Node 22325 has dup fanin 22316.
ABC: Node 22325 has dup fanin 22316.
ABC: Node 22326 has dup fanin 22316.
ABC: Node 22326 has dup fanin 22316.
ABC: Node 22327 has dup fanin 22316.
ABC: Node 22327 has dup fanin 22316.
ABC: Node 22328 has dup fanin 22316.
ABC: Node 22328 has dup fanin 22316.
ABC: Node 22329 has dup fanin 22316.
ABC: Node 22329 has dup fanin 22316.
ABC: Node 22330 has dup fanin 22316.
ABC: Node 22330 has dup fanin 22316.
ABC: Node 22331 has dup fanin 22316.
ABC: Node 22331 has dup fanin 22316.
ABC: Node 22332 has dup fanin 22316.
ABC: Node 22332 has dup fanin 22316.
ABC: Node 22333 has dup fanin 22316.
ABC: Node 22333 has dup fanin 22316.
ABC: Node 22334 has dup fanin 22316.
ABC: Node 22334 has dup fanin 22316.
ABC: Node 22335 has dup fanin 22316.
ABC: Node 22335 has dup fanin 22316.
ABC: Node 22336 has dup fanin 22316.
ABC: Node 22336 has dup fanin 22316.
ABC: Node 22337 has dup fanin 22316.
ABC: Node 22337 has dup fanin 22316.
ABC: Node 22338 has dup fanin 22316.
ABC: Node 22338 has dup fanin 22316.
ABC: Node 22339 has dup fanin 22316.
ABC: Node 22339 has dup fanin 22316.
ABC: Node 22340 has dup fanin 22316.
ABC: Node 22340 has dup fanin 22316.
ABC: Node 22341 has dup fanin 22316.
ABC: Node 22341 has dup fanin 22316.
ABC: Node 22342 has dup fanin 22316.
ABC: Node 22342 has dup fanin 22316.
ABC: Node 22343 has dup fanin 22316.
ABC: Node 22343 has dup fanin 22316.
ABC: Node 22344 has dup fanin 22316.
ABC: Node 22344 has dup fanin 22316.
ABC: Node 22345 has dup fanin 22316.
ABC: Node 22345 has dup fanin 22316.
ABC: Node 22346 has dup fanin 22316.
ABC: Node 22346 has dup fanin 22316.
ABC: Node 22347 has dup fanin 22316.
ABC: Node 22347 has dup fanin 22316.
ABC: Node 22348 has dup fanin 22316.
ABC: Node 22348 has dup fanin 22316.
ABC: Node 22351 has dup fanin 22350.
ABC: Node 22351 has dup fanin 22350.
ABC: Node 22352 has dup fanin 22350.
ABC: Node 22352 has dup fanin 22350.
ABC: Node 22353 has dup fanin 22350.
ABC: Node 22353 has dup fanin 22350.
ABC: Node 22354 has dup fanin 22350.
ABC: Node 22354 has dup fanin 22350.
ABC: Node 22355 has dup fanin 22350.
ABC: Node 22355 has dup fanin 22350.
ABC: Node 22356 has dup fanin 22350.
ABC: Node 22356 has dup fanin 22350.
ABC: Node 22357 has dup fanin 22350.
ABC: Node 22357 has dup fanin 22350.
ABC: Node 22358 has dup fanin 22350.
ABC: Node 22358 has dup fanin 22350.
ABC: Node 22359 has dup fanin 22350.
ABC: Node 22359 has dup fanin 22350.
ABC: Node 22360 has dup fanin 22350.
ABC: Node 22360 has dup fanin 22350.
ABC: Node 22361 has dup fanin 22350.
ABC: Node 22361 has dup fanin 22350.
ABC: Node 22362 has dup fanin 22350.
ABC: Node 22362 has dup fanin 22350.
ABC: Node 22363 has dup fanin 22350.
ABC: Node 22363 has dup fanin 22350.
ABC: Node 22364 has dup fanin 22350.
ABC: Node 22364 has dup fanin 22350.
ABC: Node 22365 has dup fanin 22350.
ABC: Node 22365 has dup fanin 22350.
ABC: Node 22366 has dup fanin 22350.
ABC: Node 22366 has dup fanin 22350.
ABC: Node 22367 has dup fanin 22350.
ABC: Node 22367 has dup fanin 22350.
ABC: Node 22368 has dup fanin 22350.
ABC: Node 22368 has dup fanin 22350.
ABC: Node 22369 has dup fanin 22350.
ABC: Node 22369 has dup fanin 22350.
ABC: Node 22370 has dup fanin 22350.
ABC: Node 22370 has dup fanin 22350.
ABC: Node 22371 has dup fanin 22350.
ABC: Node 22371 has dup fanin 22350.
ABC: Node 22372 has dup fanin 22350.
ABC: Node 22372 has dup fanin 22350.
ABC: Node 22373 has dup fanin 22350.
ABC: Node 22373 has dup fanin 22350.
ABC: Node 22374 has dup fanin 22350.
ABC: Node 22374 has dup fanin 22350.
ABC: Node 22375 has dup fanin 22350.
ABC: Node 22375 has dup fanin 22350.
ABC: Node 22376 has dup fanin 22350.
ABC: Node 22376 has dup fanin 22350.
ABC: Node 22377 has dup fanin 22350.
ABC: Node 22377 has dup fanin 22350.
ABC: Node 22378 has dup fanin 22350.
ABC: Node 22378 has dup fanin 22350.
ABC: Node 22379 has dup fanin 22350.
ABC: Node 22379 has dup fanin 22350.
ABC: Node 22380 has dup fanin 22350.
ABC: Node 22380 has dup fanin 22350.
ABC: Node 22381 has dup fanin 22350.
ABC: Node 22381 has dup fanin 22350.
ABC: Node 22382 has dup fanin 22350.
ABC: Node 22382 has dup fanin 22350.
ABC: Node 22387 has dup fanin 22386.
ABC: Node 22387 has dup fanin 22386.
ABC: Node 22388 has dup fanin 22386.
ABC: Node 22388 has dup fanin 22386.
ABC: Node 22389 has dup fanin 22386.
ABC: Node 22389 has dup fanin 22386.
ABC: Node 22390 has dup fanin 22386.
ABC: Node 22390 has dup fanin 22386.
ABC: Node 22391 has dup fanin 22386.
ABC: Node 22391 has dup fanin 22386.
ABC: Node 22392 has dup fanin 22386.
ABC: Node 22392 has dup fanin 22386.
ABC: Node 22393 has dup fanin 22386.
ABC: Node 22393 has dup fanin 22386.
ABC: Node 22394 has dup fanin 22386.
ABC: Node 22394 has dup fanin 22386.
ABC: Node 22395 has dup fanin 22386.
ABC: Node 22395 has dup fanin 22386.
ABC: Node 22396 has dup fanin 22386.
ABC: Node 22396 has dup fanin 22386.
ABC: Node 22397 has dup fanin 22386.
ABC: Node 22397 has dup fanin 22386.
ABC: Node 22398 has dup fanin 22386.
ABC: Node 22398 has dup fanin 22386.
ABC: Node 22419 has dup fanin 12202.
ABC: Node 22419 has dup fanin 12202.
ABC: Node 22420 has dup fanin 12202.
ABC: Node 22420 has dup fanin 12202.
ABC: Node 22421 has dup fanin 12202.
ABC: Node 22421 has dup fanin 12202.
ABC: Node 22422 has dup fanin 12202.
ABC: Node 22422 has dup fanin 12202.
ABC: Node 22425 has dup fanin 12202.
ABC: Node 22425 has dup fanin 12202.
ABC: Node 22426 has dup fanin 12202.
ABC: Node 22426 has dup fanin 12202.
ABC: Node 22431 has dup fanin 12202.
ABC: Node 22431 has dup fanin 12202.
ABC: Node 22432 has dup fanin 12202.
ABC: Node 22432 has dup fanin 12202.
ABC: Node 22472 has dup fanin 12151.
ABC: Node 22472 has dup fanin 12151.
ABC: Node 22634 has dup fanin 12286.
ABC: Node 22634 has dup fanin 12286.
ABC: Node 22650 has dup fanin 12286.
ABC: Node 22650 has dup fanin 12286.
ABC: Node 22658 has dup fanin 12286.
ABC: Node 22658 has dup fanin 12286.
ABC: Node 22675 has dup fanin 12286.
ABC: Node 22675 has dup fanin 12286.
ABC: Node 22682 has dup fanin 12286.
ABC: Node 22682 has dup fanin 12286.
ABC: Node 22696 has dup fanin 12286.
ABC: Node 22696 has dup fanin 12286.
ABC: Node 22715 has dup fanin 12286.
ABC: Node 22715 has dup fanin 12286.
ABC: Node 22730 has dup fanin 12287.
ABC: Node 22730 has dup fanin 12287.
ABC: Node 22732 has dup fanin 12287.
ABC: Node 22732 has dup fanin 12287.
ABC: Node 22742 has dup fanin 12287.
ABC: Node 22742 has dup fanin 12287.
ABC: Node 22769 has dup fanin 12286.
ABC: Node 22769 has dup fanin 12286.
ABC: Node 22770 has dup fanin 12287.
ABC: Node 22770 has dup fanin 12287.
ABC: Node 22795 has dup fanin 12286.
ABC: Node 22795 has dup fanin 12286.
ABC: Node 22816 has dup fanin 12151.
ABC: Node 22816 has dup fanin 12151.
ABC: Node 22817 has dup fanin 12151.
ABC: Node 22817 has dup fanin 12151.
ABC: Node 22818 has dup fanin 12151.
ABC: Node 22818 has dup fanin 12151.
ABC: Node 22819 has dup fanin 12151.
ABC: Node 22819 has dup fanin 12151.
ABC: Node 22820 has dup fanin 12151.
ABC: Node 22820 has dup fanin 12151.
ABC: Node 22821 has dup fanin 12151.
ABC: Node 22821 has dup fanin 12151.
ABC: Node 22822 has dup fanin 12151.
ABC: Node 22822 has dup fanin 12151.
ABC: Node 22825 has dup fanin 22824.
ABC: Node 22825 has dup fanin 22824.
ABC: Node 22826 has dup fanin 22824.
ABC: Node 22826 has dup fanin 22824.
ABC: Node 22827 has dup fanin 22824.
ABC: Node 22827 has dup fanin 22824.
ABC: Node 22828 has dup fanin 22824.
ABC: Node 22828 has dup fanin 22824.
ABC: Node 22829 has dup fanin 22824.
ABC: Node 22829 has dup fanin 22824.
ABC: Node 22830 has dup fanin 22824.
ABC: Node 22830 has dup fanin 22824.
ABC: Node 22831 has dup fanin 22824.
ABC: Node 22831 has dup fanin 22824.
ABC: Node 22832 has dup fanin 22824.
ABC: Node 22832 has dup fanin 22824.
ABC: Node 22833 has dup fanin 22824.
ABC: Node 22833 has dup fanin 22824.
ABC: Node 22834 has dup fanin 22824.
ABC: Node 22834 has dup fanin 22824.
ABC: Node 22835 has dup fanin 22824.
ABC: Node 22835 has dup fanin 22824.
ABC: Node 22836 has dup fanin 22824.
ABC: Node 22836 has dup fanin 22824.
ABC: Node 22837 has dup fanin 22824.
ABC: Node 22837 has dup fanin 22824.
ABC: Node 22838 has dup fanin 22824.
ABC: Node 22838 has dup fanin 22824.
ABC: Node 22839 has dup fanin 22824.
ABC: Node 22839 has dup fanin 22824.
ABC: Node 22840 has dup fanin 22824.
ABC: Node 22840 has dup fanin 22824.
ABC: Node 22841 has dup fanin 22824.
ABC: Node 22841 has dup fanin 22824.
ABC: Node 22842 has dup fanin 22824.
ABC: Node 22842 has dup fanin 22824.
ABC: Node 22843 has dup fanin 22824.
ABC: Node 22843 has dup fanin 22824.
ABC: Node 22844 has dup fanin 22824.
ABC: Node 22844 has dup fanin 22824.
ABC: Node 22845 has dup fanin 22824.
ABC: Node 22845 has dup fanin 22824.
ABC: Node 22846 has dup fanin 22824.
ABC: Node 22846 has dup fanin 22824.
ABC: Node 22847 has dup fanin 22824.
ABC: Node 22847 has dup fanin 22824.
ABC: Node 22848 has dup fanin 22824.
ABC: Node 22848 has dup fanin 22824.
ABC: Node 22849 has dup fanin 22824.
ABC: Node 22849 has dup fanin 22824.
ABC: Node 22850 has dup fanin 22824.
ABC: Node 22850 has dup fanin 22824.
ABC: Node 22851 has dup fanin 22824.
ABC: Node 22851 has dup fanin 22824.
ABC: Node 22852 has dup fanin 22824.
ABC: Node 22852 has dup fanin 22824.
ABC: Node 22853 has dup fanin 22824.
ABC: Node 22853 has dup fanin 22824.
ABC: Node 22854 has dup fanin 22824.
ABC: Node 22854 has dup fanin 22824.
ABC: Node 22855 has dup fanin 22824.
ABC: Node 22855 has dup fanin 22824.
ABC: Node 22856 has dup fanin 22824.
ABC: Node 22856 has dup fanin 22824.
ABC: Node 22858 has dup fanin 22857.
ABC: Node 22858 has dup fanin 22857.
ABC: Node 22859 has dup fanin 22857.
ABC: Node 22859 has dup fanin 22857.
ABC: Node 22860 has dup fanin 22857.
ABC: Node 22860 has dup fanin 22857.
ABC: Node 22861 has dup fanin 22857.
ABC: Node 22861 has dup fanin 22857.
ABC: Node 22862 has dup fanin 22857.
ABC: Node 22862 has dup fanin 22857.
ABC: Node 22863 has dup fanin 22857.
ABC: Node 22863 has dup fanin 22857.
ABC: Node 22864 has dup fanin 22857.
ABC: Node 22864 has dup fanin 22857.
ABC: Node 22865 has dup fanin 22857.
ABC: Node 22865 has dup fanin 22857.
ABC: Node 22866 has dup fanin 22857.
ABC: Node 22866 has dup fanin 22857.
ABC: Node 22867 has dup fanin 22857.
ABC: Node 22867 has dup fanin 22857.
ABC: Node 22868 has dup fanin 22857.
ABC: Node 22868 has dup fanin 22857.
ABC: Node 22869 has dup fanin 22857.
ABC: Node 22869 has dup fanin 22857.
ABC: Node 22870 has dup fanin 22857.
ABC: Node 22870 has dup fanin 22857.
ABC: Node 22871 has dup fanin 22857.
ABC: Node 22871 has dup fanin 22857.
ABC: Node 22872 has dup fanin 22857.
ABC: Node 22872 has dup fanin 22857.
ABC: Node 22873 has dup fanin 22857.
ABC: Node 22873 has dup fanin 22857.
ABC: Node 22874 has dup fanin 22857.
ABC: Node 22874 has dup fanin 22857.
ABC: Node 22875 has dup fanin 22857.
ABC: Node 22875 has dup fanin 22857.
ABC: Node 22876 has dup fanin 22857.
ABC: Node 22876 has dup fanin 22857.
ABC: Node 22877 has dup fanin 22857.
ABC: Node 22877 has dup fanin 22857.
ABC: Node 22878 has dup fanin 22857.
ABC: Node 22878 has dup fanin 22857.
ABC: Node 22879 has dup fanin 22857.
ABC: Node 22879 has dup fanin 22857.
ABC: Node 22880 has dup fanin 22857.
ABC: Node 22880 has dup fanin 22857.
ABC: Node 22881 has dup fanin 22857.
ABC: Node 22881 has dup fanin 22857.
ABC: Node 22882 has dup fanin 22857.
ABC: Node 22882 has dup fanin 22857.
ABC: Node 22883 has dup fanin 22857.
ABC: Node 22883 has dup fanin 22857.
ABC: Node 22884 has dup fanin 22857.
ABC: Node 22884 has dup fanin 22857.
ABC: Node 22885 has dup fanin 22857.
ABC: Node 22885 has dup fanin 22857.
ABC: Node 22886 has dup fanin 22857.
ABC: Node 22886 has dup fanin 22857.
ABC: Node 22887 has dup fanin 22857.
ABC: Node 22887 has dup fanin 22857.
ABC: Node 22888 has dup fanin 22857.
ABC: Node 22888 has dup fanin 22857.
ABC: Node 22889 has dup fanin 22857.
ABC: Node 22889 has dup fanin 22857.
ABC: Node 22892 has dup fanin 22891.
ABC: Node 22892 has dup fanin 22891.
ABC: Node 22893 has dup fanin 22891.
ABC: Node 22893 has dup fanin 22891.
ABC: Node 22894 has dup fanin 22891.
ABC: Node 22894 has dup fanin 22891.
ABC: Node 22895 has dup fanin 22891.
ABC: Node 22895 has dup fanin 22891.
ABC: Node 22896 has dup fanin 22891.
ABC: Node 22896 has dup fanin 22891.
ABC: Node 22897 has dup fanin 22891.
ABC: Node 22897 has dup fanin 22891.
ABC: Node 22898 has dup fanin 22891.
ABC: Node 22898 has dup fanin 22891.
ABC: Node 22899 has dup fanin 22891.
ABC: Node 22899 has dup fanin 22891.
ABC: Node 22900 has dup fanin 22891.
ABC: Node 22900 has dup fanin 22891.
ABC: Node 22901 has dup fanin 22891.
ABC: Node 22901 has dup fanin 22891.
ABC: Node 22902 has dup fanin 22891.
ABC: Node 22902 has dup fanin 22891.
ABC: Node 22903 has dup fanin 22891.
ABC: Node 22903 has dup fanin 22891.
ABC: Node 22904 has dup fanin 22891.
ABC: Node 22904 has dup fanin 22891.
ABC: Node 22905 has dup fanin 22891.
ABC: Node 22905 has dup fanin 22891.
ABC: Node 22906 has dup fanin 22891.
ABC: Node 22906 has dup fanin 22891.
ABC: Node 22907 has dup fanin 22891.
ABC: Node 22907 has dup fanin 22891.
ABC: Node 22908 has dup fanin 22891.
ABC: Node 22908 has dup fanin 22891.
ABC: Node 22909 has dup fanin 22891.
ABC: Node 22909 has dup fanin 22891.
ABC: Node 22910 has dup fanin 22891.
ABC: Node 22910 has dup fanin 22891.
ABC: Node 22911 has dup fanin 22891.
ABC: Node 22911 has dup fanin 22891.
ABC: Node 22912 has dup fanin 22891.
ABC: Node 22912 has dup fanin 22891.
ABC: Node 22913 has dup fanin 22891.
ABC: Node 22913 has dup fanin 22891.
ABC: Node 22914 has dup fanin 22891.
ABC: Node 22914 has dup fanin 22891.
ABC: Node 22915 has dup fanin 22891.
ABC: Node 22915 has dup fanin 22891.
ABC: Node 22916 has dup fanin 22891.
ABC: Node 22916 has dup fanin 22891.
ABC: Node 22917 has dup fanin 22891.
ABC: Node 22917 has dup fanin 22891.
ABC: Node 22918 has dup fanin 22891.
ABC: Node 22918 has dup fanin 22891.
ABC: Node 22919 has dup fanin 22891.
ABC: Node 22919 has dup fanin 22891.
ABC: Node 22920 has dup fanin 22891.
ABC: Node 22920 has dup fanin 22891.
ABC: Node 22921 has dup fanin 22891.
ABC: Node 22921 has dup fanin 22891.
ABC: Node 22922 has dup fanin 22891.
ABC: Node 22922 has dup fanin 22891.
ABC: Node 22923 has dup fanin 22891.
ABC: Node 22923 has dup fanin 22891.
ABC: Node 22929 has dup fanin 22928.
ABC: Node 22929 has dup fanin 22928.
ABC: Node 22930 has dup fanin 22928.
ABC: Node 22930 has dup fanin 22928.
ABC: Node 22931 has dup fanin 22928.
ABC: Node 22931 has dup fanin 22928.
ABC: Node 22932 has dup fanin 22928.
ABC: Node 22932 has dup fanin 22928.
ABC: Node 22933 has dup fanin 22928.
ABC: Node 22933 has dup fanin 22928.
ABC: Node 22934 has dup fanin 22928.
ABC: Node 22934 has dup fanin 22928.
ABC: Node 22935 has dup fanin 22928.
ABC: Node 22935 has dup fanin 22928.
ABC: Node 22936 has dup fanin 22928.
ABC: Node 22936 has dup fanin 22928.
ABC: Node 22937 has dup fanin 22928.
ABC: Node 22937 has dup fanin 22928.
ABC: Node 22938 has dup fanin 22928.
ABC: Node 22938 has dup fanin 22928.
ABC: Node 22939 has dup fanin 22928.
ABC: Node 22939 has dup fanin 22928.
ABC: Node 22940 has dup fanin 22928.
ABC: Node 22940 has dup fanin 22928.
ABC: Node 22941 has dup fanin 22928.
ABC: Node 22941 has dup fanin 22928.
ABC: Node 22942 has dup fanin 22928.
ABC: Node 22942 has dup fanin 22928.
ABC: Node 22943 has dup fanin 22928.
ABC: Node 22943 has dup fanin 22928.
ABC: Node 22944 has dup fanin 22928.
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ABC: Node 27693 has dup fanin 27666.
ABC: Node 27693 has dup fanin 27666.
ABC: Node 27694 has dup fanin 27666.
ABC: Node 27694 has dup fanin 27666.
ABC: Node 27695 has dup fanin 27666.
ABC: Node 27695 has dup fanin 27666.
ABC: Node 27696 has dup fanin 27666.
ABC: Node 27696 has dup fanin 27666.
ABC: Node 27697 has dup fanin 27666.
ABC: Node 27697 has dup fanin 27666.
ABC: Node 27698 has dup fanin 27666.
ABC: Node 27698 has dup fanin 27666.
ABC: Node 27700 has dup fanin 27699.
ABC: Node 27700 has dup fanin 27699.
ABC: Node 27701 has dup fanin 27699.
ABC: Node 27701 has dup fanin 27699.
ABC: Node 27702 has dup fanin 27699.
ABC: Node 27702 has dup fanin 27699.
ABC: Node 27703 has dup fanin 27699.
ABC: Node 27703 has dup fanin 27699.
ABC: Node 27704 has dup fanin 27699.
ABC: Node 27704 has dup fanin 27699.
ABC: Node 27705 has dup fanin 27699.
ABC: Node 27705 has dup fanin 27699.
ABC: Node 27706 has dup fanin 27699.
ABC: Node 27706 has dup fanin 27699.
ABC: Node 27707 has dup fanin 27699.
ABC: Node 27707 has dup fanin 27699.
ABC: Node 27708 has dup fanin 27699.
ABC: Node 27708 has dup fanin 27699.
ABC: Node 27709 has dup fanin 27699.
ABC: Node 27709 has dup fanin 27699.
ABC: Node 27710 has dup fanin 27699.
ABC: Node 27710 has dup fanin 27699.
ABC: Node 27711 has dup fanin 27699.
ABC: Node 27711 has dup fanin 27699.
ABC: Node 27712 has dup fanin 27699.
ABC: Node 27712 has dup fanin 27699.
ABC: Node 27713 has dup fanin 27699.
ABC: Node 27713 has dup fanin 27699.
ABC: Node 27714 has dup fanin 27699.
ABC: Node 27714 has dup fanin 27699.
ABC: Node 27715 has dup fanin 27699.
ABC: Node 27715 has dup fanin 27699.
ABC: Node 27716 has dup fanin 27699.
ABC: Node 27716 has dup fanin 27699.
ABC: Node 27717 has dup fanin 27699.
ABC: Node 27717 has dup fanin 27699.
ABC: Node 27718 has dup fanin 27699.
ABC: Node 27718 has dup fanin 27699.
ABC: Node 27719 has dup fanin 27699.
ABC: Node 27719 has dup fanin 27699.
ABC: Node 27720 has dup fanin 27699.
ABC: Node 27720 has dup fanin 27699.
ABC: Node 27721 has dup fanin 27699.
ABC: Node 27721 has dup fanin 27699.
ABC: Node 27722 has dup fanin 27699.
ABC: Node 27722 has dup fanin 27699.
ABC: Node 27723 has dup fanin 27699.
ABC: Node 27723 has dup fanin 27699.
ABC: Node 27724 has dup fanin 27699.
ABC: Node 27724 has dup fanin 27699.
ABC: Node 27725 has dup fanin 27699.
ABC: Node 27725 has dup fanin 27699.
ABC: Node 27726 has dup fanin 27699.
ABC: Node 27726 has dup fanin 27699.
ABC: Node 27727 has dup fanin 27699.
ABC: Node 27727 has dup fanin 27699.
ABC: Node 27728 has dup fanin 27699.
ABC: Node 27728 has dup fanin 27699.
ABC: Node 27729 has dup fanin 27699.
ABC: Node 27729 has dup fanin 27699.
ABC: Node 27730 has dup fanin 27699.
ABC: Node 27730 has dup fanin 27699.
ABC: Node 27731 has dup fanin 27699.
ABC: Node 27731 has dup fanin 27699.
ABC: Node 27733 has dup fanin 27732.
ABC: Node 27733 has dup fanin 27732.
ABC: Node 27734 has dup fanin 27732.
ABC: Node 27734 has dup fanin 27732.
ABC: Node 27735 has dup fanin 27732.
ABC: Node 27735 has dup fanin 27732.
ABC: Node 27736 has dup fanin 27732.
ABC: Node 27736 has dup fanin 27732.
ABC: Node 27737 has dup fanin 27732.
ABC: Node 27737 has dup fanin 27732.
ABC: Node 27738 has dup fanin 27732.
ABC: Node 27738 has dup fanin 27732.
ABC: Node 27739 has dup fanin 27732.
ABC: Node 27739 has dup fanin 27732.
ABC: Node 27740 has dup fanin 27732.
ABC: Node 27740 has dup fanin 27732.
ABC: Node 27741 has dup fanin 27732.
ABC: Node 27741 has dup fanin 27732.
ABC: Node 27742 has dup fanin 27732.
ABC: Node 27742 has dup fanin 27732.
ABC: Node 27743 has dup fanin 27732.
ABC: Node 27743 has dup fanin 27732.
ABC: Node 27744 has dup fanin 27732.
ABC: Node 27744 has dup fanin 27732.
ABC: Node 27745 has dup fanin 27732.
ABC: Node 27745 has dup fanin 27732.
ABC: Node 27746 has dup fanin 27732.
ABC: Node 27746 has dup fanin 27732.
ABC: Node 27747 has dup fanin 27732.
ABC: Node 27747 has dup fanin 27732.
ABC: Node 27748 has dup fanin 27732.
ABC: Node 27748 has dup fanin 27732.
ABC: Node 27749 has dup fanin 27732.
ABC: Node 27749 has dup fanin 27732.
ABC: Node 27750 has dup fanin 27732.
ABC: Node 27750 has dup fanin 27732.
ABC: Node 27751 has dup fanin 27732.
ABC: Node 27751 has dup fanin 27732.
ABC: Node 27752 has dup fanin 27732.
ABC: Node 27752 has dup fanin 27732.
ABC: Node 27753 has dup fanin 27732.
ABC: Node 27753 has dup fanin 27732.
ABC: Node 27754 has dup fanin 27732.
ABC: Node 27754 has dup fanin 27732.
ABC: Node 27755 has dup fanin 27732.
ABC: Node 27755 has dup fanin 27732.
ABC: Node 27756 has dup fanin 27732.
ABC: Node 27756 has dup fanin 27732.
ABC: Node 27757 has dup fanin 27732.
ABC: Node 27757 has dup fanin 27732.
ABC: Node 27758 has dup fanin 27732.
ABC: Node 27758 has dup fanin 27732.
ABC: Node 27759 has dup fanin 27732.
ABC: Node 27759 has dup fanin 27732.
ABC: Node 27760 has dup fanin 27732.
ABC: Node 27760 has dup fanin 27732.
ABC: Node 27761 has dup fanin 27732.
ABC: Node 27761 has dup fanin 27732.
ABC: Node 27762 has dup fanin 27732.
ABC: Node 27762 has dup fanin 27732.
ABC: Node 27763 has dup fanin 27732.
ABC: Node 27763 has dup fanin 27732.
ABC: Node 27764 has dup fanin 27732.
ABC: Node 27764 has dup fanin 27732.
ABC: Node 27766 has dup fanin 27765.
ABC: Node 27766 has dup fanin 27765.
ABC: Node 27767 has dup fanin 27765.
ABC: Node 27767 has dup fanin 27765.
ABC: Node 27768 has dup fanin 27765.
ABC: Node 27768 has dup fanin 27765.
ABC: Node 27769 has dup fanin 27765.
ABC: Node 27769 has dup fanin 27765.
ABC: Node 27770 has dup fanin 27765.
ABC: Node 27770 has dup fanin 27765.
ABC: Node 27771 has dup fanin 27765.
ABC: Node 27771 has dup fanin 27765.
ABC: Node 27772 has dup fanin 27765.
ABC: Node 27772 has dup fanin 27765.
ABC: Node 27773 has dup fanin 27765.
ABC: Node 27773 has dup fanin 27765.
ABC: Node 27774 has dup fanin 27765.
ABC: Node 27774 has dup fanin 27765.
ABC: Node 27775 has dup fanin 27765.
ABC: Node 27775 has dup fanin 27765.
ABC: Node 27776 has dup fanin 27765.
ABC: Node 27776 has dup fanin 27765.
ABC: Node 27777 has dup fanin 27765.
ABC: Node 27777 has dup fanin 27765.
ABC: Node 27778 has dup fanin 27765.
ABC: Node 27778 has dup fanin 27765.
ABC: Node 27779 has dup fanin 27765.
ABC: Node 27779 has dup fanin 27765.
ABC: Node 27780 has dup fanin 27765.
ABC: Node 27780 has dup fanin 27765.
ABC: Node 27781 has dup fanin 27765.
ABC: Node 27781 has dup fanin 27765.
ABC: Node 27782 has dup fanin 27765.
ABC: Node 27782 has dup fanin 27765.
ABC: Node 27783 has dup fanin 27765.
ABC: Node 27783 has dup fanin 27765.
ABC: Node 27784 has dup fanin 27765.
ABC: Node 27784 has dup fanin 27765.
ABC: Node 27785 has dup fanin 27765.
ABC: Node 27785 has dup fanin 27765.
ABC: Node 27786 has dup fanin 27765.
ABC: Node 27786 has dup fanin 27765.
ABC: Node 27787 has dup fanin 27765.
ABC: Node 27787 has dup fanin 27765.
ABC: Node 27788 has dup fanin 27765.
ABC: Node 27788 has dup fanin 27765.
ABC: Node 27789 has dup fanin 27765.
ABC: Node 27789 has dup fanin 27765.
ABC: Node 27790 has dup fanin 27765.
ABC: Node 27790 has dup fanin 27765.
ABC: Node 27791 has dup fanin 27765.
ABC: Node 27791 has dup fanin 27765.
ABC: Node 27792 has dup fanin 27765.
ABC: Node 27792 has dup fanin 27765.
ABC: Node 27793 has dup fanin 27765.
ABC: Node 27793 has dup fanin 27765.
ABC: Node 27794 has dup fanin 27765.
ABC: Node 27794 has dup fanin 27765.
ABC: Node 27795 has dup fanin 27765.
ABC: Node 27795 has dup fanin 27765.
ABC: Node 27796 has dup fanin 27765.
ABC: Node 27796 has dup fanin 27765.
ABC: Node 27797 has dup fanin 27765.
ABC: Node 27797 has dup fanin 27765.
ABC: Node 27809 has dup fanin 27808.
ABC: Node 27809 has dup fanin 27808.
ABC: Node 27810 has dup fanin 27808.
ABC: Node 27810 has dup fanin 27808.
ABC: Node 27811 has dup fanin 27808.
ABC: Node 27811 has dup fanin 27808.
ABC: Node 27812 has dup fanin 27808.
ABC: Node 27812 has dup fanin 27808.
ABC: Node 27813 has dup fanin 27808.
ABC: Node 27813 has dup fanin 27808.
ABC: Node 27814 has dup fanin 27808.
ABC: Node 27814 has dup fanin 27808.
ABC: Node 27815 has dup fanin 27808.
ABC: Node 27815 has dup fanin 27808.
ABC: Node 27816 has dup fanin 27808.
ABC: Node 27816 has dup fanin 27808.
ABC: Node 27817 has dup fanin 27808.
ABC: Node 27817 has dup fanin 27808.
ABC: Node 27818 has dup fanin 27808.
ABC: Node 27818 has dup fanin 27808.
ABC: Node 27819 has dup fanin 27808.
ABC: Node 27819 has dup fanin 27808.
ABC: Node 27820 has dup fanin 27808.
ABC: Node 27820 has dup fanin 27808.
ABC: Node 27821 has dup fanin 27808.
ABC: Node 27821 has dup fanin 27808.
ABC: Node 27822 has dup fanin 27808.
ABC: Node 27822 has dup fanin 27808.
ABC: Node 27823 has dup fanin 27808.
ABC: Node 27823 has dup fanin 27808.
ABC: Node 27824 has dup fanin 27808.
ABC: Node 27824 has dup fanin 27808.
ABC: Node 27825 has dup fanin 27808.
ABC: Node 27825 has dup fanin 27808.
ABC: Node 27826 has dup fanin 27808.
ABC: Node 27826 has dup fanin 27808.
ABC: Node 27827 has dup fanin 27808.
ABC: Node 27827 has dup fanin 27808.
ABC: Node 27828 has dup fanin 27808.
ABC: Node 27828 has dup fanin 27808.
ABC: Node 27829 has dup fanin 27808.
ABC: Node 27829 has dup fanin 27808.
ABC: Node 27830 has dup fanin 27808.
ABC: Node 27830 has dup fanin 27808.
ABC: Node 27831 has dup fanin 27808.
ABC: Node 27831 has dup fanin 27808.
ABC: Node 27832 has dup fanin 27808.
ABC: Node 27832 has dup fanin 27808.
ABC: Node 27833 has dup fanin 27808.
ABC: Node 27833 has dup fanin 27808.
ABC: Node 27834 has dup fanin 27808.
ABC: Node 27834 has dup fanin 27808.
ABC: Node 27835 has dup fanin 27808.
ABC: Node 27835 has dup fanin 27808.
ABC: Node 27836 has dup fanin 27808.
ABC: Node 27836 has dup fanin 27808.
ABC: Node 27837 has dup fanin 27808.
ABC: Node 27837 has dup fanin 27808.
ABC: Node 27838 has dup fanin 27808.
ABC: Node 27838 has dup fanin 27808.
ABC: Node 27839 has dup fanin 27808.
ABC: Node 27839 has dup fanin 27808.
ABC: Node 27840 has dup fanin 27808.
ABC: Node 27840 has dup fanin 27808.
ABC: Node 27842 has dup fanin 27841.
ABC: Node 27842 has dup fanin 27841.
ABC: Node 27843 has dup fanin 27841.
ABC: Node 27843 has dup fanin 27841.
ABC: Node 27844 has dup fanin 27841.
ABC: Node 27844 has dup fanin 27841.
ABC: Node 27845 has dup fanin 27841.
ABC: Node 27845 has dup fanin 27841.
ABC: Node 27846 has dup fanin 27841.
ABC: Node 27846 has dup fanin 27841.
ABC: Node 27847 has dup fanin 27841.
ABC: Node 27847 has dup fanin 27841.
ABC: Node 27848 has dup fanin 27841.
ABC: Node 27848 has dup fanin 27841.
ABC: Node 27849 has dup fanin 27841.
ABC: Node 27849 has dup fanin 27841.
ABC: Node 27850 has dup fanin 27841.
ABC: Node 27850 has dup fanin 27841.
ABC: Node 27851 has dup fanin 27841.
ABC: Node 27851 has dup fanin 27841.
ABC: Node 27852 has dup fanin 27841.
ABC: Node 27852 has dup fanin 27841.
ABC: Node 27853 has dup fanin 27841.
ABC: Node 27853 has dup fanin 27841.
ABC: Node 27854 has dup fanin 27841.
ABC: Node 27854 has dup fanin 27841.
ABC: Node 27855 has dup fanin 27841.
ABC: Node 27855 has dup fanin 27841.
ABC: Node 27856 has dup fanin 27841.
ABC: Node 27856 has dup fanin 27841.
ABC: Node 27857 has dup fanin 27841.
ABC: Node 27857 has dup fanin 27841.
ABC: Node 27858 has dup fanin 27841.
ABC: Node 27858 has dup fanin 27841.
ABC: Node 27859 has dup fanin 27841.
ABC: Node 27859 has dup fanin 27841.
ABC: Node 27860 has dup fanin 27841.
ABC: Node 27860 has dup fanin 27841.
ABC: Node 27861 has dup fanin 27841.
ABC: Node 27861 has dup fanin 27841.
ABC: Node 27862 has dup fanin 27841.
ABC: Node 27862 has dup fanin 27841.
ABC: Node 27863 has dup fanin 27841.
ABC: Node 27863 has dup fanin 27841.
ABC: Node 27864 has dup fanin 27841.
ABC: Node 27864 has dup fanin 27841.
ABC: Node 27865 has dup fanin 27841.
ABC: Node 27865 has dup fanin 27841.
ABC: Node 27866 has dup fanin 27841.
ABC: Node 27866 has dup fanin 27841.
ABC: Node 27867 has dup fanin 27841.
ABC: Node 27867 has dup fanin 27841.
ABC: Node 27868 has dup fanin 27841.
ABC: Node 27868 has dup fanin 27841.
ABC: Node 27869 has dup fanin 27841.
ABC: Node 27869 has dup fanin 27841.
ABC: Node 27870 has dup fanin 27841.
ABC: Node 27870 has dup fanin 27841.
ABC: Node 27871 has dup fanin 27841.
ABC: Node 27871 has dup fanin 27841.
ABC: Node 27872 has dup fanin 27841.
ABC: Node 27872 has dup fanin 27841.
ABC: Node 27873 has dup fanin 27841.
ABC: Node 27873 has dup fanin 27841.
ABC: Node 27875 has dup fanin 27874.
ABC: Node 27875 has dup fanin 27874.
ABC: Node 27876 has dup fanin 27874.
ABC: Node 27876 has dup fanin 27874.
ABC: Node 27877 has dup fanin 27874.
ABC: Node 27877 has dup fanin 27874.
ABC: Node 27878 has dup fanin 27874.
ABC: Node 27878 has dup fanin 27874.
ABC: Node 27879 has dup fanin 27874.
ABC: Node 27879 has dup fanin 27874.
ABC: Node 27880 has dup fanin 27874.
ABC: Node 27880 has dup fanin 27874.
ABC: Node 27881 has dup fanin 27874.
ABC: Node 27881 has dup fanin 27874.
ABC: Node 27882 has dup fanin 27874.
ABC: Node 27882 has dup fanin 27874.
ABC: Node 27883 has dup fanin 27874.
ABC: Node 27883 has dup fanin 27874.
ABC: Node 27884 has dup fanin 27874.
ABC: Node 27884 has dup fanin 27874.
ABC: Node 27885 has dup fanin 27874.
ABC: Node 27885 has dup fanin 27874.
ABC: Node 27886 has dup fanin 27874.
ABC: Node 27886 has dup fanin 27874.
ABC: Node 27887 has dup fanin 27874.
ABC: Node 27887 has dup fanin 27874.
ABC: Node 27888 has dup fanin 27874.
ABC: Node 27888 has dup fanin 27874.
ABC: Node 27889 has dup fanin 27874.
ABC: Node 27889 has dup fanin 27874.
ABC: Node 27890 has dup fanin 27874.
ABC: Node 27890 has dup fanin 27874.
ABC: Node 27891 has dup fanin 27874.
ABC: Node 27891 has dup fanin 27874.
ABC: Node 27892 has dup fanin 27874.
ABC: Node 27892 has dup fanin 27874.
ABC: Node 27893 has dup fanin 27874.
ABC: Node 27893 has dup fanin 27874.
ABC: Node 27894 has dup fanin 27874.
ABC: Node 27894 has dup fanin 27874.
ABC: Node 27895 has dup fanin 27874.
ABC: Node 27895 has dup fanin 27874.
ABC: Node 27896 has dup fanin 27874.
ABC: Node 27896 has dup fanin 27874.
ABC: Node 27897 has dup fanin 27874.
ABC: Node 27897 has dup fanin 27874.
ABC: Node 27898 has dup fanin 27874.
ABC: Node 27898 has dup fanin 27874.
ABC: Node 27899 has dup fanin 27874.
ABC: Node 27899 has dup fanin 27874.
ABC: Node 27900 has dup fanin 27874.
ABC: Node 27900 has dup fanin 27874.
ABC: Node 27901 has dup fanin 27874.
ABC: Node 27901 has dup fanin 27874.
ABC: Node 27902 has dup fanin 27874.
ABC: Node 27902 has dup fanin 27874.
ABC: Node 27903 has dup fanin 27874.
ABC: Node 27903 has dup fanin 27874.
ABC: Node 27904 has dup fanin 27874.
ABC: Node 27904 has dup fanin 27874.
ABC: Node 27905 has dup fanin 27874.
ABC: Node 27905 has dup fanin 27874.
ABC: Node 27906 has dup fanin 27874.
ABC: Node 27906 has dup fanin 27874.
ABC: Node 27908 has dup fanin 27907.
ABC: Node 27908 has dup fanin 27907.
ABC: Node 27909 has dup fanin 27907.
ABC: Node 27909 has dup fanin 27907.
ABC: Node 27910 has dup fanin 27907.
ABC: Node 27910 has dup fanin 27907.
ABC: Node 27911 has dup fanin 27907.
ABC: Node 27911 has dup fanin 27907.
ABC: Node 27912 has dup fanin 27907.
ABC: Node 27912 has dup fanin 27907.
ABC: Node 27913 has dup fanin 27907.
ABC: Node 27913 has dup fanin 27907.
ABC: Node 27914 has dup fanin 27907.
ABC: Node 27914 has dup fanin 27907.
ABC: Node 27915 has dup fanin 27907.
ABC: Node 27915 has dup fanin 27907.
ABC: Node 27916 has dup fanin 27907.
ABC: Node 27916 has dup fanin 27907.
ABC: Node 27917 has dup fanin 27907.
ABC: Node 27917 has dup fanin 27907.
ABC: Node 27918 has dup fanin 27907.
ABC: Node 27918 has dup fanin 27907.
ABC: Node 27919 has dup fanin 27907.
ABC: Node 27919 has dup fanin 27907.
ABC: Node 27920 has dup fanin 27907.
ABC: Node 27920 has dup fanin 27907.
ABC: Node 27921 has dup fanin 27907.
ABC: Node 27921 has dup fanin 27907.
ABC: Node 27922 has dup fanin 27907.
ABC: Node 27922 has dup fanin 27907.
ABC: Node 27923 has dup fanin 27907.
ABC: Node 27923 has dup fanin 27907.
ABC: Node 27924 has dup fanin 27907.
ABC: Node 27924 has dup fanin 27907.
ABC: Node 27925 has dup fanin 27907.
ABC: Node 27925 has dup fanin 27907.
ABC: Node 27926 has dup fanin 27907.
ABC: Node 27926 has dup fanin 27907.
ABC: Node 27927 has dup fanin 27907.
ABC: Node 27927 has dup fanin 27907.
ABC: Node 27928 has dup fanin 27907.
ABC: Node 27928 has dup fanin 27907.
ABC: Node 27929 has dup fanin 27907.
ABC: Node 27929 has dup fanin 27907.
ABC: Node 27930 has dup fanin 27907.
ABC: Node 27930 has dup fanin 27907.
ABC: Node 27931 has dup fanin 27907.
ABC: Node 27931 has dup fanin 27907.
ABC: Node 27932 has dup fanin 27907.
ABC: Node 27932 has dup fanin 27907.
ABC: Node 27933 has dup fanin 27907.
ABC: Node 27933 has dup fanin 27907.
ABC: Node 27934 has dup fanin 27907.
ABC: Node 27934 has dup fanin 27907.
ABC: Node 27935 has dup fanin 27907.
ABC: Node 27935 has dup fanin 27907.
ABC: Node 27936 has dup fanin 27907.
ABC: Node 27936 has dup fanin 27907.
ABC: Node 27937 has dup fanin 27907.
ABC: Node 27937 has dup fanin 27907.
ABC: Node 27938 has dup fanin 27907.
ABC: Node 27938 has dup fanin 27907.
ABC: Node 27939 has dup fanin 27907.
ABC: Node 27939 has dup fanin 27907.
ABC: Node 27941 has dup fanin 27940.
ABC: Node 27941 has dup fanin 27940.
ABC: Node 27942 has dup fanin 27940.
ABC: Node 27942 has dup fanin 27940.
ABC: Node 27943 has dup fanin 27940.
ABC: Node 27943 has dup fanin 27940.
ABC: Node 27944 has dup fanin 27940.
ABC: Node 27944 has dup fanin 27940.
ABC: Node 27945 has dup fanin 27940.
ABC: Node 27945 has dup fanin 27940.
ABC: Node 27946 has dup fanin 27940.
ABC: Node 27946 has dup fanin 27940.
ABC: Node 27947 has dup fanin 27940.
ABC: Node 27947 has dup fanin 27940.
ABC: Node 27948 has dup fanin 27940.
ABC: Node 27948 has dup fanin 27940.
ABC: Node 27949 has dup fanin 27940.
ABC: Node 27949 has dup fanin 27940.
ABC: Node 27950 has dup fanin 27940.
ABC: Node 27950 has dup fanin 27940.
ABC: Node 27951 has dup fanin 27940.
ABC: Node 27951 has dup fanin 27940.
ABC: Node 27952 has dup fanin 27940.
ABC: Node 27952 has dup fanin 27940.
ABC: Node 27953 has dup fanin 27940.
ABC: Node 27953 has dup fanin 27940.
ABC: Node 27954 has dup fanin 27940.
ABC: Node 27954 has dup fanin 27940.
ABC: Node 27955 has dup fanin 27940.
ABC: Node 27955 has dup fanin 27940.
ABC: Node 27956 has dup fanin 27940.
ABC: Node 27956 has dup fanin 27940.
ABC: Node 27957 has dup fanin 27940.
ABC: Node 27957 has dup fanin 27940.
ABC: Node 27958 has dup fanin 27940.
ABC: Node 27958 has dup fanin 27940.
ABC: Node 27959 has dup fanin 27940.
ABC: Node 27959 has dup fanin 27940.
ABC: Node 27960 has dup fanin 27940.
ABC: Node 27960 has dup fanin 27940.
ABC: Node 27961 has dup fanin 27940.
ABC: Node 27961 has dup fanin 27940.
ABC: Node 27962 has dup fanin 27940.
ABC: Node 27962 has dup fanin 27940.
ABC: Node 27963 has dup fanin 27940.
ABC: Node 27963 has dup fanin 27940.
ABC: Node 27964 has dup fanin 27940.
ABC: Node 27964 has dup fanin 27940.
ABC: Node 27965 has dup fanin 27940.
ABC: Node 27965 has dup fanin 27940.
ABC: Node 27966 has dup fanin 27940.
ABC: Node 27966 has dup fanin 27940.
ABC: Node 27967 has dup fanin 27940.
ABC: Node 27967 has dup fanin 27940.
ABC: Node 27968 has dup fanin 27940.
ABC: Node 27968 has dup fanin 27940.
ABC: Node 27969 has dup fanin 27940.
ABC: Node 27969 has dup fanin 27940.
ABC: Node 27970 has dup fanin 27940.
ABC: Node 27970 has dup fanin 27940.
ABC: Node 27971 has dup fanin 27940.
ABC: Node 27971 has dup fanin 27940.
ABC: Node 27972 has dup fanin 27940.
ABC: Node 27972 has dup fanin 27940.
ABC: Node 27974 has dup fanin 27973.
ABC: Node 27974 has dup fanin 27973.
ABC: Node 27975 has dup fanin 27973.
ABC: Node 27975 has dup fanin 27973.
ABC: Node 27976 has dup fanin 27973.
ABC: Node 27976 has dup fanin 27973.
ABC: Node 27977 has dup fanin 27973.
ABC: Node 27977 has dup fanin 27973.
ABC: Node 27978 has dup fanin 27973.
ABC: Node 27978 has dup fanin 27973.
ABC: Node 27979 has dup fanin 27973.
ABC: Node 27979 has dup fanin 27973.
ABC: Node 27980 has dup fanin 27973.
ABC: Node 27980 has dup fanin 27973.
ABC: Node 27981 has dup fanin 27973.
ABC: Node 27981 has dup fanin 27973.
ABC: Node 27982 has dup fanin 27973.
ABC: Node 27982 has dup fanin 27973.
ABC: Node 27983 has dup fanin 27973.
ABC: Node 27983 has dup fanin 27973.
ABC: Node 27984 has dup fanin 27973.
ABC: Node 27984 has dup fanin 27973.
ABC: Node 27985 has dup fanin 27973.
ABC: Node 27985 has dup fanin 27973.
ABC: Node 27986 has dup fanin 27973.
ABC: Node 27986 has dup fanin 27973.
ABC: Node 27987 has dup fanin 27973.
ABC: Node 27987 has dup fanin 27973.
ABC: Node 27988 has dup fanin 27973.
ABC: Node 27988 has dup fanin 27973.
ABC: Node 27989 has dup fanin 27973.
ABC: Node 27989 has dup fanin 27973.
ABC: Node 27990 has dup fanin 27973.
ABC: Node 27990 has dup fanin 27973.
ABC: Node 27991 has dup fanin 27973.
ABC: Node 27991 has dup fanin 27973.
ABC: Node 27992 has dup fanin 27973.
ABC: Node 27992 has dup fanin 27973.
ABC: Node 27993 has dup fanin 27973.
ABC: Node 27993 has dup fanin 27973.
ABC: Node 27994 has dup fanin 27973.
ABC: Node 27994 has dup fanin 27973.
ABC: Node 27995 has dup fanin 27973.
ABC: Node 27995 has dup fanin 27973.
ABC: Node 27996 has dup fanin 27973.
ABC: Node 27996 has dup fanin 27973.
ABC: Node 27997 has dup fanin 27973.
ABC: Node 27997 has dup fanin 27973.
ABC: Node 27998 has dup fanin 27973.
ABC: Node 27998 has dup fanin 27973.
ABC: Node 27999 has dup fanin 27973.
ABC: Node 27999 has dup fanin 27973.
ABC: Node 28000 has dup fanin 27973.
ABC: Node 28000 has dup fanin 27973.
ABC: Node 28001 has dup fanin 27973.
ABC: Node 28001 has dup fanin 27973.
ABC: Node 28002 has dup fanin 27973.
ABC: Node 28002 has dup fanin 27973.
ABC: Node 28003 has dup fanin 27973.
ABC: Node 28003 has dup fanin 27973.
ABC: Node 28004 has dup fanin 27973.
ABC: Node 28004 has dup fanin 27973.
ABC: Node 28005 has dup fanin 27973.
ABC: Node 28005 has dup fanin 27973.
ABC: Node 28007 has dup fanin 28006.
ABC: Node 28007 has dup fanin 28006.
ABC: Node 28008 has dup fanin 28006.
ABC: Node 28008 has dup fanin 28006.
ABC: Node 28009 has dup fanin 28006.
ABC: Node 28009 has dup fanin 28006.
ABC: Node 28010 has dup fanin 28006.
ABC: Node 28010 has dup fanin 28006.
ABC: Node 28011 has dup fanin 28006.
ABC: Node 28011 has dup fanin 28006.
ABC: Node 28012 has dup fanin 28006.
ABC: Node 28012 has dup fanin 28006.
ABC: Node 28013 has dup fanin 28006.
ABC: Node 28013 has dup fanin 28006.
ABC: Node 28014 has dup fanin 28006.
ABC: Node 28014 has dup fanin 28006.
ABC: Node 28015 has dup fanin 28006.
ABC: Node 28015 has dup fanin 28006.
ABC: Node 28016 has dup fanin 28006.
ABC: Node 28016 has dup fanin 28006.
ABC: Node 28017 has dup fanin 28006.
ABC: Node 28017 has dup fanin 28006.
ABC: Node 28018 has dup fanin 28006.
ABC: Node 28018 has dup fanin 28006.
ABC: Node 28019 has dup fanin 28006.
ABC: Node 28019 has dup fanin 28006.
ABC: Node 28020 has dup fanin 28006.
ABC: Node 28020 has dup fanin 28006.
ABC: Node 28021 has dup fanin 28006.
ABC: Node 28021 has dup fanin 28006.
ABC: Node 28022 has dup fanin 28006.
ABC: Node 28022 has dup fanin 28006.
ABC: Node 28023 has dup fanin 28006.
ABC: Node 28023 has dup fanin 28006.
ABC: Node 28024 has dup fanin 28006.
ABC: Node 28024 has dup fanin 28006.
ABC: Node 28025 has dup fanin 28006.
ABC: Node 28025 has dup fanin 28006.
ABC: Node 28026 has dup fanin 28006.
ABC: Node 28026 has dup fanin 28006.
ABC: Node 28027 has dup fanin 28006.
ABC: Node 28027 has dup fanin 28006.
ABC: Node 28028 has dup fanin 28006.
ABC: Node 28028 has dup fanin 28006.
ABC: Node 28029 has dup fanin 28006.
ABC: Node 28029 has dup fanin 28006.
ABC: Node 28030 has dup fanin 28006.
ABC: Node 28030 has dup fanin 28006.
ABC: Node 28031 has dup fanin 28006.
ABC: Node 28031 has dup fanin 28006.
ABC: Node 28032 has dup fanin 28006.
ABC: Node 28032 has dup fanin 28006.
ABC: Node 28033 has dup fanin 28006.
ABC: Node 28033 has dup fanin 28006.
ABC: Node 28034 has dup fanin 28006.
ABC: Node 28034 has dup fanin 28006.
ABC: Node 28035 has dup fanin 28006.
ABC: Node 28035 has dup fanin 28006.
ABC: Node 28036 has dup fanin 28006.
ABC: Node 28036 has dup fanin 28006.
ABC: Node 28037 has dup fanin 28006.
ABC: Node 28037 has dup fanin 28006.
ABC: Node 28038 has dup fanin 28006.
ABC: Node 28038 has dup fanin 28006.
ABC: Node 28040 has dup fanin 28039.
ABC: Node 28040 has dup fanin 28039.
ABC: Node 28041 has dup fanin 28039.
ABC: Node 28041 has dup fanin 28039.
ABC: Node 28042 has dup fanin 28039.
ABC: Node 28042 has dup fanin 28039.
ABC: Node 28043 has dup fanin 28039.
ABC: Node 28043 has dup fanin 28039.
ABC: Node 28044 has dup fanin 28039.
ABC: Node 28044 has dup fanin 28039.
ABC: Node 28045 has dup fanin 28039.
ABC: Node 28045 has dup fanin 28039.
ABC: Node 28046 has dup fanin 28039.
ABC: Node 28046 has dup fanin 28039.
ABC: Node 28047 has dup fanin 28039.
ABC: Node 28047 has dup fanin 28039.
ABC: Node 28048 has dup fanin 28039.
ABC: Node 28048 has dup fanin 28039.
ABC: Node 28049 has dup fanin 28039.
ABC: Node 28049 has dup fanin 28039.
ABC: Node 28050 has dup fanin 28039.
ABC: Node 28050 has dup fanin 28039.
ABC: Node 28051 has dup fanin 28039.
ABC: Node 28051 has dup fanin 28039.
ABC: Node 28052 has dup fanin 28039.
ABC: Node 28052 has dup fanin 28039.
ABC: Node 28053 has dup fanin 28039.
ABC: Node 28053 has dup fanin 28039.
ABC: Node 28054 has dup fanin 28039.
ABC: Node 28054 has dup fanin 28039.
ABC: Node 28055 has dup fanin 28039.
ABC: Node 28055 has dup fanin 28039.
ABC: Node 28056 has dup fanin 28039.
ABC: Node 28056 has dup fanin 28039.
ABC: Node 28057 has dup fanin 28039.
ABC: Node 28057 has dup fanin 28039.
ABC: Node 28058 has dup fanin 28039.
ABC: Node 28058 has dup fanin 28039.
ABC: Node 28059 has dup fanin 28039.
ABC: Node 28059 has dup fanin 28039.
ABC: Node 28060 has dup fanin 28039.
ABC: Node 28060 has dup fanin 28039.
ABC: Node 28061 has dup fanin 28039.
ABC: Node 28061 has dup fanin 28039.
ABC: Node 28062 has dup fanin 28039.
ABC: Node 28062 has dup fanin 28039.
ABC: Node 28063 has dup fanin 28039.
ABC: Node 28063 has dup fanin 28039.
ABC: Node 28064 has dup fanin 28039.
ABC: Node 28064 has dup fanin 28039.
ABC: Node 28065 has dup fanin 28039.
ABC: Node 28065 has dup fanin 28039.
ABC: Node 28079 has dup fanin 28078.
ABC: Node 28079 has dup fanin 28078.
ABC: Node 28080 has dup fanin 28078.
ABC: Node 28080 has dup fanin 28078.
ABC: Node 28081 has dup fanin 28078.
ABC: Node 28081 has dup fanin 28078.
ABC: Node 28082 has dup fanin 28078.
ABC: Node 28082 has dup fanin 28078.
ABC: Node 28083 has dup fanin 28078.
ABC: Node 28083 has dup fanin 28078.
ABC: Node 28084 has dup fanin 28078.
ABC: Node 28084 has dup fanin 28078.
ABC: Node 28085 has dup fanin 28078.
ABC: Node 28085 has dup fanin 28078.
ABC: Node 28086 has dup fanin 28078.
ABC: Node 28086 has dup fanin 28078.
ABC: Node 28087 has dup fanin 28078.
ABC: Node 28087 has dup fanin 28078.
ABC: Node 28088 has dup fanin 28078.
ABC: Node 28088 has dup fanin 28078.
ABC: Node 28089 has dup fanin 28078.
ABC: Node 28089 has dup fanin 28078.
ABC: Node 28090 has dup fanin 28078.
ABC: Node 28090 has dup fanin 28078.
ABC: Node 28091 has dup fanin 28078.
ABC: Node 28091 has dup fanin 28078.
ABC: Node 28092 has dup fanin 28078.
ABC: Node 28092 has dup fanin 28078.
ABC: Node 28093 has dup fanin 28078.
ABC: Node 28093 has dup fanin 28078.
ABC: Node 28094 has dup fanin 28078.
ABC: Node 28094 has dup fanin 28078.
ABC: Node 28095 has dup fanin 28078.
ABC: Node 28095 has dup fanin 28078.
ABC: Node 28096 has dup fanin 28078.
ABC: Node 28096 has dup fanin 28078.
ABC: Node 28097 has dup fanin 28078.
ABC: Node 28097 has dup fanin 28078.
ABC: Node 28098 has dup fanin 28078.
ABC: Node 28098 has dup fanin 28078.
ABC: Node 28099 has dup fanin 28078.
ABC: Node 28099 has dup fanin 28078.
ABC: Node 28100 has dup fanin 28078.
ABC: Node 28100 has dup fanin 28078.
ABC: Node 28101 has dup fanin 28078.
ABC: Node 28101 has dup fanin 28078.
ABC: Node 28102 has dup fanin 28078.
ABC: Node 28102 has dup fanin 28078.
ABC: Node 28103 has dup fanin 28078.
ABC: Node 28103 has dup fanin 28078.
ABC: Node 28104 has dup fanin 28078.
ABC: Node 28104 has dup fanin 28078.
ABC: Node 28105 has dup fanin 28078.
ABC: Node 28105 has dup fanin 28078.
ABC: Node 28106 has dup fanin 28078.
ABC: Node 28106 has dup fanin 28078.
ABC: Node 28107 has dup fanin 28078.
ABC: Node 28107 has dup fanin 28078.
ABC: Node 28108 has dup fanin 28078.
ABC: Node 28108 has dup fanin 28078.
ABC: Node 28109 has dup fanin 28078.
ABC: Node 28109 has dup fanin 28078.
ABC: Node 28110 has dup fanin 28078.
ABC: Node 28110 has dup fanin 28078.
ABC: Node 28112 has dup fanin 28111.
ABC: Node 28112 has dup fanin 28111.
ABC: Node 28113 has dup fanin 28111.
ABC: Node 28113 has dup fanin 28111.
ABC: Node 28114 has dup fanin 28111.
ABC: Node 28114 has dup fanin 28111.
ABC: Node 28115 has dup fanin 28111.
ABC: Node 28115 has dup fanin 28111.
ABC: Node 28116 has dup fanin 28111.
ABC: Node 28116 has dup fanin 28111.
ABC: Node 28117 has dup fanin 28111.
ABC: Node 28117 has dup fanin 28111.
ABC: Node 28118 has dup fanin 28111.
ABC: Node 28118 has dup fanin 28111.
ABC: Node 28119 has dup fanin 28111.
ABC: Node 28119 has dup fanin 28111.
ABC: Node 28120 has dup fanin 28111.
ABC: Node 28120 has dup fanin 28111.
ABC: Node 28121 has dup fanin 28111.
ABC: Node 28121 has dup fanin 28111.
ABC: Node 28122 has dup fanin 28111.
ABC: Node 28122 has dup fanin 28111.
ABC: Node 28123 has dup fanin 28111.
ABC: Node 28123 has dup fanin 28111.
ABC: Node 28124 has dup fanin 28111.
ABC: Node 28124 has dup fanin 28111.
ABC: Node 28125 has dup fanin 28111.
ABC: Node 28125 has dup fanin 28111.
ABC: Node 28126 has dup fanin 28111.
ABC: Node 28126 has dup fanin 28111.
ABC: Node 28127 has dup fanin 28111.
ABC: Node 28127 has dup fanin 28111.
ABC: Node 28128 has dup fanin 28111.
ABC: Node 28128 has dup fanin 28111.
ABC: Node 28129 has dup fanin 28111.
ABC: Node 28129 has dup fanin 28111.
ABC: Node 28130 has dup fanin 28111.
ABC: Node 28130 has dup fanin 28111.
ABC: Node 28131 has dup fanin 28111.
ABC: Node 28131 has dup fanin 28111.
ABC: Node 28132 has dup fanin 28111.
ABC: Node 28132 has dup fanin 28111.
ABC: Node 28133 has dup fanin 28111.
ABC: Node 28133 has dup fanin 28111.
ABC: Node 28134 has dup fanin 28111.
ABC: Node 28134 has dup fanin 28111.
ABC: Node 28135 has dup fanin 28111.
ABC: Node 28135 has dup fanin 28111.
ABC: Node 28136 has dup fanin 28111.
ABC: Node 28136 has dup fanin 28111.
ABC: Node 28137 has dup fanin 28111.
ABC: Node 28137 has dup fanin 28111.
ABC: Node 28138 has dup fanin 28111.
ABC: Node 28138 has dup fanin 28111.
ABC: Node 28139 has dup fanin 28111.
ABC: Node 28139 has dup fanin 28111.
ABC: Node 28140 has dup fanin 28111.
ABC: Node 28140 has dup fanin 28111.
ABC: Node 28141 has dup fanin 28111.
ABC: Node 28141 has dup fanin 28111.
ABC: Node 28142 has dup fanin 28111.
ABC: Node 28142 has dup fanin 28111.
ABC: Node 28143 has dup fanin 28111.
ABC: Node 28143 has dup fanin 28111.
ABC: Node 28146 has dup fanin 18719.
ABC: Node 28146 has dup fanin 18719.
ABC: Node 28189 has dup fanin 18719.
ABC: Node 28189 has dup fanin 18719.
ABC: Node 28191 has dup fanin 28190.
ABC: Node 28191 has dup fanin 28190.
ABC: Node 28192 has dup fanin 28190.
ABC: Node 28192 has dup fanin 28190.
ABC: Node 28193 has dup fanin 28190.
ABC: Node 28193 has dup fanin 28190.
ABC: Node 28194 has dup fanin 28190.
ABC: Node 28194 has dup fanin 28190.
ABC: Node 28195 has dup fanin 28190.
ABC: Node 28195 has dup fanin 28190.
ABC: Node 28196 has dup fanin 28190.
ABC: Node 28196 has dup fanin 28190.
ABC: Node 28197 has dup fanin 28190.
ABC: Node 28197 has dup fanin 28190.
ABC: Node 28198 has dup fanin 28190.
ABC: Node 28198 has dup fanin 28190.
ABC: Node 28200 has dup fanin 28199.
ABC: Node 28200 has dup fanin 28199.
ABC: Node 28201 has dup fanin 28199.
ABC: Node 28201 has dup fanin 28199.
ABC: Node 28202 has dup fanin 28199.
ABC: Node 28202 has dup fanin 28199.
ABC: Node 28203 has dup fanin 28199.
ABC: Node 28203 has dup fanin 28199.
ABC: Node 28204 has dup fanin 28199.
ABC: Node 28204 has dup fanin 28199.
ABC: Node 28205 has dup fanin 28199.
ABC: Node 28205 has dup fanin 28199.
ABC: Node 28206 has dup fanin 28199.
ABC: Node 28206 has dup fanin 28199.
ABC: Node 28207 has dup fanin 28199.
ABC: Node 28207 has dup fanin 28199.
ABC: Node 28237 has dup fanin 28236.
ABC: Node 28237 has dup fanin 28236.
ABC: Node 28238 has dup fanin 28236.
ABC: Node 28238 has dup fanin 28236.
ABC: Node 28239 has dup fanin 28236.
ABC: Node 28239 has dup fanin 28236.
ABC: Node 28240 has dup fanin 28236.
ABC: Node 28240 has dup fanin 28236.
ABC: Node 28241 has dup fanin 28236.
ABC: Node 28241 has dup fanin 28236.
ABC: Node 28242 has dup fanin 28236.
ABC: Node 28242 has dup fanin 28236.
ABC: Node 28243 has dup fanin 28236.
ABC: Node 28243 has dup fanin 28236.
ABC: Node 28244 has dup fanin 28236.
ABC: Node 28244 has dup fanin 28236.
ABC: Node 28272 has dup fanin 18720.
ABC: Node 28272 has dup fanin 18720.
ABC: Node 28273 has dup fanin 18720.
ABC: Node 28273 has dup fanin 18720.
ABC: Node 28274 has dup fanin 18720.
ABC: Node 28274 has dup fanin 18720.
ABC: Node 28275 has dup fanin 18720.
ABC: Node 28275 has dup fanin 18720.
ABC: Node 28276 has dup fanin 18720.
ABC: Node 28276 has dup fanin 18720.
ABC: Node 28277 has dup fanin 18720.
ABC: Node 28277 has dup fanin 18720.
ABC: Node 28278 has dup fanin 18720.
ABC: Node 28278 has dup fanin 18720.
ABC: Node 28279 has dup fanin 18720.
ABC: Node 28279 has dup fanin 18720.
ABC: Node 28280 has dup fanin 18720.
ABC: Node 28280 has dup fanin 18720.
ABC: Node 28281 has dup fanin 18720.
ABC: Node 28281 has dup fanin 18720.
ABC: Node 28282 has dup fanin 18720.
ABC: Node 28282 has dup fanin 18720.
ABC: Node 28283 has dup fanin 18720.
ABC: Node 28283 has dup fanin 18720.
ABC: Node 28284 has dup fanin 18720.
ABC: Node 28284 has dup fanin 18720.
ABC: Node 28285 has dup fanin 18720.
ABC: Node 28285 has dup fanin 18720.
ABC: Node 28286 has dup fanin 18720.
ABC: Node 28286 has dup fanin 18720.
ABC: Node 28287 has dup fanin 18720.
ABC: Node 28287 has dup fanin 18720.
ABC: Node 28288 has dup fanin 18720.
ABC: Node 28288 has dup fanin 18720.
ABC: Node 28289 has dup fanin 18720.
ABC: Node 28289 has dup fanin 18720.
ABC: Node 28290 has dup fanin 18720.
ABC: Node 28290 has dup fanin 18720.
ABC: Node 28291 has dup fanin 18720.
ABC: Node 28291 has dup fanin 18720.
ABC: Node 28292 has dup fanin 18720.
ABC: Node 28292 has dup fanin 18720.
ABC: Node 28293 has dup fanin 18720.
ABC: Node 28293 has dup fanin 18720.
ABC: Node 28294 has dup fanin 18720.
ABC: Node 28294 has dup fanin 18720.
ABC: Node 28295 has dup fanin 18720.
ABC: Node 28295 has dup fanin 18720.
ABC: Node 28296 has dup fanin 18720.
ABC: Node 28296 has dup fanin 18720.
ABC: Node 28297 has dup fanin 18720.
ABC: Node 28297 has dup fanin 18720.
ABC: Node 28298 has dup fanin 18720.
ABC: Node 28298 has dup fanin 18720.
ABC: Node 28299 has dup fanin 18720.
ABC: Node 28299 has dup fanin 18720.
ABC: Node 28300 has dup fanin 18720.
ABC: Node 28300 has dup fanin 18720.
ABC: Node 28301 has dup fanin 18720.
ABC: Node 28301 has dup fanin 18720.
ABC: Node 28302 has dup fanin 18720.
ABC: Node 28302 has dup fanin 18720.
ABC: Node 28303 has dup fanin 18720.
ABC: Node 28303 has dup fanin 18720.
ABC: Node 28429 has dup fanin 28304.
ABC: Node 28429 has dup fanin 28304.
ABC: Node 28474 has dup fanin 28304.
ABC: Node 28474 has dup fanin 28304.
ABC: Node 28519 has dup fanin 28304.
ABC: Node 28519 has dup fanin 28304.
ABC: Node 28564 has dup fanin 28304.
ABC: Node 28564 has dup fanin 28304.
ABC: Node 28609 has dup fanin 28304.
ABC: Node 28609 has dup fanin 28304.
ABC: Node 28654 has dup fanin 28304.
ABC: Node 28654 has dup fanin 28304.
ABC: Node 28699 has dup fanin 28304.
ABC: Node 28699 has dup fanin 28304.
ABC: Node 28744 has dup fanin 28304.
ABC: Node 28744 has dup fanin 28304.
ABC: Node 28789 has dup fanin 28304.
ABC: Node 28789 has dup fanin 28304.
ABC: Node 28822 has dup fanin 28821.
ABC: Node 28822 has dup fanin 28821.
ABC: Node 28823 has dup fanin 28821.
ABC: Node 28823 has dup fanin 28821.
ABC: Node 28824 has dup fanin 28821.
ABC: Node 28824 has dup fanin 28821.
ABC: Node 28825 has dup fanin 28821.
ABC: Node 28825 has dup fanin 28821.
ABC: Node 28826 has dup fanin 28821.
ABC: Node 28826 has dup fanin 28821.
ABC: Node 28827 has dup fanin 28821.
ABC: Node 28827 has dup fanin 28821.
ABC: Node 28828 has dup fanin 28821.
ABC: Node 28828 has dup fanin 28821.
ABC: Node 28829 has dup fanin 28821.
ABC: Node 28829 has dup fanin 28821.
ABC: Node 28830 has dup fanin 28821.
ABC: Node 28830 has dup fanin 28821.
ABC: Node 28831 has dup fanin 28821.
ABC: Node 28831 has dup fanin 28821.
ABC: Node 28832 has dup fanin 28821.
ABC: Node 28832 has dup fanin 28821.
ABC: Node 28833 has dup fanin 28821.
ABC: Node 28833 has dup fanin 28821.
ABC: Node 28834 has dup fanin 28821.
ABC: Node 28834 has dup fanin 28821.
ABC: Node 28835 has dup fanin 28821.
ABC: Node 28835 has dup fanin 28821.
ABC: Node 28836 has dup fanin 28821.
ABC: Node 28836 has dup fanin 28821.
ABC: Node 28837 has dup fanin 28821.
ABC: Node 28837 has dup fanin 28821.
ABC: Node 28838 has dup fanin 28821.
ABC: Node 28838 has dup fanin 28821.
ABC: Node 28839 has dup fanin 28821.
ABC: Node 28839 has dup fanin 28821.
ABC: Node 28840 has dup fanin 28821.
ABC: Node 28840 has dup fanin 28821.
ABC: Node 28841 has dup fanin 28821.
ABC: Node 28841 has dup fanin 28821.
ABC: Node 28842 has dup fanin 28821.
ABC: Node 28842 has dup fanin 28821.
ABC: Node 28843 has dup fanin 28821.
ABC: Node 28843 has dup fanin 28821.
ABC: Node 28844 has dup fanin 28821.
ABC: Node 28844 has dup fanin 28821.
ABC: Node 28845 has dup fanin 28821.
ABC: Node 28845 has dup fanin 28821.
ABC: Node 28846 has dup fanin 28821.
ABC: Node 28846 has dup fanin 28821.
ABC: Node 28847 has dup fanin 28821.
ABC: Node 28847 has dup fanin 28821.
ABC: Node 28848 has dup fanin 28821.
ABC: Node 28848 has dup fanin 28821.
ABC: Node 28849 has dup fanin 28821.
ABC: Node 28849 has dup fanin 28821.
ABC: Node 28850 has dup fanin 28821.
ABC: Node 28850 has dup fanin 28821.
ABC: Node 28851 has dup fanin 28821.
ABC: Node 28851 has dup fanin 28821.
ABC: Node 28852 has dup fanin 28821.
ABC: Node 28852 has dup fanin 28821.
ABC: Node 28853 has dup fanin 28821.
ABC: Node 28853 has dup fanin 28821.
ABC: Node 28856 has dup fanin 331.
ABC: Node 28856 has dup fanin 332.
ABC: Node 28856 has dup fanin 331.
ABC: Node 28856 has dup fanin 332.
ABC: Node 28929 has dup fanin 28923.
ABC: Node 28929 has dup fanin 28923.
ABC: Node 28931 has dup fanin 13452.
ABC: Node 28931 has dup fanin 13452.
ABC: Node 28965 has dup fanin 28923.
ABC: Node 28965 has dup fanin 28923.
ABC: Node 28975 has dup fanin 28923.
ABC: Node 28975 has dup fanin 28923.
ABC: Node 29267 has dup fanin 91.
ABC: Node 29267 has dup fanin 335.
ABC: Node 29267 has dup fanin 91.
ABC: Node 29267 has dup fanin 335.
ABC: Node 29299 has dup fanin 8578.
ABC: Node 29299 has dup fanin 8578.
ABC: Node 29309 has dup fanin 29254.
ABC: Node 29309 has dup fanin 29254.
ABC: Node 29661 has dup fanin 12151.
ABC: Node 29661 has dup fanin 12151.
ABC: Node 29664 has dup fanin 12151.
ABC: Node 29664 has dup fanin 12151.
ABC: Node 29673 has dup fanin 12151.
ABC: Node 29673 has dup fanin 12151.
ABC: Node 29684 has dup fanin 12151.
ABC: Node 29684 has dup fanin 12151.
ABC: Node 29693 has dup fanin 12151.
ABC: Node 29693 has dup fanin 12151.
ABC: Node 29704 has dup fanin 12151.
ABC: Node 29704 has dup fanin 12151.
ABC: Node 29720 has dup fanin 12151.
ABC: Node 29720 has dup fanin 12151.
ABC: Node 29738 has dup fanin 12151.
ABC: Node 29738 has dup fanin 12151.
ABC: Node 29766 has dup fanin 12151.
ABC: Node 29766 has dup fanin 12151.
ABC: Node 29787 has dup fanin 8762.
ABC: Node 29787 has dup fanin 8762.
ABC: Node 29788 has dup fanin 1067.
ABC: Node 29788 has dup fanin 1067.
ABC: Node 29830 has dup fanin 509.
ABC: Node 29830 has dup fanin 509.
ABC: Node 29859 has dup fanin 9086.
ABC: Node 29859 has dup fanin 9086.
ABC: Node 29905 has dup fanin 2230.
ABC: Node 29905 has dup fanin 2230.
ABC: Node 29914 has dup fanin 9086.
ABC: Node 29914 has dup fanin 9086.
ABC: Node 29917 has dup fanin 9087.
ABC: Node 29917 has dup fanin 9087.
ABC: Node 29919 has dup fanin 9086.
ABC: Node 29919 has dup fanin 9086.
ABC: Node 29928 has dup fanin 9087.
ABC: Node 29928 has dup fanin 9087.
ABC: Node 30004 has dup fanin 9085.
ABC: Node 30004 has dup fanin 9085.
ABC: Node 30037 has dup fanin 9086.
ABC: Node 30037 has dup fanin 9086.
ABC: Node 30044 has dup fanin 8481.
ABC: Node 30044 has dup fanin 8481.
ABC: Node 30067 has dup fanin 418.
ABC: Node 30067 has dup fanin 418.
ABC: Node 30089 has dup fanin 8481.
ABC: Node 30089 has dup fanin 8481.
ABC: Node 30130 has dup fanin 8481.
ABC: Node 30130 has dup fanin 8481.
ABC: Node 30172 has dup fanin 8481.
ABC: Node 30172 has dup fanin 8481.
ABC: Node 30194 has dup fanin 8481.
ABC: Node 30194 has dup fanin 8481.
ABC: Node 30214 has dup fanin 8481.
ABC: Node 30214 has dup fanin 8481.
ABC: Node 30254 has dup fanin 8481.
ABC: Node 30254 has dup fanin 8481.
ABC: Node 30441 has dup fanin 8481.
ABC: Node 30441 has dup fanin 8481.
ABC: Node 30458 has dup fanin 8481.
ABC: Node 30458 has dup fanin 8481.
ABC: Node 30477 has dup fanin 8481.
ABC: Node 30477 has dup fanin 8481.
ABC: Node 30496 has dup fanin 8481.
ABC: Node 30496 has dup fanin 8481.
ABC: Node 30516 has dup fanin 8481.
ABC: Node 30516 has dup fanin 8481.
ABC: + upsize -D 50000 
ABC: Current delay (18718.59 ps) does not exceed the target delay (50000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 50000 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =  30809 ( 34.2 %)   Cap = 11.2 ff (  0.0 %)   Area =   325347.03 (100.0 %)   Delay = 29169.22 ps  (  0.7 %)               
ABC: Path  0 --     873 : 0    3 pi                        A =   0.00  Df =  29.5  -18.9 ps  S =  47.9 ps  Cin =  0.0 ff  Cout =  25.6 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --   12112 : 1    2 sky130_fd_sc_hd__inv_8    A =  11.26  Df =  52.5  -12.9 ps  S =  18.3 ps  Cin = 17.7 ff  Cout =   4.9 ff  Cmax =1035.5 ff  G =   26  
ABC: Path  2 --   12113 : 2    2 sky130_fd_sc_hd__and2_4   A =   8.76  Df = 175.3  -11.8 ps  S =  43.9 ps  Cin =  2.4 ff  Cout =   7.3 ff  Cmax = 539.3 ff  G =  288  
ABC: Path  3 --   12114 : 3    1 sky130_fd_sc_hd__a21o_4   A =  15.01  Df = 341.5 -106.1 ps  S =  29.6 ps  Cin =  4.5 ff  Cout =   2.5 ff  Cmax = 568.6 ff  G =   52  
ABC: Path  4 --   12127 : 4    1 sky130_fd_sc_hd__or4_4    A =  11.26  Df = 875.0 -523.1 ps  S =  92.6 ps  Cin =  2.4 ff  Cout =   9.1 ff  Cmax = 534.7 ff  G =  360  
ABC: Path  5 --   12174 : 4    1 sky130_fd_sc_hd__nor4_4   A =  21.27  Df =1137.4 -554.7 ps  S = 170.8 ps  Cin =  8.5 ff  Cout =   2.5 ff  Cmax = 112.6 ff  G =   26  
ABC: Path  6 --   12175 : 4    1 sky130_fd_sc_hd__or4_4    A =  11.26  Df =1280.0 -302.8 ps  S =  77.8 ps  Cin =  2.4 ff  Cout =   2.5 ff  Cmax = 534.7 ff  G =  100  
ABC: Path  7 --   12176 : 3    1 sky130_fd_sc_hd__and3_4   A =  11.26  Df =1438.9 -280.2 ps  S =  37.6 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 532.8 ff  G =   86  
ABC: Path  8 --   12177 : 1    4 sky130_fd_sc_hd__buf_1    A =   3.75  Df =1698.1 -370.0 ps  S = 307.4 ps  Cin =  2.1 ff  Cout =  25.7 ff  Cmax = 130.0 ff  G = 1163  
ABC: Path  9 --   12178 : 1    2 sky130_fd_sc_hd__inv_8    A =  11.26  Df =1725.5 -327.4 ps  S =  43.6 ps  Cin = 17.7 ff  Cout =   4.7 ff  Cmax =1035.5 ff  G =   25  
ABC: Path 10 --   12179 : 2    3 sky130_fd_sc_hd__or2_4    A =   8.76  Df =1952.9 -449.3 ps  S =  50.0 ps  Cin =  2.4 ff  Cout =   7.2 ff  Cmax = 514.5 ff  G =  283  
ABC: Path 11 --   15774 : 3    1 sky130_fd_sc_hd__or3_4    A =  11.26  Df =2265.3 -664.9 ps  S =  59.5 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 531.9 ff  G =   89  
ABC: Path 12 --   15775 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =2439.3 -601.5 ps  S = 282.9 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1064  
ABC: Path 13 --   18663 : 2    2 sky130_fd_sc_hd__or2_4    A =   8.76  Df =2726.1 -675.8 ps  S =  79.3 ps  Cin =  2.4 ff  Cout =  20.9 ff  Cmax = 514.5 ff  G =  838  
ABC: Path 14 --   18664 : 1    2 sky130_fd_sc_hd__inv_8    A =  11.26  Df =2775.8 -699.6 ps  S =  25.6 ps  Cin = 17.7 ff  Cout =   5.1 ff  Cmax =1035.5 ff  G =   27  
ABC: Path 15 --   18665 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =2892.3 -682.7 ps  S =  30.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 16 --   18666 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =3131.9 -762.2 ps  S = 283.2 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 17 --   18667 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =3316.5 -763.8 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 18 --   18668 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =3557.3 -844.5 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 19 --   18669 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =3742.0 -846.2 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 20 --   18670 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =3982.8 -926.9 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 21 --   18671 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =4167.4 -928.6 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 22 --   18672 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =4408.2-1009.2 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 23 --   18673 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =4592.8-1010.9 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 24 --   18674 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =4833.6-1091.6 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 25 --   18675 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =5018.2-1093.3 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 26 --   18676 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =5259.0-1174.0 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 27 --   18677 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =5443.7-1175.6 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 28 --   18678 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =5684.5-1256.3 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 29 --   18679 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =5869.1-1258.0 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 30 --   18680 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =6109.9-1338.7 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 31 --   18681 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =6294.5-1340.4 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 32 --   18682 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =6535.3-1421.0 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 33 --   18683 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =6719.9-1422.7 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 34 --   18684 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =6960.7-1503.4 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 35 --   18685 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =7145.4-1505.1 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 36 --   18686 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =7386.2-1585.8 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 37 --   18687 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =7570.8-1587.4 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 38 --   18688 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =7811.6-1668.1 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 39 --   18689 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =7996.2-1669.8 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 40 --   18690 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =8237.0-1750.5 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 41 --   18691 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =8421.6-1752.2 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 42 --   18692 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =8662.4-1832.8 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 43 --   18693 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =8847.1-1834.5 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 44 --   18694 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =9087.9-1915.2 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 45 --   18695 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =9272.5-1916.9 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 46 --   18696 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =9513.3-1997.6 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 47 --   18697 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =9697.9-1999.2 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 48 --   18698 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =9938.7-2079.9 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 49 --   18699 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =10123.3-2081.6 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 50 --   18700 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =10364.1-2162.3 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 51 --   18701 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =10548.7-2164.0 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 52 --   18702 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =10789.6-2244.6 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 53 --   18703 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =10974.2-2246.3 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 54 --   18704 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =11215.0-2327.0 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 55 --   18705 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =11399.6-2328.7 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 56 --   18706 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =11640.4-2409.4 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 57 --   18707 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =11825.0-2411.0 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 58 --   18708 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =12065.8-2491.7 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 59 --   18709 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =12250.4-2493.4 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 60 --   18710 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =12491.2-2574.1 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 61 --   18711 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =12675.9-2575.8 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 62 --   18712 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =12916.7-2656.4 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 63 --   18713 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =13101.3-2658.1 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 64 --   18714 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =13342.1-2738.8 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 65 --   18715 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =13526.7-2740.5 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 66 --   18716 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =13767.5-2821.2 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 67 --   18717 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =13952.1-2822.8 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 68 --   18718 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =14192.9-2903.5 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 69 --   18719 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =14377.6-2905.2 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 70 --   18720 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =14618.4-2985.9 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 71 --   18721 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =14803.0-2987.6 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 72 --   18722 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =15043.8-3068.2 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 73 --   18723 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =15228.4-3069.9 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 74 --   18724 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =15469.2-3150.6 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 75 --   18725 : 2    2 sky130_fd_sc_hd__and2_4   A =   8.76  Df =15702.3-3169.7 ps  S =  81.5 ps  Cin =  2.4 ff  Cout =  21.0 ff  Cmax = 539.3 ff  G =  843  
ABC: Path 76 --   18726 : 1    2 sky130_fd_sc_hd__inv_8    A =  11.26  Df =15728.3-3153.3 ps  S =  21.7 ps  Cin = 17.7 ff  Cout =   5.0 ff  Cmax =1035.5 ff  G =   26  
ABC: Path 77 --   18727 : 2    2 sky130_fd_sc_hd__or2_4    A =   8.76  Df =15975.7-3270.3 ps  S =  77.0 ps  Cin =  2.4 ff  Cout =  20.9 ff  Cmax = 514.5 ff  G =  838  
ABC: Path 78 --   18728 : 1    2 sky130_fd_sc_hd__inv_8    A =  11.26  Df =16025.5-3294.4 ps  S =  25.6 ps  Cin = 17.7 ff  Cout =   5.1 ff  Cmax =1035.5 ff  G =   27  
ABC: Path 79 --   18729 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =16142.0-3277.5 ps  S =  30.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 80 --   18730 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =16381.6-3357.0 ps  S = 283.2 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 81 --   18731 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =16566.2-3358.7 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 82 --   18732 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =16807.0-3439.4 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 83 --   18733 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =16991.6-3441.1 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 84 --   18734 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =17232.4-3521.7 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 85 --   18735 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =17417.0-3523.4 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 86 --   18736 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =17657.8-3604.1 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 87 --   18737 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =17842.4-3605.8 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 88 --   18738 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =18083.3-3686.4 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 89 --   18739 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =18267.9-3688.1 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 90 --   18740 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =18508.7-3768.8 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 91 --   18741 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =18693.3-3770.5 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 92 --   18742 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =18934.1-3851.2 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 93 --   18743 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =19118.7-3852.9 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 94 --   18744 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =19359.5-3933.5 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 95 --   18745 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =19544.1-3935.2 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 96 --   18746 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =19784.9-4015.9 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 97 --   18747 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =19969.6-4017.6 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path 98 --   18748 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =20210.4-4098.2 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path 99 --   18749 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =20395.0-4099.9 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path100 --   18750 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =20635.8-4180.6 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path101 --   18751 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =20820.4-4182.3 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path102 --   18752 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =21061.2-4263.0 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path103 --   18753 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =21245.8-4264.7 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path104 --   18754 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =21486.6-4345.3 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path105 --   18755 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =21671.3-4347.0 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path106 --   18756 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =21912.1-4427.7 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path107 --   18757 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =22096.7-4429.4 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path108 --   18758 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =22337.5-4510.0 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path109 --   18759 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =22522.1-4511.7 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path110 --   18760 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =22762.9-4592.4 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path111 --   18761 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =22947.5-4594.1 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path112 --   18762 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =23188.3-4674.8 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path113 --   18763 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =23373.0-4676.4 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path114 --   18764 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =23613.8-4757.1 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path115 --   18765 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =23798.4-4758.8 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path116 --   18766 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =24039.2-4839.5 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path117 --   18767 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =24223.8-4841.2 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path118 --   18768 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =24464.6-4921.8 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path119 --   18769 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =24649.2-4923.5 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path120 --   18770 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =24890.0-5004.2 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path121 --   18771 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =25074.7-5005.9 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path122 --   18772 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =25315.5-5086.6 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path123 --   18773 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =25500.1-5088.2 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path124 --   18774 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =25740.9-5168.9 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path125 --   18775 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =25925.5-5170.6 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path126 --   18776 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =26166.3-5251.3 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path127 --   18777 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =26350.9-5253.0 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path128 --   18778 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =26591.7-5333.6 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path129 --   18779 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =26776.3-5335.3 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path130 --   18780 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =27017.2-5416.0 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path131 --   18781 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =27201.8-5417.7 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path132 --   18782 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =27442.6-5498.3 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path133 --   18783 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =27627.2-5500.0 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path134 --   18784 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =27868.0-5580.7 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path135 --   18785 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =28052.6-5582.4 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path136 --   18786 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =28293.4-5663.1 ps  S = 283.3 ps  Cin =  2.1 ff  Cout =  23.6 ff  Cmax = 130.0 ff  G = 1067  
ABC: Path137 --   18787 : 2    1 sky130_fd_sc_hd__and2_4   A =   8.76  Df =28478.0-5664.8 ps  S =  33.1 ps  Cin =  2.4 ff  Cout =   2.2 ff  Cmax = 539.3 ff  G =   88  
ABC: Path138 --   18788 : 1    3 sky130_fd_sc_hd__buf_1    A =   3.75  Df =28792.6-5784.2 ps  S = 390.2 ps  Cin =  2.1 ff  Cout =  32.9 ff  Cmax = 130.0 ff  G = 1489  
ABC: Path139 --   18791 : 3    1 sky130_fd_sc_hd__a21boi_4 A =  18.77  Df =29169.2 -248.3 ps  S = 179.2 ps  Cin =  6.8 ff  Cout =  17.6 ff  Cmax = 215.2 ff  G =  260  
ABC: Start-point = pi872 (\soc.cpu.picorv32_core.irq_mask [30]).  End-point = po934 ($auto$rtlil.cc:2290:MuxGate$93503).
ABC: + print_stats -m 
ABC: netlist                       : i/o = 4227/ 4046  lat =    0  nd = 30809  edge =  68857  area =325336.41  delay =140.00  lev = 140
ABC: + write_blif /tmp/yosys-abc-PAFRQ6/output.blif 

19.1.2. Re-integrating ABC results.
ABC RESULTS:   sky130_fd_sc_hd__a2111o_4 cells:       10
ABC RESULTS:   sky130_fd_sc_hd__a2111oi_4 cells:       39
ABC RESULTS:   sky130_fd_sc_hd__a211o_4 cells:      672
ABC RESULTS:   sky130_fd_sc_hd__a21bo_4 cells:      152
ABC RESULTS:   sky130_fd_sc_hd__a21boi_4 cells:       78
ABC RESULTS:   sky130_fd_sc_hd__a21o_4 cells:      510
ABC RESULTS:   sky130_fd_sc_hd__a21oi_4 cells:      199
ABC RESULTS:   sky130_fd_sc_hd__a22oi_4 cells:       45
ABC RESULTS:   sky130_fd_sc_hd__a2bb2o_4 cells:     1791
ABC RESULTS:   sky130_fd_sc_hd__a2bb2oi_4 cells:      142
ABC RESULTS:   sky130_fd_sc_hd__a32o_4 cells:      375
ABC RESULTS:   sky130_fd_sc_hd__a32oi_4 cells:      216
ABC RESULTS:   sky130_fd_sc_hd__and2_4 cells:     2092
ABC RESULTS:   sky130_fd_sc_hd__and3_4 cells:     1719
ABC RESULTS:   sky130_fd_sc_hd__and4_4 cells:       98
ABC RESULTS:   sky130_fd_sc_hd__buf_1 cells:     8516
ABC RESULTS:   sky130_fd_sc_hd__inv_8 cells:     2028
ABC RESULTS:   sky130_fd_sc_hd__nand2_4 cells:      315
ABC RESULTS:   sky130_fd_sc_hd__nand3_4 cells:       20
ABC RESULTS:   sky130_fd_sc_hd__nand4_4 cells:        8
ABC RESULTS:   sky130_fd_sc_hd__nor2_4 cells:     1186
ABC RESULTS:   sky130_fd_sc_hd__nor3_4 cells:     1678
ABC RESULTS:   sky130_fd_sc_hd__nor4_4 cells:       33
ABC RESULTS:   sky130_fd_sc_hd__o21a_4 cells:     1055
ABC RESULTS:   sky130_fd_sc_hd__o21ai_4 cells:      488
ABC RESULTS:   sky130_fd_sc_hd__o22a_4 cells:     1305
ABC RESULTS:   sky130_fd_sc_hd__o32a_4 cells:      100
ABC RESULTS:   sky130_fd_sc_hd__o32ai_4 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__o41a_4 cells:        6
ABC RESULTS:   sky130_fd_sc_hd__or2_4 cells:     5036
ABC RESULTS:   sky130_fd_sc_hd__or3_4 cells:      254
ABC RESULTS:   sky130_fd_sc_hd__or4_4 cells:      596
ABC RESULTS:   sky130_fd_sc_hd__xor2_4 cells:       43
ABC RESULTS:        internal signals:    20842
ABC RESULTS:           input signals:     4227
ABC RESULTS:          output signals:     4046
Removing temp directory.

20. Executing SETUNDEF pass (replace undef values with defined constants).

21. Executing HILOMAP pass (mapping to constant drivers).

22. Executing SPLITNETS pass (splitting up multi-bit signals).

23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 269 unused cells and 30419 unused wires.


24. Executing INSBUF pass (insert buffer cells for connected wires).
Added mgmt_core.$auto$insbuf.cc:79:execute$127934: \flash_clk_oeb -> \flash_csb_oeb
Added mgmt_core.$auto$insbuf.cc:79:execute$127935: \mgmt_addr [0] -> \mgmt_addr_ro [0]
Added mgmt_core.$auto$insbuf.cc:79:execute$127936: \mgmt_addr [1] -> \mgmt_addr_ro [1]
Added mgmt_core.$auto$insbuf.cc:79:execute$127937: \mgmt_addr [2] -> \mgmt_addr_ro [2]
Added mgmt_core.$auto$insbuf.cc:79:execute$127938: \mgmt_addr [3] -> \mgmt_addr_ro [3]
Added mgmt_core.$auto$insbuf.cc:79:execute$127939: \mgmt_addr [4] -> \mgmt_addr_ro [4]
Added mgmt_core.$auto$insbuf.cc:79:execute$127940: \mgmt_addr [5] -> \mgmt_addr_ro [5]
Added mgmt_core.$auto$insbuf.cc:79:execute$127941: \mgmt_addr [6] -> \mgmt_addr_ro [6]
Added mgmt_core.$auto$insbuf.cc:79:execute$127942: \mgmt_addr [7] -> \mgmt_addr_ro [7]
Added mgmt_core.$auto$insbuf.cc:79:execute$127943: \mgmt_wen [1] -> \mgmt_wen [0]
Added mgmt_core.$auto$insbuf.cc:79:execute$127944: \mgmt_wen_mask [4] -> \mgmt_wen_mask [0]
Added mgmt_core.$auto$insbuf.cc:79:execute$127945: \mgmt_wen_mask [5] -> \mgmt_wen_mask [1]
Added mgmt_core.$auto$insbuf.cc:79:execute$127946: \mgmt_wen_mask [6] -> \mgmt_wen_mask [2]
Added mgmt_core.$auto$insbuf.cc:79:execute$127947: \mgmt_wen_mask [7] -> \mgmt_wen_mask [3]
Added mgmt_core.$auto$insbuf.cc:79:execute$127948: \mgmt_addr [0] -> \mprj_adr_o [2]
Added mgmt_core.$auto$insbuf.cc:79:execute$127949: \mgmt_addr [1] -> \mprj_adr_o [3]
Added mgmt_core.$auto$insbuf.cc:79:execute$127950: \mgmt_addr [2] -> \mprj_adr_o [4]
Added mgmt_core.$auto$insbuf.cc:79:execute$127951: \mgmt_addr [3] -> \mprj_adr_o [5]
Added mgmt_core.$auto$insbuf.cc:79:execute$127952: \mgmt_addr [4] -> \mprj_adr_o [6]
Added mgmt_core.$auto$insbuf.cc:79:execute$127953: \mgmt_addr [5] -> \mprj_adr_o [7]
Added mgmt_core.$auto$insbuf.cc:79:execute$127954: \mgmt_addr [6] -> \mprj_adr_o [8]
Added mgmt_core.$auto$insbuf.cc:79:execute$127955: \mgmt_addr [7] -> \mprj_adr_o [9]
Added mgmt_core.$auto$insbuf.cc:79:execute$127956: \mgmt_wdata [0] -> \mprj_dat_o [0]
Added mgmt_core.$auto$insbuf.cc:79:execute$127957: \mgmt_wdata [1] -> \mprj_dat_o [1]
Added mgmt_core.$auto$insbuf.cc:79:execute$127958: \mgmt_wdata [2] -> \mprj_dat_o [2]
Added mgmt_core.$auto$insbuf.cc:79:execute$127959: \mgmt_wdata [3] -> \mprj_dat_o [3]
Added mgmt_core.$auto$insbuf.cc:79:execute$127960: \mgmt_wdata [4] -> \mprj_dat_o [4]
Added mgmt_core.$auto$insbuf.cc:79:execute$127961: \mgmt_wdata [5] -> \mprj_dat_o [5]
Added mgmt_core.$auto$insbuf.cc:79:execute$127962: \mgmt_wdata [6] -> \mprj_dat_o [6]
Added mgmt_core.$auto$insbuf.cc:79:execute$127963: \mgmt_wdata [7] -> \mprj_dat_o [7]
Added mgmt_core.$auto$insbuf.cc:79:execute$127964: \mgmt_wdata [8] -> \mprj_dat_o [8]
Added mgmt_core.$auto$insbuf.cc:79:execute$127965: \mgmt_wdata [9] -> \mprj_dat_o [9]
Added mgmt_core.$auto$insbuf.cc:79:execute$127966: \mgmt_wdata [10] -> \mprj_dat_o [10]
Added mgmt_core.$auto$insbuf.cc:79:execute$127967: \mgmt_wdata [11] -> \mprj_dat_o [11]
Added mgmt_core.$auto$insbuf.cc:79:execute$127968: \mgmt_wdata [12] -> \mprj_dat_o [12]
Added mgmt_core.$auto$insbuf.cc:79:execute$127969: \mgmt_wdata [13] -> \mprj_dat_o [13]
Added mgmt_core.$auto$insbuf.cc:79:execute$127970: \mgmt_wdata [14] -> \mprj_dat_o [14]
Added mgmt_core.$auto$insbuf.cc:79:execute$127971: \mgmt_wdata [15] -> \mprj_dat_o [15]
Added mgmt_core.$auto$insbuf.cc:79:execute$127972: \mgmt_wdata [16] -> \mprj_dat_o [16]
Added mgmt_core.$auto$insbuf.cc:79:execute$127973: \mgmt_wdata [17] -> \mprj_dat_o [17]
Added mgmt_core.$auto$insbuf.cc:79:execute$127974: \mgmt_wdata [18] -> \mprj_dat_o [18]
Added mgmt_core.$auto$insbuf.cc:79:execute$127975: \mgmt_wdata [19] -> \mprj_dat_o [19]
Added mgmt_core.$auto$insbuf.cc:79:execute$127976: \mgmt_wdata [20] -> \mprj_dat_o [20]
Added mgmt_core.$auto$insbuf.cc:79:execute$127977: \mgmt_wdata [21] -> \mprj_dat_o [21]
Added mgmt_core.$auto$insbuf.cc:79:execute$127978: \mgmt_wdata [22] -> \mprj_dat_o [22]
Added mgmt_core.$auto$insbuf.cc:79:execute$127979: \mgmt_wdata [23] -> \mprj_dat_o [23]
Added mgmt_core.$auto$insbuf.cc:79:execute$127980: \mgmt_wdata [24] -> \mprj_dat_o [24]
Added mgmt_core.$auto$insbuf.cc:79:execute$127981: \mgmt_wdata [25] -> \mprj_dat_o [25]
Added mgmt_core.$auto$insbuf.cc:79:execute$127982: \mgmt_wdata [26] -> \mprj_dat_o [26]
Added mgmt_core.$auto$insbuf.cc:79:execute$127983: \mgmt_wdata [27] -> \mprj_dat_o [27]
Added mgmt_core.$auto$insbuf.cc:79:execute$127984: \mgmt_wdata [28] -> \mprj_dat_o [28]
Added mgmt_core.$auto$insbuf.cc:79:execute$127985: \mgmt_wdata [29] -> \mprj_dat_o [29]
Added mgmt_core.$auto$insbuf.cc:79:execute$127986: \mgmt_wdata [30] -> \mprj_dat_o [30]
Added mgmt_core.$auto$insbuf.cc:79:execute$127987: \mgmt_wdata [31] -> \mprj_dat_o [31]

25. Executing CHECK pass (checking for obvious problems).
checking module mgmt_core..
Warning: Wire mgmt_core.\user_clk is used but has no driver.
Warning: Wire mgmt_core.\sdo_outenb is used but has no driver.
Warning: Wire mgmt_core.\sdo_out is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [3] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [2] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [1] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [0] is used but has no driver.
Warning: Wire mgmt_core.\mprj_we_o is used but has no driver.
Warning: Wire mgmt_core.\mprj_stb_o is used but has no driver.
Warning: Wire mgmt_core.\mprj_sel_o [3] is used but has no driver.
Warning: Wire mgmt_core.\mprj_sel_o [2] is used but has no driver.
Warning: Wire mgmt_core.\mprj_sel_o [1] is used but has no driver.
Warning: Wire mgmt_core.\mprj_sel_o [0] is used but has no driver.
Warning: Wire mgmt_core.\mprj_io_loader_resetn is used but has no driver.
Warning: Wire mgmt_core.\mprj_io_loader_data is used but has no driver.
Warning: Wire mgmt_core.\mprj_io_loader_clock is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [31] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [30] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [29] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [28] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [27] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [26] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [25] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [24] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [23] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [22] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [21] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [20] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [19] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [18] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [17] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [16] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [15] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [14] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [13] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [12] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [11] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [10] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [9] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [8] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [7] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [6] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [5] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [4] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [3] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [2] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [1] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [0] is used but has no driver.
Warning: Wire mgmt_core.\mprj_cyc_o is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [31] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [30] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [29] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [28] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [27] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [26] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [25] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [24] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [23] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [22] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [21] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [20] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [19] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [18] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [17] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [16] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [15] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [14] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [13] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [12] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [11] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [10] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [9] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [8] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [7] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [6] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [5] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [4] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [3] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [2] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [1] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [0] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [7] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [6] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [5] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [4] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [3] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [2] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [0] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen [0] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [37] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [36] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [35] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [34] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [33] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [32] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [31] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [30] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [29] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [28] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [27] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [26] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [25] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [24] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [23] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [22] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [21] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [20] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [19] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [18] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [17] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [16] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [15] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [14] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [13] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [12] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [11] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [10] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [9] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [8] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [7] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [6] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [5] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [4] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [3] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [2] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [0] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_ena_ro is used but has no driver.
Warning: Wire mgmt_core.\mgmt_ena [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_ena [0] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [7] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [6] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [5] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [4] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [3] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [2] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [0] is used but has no driver.
Warning: Wire mgmt_core.\la_output [127] is used but has no driver.
Warning: Wire mgmt_core.\la_output [126] is used but has no driver.
Warning: Wire mgmt_core.\la_output [125] is used but has no driver.
Warning: Wire mgmt_core.\la_output [124] is used but has no driver.
Warning: Wire mgmt_core.\la_output [123] is used but has no driver.
Warning: Wire mgmt_core.\la_output [122] is used but has no driver.
Warning: Wire mgmt_core.\la_output [121] is used but has no driver.
Warning: Wire mgmt_core.\la_output [120] is used but has no driver.
Warning: Wire mgmt_core.\la_output [119] is used but has no driver.
Warning: Wire mgmt_core.\la_output [118] is used but has no driver.
Warning: Wire mgmt_core.\la_output [117] is used but has no driver.
Warning: Wire mgmt_core.\la_output [116] is used but has no driver.
Warning: Wire mgmt_core.\la_output [115] is used but has no driver.
Warning: Wire mgmt_core.\la_output [114] is used but has no driver.
Warning: Wire mgmt_core.\la_output [113] is used but has no driver.
Warning: Wire mgmt_core.\la_output [112] is used but has no driver.
Warning: Wire mgmt_core.\la_output [111] is used but has no driver.
Warning: Wire mgmt_core.\la_output [110] is used but has no driver.
Warning: Wire mgmt_core.\la_output [109] is used but has no driver.
Warning: Wire mgmt_core.\la_output [108] is used but has no driver.
Warning: Wire mgmt_core.\la_output [107] is used but has no driver.
Warning: Wire mgmt_core.\la_output [106] is used but has no driver.
Warning: Wire mgmt_core.\la_output [105] is used but has no driver.
Warning: Wire mgmt_core.\la_output [104] is used but has no driver.
Warning: Wire mgmt_core.\la_output [103] is used but has no driver.
Warning: Wire mgmt_core.\la_output [102] is used but has no driver.
Warning: Wire mgmt_core.\la_output [101] is used but has no driver.
Warning: Wire mgmt_core.\la_output [100] is used but has no driver.
Warning: Wire mgmt_core.\la_output [99] is used but has no driver.
Warning: Wire mgmt_core.\la_output [98] is used but has no driver.
Warning: Wire mgmt_core.\la_output [97] is used but has no driver.
Warning: Wire mgmt_core.\la_output [96] is used but has no driver.
Warning: Wire mgmt_core.\la_output [95] is used but has no driver.
Warning: Wire mgmt_core.\la_output [94] is used but has no driver.
Warning: Wire mgmt_core.\la_output [93] is used but has no driver.
Warning: Wire mgmt_core.\la_output [92] is used but has no driver.
Warning: Wire mgmt_core.\la_output [91] is used but has no driver.
Warning: Wire mgmt_core.\la_output [90] is used but has no driver.
Warning: Wire mgmt_core.\la_output [89] is used but has no driver.
Warning: Wire mgmt_core.\la_output [88] is used but has no driver.
Warning: Wire mgmt_core.\la_output [87] is used but has no driver.
Warning: Wire mgmt_core.\la_output [86] is used but has no driver.
Warning: Wire mgmt_core.\la_output [85] is used but has no driver.
Warning: Wire mgmt_core.\la_output [84] is used but has no driver.
Warning: Wire mgmt_core.\la_output [83] is used but has no driver.
Warning: Wire mgmt_core.\la_output [82] is used but has no driver.
Warning: Wire mgmt_core.\la_output [81] is used but has no driver.
Warning: Wire mgmt_core.\la_output [80] is used but has no driver.
Warning: Wire mgmt_core.\la_output [79] is used but has no driver.
Warning: Wire mgmt_core.\la_output [78] is used but has no driver.
Warning: Wire mgmt_core.\la_output [77] is used but has no driver.
Warning: Wire mgmt_core.\la_output [76] is used but has no driver.
Warning: Wire mgmt_core.\la_output [75] is used but has no driver.
Warning: Wire mgmt_core.\la_output [74] is used but has no driver.
Warning: Wire mgmt_core.\la_output [73] is used but has no driver.
Warning: Wire mgmt_core.\la_output [72] is used but has no driver.
Warning: Wire mgmt_core.\la_output [71] is used but has no driver.
Warning: Wire mgmt_core.\la_output [70] is used but has no driver.
Warning: Wire mgmt_core.\la_output [69] is used but has no driver.
Warning: Wire mgmt_core.\la_output [68] is used but has no driver.
Warning: Wire mgmt_core.\la_output [67] is used but has no driver.
Warning: Wire mgmt_core.\la_output [66] is used but has no driver.
Warning: Wire mgmt_core.\la_output [65] is used but has no driver.
Warning: Wire mgmt_core.\la_output [64] is used but has no driver.
Warning: Wire mgmt_core.\la_output [63] is used but has no driver.
Warning: Wire mgmt_core.\la_output [62] is used but has no driver.
Warning: Wire mgmt_core.\la_output [61] is used but has no driver.
Warning: Wire mgmt_core.\la_output [60] is used but has no driver.
Warning: Wire mgmt_core.\la_output [59] is used but has no driver.
Warning: Wire mgmt_core.\la_output [58] is used but has no driver.
Warning: Wire mgmt_core.\la_output [57] is used but has no driver.
Warning: Wire mgmt_core.\la_output [56] is used but has no driver.
Warning: Wire mgmt_core.\la_output [55] is used but has no driver.
Warning: Wire mgmt_core.\la_output [54] is used but has no driver.
Warning: Wire mgmt_core.\la_output [53] is used but has no driver.
Warning: Wire mgmt_core.\la_output [52] is used but has no driver.
Warning: Wire mgmt_core.\la_output [51] is used but has no driver.
Warning: Wire mgmt_core.\la_output [50] is used but has no driver.
Warning: Wire mgmt_core.\la_output [49] is used but has no driver.
Warning: Wire mgmt_core.\la_output [48] is used but has no driver.
Warning: Wire mgmt_core.\la_output [47] is used but has no driver.
Warning: Wire mgmt_core.\la_output [46] is used but has no driver.
Warning: Wire mgmt_core.\la_output [45] is used but has no driver.
Warning: Wire mgmt_core.\la_output [44] is used but has no driver.
Warning: Wire mgmt_core.\la_output [43] is used but has no driver.
Warning: Wire mgmt_core.\la_output [42] is used but has no driver.
Warning: Wire mgmt_core.\la_output [41] is used but has no driver.
Warning: Wire mgmt_core.\la_output [40] is used but has no driver.
Warning: Wire mgmt_core.\la_output [39] is used but has no driver.
Warning: Wire mgmt_core.\la_output [38] is used but has no driver.
Warning: Wire mgmt_core.\la_output [37] is used but has no driver.
Warning: Wire mgmt_core.\la_output [36] is used but has no driver.
Warning: Wire mgmt_core.\la_output [35] is used but has no driver.
Warning: Wire mgmt_core.\la_output [34] is used but has no driver.
Warning: Wire mgmt_core.\la_output [33] is used but has no driver.
Warning: Wire mgmt_core.\la_output [32] is used but has no driver.
Warning: Wire mgmt_core.\la_output [31] is used but has no driver.
Warning: Wire mgmt_core.\la_output [30] is used but has no driver.
Warning: Wire mgmt_core.\la_output [29] is used but has no driver.
Warning: Wire mgmt_core.\la_output [28] is used but has no driver.
Warning: Wire mgmt_core.\la_output [27] is used but has no driver.
Warning: Wire mgmt_core.\la_output [26] is used but has no driver.
Warning: Wire mgmt_core.\la_output [25] is used but has no driver.
Warning: Wire mgmt_core.\la_output [24] is used but has no driver.
Warning: Wire mgmt_core.\la_output [23] is used but has no driver.
Warning: Wire mgmt_core.\la_output [22] is used but has no driver.
Warning: Wire mgmt_core.\la_output [21] is used but has no driver.
Warning: Wire mgmt_core.\la_output [20] is used but has no driver.
Warning: Wire mgmt_core.\la_output [19] is used but has no driver.
Warning: Wire mgmt_core.\la_output [18] is used but has no driver.
Warning: Wire mgmt_core.\la_output [17] is used but has no driver.
Warning: Wire mgmt_core.\la_output [16] is used but has no driver.
Warning: Wire mgmt_core.\la_output [15] is used but has no driver.
Warning: Wire mgmt_core.\la_output [14] is used but has no driver.
Warning: Wire mgmt_core.\la_output [13] is used but has no driver.
Warning: Wire mgmt_core.\la_output [12] is used but has no driver.
Warning: Wire mgmt_core.\la_output [11] is used but has no driver.
Warning: Wire mgmt_core.\la_output [10] is used but has no driver.
Warning: Wire mgmt_core.\la_output [9] is used but has no driver.
Warning: Wire mgmt_core.\la_output [8] is used but has no driver.
Warning: Wire mgmt_core.\la_output [7] is used but has no driver.
Warning: Wire mgmt_core.\la_output [6] is used but has no driver.
Warning: Wire mgmt_core.\la_output [5] is used but has no driver.
Warning: Wire mgmt_core.\la_output [4] is used but has no driver.
Warning: Wire mgmt_core.\la_output [3] is used but has no driver.
Warning: Wire mgmt_core.\la_output [2] is used but has no driver.
Warning: Wire mgmt_core.\la_output [1] is used but has no driver.
Warning: Wire mgmt_core.\la_output [0] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [127] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [126] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [125] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [124] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [123] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [122] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [121] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [120] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [119] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [118] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [117] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [116] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [115] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [114] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [113] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [112] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [111] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [110] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [109] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [108] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [107] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [106] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [105] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [104] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [103] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [102] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [101] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [100] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [99] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [98] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [97] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [96] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [95] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [94] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [93] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [92] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [91] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [90] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [89] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [88] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [87] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [86] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [85] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [84] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [83] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [82] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [81] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [80] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [79] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [78] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [77] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [76] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [75] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [74] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [73] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [72] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [71] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [70] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [69] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [68] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [67] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [66] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [65] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [64] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [63] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [62] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [61] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [60] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [59] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [58] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [57] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [56] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [55] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [54] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [53] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [52] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [51] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [50] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [49] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [48] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [47] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [46] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [45] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [44] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [43] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [42] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [41] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [40] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [39] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [38] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [37] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [36] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [35] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [34] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [33] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [32] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [31] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [30] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [29] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [28] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [27] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [26] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [25] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [24] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [23] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [22] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [21] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [20] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [19] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [18] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [17] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [16] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [15] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [14] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [13] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [12] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [11] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [10] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [9] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [8] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [7] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [6] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [5] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [4] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [3] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [2] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [1] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [0] is used but has no driver.
Warning: Wire mgmt_core.\jtag_outenb is used but has no driver.
Warning: Wire mgmt_core.\jtag_out is used but has no driver.
Warning: Wire mgmt_core.\gpio_outenb_pad is used but has no driver.
Warning: Wire mgmt_core.\gpio_out_pad is used but has no driver.
Warning: Wire mgmt_core.\gpio_mode1_pad is used but has no driver.
Warning: Wire mgmt_core.\gpio_mode0_pad is used but has no driver.
Warning: Wire mgmt_core.\gpio_inenb_pad is used but has no driver.
Warning: Wire mgmt_core.\flash_io1_oeb is used but has no driver.
Warning: Wire mgmt_core.\flash_io1_ieb is used but has no driver.
Warning: Wire mgmt_core.\flash_io1_do is used but has no driver.
Warning: Wire mgmt_core.\flash_io0_oeb is used but has no driver.
Warning: Wire mgmt_core.\flash_io0_ieb is used but has no driver.
Warning: Wire mgmt_core.\flash_io0_do is used but has no driver.
Warning: Wire mgmt_core.\flash_csb_oeb is used but has no driver.
Warning: Wire mgmt_core.\flash_csb_ieb is used but has no driver.
Warning: Wire mgmt_core.\flash_csb is used but has no driver.
Warning: Wire mgmt_core.\flash_clk_oeb is used but has no driver.
Warning: Wire mgmt_core.\flash_clk_ieb is used but has no driver.
Warning: Wire mgmt_core.\flash_clk is used but has no driver.
Warning: Wire mgmt_core.\core_rstn is used but has no driver.
Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[3] is used but has no driver.
Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[2] is used but has no driver.
Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[1] is used but has no driver.
Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[0] is used but has no driver.
Warning: Wire mgmt_core.\soc.soc_mem.mem.ena is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [31] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [30] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [29] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [28] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [27] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [26] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [25] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [24] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [23] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [22] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [21] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [20] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [19] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [18] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [17] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [16] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [15] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [14] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [13] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [12] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [11] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [10] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [9] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [8] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [7] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [6] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [5] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [4] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [3] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [2] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [0] is used but has no driver.
Warning: Wire mgmt_core.\core_clk is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [7] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [6] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [5] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [4] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [3] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [2] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [0] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[25] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[24] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[23] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[22] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[21] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[20] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[19] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[18] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[17] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[16] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[15] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[14] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[13] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[12] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[11] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[10] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[9] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[8] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[7] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[6] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[5] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[4] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[3] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[2] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[1] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[0] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_ena is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_div[4] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_div[3] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_div[2] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_div[1] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_div[0] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_dco_ena is used but has no driver.
found and reported 495 problems.

26. Printing statistics.

=== mgmt_core ===

   Number of wires:              34389
   Number of wire bits:          35122
   Number of public wires:        3633
   Number of public wire bits:    4366
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              34741
     DFFRAM                          1
     digital_pll                     1
     sky130_fd_sc_hd__a2111o_4      10
     sky130_fd_sc_hd__a2111oi_4     39
     sky130_fd_sc_hd__a211o_4      672
     sky130_fd_sc_hd__a21bo_4      152
     sky130_fd_sc_hd__a21boi_4      78
     sky130_fd_sc_hd__a21o_4       510
     sky130_fd_sc_hd__a21oi_4      199
     sky130_fd_sc_hd__a22oi_4       45
     sky130_fd_sc_hd__a2bb2o_4    1791
     sky130_fd_sc_hd__a2bb2oi_4    142
     sky130_fd_sc_hd__a32o_4       375
     sky130_fd_sc_hd__a32oi_4      216
     sky130_fd_sc_hd__and2_4      2092
     sky130_fd_sc_hd__and3_4      1719
     sky130_fd_sc_hd__and4_4        98
     sky130_fd_sc_hd__buf_1       8516
     sky130_fd_sc_hd__buf_2         54
     sky130_fd_sc_hd__conb_1        10
     sky130_fd_sc_hd__dfbbn_2       18
     sky130_fd_sc_hd__dfrtp_4      268
     sky130_fd_sc_hd__dfstp_4       70
     sky130_fd_sc_hd__dfxtp_4     3510
     sky130_fd_sc_hd__inv_8       2028
     sky130_fd_sc_hd__nand2_4      315
     sky130_fd_sc_hd__nand3_4       20
     sky130_fd_sc_hd__nand4_4        8
     sky130_fd_sc_hd__nor2_4      1186
     sky130_fd_sc_hd__nor3_4      1678
     sky130_fd_sc_hd__nor4_4        33
     sky130_fd_sc_hd__o21a_4      1055
     sky130_fd_sc_hd__o21ai_4      488
     sky130_fd_sc_hd__o22a_4      1305
     sky130_fd_sc_hd__o32a_4       100
     sky130_fd_sc_hd__o32ai_4        4
     sky130_fd_sc_hd__o41a_4         6
     sky130_fd_sc_hd__or2_4       5036
     sky130_fd_sc_hd__or3_4        254
     sky130_fd_sc_hd__or4_4        596
     sky130_fd_sc_hd__xor2_4        43

   Area for cell type \DFFRAM is unknown!
   Area for cell type \digital_pll is unknown!
   Area for cell type \sky130_fd_sc_hd__buf_2 is unknown!

   Chip area for module '\mgmt_core': 419272.115200

27. Executing Verilog backend.
Dumping module `\mgmt_core'.

Warnings: 555 unique messages, 562 total
End of script. Logfile hash: 882b99d8d4, CPU: user 121.44s system 0.47s, MEM: 219.33 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 44% 2x abc (93 sec), 14% 44x opt_expr (31 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Error: /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis.v, line 215655 syntax error, unexpected '.'.
Warning: /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis.v, line 215645 module digital_pll not found.  Creating black box for pll.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 10.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 10.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns -128.00
wns -48.55
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Error: /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis.v, line 215655 syntax error, unexpected '.'.
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF master digital_pll has no liberty cell.
Info: Added 304 rows of 4649 sites.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 2138.96
[INFO]: Core area height: 828.24
[INFO]: Changing layout from 0 to /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/verilog2def_openroad.def
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: mgmt_core
Notice 0:     Created 794 pins.
Notice 0:     Created 34740 components and 181301 component-terminals.
Notice 0:     Created 35122 nets and 111811 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/verilog2def_openroad.def
Top-level design name: mgmt_core
Warning: Some pins weren't matched by the config file
Those are: ['porb']
Assigning random sides to the above pins
Block boundaries: 0 0 2150000 850000
Writing /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/verilog2def_openroad.def to /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/ioPlacer.def
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/ioPlacer.def
Notice 0: Design: mgmt_core
Notice 0:     Created 794 pins.
Notice 0:     Created 34740 components and 181301 component-terminals.
Notice 0:     Created 35122 nets and 111811 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/ioPlacer.def
[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (2144060, 837760)
[INFO] NumInstances = 34740
[INFO] NumPlaceInstances = 34740
[INFO] NumFixedInstances = 0
[INFO] NumDummyInstances = 0
[INFO] NumNets = 35122
[INFO] NumPins = 112605
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (2150000, 850000)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (2144060, 837760)
[INFO] CoreArea = 1768315955200
[INFO] NonPlaceInstsArea = 0
[INFO] PlaceInstsArea = 471025980800
[INFO] Util(%) = 26.636982
[INFO] StdInstsArea = 419542374400
[INFO] MacroInstsArea = 51483606400
[InitialPlace]  Iter: 1 CG Error: 0.00996169 HPWL: 1799690870
[InitialPlace]  Iter: 2 CG Error: 0.0109763 HPWL: 997292889
[InitialPlace]  Iter: 3 CG Error: 0.00470546 HPWL: 907355928
[InitialPlace]  Iter: 4 CG Error: 0.00147723 HPWL: 855207203
[InitialPlace]  Iter: 5 CG Error: 0.000142691 HPWL: 826816832
[InitialPlace]  Iter: 6 CG Error: 4.53307e-05 HPWL: 811778892
[InitialPlace]  Iter: 7 CG Error: 0.000100819 HPWL: 805745830
[InitialPlace]  Iter: 8 CG Error: 0.00012309 HPWL: 802686386
[InitialPlace]  Iter: 9 CG Error: 8.16292e-05 HPWL: 800009824
[InitialPlace]  Iter: 10 CG Error: 7.28909e-05 HPWL: 797481037
[InitialPlace]  Iter: 11 CG Error: 9.7066e-05 HPWL: 794652951
[InitialPlace]  Iter: 12 CG Error: 6.94361e-05 HPWL: 792210301
[InitialPlace]  Iter: 13 CG Error: 8.59751e-05 HPWL: 789710077
[InitialPlace]  Iter: 14 CG Error: 0.000241055 HPWL: 787850775
[InitialPlace]  Iter: 15 CG Error: 8.30105e-05 HPWL: 788911881
[InitialPlace]  Iter: 16 CG Error: 7.99657e-05 HPWL: 786870090
[InitialPlace]  Iter: 17 CG Error: 6.40309e-05 HPWL: 784946388
[InitialPlace]  Iter: 18 CG Error: 7.39355e-05 HPWL: 783207535
[InitialPlace]  Iter: 19 CG Error: 7.72509e-05 HPWL: 781293025
[InitialPlace]  Iter: 20 CG Error: 6.66733e-05 HPWL: 779513586
[INFO] FillerInit: NumGCells = 74918
[INFO] FillerInit: NumGNets = 35122
[INFO] FillerInit: NumGPins = 112605
[INFO] TargetDensity = 0.520000
[INFO] AveragePlaceInstArea = 13558606
[INFO] IdealBinArea = 26074244
[INFO] IdealBinCnt = 67818
[INFO] TotalBinArea = 1768315955200
[INFO] BinCnt = (256, 256)
[INFO] BinSize = (8354, 3230)
[INFO] NumBins = 65536
[NesterovSolve] Iter: 1 overflow: 0.931267 HPWL: 558610427
[NesterovSolve] Iter: 10 overflow: 0.916798 HPWL: 639781935
[NesterovSolve] Iter: 20 overflow: 0.910754 HPWL: 669559566
[NesterovSolve] Iter: 30 overflow: 0.908911 HPWL: 678486601
[NesterovSolve] Iter: 40 overflow: 0.906909 HPWL: 679476353
[NesterovSolve] Iter: 50 overflow: 0.905693 HPWL: 681037393
[NesterovSolve] Iter: 60 overflow: 0.905371 HPWL: 683326346
[NesterovSolve] Iter: 70 overflow: 0.904943 HPWL: 684740423
[NesterovSolve] Iter: 80 overflow: 0.904412 HPWL: 685200318
[NesterovSolve] Iter: 90 overflow: 0.904135 HPWL: 685411315
[NesterovSolve] Iter: 100 overflow: 0.904035 HPWL: 685635030
[NesterovSolve] Iter: 110 overflow: 0.903886 HPWL: 685546945
[NesterovSolve] Iter: 120 overflow: 0.903601 HPWL: 685310289
[NesterovSolve] Iter: 130 overflow: 0.903078 HPWL: 685373153
[NesterovSolve] Iter: 140 overflow: 0.902449 HPWL: 686095986
[NesterovSolve] Iter: 150 overflow: 0.901862 HPWL: 687787403
[NesterovSolve] Iter: 160 overflow: 0.901122 HPWL: 690743342
[NesterovSolve] Iter: 170 overflow: 0.899807 HPWL: 695836325
[NesterovSolve] Iter: 180 overflow: 0.89769 HPWL: 704843048
[NesterovSolve] Iter: 190 overflow: 0.893683 HPWL: 718589054
[NesterovSolve] Iter: 200 overflow: 0.888803 HPWL: 735681610
[NesterovSolve] Iter: 210 overflow: 0.882037 HPWL: 760209125
[NesterovSolve] Iter: 220 overflow: 0.873412 HPWL: 795815425
[NesterovSolve] Iter: 230 overflow: 0.863765 HPWL: 836924457
[NesterovSolve] Iter: 240 overflow: 0.85333 HPWL: 880586630
[NesterovSolve] Iter: 250 overflow: 0.842069 HPWL: 912128233
[NesterovSolve] Iter: 260 overflow: 0.825822 HPWL: 951814423
[NesterovSolve] Iter: 270 overflow: 0.806289 HPWL: 1045168835
[NesterovSolve] Iter: 280 overflow: 0.788954 HPWL: 1086815793
[NesterovSolve] Iter: 290 overflow: 0.766312 HPWL: 1250972881
[NesterovSolve] Iter: 300 overflow: 0.74185 HPWL: 1351573162
[NesterovSolve] Iter: 310 overflow: 0.708736 HPWL: 1423220688
[NesterovSolve] Iter: 320 overflow: 0.670231 HPWL: 1554094053
[NesterovSolve] Iter: 330 overflow: 0.631868 HPWL: 1681017112
[NesterovSolve] Iter: 340 overflow: 0.596883 HPWL: 1728041170
[NesterovSolve] Iter: 350 overflow: 0.548034 HPWL: 1808322875
[NesterovSolve] Iter: 360 overflow: 0.495997 HPWL: 1948080259
[NesterovSolve] Iter: 370 overflow: 0.443583 HPWL: 2039336511
[NesterovSolve] Iter: 380 overflow: 0.406081 HPWL: 2108380394
[NesterovSolve] Iter: 390 overflow: 0.378672 HPWL: 2103857001
[NesterovSolve] Iter: 400 overflow: 0.349877 HPWL: 2077699337
[NesterovSolve] Iter: 410 overflow: 0.321619 HPWL: 2106088091
[NesterovSolve] Iter: 420 overflow: 0.295282 HPWL: 2133408651
[NesterovSolve] Iter: 430 overflow: 0.269362 HPWL: 2152448301
[NesterovSolve] Iter: 440 overflow: 0.242019 HPWL: 2169905023
[NesterovSolve] Iter: 450 overflow: 0.220002 HPWL: 2185850804
[NesterovSolve] Iter: 460 overflow: 0.195495 HPWL: 2202188677
[NesterovSolve] Iter: 470 overflow: 0.172051 HPWL: 2215519349
[NesterovSolve] Iter: 480 overflow: 0.151688 HPWL: 2226014097
[NesterovSolve] Iter: 490 overflow: 0.134351 HPWL: 2236225378
[NesterovSolve] Iter: 500 overflow: 0.116675 HPWL: 2246860214
[NesterovSolve] Iter: 510 overflow: 0.102261 HPWL: 2258276984
[NesterovSolve] Finished with Overflow: 0.0992196
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 10.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 10.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/ioPlacer.def to /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/replace.def
[INFO]:  Manual Macro Placement...
Placing the following macros:
{'pll': ['14360', '256399', 'N'], 'soc.soc_mem.mem.SRAM': ['1333285', '123980', 'N']}
Placing  pll
[INFO]: Changing layout from /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/replace.def to /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/replace.def.macro_placement.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/replace.def.macro_placement.def
Notice 0: Design: mgmt_core
Notice 0:     Created 794 pins.
Notice 0:     Created 34740 components and 181301 component-terminals.
Notice 0:     Created 35122 nets and 111811 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/replace.def.macro_placement.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 1
[INFO] #Original rows: 304
[INFO] #Cut rows: 88
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 608
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 22458
Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/replace.def.macro_placement.def to /project/openlane/mgmt_core/runs/mgmt_core/results/floorplan/mgmt_core.floorplan.def
[INFO]: Running Placement...
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/results/floorplan/mgmt_core.floorplan.def
Notice 0: Design: mgmt_core
Notice 0:     Created 794 pins.
Notice 0:     Created 57806 components and 227433 component-terminals.
Notice 0:     Created 35122 nets and 111811 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/results/floorplan/mgmt_core.floorplan.def
[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (2144060, 837760)
[INFO] NumInstances = 57978
[INFO] NumPlaceInstances = 34739
[INFO] NumFixedInstances = 23067
[INFO] NumDummyInstances = 172
[INFO] NumNets = 35122
[INFO] NumPins = 112605
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (2150000, 850000)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (2144060, 837760)
[INFO] CoreArea = 1768315955200
[INFO] NonPlaceInstsArea = 88851945600
[INFO] PlaceInstsArea = 419542374400
[INFO] Util(%) = 24.980728
[INFO] StdInstsArea = 419542374400
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 0.00861112 HPWL: 2560533189
[InitialPlace]  Iter: 2 CG Error: 0.0384048 HPWL: 1092143942
[InitialPlace]  Iter: 3 CG Error: 0.00553817 HPWL: 996783652
[InitialPlace]  Iter: 4 CG Error: 0.00168154 HPWL: 916721756
[InitialPlace]  Iter: 5 CG Error: 0.000682243 HPWL: 863124957
[InitialPlace]  Iter: 6 CG Error: 0.000101434 HPWL: 829806318
[InitialPlace]  Iter: 7 CG Error: 3.70421e-05 HPWL: 800824602
[InitialPlace]  Iter: 8 CG Error: 3.0077e-05 HPWL: 794230728
[InitialPlace]  Iter: 9 CG Error: 2.70246e-05 HPWL: 791554351
[InitialPlace]  Iter: 10 CG Error: 2.3387e-05 HPWL: 789853394
[InitialPlace]  Iter: 11 CG Error: 1.83705e-05 HPWL: 788017738
[InitialPlace]  Iter: 12 CG Error: 1.67157e-05 HPWL: 786446291
[InitialPlace]  Iter: 13 CG Error: 1.38494e-05 HPWL: 785213135
[InitialPlace]  Iter: 14 CG Error: 1.11248e-05 HPWL: 784149662
[InitialPlace]  Iter: 15 CG Error: 7.9403e-06 HPWL: 782927780
[INFO] FillerInit: NumGCells = 73267
[INFO] FillerInit: NumGNets = 35122
[INFO] FillerInit: NumGPins = 112605
[INFO] TargetDensity = 0.520000
[INFO] AveragePlaceInstArea = 12076984
[INFO] IdealBinArea = 23224970
[INFO] IdealBinCnt = 76138
[INFO] TotalBinArea = 1768315955200
[INFO] BinCnt = (256, 256)
[INFO] BinSize = (8354, 3230)
[INFO] NumBins = 65536
[NesterovSolve] Iter: 1 overflow: 0.990739 HPWL: 569359777
[NesterovSolve] Iter: 10 overflow: 0.970949 HPWL: 677207935
[NesterovSolve] Iter: 20 overflow: 0.961576 HPWL: 714691395
[NesterovSolve] Iter: 30 overflow: 0.958978 HPWL: 723394255
[NesterovSolve] Iter: 40 overflow: 0.956544 HPWL: 725070728
[NesterovSolve] Iter: 50 overflow: 0.954865 HPWL: 728476878
[NesterovSolve] Iter: 60 overflow: 0.954558 HPWL: 730726637
[NesterovSolve] Iter: 70 overflow: 0.954286 HPWL: 730785915
[NesterovSolve] Iter: 80 overflow: 0.954324 HPWL: 730622870
[NesterovSolve] Iter: 90 overflow: 0.954158 HPWL: 730863409
[NesterovSolve] Iter: 100 overflow: 0.953704 HPWL: 730498220
[NesterovSolve] Iter: 110 overflow: 0.953375 HPWL: 729523376
[NesterovSolve] Iter: 120 overflow: 0.952993 HPWL: 728722308
[NesterovSolve] Iter: 130 overflow: 0.952557 HPWL: 728417138
[NesterovSolve] Iter: 140 overflow: 0.952001 HPWL: 728703293
[NesterovSolve] Iter: 150 overflow: 0.95133 HPWL: 729665375
[NesterovSolve] Iter: 160 overflow: 0.950628 HPWL: 732005206
[NesterovSolve] Iter: 170 overflow: 0.949316 HPWL: 736620848
[NesterovSolve] Iter: 180 overflow: 0.947097 HPWL: 745126538
[NesterovSolve] Iter: 190 overflow: 0.943301 HPWL: 757550272
[NesterovSolve] Iter: 200 overflow: 0.938186 HPWL: 773677396
[NesterovSolve] Iter: 210 overflow: 0.931605 HPWL: 795803252
[NesterovSolve] Iter: 220 overflow: 0.922833 HPWL: 825393939
[NesterovSolve] Iter: 230 overflow: 0.912254 HPWL: 861703869
[NesterovSolve] Iter: 240 overflow: 0.901406 HPWL: 898516411
[NesterovSolve] Iter: 250 overflow: 0.890252 HPWL: 925092198
[NesterovSolve] Iter: 260 overflow: 0.876297 HPWL: 965486286
[NesterovSolve] Iter: 270 overflow: 0.856797 HPWL: 1048030531
[NesterovSolve] Iter: 280 overflow: 0.837027 HPWL: 1105487129
[NesterovSolve] Iter: 290 overflow: 0.81007 HPWL: 1259552061
[NesterovSolve] Iter: 300 overflow: 0.784551 HPWL: 1373697695
[NesterovSolve] Iter: 310 overflow: 0.75127 HPWL: 1449935745
[NesterovSolve] Iter: 320 overflow: 0.709413 HPWL: 1566177640
[NesterovSolve] Iter: 330 overflow: 0.681439 HPWL: 1690772602
[NesterovSolve] Iter: 340 overflow: 0.642446 HPWL: 1757177403
[NesterovSolve] Iter: 350 overflow: 0.594544 HPWL: 1797885673
[NesterovSolve] Iter: 360 overflow: 0.535305 HPWL: 1901236311
[NesterovSolve] Iter: 370 overflow: 0.492657 HPWL: 1977644338
[NesterovSolve] Iter: 380 overflow: 0.455676 HPWL: 2034360274
[NesterovSolve] Iter: 390 overflow: 0.414807 HPWL: 2097340019
[NesterovSolve] Iter: 400 overflow: 0.375058 HPWL: 2151342675
[NesterovSolve] Iter: 410 overflow: 0.338699 HPWL: 2195515256
[NesterovSolve] Iter: 420 overflow: 0.312978 HPWL: 2208778823
[NesterovSolve] Iter: 430 overflow: 0.290187 HPWL: 2181627146
[NesterovSolve] Iter: 440 overflow: 0.268228 HPWL: 2208309670
[NesterovSolve] Iter: 450 overflow: 0.242378 HPWL: 2233461702
[NesterovSolve] Iter: 460 overflow: 0.21937 HPWL: 2257661295
[NesterovSolve] Iter: 470 overflow: 0.194238 HPWL: 2276930699
[NesterovSolve] Iter: 480 overflow: 0.170584 HPWL: 2294169130
[NesterovSolve] Iter: 490 overflow: 0.149997 HPWL: 2309474240
[NesterovSolve] Iter: 500 overflow: 0.131586 HPWL: 2323837312
[NesterovSolve] Iter: 510 overflow: 0.114444 HPWL: 2337743409
[NesterovSolve] Iter: 520 overflow: 0.100493 HPWL: 2350472776
[NesterovSolve] Finished with Overflow: 0.0993933
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 10.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 10.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/mgmt_core/runs/mgmt_core/results/floorplan/mgmt_core.floorplan.def to /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/replace.def
[INFO]: Running OpenPhySyn Timing Optimization...
[INFO]: Trimming Liberty...
[OpenPhySyn] [2020-11-20 15:35:27.513] [info] Loaded 6 transforms.
[OpenPhySyn] [2020-11-20 15:35:29.860] [info] OpenPhySyn: 1.8.1
Warning: /project/openlane/mgmt_core/runs/mgmt_core/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/replace.def
Notice 0: Design: mgmt_core
Notice 0:     Created 794 pins.
Notice 0:     Created 57806 components and 227433 component-terminals.
Notice 0:     Created 35122 nets and 111811 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/replace.def
[INFO]: Setting output delay to: 10.0
[INFO]: Setting input delay to: 10.0
[INFO]: Setting load to: 0.01765
=============== Initial Reports =============
Startpoint: _63543_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: _65267_ (recovery check against rising-edge clock clock)
Path Group: **async_default**
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _63543_/CLK (sky130_fd_sc_hd__dfstp_4)
   0.87    0.87 v _63543_/Q (sky130_fd_sc_hd__dfstp_4)
   0.87    1.74 v _58132_/X (sky130_fd_sc_hd__or4_4)
   0.45    2.19 v _58133_/X (sky130_fd_sc_hd__buf_1)
   0.20    2.39 ^ _58134_/Y (sky130_fd_sc_hd__inv_8)
   0.37    2.77 ^ _58135_/X (sky130_fd_sc_hd__buf_1)
   0.42    3.18 ^ _58136_/X (sky130_fd_sc_hd__buf_1)
   0.32    3.51 ^ _58137_/X (sky130_fd_sc_hd__buf_1)
   0.33    3.83 ^ _58138_/X (sky130_fd_sc_hd__buf_1)
   0.31    4.15 ^ _58139_/X (sky130_fd_sc_hd__buf_1)
   0.35    4.49 ^ _58140_/X (sky130_fd_sc_hd__buf_1)
   0.52    5.01 ^ _58141_/X (sky130_fd_sc_hd__buf_1)
  10.21   15.22 ^ _58142_/X (sky130_fd_sc_hd__buf_1)
   0.50   15.73 ^ _65267_/RESET_B (sky130_fd_sc_hd__dfrtp_4)
          15.73   data arrival time

  50.00   50.00   clock clock (rise edge)
   0.00   50.00   clock network delay (ideal)
   0.00   50.00   clock reconvergence pessimism
          50.00 ^ _65267_/CLK (sky130_fd_sc_hd__dfrtp_4)
  -8.24   41.76   library recovery time
          41.76   data required time
---------------------------------------------------------
          41.76   data required time
         -15.73   data arrival time
---------------------------------------------------------
          26.03   slack (MET)


Startpoint: _65197_ (rising edge-triggered flip-flop)
Endpoint: mgmt_out_data[14] (output port clocked by clock)
Path Group: clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00 ^ _65197_/CLK (sky130_fd_sc_hd__dfstp_4)
   1.35    1.35 ^ _65197_/Q (sky130_fd_sc_hd__dfstp_4)
   0.27    1.62 ^ _55999_/Y (sky130_fd_sc_hd__a2bb2oi_4)
   0.33    1.95 ^ _56000_/X (sky130_fd_sc_hd__a32o_4)
   0.24    2.19 ^ _56004_/X (sky130_fd_sc_hd__a21bo_4)
  77.22   79.41 ^ _56005_/X (sky130_fd_sc_hd__buf_1)
  15.60   95.01 v _56006_/Y (sky130_fd_sc_hd__inv_8)
   2.58   97.59 ^ _57115_/X (sky130_fd_sc_hd__a2bb2o_4)
   0.00   97.59 ^ mgmt_out_data[14] (out)
          97.59   data arrival time

  50.00   50.00   clock clock (rise edge)
   0.00   50.00   clock network delay (ideal)
   0.00   50.00   clock reconvergence pessimism
 -10.00   40.00   output external delay
          40.00   data required time
---------------------------------------------------------
          40.00   data required time
         -97.59   data arrival time
---------------------------------------------------------
         -57.59   slack (VIOLATED)


max slew

Pin                                    Limit    Slew   Slack
------------------------------------------------------------
_65267_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65260_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65263_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65264_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65265_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65258_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65259_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65257_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65262_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65266_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65268_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65256_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65261_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65269_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65254_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65255_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65253_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_64831_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_64830_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_64832_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_63594_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_64829_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65251_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65252_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_64827_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_64833_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_64834_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_64828_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_64824_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65250_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_64825_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65249_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65230_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65227_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65228_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65229_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65280_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65278_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65277_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65270_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65271_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65272_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65274_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65276_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65273_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65275_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65237_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65244_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65236_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65238_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65235_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65234_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65233_/RESET_B                         1.50   16.91  -15.41 (VIOLATED)
_65279_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65231_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65232_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65248_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65282_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65281_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65283_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64822_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64823_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64826_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65225_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65226_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64785_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64787_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64792_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65240_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65241_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65242_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65243_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64791_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65245_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65246_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65247_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64789_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64790_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64523_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64788_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64786_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64815_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64813_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64521_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64519_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64525_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64520_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64795_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65212_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64793_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64794_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64797_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64798_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65211_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65239_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65208_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65210_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65209_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64526_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64524_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64783_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64522_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64527_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64528_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64529_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64784_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64814_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63855_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64816_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63854_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63852_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63583_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63584_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63839_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_63849_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63853_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63856_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63857_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63841_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_63848_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63840_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_63585_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63838_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_63847_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63850_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64530_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64531_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64796_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65213_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65214_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65215_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63593_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63842_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_63851_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64817_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63843_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_63837_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_63582_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_63836_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_64819_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64820_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63835_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63858_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64533_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64849_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63845_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_64861_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_63603_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_63846_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_64868_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_64847_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64862_/SET_B                           1.50   16.90  -15.40 (VIOLATED)
_64534_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64799_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64800_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64810_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64811_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64821_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_65224_/RESET_B                         1.50   16.90  -15.40 (VIOLATED)
_64532_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64809_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64812_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64818_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64863_/SET_B                           1.50   16.89  -15.39 (VIOLATED)
_64867_/SET_B                           1.50   16.89  -15.39 (VIOLATED)
_64854_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63844_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64855_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64864_/SET_B                           1.50   16.89  -15.39 (VIOLATED)
_64865_/SET_B                           1.50   16.89  -15.39 (VIOLATED)
_64866_/SET_B                           1.50   16.89  -15.39 (VIOLATED)
_64846_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64851_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64801_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64802_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_65216_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_65217_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_65218_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_65219_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_65220_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64928_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64860_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64856_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63598_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63602_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64803_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64804_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64805_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64806_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_65221_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63868_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64848_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_65222_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_65223_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64850_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64859_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63597_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64853_/SET_B                           1.50   16.89  -15.39 (VIOLATED)
_63595_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64858_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64852_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63596_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63601_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64857_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63599_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63600_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63940_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63942_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63943_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63937_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63939_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63941_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_64449_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63938_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63935_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63932_/SET_B                           1.50   16.89  -15.39 (VIOLATED)
_63936_/SET_B                           1.50   16.89  -15.39 (VIOLATED)
_63934_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_63933_/SET_B                           1.50   16.89  -15.39 (VIOLATED)
_63931_/RESET_B                         1.50   16.89  -15.39 (VIOLATED)
_38636_/B2                              1.50   16.89  -15.39 (VIOLATED)
_38307_/B1                              1.50   16.89  -15.39 (VIOLATED)
_42073_/B1                              1.50   16.89  -15.39 (VIOLATED)
_58142_/X                               1.51   16.89  -15.38 (VIOLATED)

max capacitance

Pin                                    Limit     Cap   Slack
------------------------------------------------------------
_58142_/X                               0.08    0.78   -0.70 (VIOLATED)

Capacitance violations: 1
Transition violations: 224
wns -57.59
tns -151.18
Initial area: 5012983 um2
OpenPhySyn timing repair:
[OpenPhySyn] [2020-11-20 15:36:46.407] [info] Invoking repair_timing transform
[OpenPhySyn] [2020-11-20 15:36:47.281] [info] Buffer library: sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_1
[OpenPhySyn] [2020-11-20 15:36:47.288] [info] Inverter library: None
[OpenPhySyn] [2020-11-20 15:36:47.288] [info] Buffering: enabled
[OpenPhySyn] [2020-11-20 15:36:47.288] [info] Driver sizing: enabled
[OpenPhySyn] [2020-11-20 15:36:47.289] [info] Pin-swapping: enabled
[OpenPhySyn] [2020-11-20 15:36:47.289] [info] Mode: Timing-Driven
[OpenPhySyn] [2020-11-20 15:36:47.289] [info] Iteration 1
[OpenPhySyn] [2020-11-20 15:37:10.714] [info] Found 18 negative slack paths
[OpenPhySyn] [2020-11-20 15:37:19.768] [warning] Top-level
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Runtime: 85s
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Buffers: 789
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Resize up: 2
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Resize down: 0
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Pin Swap: 2
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Buffered nets: 29
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Fanout violations: 0
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Transition violations: 224
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Capacitance violations: 1
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Slack gain: 6.7824e-09
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Initial area: 501298
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] New area: 504622
[OpenPhySyn] [2020-11-20 15:38:13.061] [info] Finished repair_timing transform (793)
Added/updated 793 cells
=============== Final Reports =============
Startpoint: resetb (input port clocked by clock)
Endpoint: _63543_ (recovery check against rising-edge clock clock)
Path Group: **async_default**
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
   0.00    0.00   clock network delay (ideal)
  10.00   10.00 ^ input external delay
   0.21   10.21 ^ resetb (in)
   0.00   10.21 ^ _63543_/SET_B (sky130_fd_sc_hd__dfstp_4)
          10.21   data arrival time

  50.00   50.00   clock clock (rise edge)
   0.00   50.00   clock network delay (ideal)
   0.00   50.00   clock reconvergence pessimism
          50.00 ^ _63543_/CLK (sky130_fd_sc_hd__dfstp_4)
   0.21   50.21   library recovery time
          50.21   data required time
---------------------------------------------------------
          50.21   data required time
         -10.21   data arrival time
---------------------------------------------------------
          40.00   slack (MET)


Startpoint: _64705_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: _64671_ (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _64705_/CLK (sky130_fd_sc_hd__dfxtp_4)
   0.73    0.73 ^ _64705_/Q (sky130_fd_sc_hd__dfxtp_4)
   0.07    0.80 v _31161_/Y (sky130_fd_sc_hd__inv_8)
   0.24    1.04 v _31162_/X (sky130_fd_sc_hd__and2_4)
   0.32    1.35 v _31163_/X (sky130_fd_sc_hd__a21o_4)
   1.06    2.42 v _31176_/X (sky130_fd_sc_hd__or4_4)
   0.47    2.88 ^ _31223_/Y (sky130_fd_sc_hd__nor4_4)
   0.29    3.17 ^ _31224_/X (sky130_fd_sc_hd__or4_4)
   0.37    3.54 ^ _31225_/X (sky130_fd_sc_hd__and3_4)
   0.45    3.99 ^ _31226_/X (sky130_fd_sc_hd__buf_1)
   0.12    4.11 v _31227_/Y (sky130_fd_sc_hd__inv_8)
   0.46    4.56 v _31228_/X (sky130_fd_sc_hd__or2_4)
   0.63    5.20 v _34823_/X (sky130_fd_sc_hd__or3_4)
   0.34    5.54 v _34824_/X (sky130_fd_sc_hd__buf_1)
   0.59    6.13 v _37712_/X (sky130_fd_sc_hd__or2_4)
   0.09    6.22 ^ _37713_/Y (sky130_fd_sc_hd__inv_8)
   0.25    6.47 ^ _37714_/X (sky130_fd_sc_hd__and2_4)
   0.41    6.89 ^ _37715_/X (sky130_fd_sc_hd__buf_1)
   0.40    7.29 ^ _37716_/X (sky130_fd_sc_hd__and2_4)
   0.42    7.70 ^ _37717_/X (sky130_fd_sc_hd__buf_1)
   0.40    8.10 ^ _37718_/X (sky130_fd_sc_hd__and2_4)
   0.43    8.53 ^ _37719_/X (sky130_fd_sc_hd__buf_1)
   0.42    8.95 ^ _37720_/X (sky130_fd_sc_hd__and2_4)
   0.42    9.37 ^ _37721_/X (sky130_fd_sc_hd__buf_1)
   0.40    9.77 ^ _37722_/X (sky130_fd_sc_hd__and2_4)
   0.42   10.18 ^ _37723_/X (sky130_fd_sc_hd__buf_1)
   0.40   10.58 ^ _37724_/X (sky130_fd_sc_hd__and2_4)
   0.42   11.00 ^ _37725_/X (sky130_fd_sc_hd__buf_1)
   0.40   11.39 ^ _37726_/X (sky130_fd_sc_hd__and2_4)
   0.42   11.81 ^ _37727_/X (sky130_fd_sc_hd__buf_1)
   0.40   12.21 ^ _37728_/X (sky130_fd_sc_hd__and2_4)
   0.42   12.62 ^ _37729_/X (sky130_fd_sc_hd__buf_1)
   0.40   13.02 ^ _37730_/X (sky130_fd_sc_hd__and2_4)
   0.42   13.44 ^ _37731_/X (sky130_fd_sc_hd__buf_1)
   0.40   13.84 ^ _37732_/X (sky130_fd_sc_hd__and2_4)
   0.42   14.25 ^ _37733_/X (sky130_fd_sc_hd__buf_1)
   0.40   14.65 ^ _37734_/X (sky130_fd_sc_hd__and2_4)
   0.42   15.07 ^ _37735_/X (sky130_fd_sc_hd__buf_1)
   0.40   15.47 ^ _37736_/X (sky130_fd_sc_hd__and2_4)
   0.42   15.88 ^ _37737_/X (sky130_fd_sc_hd__buf_1)
   0.40   16.28 ^ _37738_/X (sky130_fd_sc_hd__and2_4)
   0.42   16.70 ^ _37739_/X (sky130_fd_sc_hd__buf_1)
   0.40   17.09 ^ _37740_/X (sky130_fd_sc_hd__and2_4)
   0.43   17.52 ^ _37741_/X (sky130_fd_sc_hd__buf_1)
   0.42   17.94 ^ _37742_/X (sky130_fd_sc_hd__and2_4)
   0.42   18.37 ^ _37743_/X (sky130_fd_sc_hd__buf_1)
   0.42   18.79 ^ _37744_/X (sky130_fd_sc_hd__and2_4)
   0.42   19.21 ^ _37745_/X (sky130_fd_sc_hd__buf_1)
   0.40   19.61 ^ _37746_/X (sky130_fd_sc_hd__and2_4)
   0.42   20.02 ^ _37747_/X (sky130_fd_sc_hd__buf_1)
   0.40   20.42 ^ _37748_/X (sky130_fd_sc_hd__and2_4)
   0.42   20.84 ^ _37749_/X (sky130_fd_sc_hd__buf_1)
   0.40   21.24 ^ _37750_/X (sky130_fd_sc_hd__and2_4)
   0.42   21.66 ^ _37751_/X (sky130_fd_sc_hd__buf_1)
   0.42   22.08 ^ _37752_/X (sky130_fd_sc_hd__and2_4)
   0.42   22.50 ^ _37753_/X (sky130_fd_sc_hd__buf_1)
   0.40   22.90 ^ _37754_/X (sky130_fd_sc_hd__and2_4)
   0.42   23.32 ^ _37755_/X (sky130_fd_sc_hd__buf_1)
   0.40   23.71 ^ _37756_/X (sky130_fd_sc_hd__and2_4)
   0.42   24.13 ^ _37757_/X (sky130_fd_sc_hd__buf_1)
   0.42   24.55 ^ _37758_/X (sky130_fd_sc_hd__and2_4)
   0.42   24.97 ^ _37759_/X (sky130_fd_sc_hd__buf_1)
   0.40   25.37 ^ _37760_/X (sky130_fd_sc_hd__and2_4)
   0.42   25.78 ^ _37761_/X (sky130_fd_sc_hd__buf_1)
   0.40   26.18 ^ _37762_/X (sky130_fd_sc_hd__and2_4)
   0.42   26.60 ^ _37763_/X (sky130_fd_sc_hd__buf_1)
   0.42   27.01 ^ _37764_/X (sky130_fd_sc_hd__and2_4)
   0.42   27.43 ^ _37765_/X (sky130_fd_sc_hd__buf_1)
   0.40   27.83 ^ _37766_/X (sky130_fd_sc_hd__and2_4)
   0.42   28.25 ^ _37767_/X (sky130_fd_sc_hd__buf_1)
   0.42   28.67 ^ _37768_/X (sky130_fd_sc_hd__and2_4)
   0.42   29.09 ^ _37769_/X (sky130_fd_sc_hd__buf_1)
   0.40   29.49 ^ _37770_/X (sky130_fd_sc_hd__and2_4)
   0.42   29.90 ^ _37771_/X (sky130_fd_sc_hd__buf_1)
   0.40   30.30 ^ _37772_/X (sky130_fd_sc_hd__and2_4)
   0.42   30.72 ^ _37773_/X (sky130_fd_sc_hd__buf_1)
   0.49   31.20 ^ _37774_/X (sky130_fd_sc_hd__and2_4)
   0.07   31.27 v _37775_/Y (sky130_fd_sc_hd__inv_8)
   0.48   31.75 v _37776_/X (sky130_fd_sc_hd__or2_4)
   0.09   31.84 ^ _37777_/Y (sky130_fd_sc_hd__inv_8)
   0.25   32.09 ^ _37778_/X (sky130_fd_sc_hd__and2_4)
   0.41   32.51 ^ _37779_/X (sky130_fd_sc_hd__buf_1)
   0.40   32.91 ^ _37780_/X (sky130_fd_sc_hd__and2_4)
   0.42   33.32 ^ _37781_/X (sky130_fd_sc_hd__buf_1)
   0.40   33.72 ^ _37782_/X (sky130_fd_sc_hd__and2_4)
   0.42   34.14 ^ _37783_/X (sky130_fd_sc_hd__buf_1)
   0.40   34.54 ^ _37784_/X (sky130_fd_sc_hd__and2_4)
   0.42   34.95 ^ _37785_/X (sky130_fd_sc_hd__buf_1)
   0.40   35.35 ^ _37786_/X (sky130_fd_sc_hd__and2_4)
   0.42   35.77 ^ _37787_/X (sky130_fd_sc_hd__buf_1)
   0.40   36.17 ^ _37788_/X (sky130_fd_sc_hd__and2_4)
   0.42   36.58 ^ _37789_/X (sky130_fd_sc_hd__buf_1)
   0.40   36.98 ^ _37790_/X (sky130_fd_sc_hd__and2_4)
   0.24   37.23 ^ _37791_/X (sky130_fd_sc_hd__buf_4)
   0.28   37.51 ^ _37792_/X (sky130_fd_sc_hd__and2_4)
   0.24   37.75 ^ _37793_/X (sky130_fd_sc_hd__buf_4)
   0.29   38.04 ^ _37794_/X (sky130_fd_sc_hd__and2_4)
   0.20   38.24 ^ _37795_/X (sky130_fd_sc_hd__buf_1)
   0.30   38.54 ^ _37796_/X (sky130_fd_sc_hd__and2_4)
   0.20   38.74 ^ _37797_/X (sky130_fd_sc_hd__buf_1)
   0.30   39.03 ^ _37798_/X (sky130_fd_sc_hd__and2_4)
   0.20   39.23 ^ _37799_/X (sky130_fd_sc_hd__buf_1)
   0.30   39.53 ^ _37800_/X (sky130_fd_sc_hd__and2_4)
   0.20   39.73 ^ _37801_/X (sky130_fd_sc_hd__buf_1)
   0.30   40.02 ^ _37802_/X (sky130_fd_sc_hd__and2_4)
   0.20   40.22 ^ _37803_/X (sky130_fd_sc_hd__buf_1)
   0.29   40.51 ^ _37804_/X (sky130_fd_sc_hd__and2_4)
   0.20   40.71 ^ _37805_/X (sky130_fd_sc_hd__buf_1)
   0.30   41.01 ^ _37806_/X (sky130_fd_sc_hd__and2_4)
   0.20   41.21 ^ _37807_/X (sky130_fd_sc_hd__buf_1)
   0.29   41.50 ^ _37808_/X (sky130_fd_sc_hd__and2_4)
   0.20   41.70 ^ _37809_/X (sky130_fd_sc_hd__buf_1)
   0.30   41.99 ^ _37810_/X (sky130_fd_sc_hd__and2_4)
   0.20   42.19 ^ _37811_/X (sky130_fd_sc_hd__buf_1)
   0.29   42.48 ^ _37812_/X (sky130_fd_sc_hd__and2_4)
   0.20   42.68 ^ _37813_/X (sky130_fd_sc_hd__buf_1)
   0.29   42.97 ^ _37814_/X (sky130_fd_sc_hd__and2_4)
   0.21   43.18 ^ _37815_/X (sky130_fd_sc_hd__buf_1)
   0.30   43.48 ^ _37816_/X (sky130_fd_sc_hd__and2_4)
   0.20   43.68 ^ _37817_/X (sky130_fd_sc_hd__buf_1)
   0.29   43.97 ^ _37818_/X (sky130_fd_sc_hd__and2_4)
   0.20   44.17 ^ _37819_/X (sky130_fd_sc_hd__buf_1)
   0.29   44.46 ^ _37820_/X (sky130_fd_sc_hd__and2_4)
   0.20   44.66 ^ _37821_/X (sky130_fd_sc_hd__buf_1)
   0.29   44.95 ^ _37822_/X (sky130_fd_sc_hd__and2_4)
   0.22   45.17 ^ _37823_/X (sky130_fd_sc_hd__buf_1)
   0.31   45.48 ^ _37824_/X (sky130_fd_sc_hd__and2_4)
   0.20   45.68 ^ _37825_/X (sky130_fd_sc_hd__buf_1)
   0.29   45.97 ^ _37826_/X (sky130_fd_sc_hd__and2_4)
   0.20   46.17 ^ _37827_/X (sky130_fd_sc_hd__buf_1)
   0.29   46.46 ^ _37828_/X (sky130_fd_sc_hd__and2_4)
   0.20   46.66 ^ _37829_/X (sky130_fd_sc_hd__buf_1)
   0.29   46.95 ^ _37830_/X (sky130_fd_sc_hd__and2_4)
   0.20   47.14 ^ _37831_/X (sky130_fd_sc_hd__buf_1)
   0.29   47.44 ^ _37832_/X (sky130_fd_sc_hd__and2_4)
   0.20   47.64 ^ _37833_/X (sky130_fd_sc_hd__buf_1)
   0.30   47.93 ^ _37834_/X (sky130_fd_sc_hd__and2_4)
   0.20   48.13 ^ _37835_/X (sky130_fd_sc_hd__buf_1)
   0.30   48.43 ^ _37836_/X (sky130_fd_sc_hd__and2_4)
   0.25   48.68 ^ _37837_/X (sky130_fd_sc_hd__buf_1)
   0.31   48.98 ^ psn_inst_psn_buff_745/X (sky130_fd_sc_hd__buf_4)
   0.05   49.04 v _37841_/Y (sky130_fd_sc_hd__inv_8)
   0.26   49.30 v _37843_/X (sky130_fd_sc_hd__and3_4)
   0.00   49.30 v _64671_/D (sky130_fd_sc_hd__dfxtp_4)
          49.30   data arrival time

  50.00   50.00   clock clock (rise edge)
   0.00   50.00   clock network delay (ideal)
   0.00   50.00   clock reconvergence pessimism
          50.00 ^ _64671_/CLK (sky130_fd_sc_hd__dfxtp_4)
  -0.28   49.72   library setup time
          49.72   data required time
---------------------------------------------------------
          49.72   data required time
         -49.30   data arrival time
---------------------------------------------------------
           0.42   slack (MET)


Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Final area: 5046223 um2
Export optimized design
[INFO]: Changing layout from /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/replace.def to /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/openphysyn.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/openphysyn.def
Notice 0: Design: mgmt_core
Notice 0:     Created 794 pins.
Notice 0:     Created 58595 components and 230589 component-terminals.
Notice 0:     Created 35911 nets and 113389 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/openphysyn.def
[INFO]: Changing netlist from /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis.v to /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis_optimized.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis_optimized.v, line 111898 module digital_pll not found.  Creating black box for pll.
Warning: /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis_optimized.v, line 112543 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found.  Creating black box for PHY_608.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 10.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 10.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Running Detailed Placement...
===========================================================================
   Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 >    
   Developers : SangGi Do, Mingyu Woo                                      
===========================================================================
Parsed 10000 number of lines!!
Parsed 20000 number of lines!!
Parsed 30000 number of lines!!
Parsed 40000 number of lines!!
Parsed 50000 number of lines!!
Parsed 60000 number of lines!!
Parsed 70000 number of lines!!
Parsed 80000 number of lines!!
Reading /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged.lef is Done

-------------------- INPUT FILES ----------------------------------
 benchmark name    : placement
 directory         : /project/openlane/mgmt_core/runs/mgmt_core/tmp
 lef               : /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged.lef
 def               : /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/openphysyn.def
-------------------------------------------------------------------
Parsed 10000 number of lines!!
Parsed 20000 number of lines!!
Parsed 30000 number of lines!!
Parsed 40000 number of lines!!
Parsed 50000 number of lines!!
Parsed 60000 number of lines!!
Parsed 70000 number of lines!!
Parsed 80000 number of lines!!
Parsed 90000 number of lines!!
CoreArea: 
5520.000000 : 10880.000000 - 2144060.000000 : 837760.000000
DieArea: 
0.000000 : 0.000000 - 2138540.000000 : 826880.000000
Reading /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/openphysyn.def is Done
-------------------- DESIGN ANALYSIS ------------------------------
  total cells              : 58595
  multi cells              : 0
  fixed cells              : 23067
  total nets               : 35911
  design area              : 1.76832e+12
  total f_area             : 8.27005e+10
  total m_area             : 7.78489e+11
  design util              : 46.1843
  num rows                 : 304
  row height               : 2720
-------------------------------------------------------------------
 non_group_cell_region_assign done ..
 - - - - - - - - - - - - - - - - - - - - - - - - 
 non_group_cell_placement done .. 
 - - - - - - - - - - - - - - - - - - - - - - - - 
Reading /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/openphysyn.def is Done
 DEF file write success !! 
 location : /project/openlane/mgmt_core/runs/mgmt_core/results/placement/mgmt_core.placement.def
-------------------------------------------------------------------
 tasks                          Wtime      Ctime
 Parser                         3.019      3.000
 resgin assign                  3.033      3.010
 pre-placement                  3.033      3.010
 non Group cell placement      24.128     24.080
 All                           24.149     24.100
 - - - - - EVALUATION - - - - - 
 AVG_displacement : 23438.1
 SUM_displacement : 1.37335e+09
 MAX_displacement : 832854
 - - - - - - - - - - - - - - - - 
 GP HPWL          : 2.38718e+06
 HPWL             : 4.047e+06
 avg_Disp_site    : 50.9523
 avg_Disp_row     : 8.61693
 delta_HPWL       : 69.5306
 ==== CHECK LEGALITY ==== 
 row_check ==>> PASS 
 site_check ==>> PASS 
 power_check ==>> PASS 
 edge_check ==>> PASS 
 placed_check ==>> PASS 
 overlap_check ==>> PASS 
 - - - - - < Program END > - - - - - 
[INFO]: Changing layout from /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/openphysyn.def to /project/openlane/mgmt_core/runs/mgmt_core/results/placement/mgmt_core.placement.def
[INFO]: Running TritonCTS...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/results/placement/mgmt_core.placement.def
Notice 0: Design: mgmt_core
Notice 0:     Created 794 pins.
Notice 0:     Created 58595 components and 230589 component-terminals.
Notice 0:     Created 35911 nets and 113389 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/results/placement/mgmt_core.placement.def
Error: /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis.v, line 215655 syntax error, unexpected '.'.
[INFO]: Setting output delay to: 10.0
[INFO]: Setting input delay to: 10.0
[INFO]: Setting load to: 0.01765
[INFO]: Configuring cts characterization...
[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s): clock
 *****************
 * TritonCTS 2.0 *
 *****************
 *****************************
 *  Create characterization  *
 *****************************
Number of created patterns = 50000.
Number of created patterns = 100000.
Number of created patterns = 150000.
Number of created patterns = 200000.
Number of created patterns = 250000.
Number of created patterns = 300000.
Number of created patterns = 313632.
 Compiling LUT
    Min. len    Max. len    Min. cap    Max. cap   Min. slew   Max. slew
           2           8           1          39           1         366
    [WARNING] 6336 wires are pure wire and no slew degration.
    TritonCTS forced slew degradation on these wires.
    Num wire segments: 313632
    Num keys in characterization LUT: 2073
    Actual min input cap: 2
 **********************
 *  Find clock roots  *
 **********************
 Running TritonCTS with user-specified clock roots: clock
 ************************
 *  Populate TritonCTS  *
 ************************
 Initializing clock nets
 Looking for clock nets in the design
 Net "clock" found
 Initializing clock net for : "clock"
 Clock net "clock" has 3 sinks
 TritonCTS found 1 clock nets.
 ****************************
 *  Check characterization  *
 ****************************
    The chacterization used 4 buffer(s) types. All of them are in the loaded DB.
 ***********************
 *  Build clock trees  *
 ***********************
 Generating H-Tree topology for net clock...
    Tot. number of sinks: 3
    Number of static layers: 0
 Wire segment unit: 13000 dbu (13 um)
 Original sink region: [(111910, 304989), (259030, 393225)]
 Normalized sink region: [(8.60846, 23.4607), (19.9254, 30.2481)]
    Width:  11.3169
    Height: 6.78738
 Level 1
    Direction: Horizontal
    # sinks per sub-region: 2
    Sub-region size: 5.65846 X 6.78738
    Segment length (rounded): 2
    Key: 0 outSlew: 2 load: 1 length: 2 isBuffered: 0
 Stop criterion found. Max number of sinks is (15)
 Building clock sub nets...
 Number of sinks covered: 3
 Clock topology of net "clock" done.
 ****************
 * Post CTS opt *
 ****************
 Avg. source sink dist: 110664 dbu.
 Num outlier sinks: 0
 ********************
 * Write data to DB *
 ********************
 Writing clock net "clock" to DB
    Created 3 clock buffers.
    Minimum number of buffers in the clock path: 2.
    Maximum number of buffers in the clock path: 2.
    Created 3 clock nets.
    Fanout distribution for the current clock = 1:1, 2:1.
    Max level of the clock tree: 1.
 ... End of TritonCTS execution.
[INFO]: Legalizing...
Warning: could not find power special net
Design Stats
--------------------------------
total instances         58598
multi row instances         0
fixed instances         23067
nets                    35914
design area          1768316.0 u^2
fixed area            34620.6 u^2
movable area         422943.1 u^2
utilization                24 %
utilization padded         24 %
rows                      304
row height                2.7 u

Placement Analysis
--------------------------------
total displacement      227.1 u
average displacement      0.0 u
max displacement         89.0 u
original HPWL        4043999.4 u
legalized HPWL       4044003.5 u
delta HPWL                  0 %

[INFO]: Clock Tree Synthesis was successful
[INFO]: Changing layout from /project/openlane/mgmt_core/runs/mgmt_core/results/placement/mgmt_core.placement.def to /project/openlane/mgmt_core/runs/mgmt_core/results/cts/mgmt_core.cts.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/results/cts/mgmt_core.cts.def
Notice 0: Design: mgmt_core
Notice 0:     Created 794 pins.
Notice 0:     Created 58598 components and 230601 component-terminals.
Notice 0:     Created 35914 nets and 113395 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/results/cts/mgmt_core.cts.def
[INFO]: Changing netlist from /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis_optimized.v to /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis_cts.v
[INFO]: Generating PDN...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/results/cts/mgmt_core.cts.def
Notice 0: Design: mgmt_core
Notice 0:     Created 794 pins.
Notice 0:     Created 58598 components and 230601 component-terminals.
Notice 0:     Created 35914 nets and 113395 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/results/cts/mgmt_core.cts.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /project/openlane/mgmt_core/pdn.tcl
[INFO] [PDNG-0008] Design Name is mgmt_core
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
    Stdcell Rails
      Layer: met1 -  width: 0.480  pitch: 2.720  offset: 0.000 
    Straps
      Layer: met4 -  width: 1.600  pitch: 50.000  offset: 16.320 
      Layer: met5 -  width: 1.600  pitch: 153.180  offset: 16.650 
    Connect: {met1 met4} {met4 met5}
Type: macro, macro_1
    Straps
    Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0010] Inserting macro grid for 1 macros
[INFO] [PDNG-0034]   - grid for instance pll
[WARN] [PDNG-0040] No via added at (14.36 256.399 34.36 257.86) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (109.88 256.399 111.48 257.86) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (159.88 256.399 161.48 257.86) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (221.2 256.399 241.2 257.86) because the full height of met5 (1.6) is not covered by the overlap
[INFO] [PDNG-0015] Writing to database
[INFO]: Changing layout from /project/openlane/mgmt_core/runs/mgmt_core/results/cts/mgmt_core.cts.def to /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/pdn.def
[INFO]: Routing...
[INFO]: Running Diode Insertion...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/pdn.def
Notice 0: Design: mgmt_core
Notice 0:     Created 796 pins.
Notice 0:     Created 58598 components and 230601 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 35914 nets and 113395 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/pdn.def
[INFO]: Inserting sky130_fd_sc_hd__diode_2...
[WARN]: Skipping VPWR
[WARN]: Skipping VGND

[INFO]: 77844 of sky130_fd_sc_hd__diode_2 inserted!
[INFO]: Legalizing...
Design Stats
--------------------------------
total instances        136442
multi row instances         0
fixed instances         23067
nets                    35916
design area          1768316.0 u^2
fixed area            34620.6 u^2
movable area         617740.0 u^2
utilization                36 %
utilization padded         47 %
rows                      304
row height                2.7 u

Placement Analysis
--------------------------------
total displacement   702542.1 u
average displacement      5.1 u
max displacement        365.2 u
original HPWL        4084696.5 u
legalized HPWL       4275593.5 u
delta HPWL                  5 %

[INFO]: Changing layout from /project/openlane/mgmt_core/runs/mgmt_core/tmp/floorplan/pdn.def to /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/diodes.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/diodes.def
Notice 0: Design: mgmt_core
Notice 0: 		Created 100000 Insts
Notice 0:     Created 796 pins.
Notice 0:     Created 136442 components and 464133 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 35914 nets and 191239 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/diodes.def
[INFO]: Changing netlist from /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis_cts.v to /project/openlane/mgmt_core/runs/mgmt_core/results/synthesis/mgmt_core.synthesis_diodes.v
[INFO]: Running Global Routing...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/diodes.def
Notice 0: Design: mgmt_core
Notice 0: 		Created 100000 Insts
Notice 0:     Created 796 pins.
Notice 0:     Created 136442 components and 464133 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 35914 nets and 191239 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/tmp/placement/diodes.def
[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 6
[PARAMS] Global adjustment: 0
[PARAMS] Unidirectional routing: 1
[PARAMS] Grid origin: (-1, -1)
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 2211898
[INFO] #DB Macros: 1
[INFO] Found 0 clock nets
[INFO] Minimum degree: 2
[INFO] Maximum degree: 777
[INFO] Processing 1525434 obstacles in layer 1
[INFO] Processing 347404 obstacles in layer 2
[INFO] Processing 53 obstacles in layer 3
[INFO] Processing 52 obstacles in layer 4
[INFO] Processing 108 obstacles in layer 5
[INFO] Processing 11 obstacles in layer 6
[INFO] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 691878, WIRELEN1 : 0
[INFO] NumSeg  : 133532
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 693261, WIRELEN1 : 693261
[INFO] NumSeg  : 133255
[INFO] NumShift: 4128
[Overflow Report] Total hCap    : 1047908
[Overflow Report] Total vCap    : 891734
[Overflow Report] Total Usage   : 693261
[Overflow Report] Max H Overflow: 40
[Overflow Report] Max V Overflow: 15
[Overflow Report] Max Overflow  : 40
[Overflow Report] Num Overflow e: 9055
[Overflow Report] H   Overflow  : 71697
[Overflow Report] V   Overflow  : 5814
[Overflow Report] Final Overflow: 77511

Second L Route
[Overflow Report] Total hCap    : 1047908
[Overflow Report] Total vCap    : 891734
[Overflow Report] Total Usage   : 693261
[Overflow Report] Max H Overflow: 39
[Overflow Report] Max V Overflow: 15
[Overflow Report] Max Overflow  : 39
[Overflow Report] Num Overflow e: 8998
[Overflow Report] H   Overflow  : 71193
[Overflow Report] V   Overflow  : 5722
[Overflow Report] Final Overflow: 76915

First Z Route
[Overflow Report] Total hCap    : 1047908
[Overflow Report] Total vCap    : 891734
[Overflow Report] Total Usage   : 693261
[Overflow Report] Max H Overflow: 38
[Overflow Report] Max V Overflow: 14
[Overflow Report] Max Overflow  : 38
[Overflow Report] Num Overflow e: 9067
[Overflow Report] H   Overflow  : 68729
[Overflow Report] V   Overflow  : 5362
[Overflow Report] Final Overflow: 74091

[INFO] LV routing round 0, enlarge 10 
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage   : 710883
[Overflow Report] Max H Overflow: 27
[Overflow Report] Max V Overflow: 12
[Overflow Report] Max Overflow  : 27
[Overflow Report] Num Overflow e: 9363
[Overflow Report] H   Overflow  : 45934
[Overflow Report] V   Overflow  : 6133
[Overflow Report] Final Overflow: 52067

[INFO] LV routing round 1, enlarge 15 
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage   : 718631
[Overflow Report] Max H Overflow: 25
[Overflow Report] Max V Overflow: 12
[Overflow Report] Max Overflow  : 25
[Overflow Report] Num Overflow e: 9435
[Overflow Report] H   Overflow  : 41319
[Overflow Report] V   Overflow  : 6344
[Overflow Report] Final Overflow: 47663

[INFO] LV routing round 2, enlarge 20 
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage   : 725535
[Overflow Report] Max H Overflow: 24
[Overflow Report] Max V Overflow: 12
[Overflow Report] Max Overflow  : 24
[Overflow Report] Num Overflow e: 9448
[Overflow Report] H   Overflow  : 37221
[Overflow Report] V   Overflow  : 6589
[Overflow Report] Final Overflow: 43810

Running extra iterations to remove overflow...
Update congestion history type 1
[INFO] iteration 1, enlarge 25, costheight 6, threshold 10 via cost 2 
[INFO] log_coef 0.478692, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 1
[Overflow Report] total Usage   : 804403
[Overflow Report] Max H Overflow: 10
[Overflow Report] Max V Overflow: 7
[Overflow Report] Max Overflow  : 10
[Overflow Report] Num Overflow e: 8796
[Overflow Report] H   Overflow  : 17595
[Overflow Report] V   Overflow  : 3018
[Overflow Report] Final Overflow: 20613

Update congestion history type 1
[INFO] iteration 2, enlarge 35, costheight 8, threshold 6 via cost 2 
[INFO] log_coef 0.605586, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 1
[Overflow Report] total Usage   : 841749
[Overflow Report] Max H Overflow: 7
[Overflow Report] Max V Overflow: 7
[Overflow Report] Max Overflow  : 7
[Overflow Report] Num Overflow e: 5602
[Overflow Report] H   Overflow  : 4784
[Overflow Report] V   Overflow  : 4463
[Overflow Report] Final Overflow: 9247

Update congestion history type 1
[INFO] iteration 3, enlarge 45, costheight 10, threshold 2 via cost 2 
[INFO] log_coef 0.678907, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 1
[Overflow Report] total Usage   : 861066
[Overflow Report] Max H Overflow: 5
[Overflow Report] Max V Overflow: 6
[Overflow Report] Max Overflow  : 6
[Overflow Report] Num Overflow e: 3311
[Overflow Report] H   Overflow  : 1599
[Overflow Report] V   Overflow  : 4019
[Overflow Report] Final Overflow: 5618

Update congestion history type 1
[INFO] iteration 4, enlarge 55, costheight 12, threshold 0 via cost 2 
[INFO] log_coef 0.716394, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 1
[Overflow Report] total Usage   : 869603
[Overflow Report] Max H Overflow: 4
[Overflow Report] Max V Overflow: 7
[Overflow Report] Max Overflow  : 7
[Overflow Report] Num Overflow e: 2692
[Overflow Report] H   Overflow  : 765
[Overflow Report] V   Overflow  : 3913
[Overflow Report] Final Overflow: 4678

Update congestion history type 1
[INFO] iteration 5, enlarge 65, costheight 19, threshold 0 via cost 2 
[INFO] log_coef 0.716394, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 1
[Overflow Report] total Usage   : 879764
[Overflow Report] Max H Overflow: 3
[Overflow Report] Max V Overflow: 6
[Overflow Report] Max Overflow  : 6
[Overflow Report] Num Overflow e: 2454
[Overflow Report] H   Overflow  : 608
[Overflow Report] V   Overflow  : 3530
[Overflow Report] Final Overflow: 4138

Update congestion history type 1
[INFO] iteration 6, enlarge 75, costheight 26, threshold 0 via cost 2 
[INFO] log_coef 0.716394, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 1
[Overflow Report] total Usage   : 886828
[Overflow Report] Max H Overflow: 4
[Overflow Report] Max V Overflow: 6
[Overflow Report] Max Overflow  : 6
[Overflow Report] Num Overflow e: 2052
[Overflow Report] H   Overflow  : 391
[Overflow Report] V   Overflow  : 2898
[Overflow Report] Final Overflow: 3289

Update congestion history type 1
[INFO] iteration 7, enlarge 85, costheight 33, threshold 0 via cost 2 
[INFO] log_coef 0.716394, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 1
[Overflow Report] total Usage   : 889836
[Overflow Report] Max H Overflow: 3
[Overflow Report] Max V Overflow: 6
[Overflow Report] Max Overflow  : 6
[Overflow Report] Num Overflow e: 2020
[Overflow Report] H   Overflow  : 577
[Overflow Report] V   Overflow  : 2376
[Overflow Report] Final Overflow: 2953

Update congestion history type 1
[INFO] iteration 8, enlarge 95, costheight 40, threshold 0 via cost 2 
[INFO] log_coef 0.716394, healingTrigger 0 cost_step 2 L 0 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 875467
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1454
[Overflow Report] H   Overflow  : 312
[Overflow Report] V   Overflow  : 1656
[Overflow Report] Final Overflow: 1968

Update congestion history type 2
[INFO] iteration 9, enlarge 100, costheight 42, threshold 0 via cost 2 
[INFO] log_coef 0.838120, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 872100
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1286
[Overflow Report] H   Overflow  : 269
[Overflow Report] V   Overflow  : 1364
[Overflow Report] Final Overflow: 1633

Update congestion history type 2
[INFO] iteration 10, enlarge 105, costheight 49, threshold 0 via cost 2 
[INFO] log_coef 0.838120, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 872366
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1208
[Overflow Report] H   Overflow  : 255
[Overflow Report] V   Overflow  : 1260
[Overflow Report] Final Overflow: 1515

Update congestion history type 2
[INFO] iteration 11, enlarge 110, costheight 56, threshold 0 via cost 2 
[INFO] log_coef 0.838120, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 872798
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1120
[Overflow Report] H   Overflow  : 259
[Overflow Report] V   Overflow  : 1142
[Overflow Report] Final Overflow: 1401

Update congestion history type 2
[INFO] iteration 12, enlarge 115, costheight 63, threshold 0 via cost 2 
[INFO] log_coef 0.838120, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 873168
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 1094
[Overflow Report] H   Overflow  : 274
[Overflow Report] V   Overflow  : 1042
[Overflow Report] Final Overflow: 1316

Update congestion history type 2
[INFO] iteration 13, enlarge 120, costheight 70, threshold 0 via cost 2 
[INFO] log_coef 0.953011, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 873131
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 5
[Overflow Report] Max Overflow  : 5
[Overflow Report] Num Overflow e: 1039
[Overflow Report] H   Overflow  : 291
[Overflow Report] V   Overflow  : 926
[Overflow Report] Final Overflow: 1217

Update congestion history type 2
[INFO] iteration 14, enlarge 125, costheight 77, threshold 0 via cost 2 
[INFO] log_coef 0.953011, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 873624
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 989
[Overflow Report] H   Overflow  : 275
[Overflow Report] V   Overflow  : 884
[Overflow Report] Final Overflow: 1159

Update congestion history type 2
[INFO] iteration 15, enlarge 130, costheight 84, threshold 0 via cost 2 
[INFO] log_coef 0.953011, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 874077
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 945
[Overflow Report] H   Overflow  : 249
[Overflow Report] V   Overflow  : 859
[Overflow Report] Final Overflow: 1108

Update congestion history type 2
[INFO] iteration 16, enlarge 135, costheight 91, threshold 0 via cost 2 
[INFO] log_coef 0.953011, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 874342
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 932
[Overflow Report] H   Overflow  : 242
[Overflow Report] V   Overflow  : 854
[Overflow Report] Final Overflow: 1096

Update congestion history type 2
[INFO] iteration 17, enlarge 140, costheight 98, threshold 0 via cost 2 
[INFO] log_coef 0.953011, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 874916
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 924
[Overflow Report] H   Overflow  : 245
[Overflow Report] V   Overflow  : 824
[Overflow Report] Final Overflow: 1069

Update congestion history type 2
[INFO] iteration 18, enlarge 145, costheight 105, threshold 0 via cost 2 
[INFO] log_coef 0.953011, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 875495
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 898
[Overflow Report] H   Overflow  : 223
[Overflow Report] V   Overflow  : 794
[Overflow Report] Final Overflow: 1017

Update congestion history type 2
[INFO] iteration 19, enlarge 150, costheight 112, threshold 0 via cost 2 
[INFO] log_coef 0.953011, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 876482
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 893
[Overflow Report] H   Overflow  : 247
[Overflow Report] V   Overflow  : 772
[Overflow Report] Final Overflow: 1019

Extra Run for hard benchmark
[Overflow Report] total Usage   : 877739
[Overflow Report] Max H Overflow: 1
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 2
[Overflow Report] Num Overflow e: 1015
[Overflow Report] H   Overflow  : 184
[Overflow Report] V   Overflow  : 941
[Overflow Report] Final Overflow: 1125

Update congestion history type 2
[INFO] iteration 20, enlarge 155, costheight 119, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 1 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 945537
[Overflow Report] Max H Overflow: 11
[Overflow Report] Max V Overflow: 6
[Overflow Report] Max Overflow  : 11
[Overflow Report] Num Overflow e: 6954
[Overflow Report] H   Overflow  : 8954
[Overflow Report] V   Overflow  : 1677
[Overflow Report] Final Overflow: 10631

Update congestion history type 2
[INFO] iteration 21, enlarge 165, costheight 126, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 2 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 935784
[Overflow Report] Max H Overflow: 4
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 3423
[Overflow Report] H   Overflow  : 2844
[Overflow Report] V   Overflow  : 1323
[Overflow Report] Final Overflow: 4167

Update congestion history type 2
[INFO] iteration 22, enlarge 166, costheight 128, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 2 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 934848
[Overflow Report] Max H Overflow: 4
[Overflow Report] Max V Overflow: 5
[Overflow Report] Max Overflow  : 5
[Overflow Report] Num Overflow e: 3388
[Overflow Report] H   Overflow  : 3174
[Overflow Report] V   Overflow  : 944
[Overflow Report] Final Overflow: 4118

Update congestion history type 2
[INFO] iteration 23, enlarge 166, costheight 135, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 2 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931987
[Overflow Report] Max H Overflow: 4
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 2523
[Overflow Report] H   Overflow  : 2160
[Overflow Report] V   Overflow  : 781
[Overflow Report] Final Overflow: 2941

Update congestion history type 2
[INFO] iteration 24, enlarge 166, costheight 142, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 2 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 930630
[Overflow Report] Max H Overflow: 3
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 2182
[Overflow Report] H   Overflow  : 1763
[Overflow Report] V   Overflow  : 732
[Overflow Report] Final Overflow: 2495

Update congestion history type 2
[INFO] iteration 25, enlarge 166, costheight 149, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 2 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 930320
[Overflow Report] Max H Overflow: 3
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 2086
[Overflow Report] H   Overflow  : 1667
[Overflow Report] V   Overflow  : 654
[Overflow Report] Final Overflow: 2321

Update congestion history type 2
[INFO] iteration 26, enlarge 166, costheight 156, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 2 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 928980
[Overflow Report] Max H Overflow: 3
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1823
[Overflow Report] H   Overflow  : 1440
[Overflow Report] V   Overflow  : 593
[Overflow Report] Final Overflow: 2033

Update congestion history type 2
[INFO] iteration 27, enlarge 166, costheight 163, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 2 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 928365
[Overflow Report] Max H Overflow: 4
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1491
[Overflow Report] H   Overflow  : 1094
[Overflow Report] V   Overflow  : 539
[Overflow Report] Final Overflow: 1633

Update congestion history type 2
[INFO] iteration 28, enlarge 166, costheight 170, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 2 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 928752
[Overflow Report] Max H Overflow: 4
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1516
[Overflow Report] H   Overflow  : 1090
[Overflow Report] V   Overflow  : 570
[Overflow Report] Final Overflow: 1660

Update congestion history type 2
[INFO] iteration 29, enlarge 166, costheight 177, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 3 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 928005
[Overflow Report] Max H Overflow: 3
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1426
[Overflow Report] H   Overflow  : 1000
[Overflow Report] V   Overflow  : 540
[Overflow Report] Final Overflow: 1540

Update congestion history type 2
[INFO] iteration 30, enlarge 166, costheight 184, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 3 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 927738
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 2
[Overflow Report] Num Overflow e: 1062
[Overflow Report] H   Overflow  : 674
[Overflow Report] V   Overflow  : 402
[Overflow Report] Final Overflow: 1076

Update congestion history type 2
[INFO] iteration 31, enlarge 166, costheight 186, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 3 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 927350
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 2
[Overflow Report] Num Overflow e: 972
[Overflow Report] H   Overflow  : 627
[Overflow Report] V   Overflow  : 352
[Overflow Report] Final Overflow: 979

Update congestion history type 2
[INFO] iteration 32, enlarge 166, costheight 193, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 3 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 927289
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 1370
[Overflow Report] H   Overflow  : 906
[Overflow Report] V   Overflow  : 596
[Overflow Report] Final Overflow: 1502

Update congestion history type 2
[INFO] iteration 33, enlarge 166, costheight 200, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 4 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 928231
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1179
[Overflow Report] H   Overflow  : 760
[Overflow Report] V   Overflow  : 498
[Overflow Report] Final Overflow: 1258

Update congestion history type 2
[INFO] iteration 34, enlarge 166, costheight 207, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 4 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 928130
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 2
[Overflow Report] Num Overflow e: 944
[Overflow Report] H   Overflow  : 551
[Overflow Report] V   Overflow  : 409
[Overflow Report] Final Overflow: 960

Update congestion history type 2
[INFO] iteration 35, enlarge 166, costheight 214, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 4 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 930696
[Overflow Report] Max H Overflow: 6
[Overflow Report] Max V Overflow: 8
[Overflow Report] Max Overflow  : 8
[Overflow Report] Num Overflow e: 1525
[Overflow Report] H   Overflow  : 1148
[Overflow Report] V   Overflow  : 1159
[Overflow Report] Final Overflow: 2307

Update congestion history type 2
[INFO] iteration 36, enlarge 166, costheight 221, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 5 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 930681
[Overflow Report] Max H Overflow: 3
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1493
[Overflow Report] H   Overflow  : 965
[Overflow Report] V   Overflow  : 688
[Overflow Report] Final Overflow: 1653

Update congestion history type 2
[INFO] iteration 37, enlarge 166, costheight 228, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 5 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931004
[Overflow Report] Max H Overflow: 4
[Overflow Report] Max V Overflow: 4
[Overflow Report] Max Overflow  : 4
[Overflow Report] Num Overflow e: 1279
[Overflow Report] H   Overflow  : 855
[Overflow Report] V   Overflow  : 594
[Overflow Report] Final Overflow: 1449

Update congestion history type 2
[INFO] iteration 38, enlarge 166, costheight 235, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 5 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931046
[Overflow Report] Max H Overflow: 3
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 1201
[Overflow Report] H   Overflow  : 768
[Overflow Report] V   Overflow  : 548
[Overflow Report] Final Overflow: 1316

Update congestion history type 2
[INFO] iteration 39, enlarge 166, costheight 242, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 5 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931088
[Overflow Report] Max H Overflow: 3
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 1154
[Overflow Report] H   Overflow  : 737
[Overflow Report] V   Overflow  : 519
[Overflow Report] Final Overflow: 1256

Update congestion history type 2
[INFO] iteration 40, enlarge 166, costheight 249, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 5 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931254
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 1148
[Overflow Report] H   Overflow  : 718
[Overflow Report] V   Overflow  : 538
[Overflow Report] Final Overflow: 1256

Update congestion history type 2
[INFO] iteration 41, enlarge 166, costheight 256, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 6 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 930959
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 1119
[Overflow Report] H   Overflow  : 692
[Overflow Report] V   Overflow  : 530
[Overflow Report] Final Overflow: 1222

Update congestion history type 2
[INFO] iteration 42, enlarge 166, costheight 263, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 6 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931081
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 1022
[Overflow Report] H   Overflow  : 610
[Overflow Report] V   Overflow  : 493
[Overflow Report] Final Overflow: 1103

Update congestion history type 2
[INFO] iteration 43, enlarge 166, costheight 270, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 6 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931109
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 1091
[Overflow Report] H   Overflow  : 658
[Overflow Report] V   Overflow  : 504
[Overflow Report] Final Overflow: 1162

Update congestion history type 2
[INFO] iteration 44, enlarge 166, costheight 277, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 7 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931075
[Overflow Report] Max H Overflow: 3
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 3
[Overflow Report] Num Overflow e: 1069
[Overflow Report] H   Overflow  : 640
[Overflow Report] V   Overflow  : 504
[Overflow Report] Final Overflow: 1144

Update congestion history type 2
[INFO] iteration 45, enlarge 166, costheight 284, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 7 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931299
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 2
[Overflow Report] Num Overflow e: 1016
[Overflow Report] H   Overflow  : 591
[Overflow Report] V   Overflow  : 488
[Overflow Report] Final Overflow: 1079

Update congestion history type 2
[INFO] iteration 46, enlarge 166, costheight 291, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 7 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931175
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 2
[Overflow Report] Num Overflow e: 890
[Overflow Report] H   Overflow  : 486
[Overflow Report] V   Overflow  : 413
[Overflow Report] Final Overflow: 899

Update congestion history type 2
[INFO] iteration 47, enlarge 166, costheight 298, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 7 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931071
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 2
[Overflow Report] Num Overflow e: 780
[Overflow Report] H   Overflow  : 417
[Overflow Report] V   Overflow  : 374
[Overflow Report] Final Overflow: 791

Update congestion history type 2
[INFO] iteration 48, enlarge 166, costheight 305, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 7 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 931031
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 2
[Overflow Report] Num Overflow e: 732
[Overflow Report] H   Overflow  : 370
[Overflow Report] V   Overflow  : 367
[Overflow Report] Final Overflow: 737

Update congestion history type 2
[INFO] iteration 49, enlarge 166, costheight 312, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 7 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 930983
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 2
[Overflow Report] Num Overflow e: 708
[Overflow Report] H   Overflow  : 356
[Overflow Report] V   Overflow  : 360
[Overflow Report] Final Overflow: 716

Update congestion history type 2
[INFO] iteration 50, enlarge 166, costheight 319, threshold 0 via cost 0 
[INFO] log_coef 1.181232, healingTrigger 7 cost_step 2 L 1 cost_type 1 updatetype 2
[Overflow Report] total Usage   : 932732
[Overflow Report] Max H Overflow: 4
[Overflow Report] Max V Overflow: 8
[Overflow Report] Max Overflow  : 8
[Overflow Report] Num Overflow e: 1283
[Overflow Report] H   Overflow  : 906
[Overflow Report] V   Overflow  : 1072
[Overflow Report] Final Overflow: 1978

[ERROR] FastRoute cannot handle very congested design
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_route.tcl |& tee >&@stdout /project/openlane/mgmt_core/runs/mgmt_core/logs/routing/fastroute.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check openroad  log file
[ERROR]: Dumping to /project/openlane/mgmt_core/runs/mgmt_core/error.log

    while executing
"try_catch openroad -exit $::env(SCRIPTS_DIR)/openroad/or_route.tcl |& tee $::env(TERMINAL_OUTPUT) $::env(fastroute_log_file_tag).log"
    (procedure "global_routing" line 5)
    invoked from within
"global_routing"
    (procedure "run_routing" line 15)
    invoked from within
"run_routing"
    (procedure "run_non_interactive_mode" line 16)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: mgmt_core] Fehler 1

Submodule: mgmt_protect

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/mgmt_protect/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/mgmt_protect/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/mgmt_protect/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/mgmt_protect/runs/mgmt_protect
[WARNING]: Removing exisiting run /project/openlane/mgmt_protect/runs/mgmt_protect
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 3.68
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/mgmt_protect/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/mgmt_protect/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/mgmt_protect/../../verilog/rtl/mgmt_protect.v
Parsing Verilog input from `/project/openlane/mgmt_protect/../../verilog/rtl/mgmt_protect.v' to AST representation.
Generating RTLIL representation for module `\mgmt_protect'.
Successfully finished Verilog frontend.

4. Executing HIERARCHY pass (managing design hierarchy).

4.1. Analyzing design hierarchy..
ERROR: Module `\sky130_fd_sc_hvl__lsbufhv2lv_1' referenced in module `\mgmt_protect' in cell `\mprj2_logic_high_lv' is not part of the design.
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/mgmt_protect/runs/mgmt_protect/logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check yosys  log file
[ERROR]: Dumping to /project/openlane/mgmt_protect/runs/mgmt_protect/error.log

    while executing
"try_catch [get_yosys_bin]  -c $::env(SYNTH_SCRIPT)  -l $::env(yosys_log_file_tag).log  |& tee $::env(TERMINAL_OUTPUT)"
    (procedure "run_yosys" line 18)
    invoked from within
"run_yosys"
    (procedure "run_synthesis" line 4)
    invoked from within
"run_synthesis"
    (procedure "run_non_interactive_mode" line 11)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: mgmt_protect] Fehler 1

Submodule: simple_por

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/simple_por/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/simple_por/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hvl
no files matched glob pattern "/media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hvl/lef/*.lef"
    while executing
"glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef""
    invoked from within
"set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"]"
    (file "/media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/openlane/config.tcl" line 13)
    invoked from within
"source $pdk_config"
    (procedure "prep" line 124)
    invoked from within
"prep {*}$args"
    (procedure "run_non_interactive_mode" line 9)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: simple_por] Fehler 1

Submodule: storage

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/storage/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/storage/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/storage/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/storage/runs/storage
[WARNING]: Removing exisiting run /project/openlane/storage/runs/storage
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
mergeLef.py : Merging LEFs
sram_1rw1r_32_256_8_sky130_lp1.lef: SITEs matched found: 0
sram_1rw1r_32_256_8_sky130_lp1.lef: MACROs matched found: 1
mergeLef.py : Merging LEFs complete
[INFO]: Merging the following extra LEFs:  /project/openlane/storage/../../lef/sram_1rw1r_32_256_8_sky130_lp1.lef
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 3.68
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /project/openlane/storage/../../verilog/rtl/sram_1rw1r_32_256_8_sky130.v
Parsing Verilog input from `/project/openlane/storage/../../verilog/rtl/sram_1rw1r_32_256_8_sky130.v' to AST representation.
Generating RTLIL representation for module `\sram_1rw1r_32_256_8_sky130'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /project/openlane/storage/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/storage/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/storage/../../verilog/rtl/storage.v
Parsing Verilog input from `/project/openlane/storage/../../verilog/rtl/storage.v' to AST representation.
Generating RTLIL representation for module `\storage'.
Successfully finished Verilog frontend.

4. Executing HIERARCHY pass (managing design hierarchy).

4.1. Analyzing design hierarchy..
Top module:  \storage

4.2. Analyzing design hierarchy..
Top module:  \storage
Removed 0 unused modules.

5. Printing statistics.

=== storage ===

   Number of wires:                 10
   Number of wire bits:            158
   Number of public wires:          10
   Number of public wire bits:     158
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     sram_1rw1r_32_256_8_sky130      2

6. Executing SPLITNETS pass (splitting up multi-bit signals).

7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \storage..

8. Executing CHECK pass (checking for obvious problems).
checking module storage..
found and reported 0 problems.

9. Printing statistics.

=== storage ===

   Number of wires:                 10
   Number of wire bits:            158
   Number of public wires:          10
   Number of public wire bits:     158
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     sram_1rw1r_32_256_8_sky130      2

   Area for cell type \sram_1rw1r_32_256_8_sky130 is unknown!

10. Executing Verilog backend.
Dumping module `\storage'.

End of script. Logfile hash: f29c70bfcc, CPU: user 0.10s system 0.02s, MEM: 13.07 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 70% 2x stat (0 sec), 14% 2x write_verilog (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis.v, line 14 module sram_1rw1r_32_256_8_sky130 not found.  Creating black box for SRAM_0.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 10.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 10.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF master sram_1rw1r_32_256_8_sky130 has no liberty cell.
Info: Added 341 rows of 954 sites.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 438.96000000000004
[INFO]: Core area height: 928.24
[INFO]: Changing layout from 0 to /project/openlane/storage/runs/storage/tmp/floorplan/verilog2def_openroad.def
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: storage
Notice 0:     Created 158 pins.
Notice 0:     Created 2 components and 246 component-terminals.
Notice 0:     Created 158 nets and 200 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/tmp/floorplan/verilog2def_openroad.def
Top-level design name: storage
Block boundaries: 0 0 450000 950000
Writing /project/openlane/storage/runs/storage/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/storage/runs/storage/tmp/floorplan/verilog2def_openroad.def to /project/openlane/storage/runs/storage/tmp/floorplan/ioPlacer.def
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/tmp/floorplan/ioPlacer.def
Notice 0: Design: storage
Notice 0:     Created 158 pins.
Notice 0:     Created 2 components and 246 component-terminals.
Notice 0:     Created 158 nets and 200 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/tmp/floorplan/ioPlacer.def
[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (444360, 938400)
[INFO] NumInstances = 2
[INFO] NumPlaceInstances = 2
[INFO] NumFixedInstances = 0
[INFO] NumDummyInstances = 0
[INFO] NumNets = 158
[INFO] NumPins = 358
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (450000, 950000)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (444360, 938400)
[INFO] CoreArea = 407032876800
[INFO] NonPlaceInstsArea = 0
[INFO] PlaceInstsArea = 352651405600
[INFO] Util(%) = 86.639534
[INFO] StdInstsArea = 0
[INFO] MacroInstsArea = 352651405600
[InitialPlace]  Iter: 1 CG Error: 1.05598e-07 HPWL: 163458380
[InitialPlace]  Iter: 2 CG Error: 4.29531e-09 HPWL: 143390863
[InitialPlace]  Iter: 3 CG Error: 1.95535e-09 HPWL: 143422808
[InitialPlace]  Iter: 4 CG Error: 5.39665e-10 HPWL: 143508218
[InitialPlace]  Iter: 5 CG Error: 6.76466e-10 HPWL: 143732067
[INFO] FillerInit: NumGCells = 234
[INFO] FillerInit: NumGNets = 158
[INFO] FillerInit: NumGPins = 358
[INFO] TargetDensity = 0.990000
[INFO] AveragePlaceInstArea = 176325702800
[INFO] IdealBinArea = 178106777600
[INFO] IdealBinCnt = 2
[INFO] TotalBinArea = 407032876800
[INFO] BinCnt = (64, 64)
[INFO] BinSize = (6857, 14493)
[INFO] NumBins = 4096
[NesterovSolve] Iter: 1 overflow: 0.315935 HPWL: 76762649
[NesterovSolve] Iter: 10 overflow: 0.304548 HPWL: 76750225
[NesterovSolve] Iter: 20 overflow: 0.30404 HPWL: 76750225
[NesterovSolve] Iter: 30 overflow: 0.303293 HPWL: 76751017
[NesterovSolve] Iter: 40 overflow: 0.302177 HPWL: 76754343
[NesterovSolve] Iter: 50 overflow: 0.3004 HPWL: 76760927
[NesterovSolve] Finished with Overflow: 0.299948
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 10.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 10.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/storage/runs/storage/tmp/floorplan/ioPlacer.def to /project/openlane/storage/runs/storage/tmp/placement/replace.def
[INFO]:  Manual Macro Placement...
Placing the following macros:
{'SRAM_0': ['30000', '11805', 'N'], 'SRAM_1': ['30000', '482040', 'N']}
Placing  SRAM_0
Placing  SRAM_1
[INFO]: Changing layout from /project/openlane/storage/runs/storage/tmp/placement/replace.def to /project/openlane/storage/runs/storage/tmp/placement/replace.def.macro_placement.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/tmp/placement/replace.def.macro_placement.def
Notice 0: Design: storage
Notice 0:     Created 158 pins.
Notice 0:     Created 2 components and 246 component-terminals.
Notice 0:     Created 158 nets and 200 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/tmp/placement/replace.def.macro_placement.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 2
[INFO] #Original rows: 341
[INFO] #Cut rows: 341
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 1364
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 342
Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/storage/runs/storage/tmp/placement/replace.def.macro_placement.def to /project/openlane/storage/runs/storage/results/floorplan/storage.floorplan.def
[INFO]: Running Placement...
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/results/floorplan/storage.floorplan.def
Notice 0: Design: storage
Notice 0:     Created 158 pins.
Notice 0:     Created 1708 components and 3658 component-terminals.
Notice 0:     Created 158 nets and 200 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/results/floorplan/storage.floorplan.def
[WARN] All instances are FIXED
[WARN] No need to use replace
[WARN] Skipping...
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/storage/runs/storage/results/floorplan/storage.floorplan.def to /project/openlane/storage/runs/storage/tmp/placement/replace.def
[INFO]: Running Detailed Placement...
===========================================================================
   Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 >    
   Developers : SangGi Do, Mingyu Woo                                      
===========================================================================
Parsed 10000 number of lines!!
Parsed 20000 number of lines!!
Parsed 30000 number of lines!!
Parsed 40000 number of lines!!
Parsed 50000 number of lines!!
Parsed 60000 number of lines!!
Reading /project/openlane/storage/runs/storage/tmp/merged.lef is Done

-------------------- INPUT FILES ----------------------------------
 benchmark name    : placement
 directory         : /project/openlane/storage/runs/storage/tmp
 lef               : /project/openlane/storage/runs/storage/tmp/merged.lef
 def               : /project/openlane/storage/runs/storage/tmp/placement/replace.def
-------------------------------------------------------------------
CoreArea: 
5520.000000 : 10880.000000 - 444360.000000 : 938400.000000
DieArea: 
0.000000 : 0.000000 - 438840.000000 : 927520.000000
Reading /project/openlane/storage/runs/storage/tmp/placement/replace.def is Done
-------------------- DESIGN ANALYSIS ------------------------------
  total cells              : 1708
  multi cells              : 0
  fixed cells              : 1708
  total nets               : 158
  design area              : 4.07033e+11
  total f_area             : 3.61557e+11
  total m_area             : 0
  design util              : 0
  num rows                 : 341
  row height               : 2720
-------------------------------------------------------------------
 non_group_cell_region_assign done ..
 - - - - - - - - - - - - - - - - - - - - - - - - 
 non_group_cell_placement done .. 
 - - - - - - - - - - - - - - - - - - - - - - - - 
Reading /project/openlane/storage/runs/storage/tmp/placement/replace.def is Done
 DEF file write success !! 
 location : /project/openlane/storage/runs/storage/results/placement/storage.placement.def
-------------------------------------------------------------------
 tasks                          Wtime      Ctime
 Parser                         0.614      0.610
 resgin assign                  0.614      0.610
 pre-placement                  0.614      0.610
 non Group cell placement       0.614      0.610
 All                            0.615      0.610
 - - - - - EVALUATION - - - - - 
 AVG_displacement : 0
 SUM_displacement : 0
 MAX_displacement : 0
 - - - - - - - - - - - - - - - - 
 GP HPWL          : 94776.4
 HPWL             : 94776.4
 avg_Disp_site    : 0
 avg_Disp_row     : 0
 delta_HPWL       : 0
 ==== CHECK LEGALITY ==== 
 row_check ==>> PASS 
 site_check ==>> PASS 
 power_check ==>> PASS 
 edge_check ==>> PASS 
 placed_check ==>> PASS 
 overlap_check ==>> PASS 
 - - - - - < Program END > - - - - - 
[INFO]: Changing layout from /project/openlane/storage/runs/storage/tmp/placement/replace.def to /project/openlane/storage/runs/storage/results/placement/storage.placement.def
[INFO]: Generating PDN...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/results/placement/storage.placement.def
Notice 0: Design: storage
Notice 0:     Created 158 pins.
Notice 0:     Created 1708 components and 3658 component-terminals.
Notice 0:     Created 158 nets and 200 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/results/placement/storage.placement.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /project/openlane/storage/pdn.tcl
[INFO] [PDNG-0008] Design Name is storage
[INFO] [PDNG-0009] Reading technology data
[ERROR] [PDNG-0037] Cannot find pin VPWR on instance SRAM_0 (sram_1rw1r_32_256_8_sky130)
[ERROR] [PDNG-0037] Cannot find pin VDD on instance SRAM_0 (sram_1rw1r_32_256_8_sky130)
[ERROR] [PDNG-0037] Cannot find pin VGND on instance SRAM_0 (sram_1rw1r_32_256_8_sky130)
[ERROR] [PDNG-0037] Cannot find pin VSS on instance SRAM_0 (sram_1rw1r_32_256_8_sky130)
[ERROR] [PDNG-0037] Cannot find pin VPWR on instance SRAM_1 (sram_1rw1r_32_256_8_sky130)
[ERROR] [PDNG-0037] Cannot find pin VDD on instance SRAM_1 (sram_1rw1r_32_256_8_sky130)
[ERROR] [PDNG-0037] Cannot find pin VGND on instance SRAM_1 (sram_1rw1r_32_256_8_sky130)
[ERROR] [PDNG-0037] Cannot find pin VSS on instance SRAM_1 (sram_1rw1r_32_256_8_sky130)
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
    Stdcell Rails
      Layer: met1 -  width: 0.480  pitch: 2.720  offset: 0.000 
    Straps
      Layer: met4 -  width: 1.600  pitch: 20.000  offset: 5.000 
      Layer: met5 -  width: 1.600  pitch: 50.000  offset: 16.650 
    Connect: {met1 met4} {met4 met5}
Type: macro, macro_1
    Straps
    Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[WARN] [PDNG-0040] No via added at (29.72 476.49 31.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (49.72 476.49 51.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (69.72 476.49 71.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (89.72 476.49 91.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (109.72 476.49 111.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (129.72 476.49 131.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (149.72 476.49 151.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (169.72 476.49 171.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (189.72 476.49 191.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (209.72 476.49 211.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (229.72 476.49 231.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (249.72 476.49 251.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (269.72 476.49 271.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (289.72 476.49 291.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (309.72 476.49 311.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (329.72 476.49 331.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (349.72 476.49 351.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (369.72 476.49 371.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (389.72 476.49 391.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (409.72 476.49 411.32 477.28) because the full height of met5 (1.6) is not covered by the overlap
[INFO] [PDNG-0010] Inserting macro grid for 2 macros
[INFO] [PDNG-0034]   - grid for instance SRAM_0
[INFO] [PDNG-0034]   - grid for instance SRAM_1
[WARN] [PDNG-0040] No via added at (412.47 926.49 414.07 926.72) because the full height of met5 (1.6) is not covered by the overlap
[INFO] [PDNG-0015] Writing to database
[INFO]: Changing layout from /project/openlane/storage/runs/storage/results/placement/storage.placement.def to /project/openlane/storage/runs/storage/tmp/floorplan/pdn.def
[INFO]: Routing...
[INFO]: Running Diode Insertion...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/tmp/floorplan/pdn.def
Notice 0: Design: storage
Notice 0:     Created 160 pins.
Notice 0:     Created 1708 components and 3658 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 158 nets and 200 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/tmp/floorplan/pdn.def
[INFO]: Inserting sky130_fd_sc_hd__diode_2...
[WARN]: Skipping VPWR
[WARN]: Skipping VGND

[INFO]: 104 of sky130_fd_sc_hd__diode_2 inserted!
[INFO]: Legalizing...
Design Stats
--------------------------------
total instances          1812
multi row instances         0
fixed instances          1708
nets                      160
design area          407032.9 u^2
fixed area             6011.9 u^2
movable area            260.2 u^2
utilization                 0 %
utilization padded          0 %
rows                      341
row height                2.7 u

Placement Analysis
--------------------------------
total displacement    10810.2 u
average displacement      6.0 u
max displacement        202.8 u
original HPWL         94803.2 u
legalized HPWL        98524.4 u
delta HPWL                  4 %

[INFO]: Changing layout from /project/openlane/storage/runs/storage/tmp/floorplan/pdn.def to /project/openlane/storage/runs/storage/tmp/placement/diodes.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/tmp/placement/diodes.def
Notice 0: Design: storage
Notice 0:     Created 160 pins.
Notice 0:     Created 1812 components and 3970 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 158 nets and 304 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/tmp/placement/diodes.def
[INFO]: Changing netlist from /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis.v to /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis_diodes.v
[INFO]: Running Global Routing...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/tmp/placement/diodes.def
Notice 0: Design: storage
Notice 0:     Created 160 pins.
Notice 0:     Created 1812 components and 3970 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 158 nets and 304 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/tmp/placement/diodes.def
[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 6
[PARAMS] Global adjustment: 0
[PARAMS] Unidirectional routing: 1
[PARAMS] Grid origin: (-1, -1)
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 19054
[INFO] #DB Macros: 2
[INFO] Found 0 clock nets
[INFO] Minimum degree: 2
[INFO] Maximum degree: 7
[INFO] Processing 9866 obstacles in layer 1
[INFO] Processing 4306 obstacles in layer 2
[INFO] Processing 2 obstacles in layer 3
[INFO] Processing 42 obstacles in layer 4
[INFO] Processing 258 obstacles in layer 5
[INFO] Processing 37 obstacles in layer 6
[INFO] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 15603, WIRELEN1 : 0
[INFO] NumSeg  : 358
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 15603, WIRELEN1 : 15603
[INFO] NumSeg  : 360
[INFO] NumShift: 5
[Overflow Report] Total hCap    : 60671
[Overflow Report] Total vCap    : 43243
[Overflow Report] Total Usage   : 15603
[Overflow Report] Max H Overflow: 6
[Overflow Report] Max V Overflow: 11
[Overflow Report] Max Overflow  : 11
[Overflow Report] Num Overflow e: 3753
[Overflow Report] H   Overflow  : 247
[Overflow Report] V   Overflow  : 4288
[Overflow Report] Final Overflow: 4535

Second L Route
[Overflow Report] Total hCap    : 60671
[Overflow Report] Total vCap    : 43243
[Overflow Report] Total Usage   : 15603
[Overflow Report] Max H Overflow: 6
[Overflow Report] Max V Overflow: 10
[Overflow Report] Max Overflow  : 10
[Overflow Report] Num Overflow e: 3816
[Overflow Report] H   Overflow  : 268
[Overflow Report] V   Overflow  : 4317
[Overflow Report] Final Overflow: 4585

First Z Route
[Overflow Report] Total hCap    : 60671
[Overflow Report] Total vCap    : 43243
[Overflow Report] Total Usage   : 15603
[Overflow Report] Max H Overflow: 6
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 6
[Overflow Report] Num Overflow e: 2613
[Overflow Report] H   Overflow  : 288
[Overflow Report] V   Overflow  : 2604
[Overflow Report] Final Overflow: 2892

[INFO] LV routing round 0, enlarge 10 
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage   : 15721
[Overflow Report] Max H Overflow: 6
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 6
[Overflow Report] Num Overflow e: 2945
[Overflow Report] H   Overflow  : 166
[Overflow Report] V   Overflow  : 3037
[Overflow Report] Final Overflow: 3203

[INFO] LV routing round 1, enlarge 15 
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage   : 15737
[Overflow Report] Max H Overflow: 6
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 6
[Overflow Report] Num Overflow e: 2843
[Overflow Report] H   Overflow  : 166
[Overflow Report] V   Overflow  : 2933
[Overflow Report] Final Overflow: 3099

[INFO] LV routing round 2, enlarge 20 
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage   : 15771
[Overflow Report] Max H Overflow: 6
[Overflow Report] Max V Overflow: 2
[Overflow Report] Max Overflow  : 6
[Overflow Report] Num Overflow e: 2908
[Overflow Report] H   Overflow  : 166
[Overflow Report] V   Overflow  : 2998
[Overflow Report] Final Overflow: 3164

Running extra iterations to remove overflow...
Update congestion history type 1
[INFO] iteration 1, enlarge 25, costheight 6, threshold 10 via cost 2 
[INFO] log_coef 0.716394, healingTrigger 0 cost_step 2 L 1 cost_type 1 updatetype 1
[Overflow Report] total Usage   : 15866
[Overflow Report] Max H Overflow: 2
[Overflow Report] Max V Overflow: 1
[Overflow Report] Max Overflow  : 2
[Overflow Report] Num Overflow e: 492
[Overflow Report] H   Overflow  : 8
[Overflow Report] V   Overflow  : 487
[Overflow Report] Final Overflow: 495

Update congestion history type 1
[INFO] iteration 2, enlarge 30, costheight 11, threshold 6 via cost 2 
[INFO] log_coef 1.181232, healingTrigger 0 cost_step 5 L 1 cost_type 1 updatetype 1
[Overflow Report] total Usage   : 15868
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Usage checked
Maze routing finished
[INFO] P3 runtime: 0.080000 sec
[INFO] Final 2D results: 
[Overflow Report] total Usage   : 15868
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 0.150000 sec
Post Processing Begins 
Post Processsing finished
 Starting via filling
[INFO] Via related to pin nodes 748
[INFO] Via related stiner nodes 109
Via filling finished

Final usage/overflow report: 
[INFO] Usage per layer: 
    Layer 1 usage: 0
    Layer 2 usage: 5334
    Layer 3 usage: 7111
    Layer 4 usage: 1923
    Layer 5 usage: 1410
    Layer 6 usage: 90

[INFO] Capacity per layer: 
    Layer 1 capacity: 0
    Layer 2 capacity: 33013
    Layer 3 capacity: 29474
    Layer 4 capacity: 17662
    Layer 5 capacity: 13769
    Layer 6 capacity: 9996

[INFO] Use percentage per layer: 
    Layer 1 use percentage: 0.0%
    Layer 2 use percentage: 16.16%
    Layer 3 use percentage: 24.13%
    Layer 4 use percentage: 10.89%
    Layer 5 use percentage: 10.24%
    Layer 6 use percentage: 0.90%

[INFO] Overflow per layer: 
    Layer 1 overflow: 0
    Layer 2 overflow: 0
    Layer 3 overflow: 0
    Layer 4 overflow: 0
    Layer 5 overflow: 0
    Layer 6 overflow: 0

[Overflow Report] Total Usage   : 15868
[Overflow Report] Total Capacity: 103914
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] Final usage          : 15868
[INFO] Final number of vias : 1291
[INFO] Final usage 3D       : 19741
[INFO] Total wirelength: 114187 um
[INFO] Num routed nets: 158
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 10.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 10.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
[INFO]: Changing layout from /project/openlane/storage/runs/storage/tmp/placement/diodes.def to /project/openlane/storage/runs/storage/tmp/routing/fastroute.def
[INFO]: Current Def is /project/openlane/storage/runs/storage/tmp/routing/fastroute.def
[INFO]: Running Fill Insertion...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/tmp/routing/fastroute.def
Notice 0: Design: storage
Notice 0:     Created 160 pins.
Notice 0:     Created 1812 components and 3970 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 158 nets and 304 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/tmp/routing/fastroute.def
Placed 3119 filler instances.
[INFO]: Changing layout from /project/openlane/storage/runs/storage/tmp/routing/fastroute.def to /project/openlane/storage/runs/storage/tmp/routing/addspacers.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/tmp/routing/addspacers.def
Notice 0: Design: storage
Notice 0:     Created 160 pins.
Notice 0:     Created 4931 components and 10208 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 158 nets and 304 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/tmp/routing/addspacers.def
[INFO]: Changing netlist from /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis_diodes.v to /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis_preroute.v
[INFO]: Running Detailed Routing...

reading lef ...

units:       1000
#layers:     13
#macros:     438
#vias:       25
#viarulegen: 25

reading def ...

design:      storage
die area:    ( 0 0 ) ( 450000 950000 )
trackPts:    12
defvias:     5
#components: 4931
#terminals:  160
#snets:      2
#nets:       158

reading guide ...

#guides:     2465
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
#unique instances = 20

init region query ...
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 26220
mcon shape region query size = 62062
met1 shape region query size = 11228
via shape region query size = 2736
met2 shape region query size = 1370
via2 shape region query size = 2736
met3 shape region query size = 1568
via3 shape region query size = 2740
met4 shape region query size = 1051
via4 shape region query size = 109
met5 shape region query size = 148


start pin access
  complete 100 pins
  complete 200 pins
  complete 244 pins
  complete 13 unique inst patterns
  complete 104 groups
Expt1 runtime (pin-level access point gen): 0.409193
Expt2 runtime (design-level access pattern gen): 0.00208878
#scanned instances     = 4931
#unique  instances     = 20
#stdCellGenAp          = 24
#stdCellValidPlanarAp  = 0
#stdCellValidViaAp     = 24
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 104
#instTermValidViaApCnt = 0
#macroGenAp            = 794
#macroValidPlanarAp    = 794
#macroValidViaAp       = 0
#macroNoAp             = 0

complete pin access
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20.07 (MB), peak = 21.04 (MB)

post process guides ...
GCELLGRID X -1 DO 147 STEP 6440 ;
GCELLGRID Y -1 DO 69 STEP 6440 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 104
mcon guide region query size = 0
met1 guide region query size = 356
via guide region query size = 0
met2 guide region query size = 488
via2 guide region query size = 0
met3 guide region query size = 408
via3 guide region query size = 0
met4 guide region query size = 208
via4 guide region query size = 0
met5 guide region query size = 3

init gr pin query ...


start track assignment
Done with 800 vertical wires in 2 frboxes and 767 horizontal wires in 3 frboxes.
Done with 251 vertical wires in 2 frboxes and 191 horizontal wires in 3 frboxes.

complete track assignment
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 31.14 (MB), peak = 39.10 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 31.14 (MB), peak = 39.10 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:04, memory = 57.13 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:05, memory = 56.88 (MB)
    completing 30% with 964 violations
    elapsed time = 00:00:09, memory = 57.85 (MB)
    completing 40% with 964 violations
    elapsed time = 00:00:10, memory = 56.29 (MB)
    completing 50% with 964 violations
    elapsed time = 00:00:11, memory = 56.29 (MB)
    completing 60% with 794 violations
    elapsed time = 00:00:12, memory = 50.23 (MB)
    completing 70% with 794 violations
    elapsed time = 00:00:14, memory = 54.03 (MB)
    completing 80% with 1096 violations
    elapsed time = 00:00:24, memory = 49.40 (MB)
    completing 90% with 1096 violations
    elapsed time = 00:00:25, memory = 50.27 (MB)
    completing 100% with 968 violations
    elapsed time = 00:00:34, memory = 38.96 (MB)
  number of violations = 968
cpu time = 00:01:03, elapsed time = 00:00:35, memory = 40.45 (MB), peak = 391.13 (MB)
total wire length = 107006 um
total wire length on LAYER li1 = 623 um
total wire length on LAYER met1 = 34159 um
total wire length on LAYER met2 = 45213 um
total wire length on LAYER met3 = 16117 um
total wire length on LAYER met4 = 9922 um
total wire length on LAYER met5 = 969 um
total number of vias = 1738
up-via summary (total 1738):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1     735
           met2     445
           met3     277
           met4      42
-----------------------
                   1738


start 1st optimization iteration ...
    completing 10% with 968 violations
    elapsed time = 00:00:02, memory = 61.30 (MB)
    completing 20% with 968 violations
    elapsed time = 00:00:03, memory = 65.94 (MB)
    completing 30% with 711 violations
    elapsed time = 00:00:05, memory = 58.82 (MB)
    completing 40% with 711 violations
    elapsed time = 00:00:06, memory = 58.99 (MB)
    completing 50% with 711 violations
    elapsed time = 00:00:07, memory = 59.04 (MB)
    completing 60% with 660 violations
    elapsed time = 00:00:08, memory = 50.76 (MB)
    completing 70% with 660 violations
    elapsed time = 00:00:09, memory = 54.91 (MB)
    completing 80% with 392 violations
    elapsed time = 00:00:15, memory = 50.03 (MB)
    completing 90% with 392 violations
    elapsed time = 00:00:16, memory = 53.02 (MB)
    completing 100% with 179 violations
    elapsed time = 00:00:22, memory = 40.77 (MB)
  number of violations = 179
cpu time = 00:00:39, elapsed time = 00:00:23, memory = 40.39 (MB), peak = 391.13 (MB)
total wire length = 106798 um
total wire length on LAYER li1 = 1077 um
total wire length on LAYER met1 = 34304 um
total wire length on LAYER met2 = 44915 um
total wire length on LAYER met3 = 16184 um
total wire length on LAYER met4 = 9734 um
total wire length on LAYER met5 = 583 um
total number of vias = 1870
up-via summary (total 1870):

-----------------------
 FR_MASTERSLICE       0
            li1     294
           met1     804
           met2     483
           met3     283
           met4       6
-----------------------
                   1870


start 2nd optimization iteration ...
    completing 10% with 179 violations
    elapsed time = 00:00:00, memory = 44.27 (MB)
    completing 20% with 179 violations
    elapsed time = 00:00:00, memory = 41.63 (MB)
    completing 30% with 189 violations
    elapsed time = 00:00:02, memory = 43.22 (MB)
    completing 40% with 189 violations
    elapsed time = 00:00:02, memory = 41.98 (MB)
    completing 50% with 189 violations
    elapsed time = 00:00:03, memory = 64.27 (MB)
    completing 60% with 206 violations
    elapsed time = 00:00:06, memory = 59.04 (MB)
    completing 70% with 206 violations
    elapsed time = 00:00:06, memory = 59.04 (MB)
    completing 80% with 231 violations
    elapsed time = 00:00:08, memory = 61.59 (MB)
    completing 90% with 231 violations
    elapsed time = 00:00:08, memory = 64.00 (MB)
    completing 100% with 249 violations
    elapsed time = 00:00:11, memory = 40.57 (MB)
  number of violations = 249
cpu time = 00:00:21, elapsed time = 00:00:12, memory = 40.43 (MB), peak = 391.20 (MB)
total wire length = 106838 um
total wire length on LAYER li1 = 1075 um
total wire length on LAYER met1 = 34382 um
total wire length on LAYER met2 = 44830 um
total wire length on LAYER met3 = 16103 um
total wire length on LAYER met4 = 9860 um
total wire length on LAYER met5 = 586 um
total number of vias = 1929
up-via summary (total 1929):

-----------------------
 FR_MASTERSLICE       0
            li1     330
           met1     814
           met2     490
           met3     289
           met4       6
-----------------------
                   1929


start 3rd optimization iteration ...
    completing 10% with 249 violations
    elapsed time = 00:00:01, memory = 66.89 (MB)
    completing 20% with 249 violations
    elapsed time = 00:00:02, memory = 68.86 (MB)
    completing 30% with 221 violations
    elapsed time = 00:00:05, memory = 65.58 (MB)
    completing 40% with 221 violations
    elapsed time = 00:00:05, memory = 65.84 (MB)
    completing 50% with 221 violations
    elapsed time = 00:00:05, memory = 63.13 (MB)
    completing 60% with 214 violations
    elapsed time = 00:00:05, memory = 56.91 (MB)
    completing 70% with 214 violations
    elapsed time = 00:00:06, memory = 63.43 (MB)
    completing 80% with 126 violations
    elapsed time = 00:00:15, memory = 41.98 (MB)
    completing 90% with 126 violations
    elapsed time = 00:00:15, memory = 41.98 (MB)
    completing 100% with 74 violations
    elapsed time = 00:00:20, memory = 41.98 (MB)
  number of violations = 74
cpu time = 00:00:38, elapsed time = 00:00:21, memory = 40.45 (MB), peak = 391.20 (MB)
total wire length = 106855 um
total wire length on LAYER li1 = 1463 um
total wire length on LAYER met1 = 34336 um
total wire length on LAYER met2 = 44557 um
total wire length on LAYER met3 = 16203 um
total wire length on LAYER met4 = 9708 um
total wire length on LAYER met5 = 586 um
total number of vias = 2029
up-via summary (total 2029):

-----------------------
 FR_MASTERSLICE       0
            li1     371
           met1     843
           met2     510
           met3     299
           met4       6
-----------------------
                   2029


start 4th optimization iteration ...
    completing 10% with 74 violations
    elapsed time = 00:00:01, memory = 61.93 (MB)
    completing 20% with 74 violations
    elapsed time = 00:00:01, memory = 64.50 (MB)
    completing 30% with 44 violations
    elapsed time = 00:00:01, memory = 52.48 (MB)
    completing 40% with 44 violations
    elapsed time = 00:00:01, memory = 52.16 (MB)
    completing 50% with 44 violations
    elapsed time = 00:00:02, memory = 49.73 (MB)
    completing 60% with 38 violations
    elapsed time = 00:00:02, memory = 40.54 (MB)
    completing 70% with 38 violations
    elapsed time = 00:00:02, memory = 50.30 (MB)
    completing 80% with 32 violations
    elapsed time = 00:00:05, memory = 41.39 (MB)
    completing 90% with 32 violations
    elapsed time = 00:00:05, memory = 41.39 (MB)
    completing 100% with 22 violations
    elapsed time = 00:00:06, memory = 41.36 (MB)
  number of violations = 22
cpu time = 00:00:12, elapsed time = 00:00:07, memory = 40.42 (MB), peak = 391.20 (MB)
total wire length = 106879 um
total wire length on LAYER li1 = 1524 um
total wire length on LAYER met1 = 34363 um
total wire length on LAYER met2 = 44481 um
total wire length on LAYER met3 = 16210 um
total wire length on LAYER met4 = 9714 um
total wire length on LAYER met5 = 586 um
total number of vias = 2073
up-via summary (total 2073):

-----------------------
 FR_MASTERSLICE       0
            li1     375
           met1     865
           met2     522
           met3     305
           met4       6
-----------------------
                   2073


start 5th optimization iteration ...
    completing 10% with 22 violations
    elapsed time = 00:00:00, memory = 49.12 (MB)
    completing 20% with 22 violations
    elapsed time = 00:00:00, memory = 50.15 (MB)
    completing 30% with 19 violations
    elapsed time = 00:00:00, memory = 49.60 (MB)
    completing 40% with 19 violations
    elapsed time = 00:00:00, memory = 43.64 (MB)
    completing 50% with 19 violations
    elapsed time = 00:00:00, memory = 44.75 (MB)
    completing 60% with 19 violations
    elapsed time = 00:00:00, memory = 43.27 (MB)
    completing 70% with 19 violations
    elapsed time = 00:00:00, memory = 43.27 (MB)
    completing 80% with 11 violations
    elapsed time = 00:00:01, memory = 45.68 (MB)
    completing 90% with 11 violations
    elapsed time = 00:00:01, memory = 45.68 (MB)
    completing 100% with 1 violations
    elapsed time = 00:00:02, memory = 40.24 (MB)
  number of violations = 1
cpu time = 00:00:04, elapsed time = 00:00:03, memory = 40.24 (MB), peak = 391.20 (MB)
total wire length = 106882 um
total wire length on LAYER li1 = 1524 um
total wire length on LAYER met1 = 34370 um
total wire length on LAYER met2 = 44633 um
total wire length on LAYER met3 = 16209 um
total wire length on LAYER met4 = 9559 um
total wire length on LAYER met5 = 586 um
total number of vias = 2091
up-via summary (total 2091):

-----------------------
 FR_MASTERSLICE       0
            li1     375
           met1     873
           met2     530
           met3     307
           met4       6
-----------------------
                   2091


start 6th optimization iteration ...
    completing 10% with 1 violations
    elapsed time = 00:00:00, memory = 46.23 (MB)
    completing 20% with 1 violations
    elapsed time = 00:00:00, memory = 46.23 (MB)
    completing 30% with 1 violations
    elapsed time = 00:00:00, memory = 46.53 (MB)
    completing 40% with 1 violations
    elapsed time = 00:00:00, memory = 43.97 (MB)
    completing 50% with 1 violations
    elapsed time = 00:00:00, memory = 47.92 (MB)
    completing 60% with 1 violations
    elapsed time = 00:00:01, memory = 40.51 (MB)
    completing 70% with 1 violations
    elapsed time = 00:00:01, memory = 40.71 (MB)
    completing 80% with 1 violations
    elapsed time = 00:00:01, memory = 40.84 (MB)
    completing 90% with 1 violations
    elapsed time = 00:00:01, memory = 40.84 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:01, memory = 43.62 (MB)
  number of violations = 0
cpu time = 00:00:03, elapsed time = 00:00:02, memory = 43.62 (MB), peak = 392.70 (MB)
total wire length = 106880 um
total wire length on LAYER li1 = 1524 um
total wire length on LAYER met1 = 34370 um
total wire length on LAYER met2 = 44633 um
total wire length on LAYER met3 = 16210 um
total wire length on LAYER met4 = 9556 um
total wire length on LAYER met5 = 586 um
total number of vias = 2093
up-via summary (total 2093):

-----------------------
 FR_MASTERSLICE       0
            li1     375
           met1     873
           met2     530
           met3     309
           met4       6
-----------------------
                   2093


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 46.62 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 46.62 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 49.21 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 43.85 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 46.52 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 40.70 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 40.70 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:01, memory = 40.51 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:01, memory = 40.45 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:01, memory = 43.91 (MB)
  number of violations = 0
cpu time = 00:00:02, elapsed time = 00:00:01, memory = 43.91 (MB), peak = 392.70 (MB)
total wire length = 106880 um
total wire length on LAYER li1 = 1524 um
total wire length on LAYER met1 = 34370 um
total wire length on LAYER met2 = 44633 um
total wire length on LAYER met3 = 16210 um
total wire length on LAYER met4 = 9556 um
total wire length on LAYER met5 = 586 um
total number of vias = 2093
up-via summary (total 2093):

-----------------------
 FR_MASTERSLICE       0
            li1     375
           met1     873
           met2     530
           met3     309
           met4       6
-----------------------
                   2093


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 45.74 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 43.96 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 43.11 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 43.85 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 44.55 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 43.66 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 43.61 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:01, memory = 42.62 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:01, memory = 42.18 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:01, memory = 42.31 (MB)
  number of violations = 0
cpu time = 00:00:02, elapsed time = 00:00:01, memory = 42.31 (MB), peak = 392.70 (MB)
total wire length = 106880 um
total wire length on LAYER li1 = 1524 um
total wire length on LAYER met1 = 34370 um
total wire length on LAYER met2 = 44633 um
total wire length on LAYER met3 = 16210 um
total wire length on LAYER met4 = 9556 um
total wire length on LAYER met5 = 586 um
total number of vias = 2093
up-via summary (total 2093):

-----------------------
 FR_MASTERSLICE       0
            li1     375
           met1     873
           met2     530
           met3     309
           met4       6
-----------------------
                   2093


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 41.80 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 41.80 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 41.70 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 41.06 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 42.82 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 43.57 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 43.48 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:01, memory = 42.44 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:01, memory = 43.49 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:01, memory = 42.42 (MB)
  number of violations = 0
cpu time = 00:00:02, elapsed time = 00:00:01, memory = 42.42 (MB), peak = 392.70 (MB)
total wire length = 106880 um
total wire length on LAYER li1 = 1524 um
total wire length on LAYER met1 = 34370 um
total wire length on LAYER met2 = 44633 um
total wire length on LAYER met3 = 16210 um
total wire length on LAYER met4 = 9556 um
total wire length on LAYER met5 = 586 um
total number of vias = 2093
up-via summary (total 2093):

-----------------------
 FR_MASTERSLICE       0
            li1     375
           met1     873
           met2     530
           met3     309
           met4       6
-----------------------
                   2093


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 40.53 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 40.53 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 40.50 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 40.50 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 41.96 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:01, memory = 44.38 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:01, memory = 44.38 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:02, memory = 43.45 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:02, memory = 42.22 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:02, memory = 42.77 (MB)
  number of violations = 0
cpu time = 00:00:02, elapsed time = 00:00:02, memory = 42.77 (MB), peak = 392.70 (MB)
total wire length = 106880 um
total wire length on LAYER li1 = 1524 um
total wire length on LAYER met1 = 34370 um
total wire length on LAYER met2 = 44633 um
total wire length on LAYER met3 = 16210 um
total wire length on LAYER met4 = 9556 um
total wire length on LAYER met5 = 586 um
total number of vias = 2093
up-via summary (total 2093):

-----------------------
 FR_MASTERSLICE       0
            li1     375
           met1     873
           met2     530
           met3     309
           met4       6
-----------------------
                   2093


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 43.92 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 42.77 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:01, memory = 43.80 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:01, memory = 43.80 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:01, memory = 42.88 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:01, memory = 41.53 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:01, memory = 41.56 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:01, memory = 42.47 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:01, memory = 41.79 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:01, memory = 41.30 (MB)
  number of violations = 0
cpu time = 00:00:02, elapsed time = 00:00:01, memory = 41.30 (MB), peak = 392.70 (MB)
total wire length = 106880 um
total wire length on LAYER li1 = 1524 um
total wire length on LAYER met1 = 34370 um
total wire length on LAYER met2 = 44633 um
total wire length on LAYER met3 = 16210 um
total wire length on LAYER met4 = 9556 um
total wire length on LAYER met5 = 586 um
total number of vias = 2093
up-via summary (total 2093):

-----------------------
 FR_MASTERSLICE       0
            li1     375
           met1     873
           met2     530
           met3     309
           met4       6
-----------------------
                   2093


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 41.64 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 41.64 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 42.36 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 42.42 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 42.88 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:01, memory = 43.63 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:01, memory = 43.63 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:01, memory = 43.58 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:01, memory = 40.59 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:01, memory = 41.73 (MB)
  number of violations = 0
cpu time = 00:00:02, elapsed time = 00:00:01, memory = 41.73 (MB), peak = 392.70 (MB)
total wire length = 106880 um
total wire length on LAYER li1 = 1524 um
total wire length on LAYER met1 = 34370 um
total wire length on LAYER met2 = 44633 um
total wire length on LAYER met3 = 16210 um
total wire length on LAYER met4 = 9556 um
total wire length on LAYER met5 = 586 um
total number of vias = 2093
up-via summary (total 2093):

-----------------------
 FR_MASTERSLICE       0
            li1     375
           met1     873
           met2     530
           met3     309
           met4       6
-----------------------
                   2093


complete detail routing
total wire length = 106880 um
total wire length on LAYER li1 = 1524 um
total wire length on LAYER met1 = 34370 um
total wire length on LAYER met2 = 44633 um
total wire length on LAYER met3 = 16210 um
total wire length on LAYER met4 = 9556 um
total wire length on LAYER met5 = 586 um
total number of vias = 2093
up-via summary (total 2093):

-----------------------
 FR_MASTERSLICE       0
            li1     375
           met1     873
           met2     530
           met3     309
           met4       6
-----------------------
                   2093

cpu time = 00:03:19, elapsed time = 00:01:57, memory = 41.73 (MB), peak = 392.70 (MB)

post processing ...

Runtime taken (hrt): 121.058
[INFO]: Changing layout from /project/openlane/storage/runs/storage/tmp/routing/addspacers.def to /project/openlane/storage/runs/storage/results/routing/storage.def
[INFO]: Running SPEF Extraction...
Start parsing LEF file...
Parsing LEF file done.
Start parsing DEF file...
Parsing DEF file done.

Parameters Used:
Edge Capacitance Factor: 1.0
Wire model: L 

RC Extraction is done
Start writing SPEF file
Writing SPEF is done
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis_preroute.v, line 26 module sram_1rw1r_32_256_8_sky130 not found.  Creating black box for SRAM_0.
Warning: /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis_preroute.v, line 1630 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found.  Creating black box for PHY_1364.
Warning: /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis_preroute.v, line 2077 module sky130_fd_sc_hd__fill_2 not found.  Creating black box for FILLER_0_15.
Warning: /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis_preroute.v, line 2082 module sky130_fd_sc_hd__fill_1 not found.  Creating black box for FILLER_0_36.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 180 instance ANTENNA_SRAM_0_addr0[0]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 181 instance ANTENNA_SRAM_1_addr0[0]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 206 net ANTENNA_SRAM_0_addr0[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 220 net ANTENNA_SRAM_1_addr0[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 244 SRAM_0 not connected to net mgmt_addr[0].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 253 SRAM_1 not connected to net mgmt_addr[0].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 262 net ANTENNA_SRAM_0_addr0[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 279 net ANTENNA_SRAM_1_addr0[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 304 net ANTENNA_SRAM_0_addr0[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 304 net ANTENNA_SRAM_0_addr0[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 315 net ANTENNA_SRAM_1_addr0[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 315 net ANTENNA_SRAM_1_addr0[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 321 instance ANTENNA_SRAM_0_addr0[1]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 322 instance ANTENNA_SRAM_1_addr0[1]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 336 net ANTENNA_SRAM_0_addr0[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 348 net ANTENNA_SRAM_1_addr0[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 355 SRAM_1 not connected to net mgmt_addr[1].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 365 net ANTENNA_SRAM_0_addr0[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 366 SRAM_0 not connected to net mgmt_addr[1].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 379 net ANTENNA_SRAM_1_addr0[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 379 net ANTENNA_SRAM_1_addr0[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 380 net ANTENNA_SRAM_1_addr0[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 386 net ANTENNA_SRAM_0_addr0[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 386 net ANTENNA_SRAM_0_addr0[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 397 instance ANTENNA_SRAM_0_addr0[2]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 398 instance ANTENNA_SRAM_1_addr0[2]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 407 net ANTENNA_SRAM_1_addr0[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 412 net ANTENNA_SRAM_0_addr0[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 413 SRAM_0 not connected to net mgmt_addr[2].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 433 net ANTENNA_SRAM_1_addr0[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 434 SRAM_1 not connected to net mgmt_addr[2].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 437 net ANTENNA_SRAM_1_addr0[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 442 net ANTENNA_SRAM_0_addr0[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 443 SRAM_0 not connected to net mgmt_addr[2].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 459 net ANTENNA_SRAM_1_addr0[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 459 net ANTENNA_SRAM_1_addr0[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 465 net ANTENNA_SRAM_0_addr0[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 465 net ANTENNA_SRAM_0_addr0[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 474 instance ANTENNA_SRAM_0_addr0[3]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 475 instance ANTENNA_SRAM_1_addr0[3]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 480 net ANTENNA_SRAM_1_addr0[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 485 net ANTENNA_SRAM_0_addr0[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 486 SRAM_0 not connected to net mgmt_addr[3].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 497 net ANTENNA_SRAM_1_addr0[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 498 SRAM_1 not connected to net mgmt_addr[3].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 502 net ANTENNA_SRAM_0_addr0[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 503 SRAM_0 not connected to net mgmt_addr[3].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 503 SRAM_0 not connected to net mgmt_addr[3].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 504 SRAM_0 not connected to net mgmt_addr[3].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 509 net ANTENNA_SRAM_1_addr0[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 509 net ANTENNA_SRAM_1_addr0[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 513 net ANTENNA_SRAM_0_addr0[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 513 net ANTENNA_SRAM_0_addr0[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 521 instance ANTENNA_SRAM_0_addr0[4]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 522 instance ANTENNA_SRAM_1_addr0[4]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 529 SRAM_1 not connected to net mgmt_addr[4].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 531 net ANTENNA_SRAM_0_addr0[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 550 net ANTENNA_SRAM_1_addr0[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 557 SRAM_1 not connected to net mgmt_addr[4].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 558 SRAM_1 not connected to net mgmt_addr[4].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 558 SRAM_1 not connected to net mgmt_addr[4].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 559 net ANTENNA_SRAM_1_addr0[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 560 net ANTENNA_SRAM_0_addr0[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 567 SRAM_0 not connected to net mgmt_addr[4].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 581 net ANTENNA_SRAM_1_addr0[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 581 net ANTENNA_SRAM_1_addr0[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 582 net ANTENNA_SRAM_1_addr0[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 585 net ANTENNA_SRAM_0_addr0[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 585 net ANTENNA_SRAM_0_addr0[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 600 instance ANTENNA_SRAM_0_addr0[5]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 601 instance ANTENNA_SRAM_1_addr0[5]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 614 net ANTENNA_SRAM_0_addr0[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 615 SRAM_0 not connected to net mgmt_addr[5].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 622 net ANTENNA_SRAM_1_addr0[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 630 SRAM_1 not connected to net mgmt_addr[5].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 638 net ANTENNA_SRAM_0_addr0[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 639 SRAM_0 not connected to net mgmt_addr[5].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 643 SRAM_0 not connected to net mgmt_addr[5].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 647 net ANTENNA_SRAM_1_addr0[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 647 net ANTENNA_SRAM_1_addr0[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 648 net ANTENNA_SRAM_1_addr0[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 653 net ANTENNA_SRAM_0_addr0[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 653 net ANTENNA_SRAM_0_addr0[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 661 instance ANTENNA_SRAM_0_addr0[6]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 662 instance ANTENNA_SRAM_1_addr0[6]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 669 SRAM_1 not connected to net mgmt_addr[6].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 673 net ANTENNA_SRAM_0_addr0[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 681 net ANTENNA_SRAM_1_addr0[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 689 SRAM_1 not connected to net mgmt_addr[6].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 693 net ANTENNA_SRAM_0_addr0[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 694 SRAM_0 not connected to net mgmt_addr[6].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 702 net ANTENNA_SRAM_1_addr0[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 702 net ANTENNA_SRAM_1_addr0[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 703 net ANTENNA_SRAM_1_addr0[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 708 net ANTENNA_SRAM_0_addr0[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 708 net ANTENNA_SRAM_0_addr0[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 715 instance ANTENNA_SRAM_0_addr0[7]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 716 instance ANTENNA_SRAM_1_addr0[7]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 721 net ANTENNA_SRAM_1_addr0[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 722 SRAM_1 not connected to net mgmt_addr[7].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 737 net ANTENNA_SRAM_0_addr0[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 740 SRAM_0 not connected to net mgmt_addr[7].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 761 net ANTENNA_SRAM_1_addr0[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 762 SRAM_1 not connected to net mgmt_addr[7].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 762 SRAM_1 not connected to net mgmt_addr[7].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 763 SRAM_1 not connected to net mgmt_addr[7].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 777 net ANTENNA_SRAM_0_addr0[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 781 SRAM_0 not connected to net mgmt_addr[7].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 793 net ANTENNA_SRAM_1_addr0[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 793 net ANTENNA_SRAM_1_addr0[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 806 net ANTENNA_SRAM_0_addr0[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 806 net ANTENNA_SRAM_0_addr0[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 819 instance ANTENNA_SRAM_0_addr1[0]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 825 SRAM_0 not connected to net mgmt_addr_ro[0].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 854 net ANTENNA_SRAM_0_addr1[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 865 SRAM_0 not connected to net mgmt_addr_ro[0].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 865 SRAM_0 not connected to net mgmt_addr_ro[0].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 866 SRAM_0 not connected to net mgmt_addr_ro[0].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 877 net ANTENNA_SRAM_0_addr1[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 904 net ANTENNA_SRAM_0_addr1[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 904 net ANTENNA_SRAM_0_addr1[0] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 922 instance ANTENNA_SRAM_0_addr1[1]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 927 net ANTENNA_SRAM_0_addr1[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 942 net ANTENNA_SRAM_0_addr1[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 951 SRAM_0 not connected to net mgmt_addr_ro[1].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 953 net ANTENNA_SRAM_0_addr1[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 953 net ANTENNA_SRAM_0_addr1[1] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 964 instance ANTENNA_SRAM_0_addr1[2]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 978 net ANTENNA_SRAM_0_addr1[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 989 net ANTENNA_SRAM_0_addr1[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 992 SRAM_0 not connected to net mgmt_addr_ro[2].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 996 net ANTENNA_SRAM_0_addr1[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1001 net ANTENNA_SRAM_0_addr1[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1001 net ANTENNA_SRAM_0_addr1[2] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1011 instance ANTENNA_SRAM_0_addr1[3]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1016 net ANTENNA_SRAM_0_addr1[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1032 net ANTENNA_SRAM_0_addr1[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1040 net ANTENNA_SRAM_0_addr1[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1041 SRAM_0 not connected to net mgmt_addr_ro[3].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1047 net ANTENNA_SRAM_0_addr1[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1047 net ANTENNA_SRAM_0_addr1[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1057 instance ANTENNA_SRAM_0_addr1[4]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1062 net ANTENNA_SRAM_0_addr1[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1065 SRAM_0 not connected to net mgmt_addr_ro[4].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1076 net ANTENNA_SRAM_0_addr1[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1078 net ANTENNA_SRAM_0_addr1[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1079 SRAM_0 not connected to net mgmt_addr_ro[4].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1079 SRAM_0 not connected to net mgmt_addr_ro[4].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1080 SRAM_0 not connected to net mgmt_addr_ro[4].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1087 net ANTENNA_SRAM_0_addr1[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1087 net ANTENNA_SRAM_0_addr1[4] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1099 instance ANTENNA_SRAM_0_addr1[5]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1108 SRAM_0 not connected to net mgmt_addr_ro[5].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1113 net ANTENNA_SRAM_0_addr1[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1121 net ANTENNA_SRAM_0_addr1[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1122 SRAM_0 not connected to net mgmt_addr_ro[5].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1130 net ANTENNA_SRAM_0_addr1[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1130 net ANTENNA_SRAM_0_addr1[5] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1138 instance ANTENNA_SRAM_0_addr1[6]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1152 net ANTENNA_SRAM_0_addr1[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1161 net ANTENNA_SRAM_0_addr1[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1167 SRAM_0 not connected to net mgmt_addr_ro[6].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1170 net ANTENNA_SRAM_0_addr1[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1170 net ANTENNA_SRAM_0_addr1[6] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1180 instance ANTENNA_SRAM_0_addr1[7]:DIODE not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1184 net ANTENNA_SRAM_0_addr1[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1193 net ANTENNA_SRAM_0_addr1[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1196 SRAM_0 not connected to net mgmt_addr_ro[7].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1199 net ANTENNA_SRAM_0_addr1[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1199 net ANTENNA_SRAM_0_addr1[7] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1520 SRAM_0 not connected to net mgmt_rdata[0].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1563 SRAM_0 not connected to net mgmt_rdata[10].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1608 SRAM_0 not connected to net mgmt_rdata[11].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1654 SRAM_0 not connected to net mgmt_rdata[12].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1697 SRAM_0 not connected to net mgmt_rdata[13].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1730 SRAM_0 not connected to net mgmt_rdata[14].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1748 SRAM_0 not connected to net mgmt_rdata[14].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1791 SRAM_0 not connected to net mgmt_rdata[15].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1822 SRAM_0 not connected to net mgmt_rdata[16].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1836 SRAM_0 not connected to net mgmt_rdata[16].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1859 SRAM_0 not connected to net mgmt_rdata[17].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1875 SRAM_0 not connected to net mgmt_rdata[17].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1925 SRAM_0 not connected to net mgmt_rdata[18].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1957 SRAM_0 not connected to net mgmt_rdata[19].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 1973 SRAM_0 not connected to net mgmt_rdata[19].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2013 SRAM_0 not connected to net mgmt_rdata[1].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2045 SRAM_0 not connected to net mgmt_rdata[20].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2059 SRAM_0 not connected to net mgmt_rdata[20].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2094 SRAM_0 not connected to net mgmt_rdata[21].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2125 SRAM_0 not connected to net mgmt_rdata[22].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2166 SRAM_0 not connected to net mgmt_rdata[23].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2207 SRAM_0 not connected to net mgmt_rdata[24].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2230 SRAM_0 not connected to net mgmt_rdata[25].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2253 SRAM_0 not connected to net mgmt_rdata[25].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2301 SRAM_0 not connected to net mgmt_rdata[26].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2345 SRAM_0 not connected to net mgmt_rdata[27].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2393 SRAM_0 not connected to net mgmt_rdata[28].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2425 SRAM_0 not connected to net mgmt_rdata[29].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2455 SRAM_0 not connected to net mgmt_rdata[2].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2480 SRAM_0 not connected to net mgmt_rdata[2].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2505 SRAM_0 not connected to net mgmt_rdata[30].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2523 SRAM_0 not connected to net mgmt_rdata[30].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2563 SRAM_0 not connected to net mgmt_rdata[31].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2582 SRAM_1 not connected to net mgmt_rdata[32].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2600 SRAM_1 not connected to net mgmt_rdata[32].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2629 SRAM_1 not connected to net mgmt_rdata[33].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2645 SRAM_1 not connected to net mgmt_rdata[33].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2676 SRAM_1 not connected to net mgmt_rdata[34].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2689 SRAM_1 not connected to net mgmt_rdata[34].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2711 SRAM_1 not connected to net mgmt_rdata[35].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2722 SRAM_1 not connected to net mgmt_rdata[35].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2744 SRAM_1 not connected to net mgmt_rdata[36].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2762 SRAM_1 not connected to net mgmt_rdata[36].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2794 SRAM_1 not connected to net mgmt_rdata[37].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2815 SRAM_1 not connected to net mgmt_rdata[37].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2839 SRAM_1 not connected to net mgmt_rdata[38].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2851 SRAM_1 not connected to net mgmt_rdata[38].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2889 SRAM_1 not connected to net mgmt_rdata[39].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2932 SRAM_0 not connected to net mgmt_rdata[3].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 2988 SRAM_1 not connected to net mgmt_rdata[40].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3019 SRAM_1 not connected to net mgmt_rdata[41].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3034 SRAM_1 not connected to net mgmt_rdata[41].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3067 SRAM_1 not connected to net mgmt_rdata[42].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3103 SRAM_1 not connected to net mgmt_rdata[42].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3151 SRAM_1 not connected to net mgmt_rdata[43].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3174 SRAM_1 not connected to net mgmt_rdata[44].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3189 SRAM_1 not connected to net mgmt_rdata[44].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3216 SRAM_1 not connected to net mgmt_rdata[45].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3234 SRAM_1 not connected to net mgmt_rdata[45].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3263 SRAM_1 not connected to net mgmt_rdata[46].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3277 SRAM_1 not connected to net mgmt_rdata[46].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3302 SRAM_1 not connected to net mgmt_rdata[47].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3318 SRAM_1 not connected to net mgmt_rdata[47].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3348 SRAM_1 not connected to net mgmt_rdata[48].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3358 SRAM_1 not connected to net mgmt_rdata[48].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3385 SRAM_1 not connected to net mgmt_rdata[49].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3406 SRAM_1 not connected to net mgmt_rdata[49].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3450 SRAM_0 not connected to net mgmt_rdata[4].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3483 SRAM_1 not connected to net mgmt_rdata[50].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3493 SRAM_1 not connected to net mgmt_rdata[50].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3514 SRAM_1 not connected to net mgmt_rdata[51].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3528 SRAM_1 not connected to net mgmt_rdata[51].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3556 SRAM_1 not connected to net mgmt_rdata[52].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3577 SRAM_1 not connected to net mgmt_rdata[52].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3599 SRAM_1 not connected to net mgmt_rdata[53].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3609 SRAM_1 not connected to net mgmt_rdata[53].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3630 SRAM_1 not connected to net mgmt_rdata[54].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3643 SRAM_1 not connected to net mgmt_rdata[54].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3685 SRAM_1 not connected to net mgmt_rdata[55].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3722 SRAM_1 not connected to net mgmt_rdata[56].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3742 SRAM_1 not connected to net mgmt_rdata[57].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3753 SRAM_1 not connected to net mgmt_rdata[57].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3774 SRAM_1 not connected to net mgmt_rdata[58].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3784 SRAM_1 not connected to net mgmt_rdata[58].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3820 SRAM_1 not connected to net mgmt_rdata[59].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3839 SRAM_0 not connected to net mgmt_rdata[5].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3849 SRAM_0 not connected to net mgmt_rdata[5].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3874 SRAM_1 not connected to net mgmt_rdata[60].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3889 SRAM_1 not connected to net mgmt_rdata[60].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3906 SRAM_1 not connected to net mgmt_rdata[61].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3921 SRAM_1 not connected to net mgmt_rdata[61].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3946 SRAM_1 not connected to net mgmt_rdata[62].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3964 SRAM_1 not connected to net mgmt_rdata[62].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 3993 SRAM_1 not connected to net mgmt_rdata[63].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4005 SRAM_1 not connected to net mgmt_rdata[63].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4044 SRAM_0 not connected to net mgmt_rdata[6].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4090 SRAM_0 not connected to net mgmt_rdata[7].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4145 SRAM_0 not connected to net mgmt_rdata[8].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4213 SRAM_0 not connected to net mgmt_rdata[9].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4254 SRAM_0 not connected to net mgmt_rdata_ro[0].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4276 SRAM_0 not connected to net mgmt_rdata_ro[0].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4333 SRAM_0 not connected to net mgmt_rdata_ro[10].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4370 SRAM_0 not connected to net mgmt_rdata_ro[11].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4387 SRAM_0 not connected to net mgmt_rdata_ro[11].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4387 SRAM_0 not connected to net mgmt_rdata_ro[11].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4388 SRAM_0 not connected to net mgmt_rdata_ro[11].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4410 SRAM_0 not connected to net mgmt_rdata_ro[12].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4425 SRAM_0 not connected to net mgmt_rdata_ro[12].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4425 SRAM_0 not connected to net mgmt_rdata_ro[12].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4426 SRAM_0 not connected to net mgmt_rdata_ro[12].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4451 SRAM_0 not connected to net mgmt_rdata_ro[13].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4464 SRAM_0 not connected to net mgmt_rdata_ro[13].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4487 SRAM_0 not connected to net mgmt_rdata_ro[14].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4500 SRAM_0 not connected to net mgmt_rdata_ro[14].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4537 SRAM_0 not connected to net mgmt_rdata_ro[15].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4563 SRAM_0 not connected to net mgmt_rdata_ro[16].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4578 SRAM_0 not connected to net mgmt_rdata_ro[16].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4601 SRAM_0 not connected to net mgmt_rdata_ro[17].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4614 SRAM_0 not connected to net mgmt_rdata_ro[17].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4637 SRAM_0 not connected to net mgmt_rdata_ro[18].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4650 SRAM_0 not connected to net mgmt_rdata_ro[18].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4675 SRAM_0 not connected to net mgmt_rdata_ro[19].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4693 SRAM_0 not connected to net mgmt_rdata_ro[19].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4725 SRAM_0 not connected to net mgmt_rdata_ro[1].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4737 SRAM_0 not connected to net mgmt_rdata_ro[1].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4779 SRAM_0 not connected to net mgmt_rdata_ro[20].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4814 SRAM_0 not connected to net mgmt_rdata_ro[21].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4835 SRAM_0 not connected to net mgmt_rdata_ro[21].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4867 SRAM_0 not connected to net mgmt_rdata_ro[22].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4881 SRAM_0 not connected to net mgmt_rdata_ro[22].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4907 SRAM_0 not connected to net mgmt_rdata_ro[23].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4924 SRAM_0 not connected to net mgmt_rdata_ro[23].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4956 SRAM_0 not connected to net mgmt_rdata_ro[24].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 4975 SRAM_0 not connected to net mgmt_rdata_ro[24].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 5006 SRAM_0 not connected to net mgmt_rdata_ro[25].
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Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 5720 SRAM_0 not connected to net mgmt_rdata_ro[9].
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Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 8895 SRAM_0 not connected to net mgmt_wdata[3].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 8907 net ANTENNA_SRAM_1_din0[3] not found.
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 8910 SRAM_1 not connected to net mgmt_wdata[3].
Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 8921 net ANTENNA_SRAM_0_din0[3] not found.
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Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 9024 SRAM_1 not connected to net mgmt_wdata[4].
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Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 9898 SRAM_0 not connected to net mgmt_wen_mask[0].
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Warning: /project/openlane/storage/runs/storage/results/routing/storage.spef, line 10062 SRAM_0 not connected to net mgmt_wen_mask[2].
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create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 10.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 10.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Routing completed for storage/20-11_16-26 in 0h3m9s
[INFO]: Writing Powered Verilog...
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/results/routing/storage.def
Notice 0: Design: storage
Notice 0:     Created 160 pins.
Notice 0:     Created 4931 components and 10208 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 158 nets and 304 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/results/routing/storage.def
Top-level design name: storage
Found port VPWR of type SIGNAL
Found port VGND of type SIGNAL
Power net:  VPWR
Ground net: VGND
Modified power connections of 4931 cells (Remaining: 0 ).
[INFO]: Writing Verilog...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/tmp/routing/storage.powered.def
Notice 0: Design: storage
Notice 0:     Created 160 pins.
Notice 0:     Created 4931 components and 10208 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 160 nets and 10166 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/tmp/routing/storage.powered.def
[INFO]: Rewriting /project/openlane/storage/runs/storage/results/lvs/storage.lvs.powered.v into /project/openlane/storage/runs/storage/results/lvs/storage.lvs.powered.v
[INFO]: Changing netlist from /project/openlane/storage/runs/storage/results/synthesis/storage.synthesis_preroute.v to /project/openlane/storage/runs/storage/results/lvs/storage.lvs.powered.v
[INFO]: Running Magic...
[INFO]: Streaming out GDS II...

Magic 8.3 revision 64 - Compiled on Fri Oct  9 12:13:18 UTC 2020.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130: scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
This action cannot be undone.
LEF read, Line 61 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 62 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 95 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 96 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 102 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 103 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 104 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 142 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 143 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 145 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 146 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 147 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 183 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 184 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 186 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 187 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 188 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 224 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 225 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 227 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 228 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 229 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 265 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 266 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 772 lines.
Reading LEF data from file /project/openlane/storage/../../lef/sram_1rw1r_32_256_8_sky130_lp1.lef.
This action cannot be undone.
LEF read: Processed 1143 lines.
Reading DEF data from file /project/openlane/storage/runs/storage/results/routing/storage.def.
This action cannot be undone.
  Processed 7 vias total.
  Processed 4931 subcell instances total.
  Processed 160 pins total.
  Processed 2 special nets total.
  Processed 158 nets total.
DEF read: Processed 15428 lines.
Warning: Calma reading is not undoable!  I hope that's OK.
Library written using GDS-II Release 3.0
Library name: sram_1rw1r_32_256_8_sky130
Reading "pk_contact_11".
Reading "pk_contact_17".
Reading "pk_contact_12".
Reading "pk_contact_7".
Reading "pk_pmos_m2_w1_120_sli_dli_da_p".
Reading "pk_contact_23".
Reading "pk_contact_24".
Reading "pk_nmos_m2_w0_740_sli_dli_da_p".
Reading "pk_pmos_m1_w1_120_sli_dli_da_p".
Reading "pk_nmos_m1_w0_360_sli_dli_da_p".
Reading "pk_contact_18".
Reading "pk_contact_13".
Reading "pk_nand3_dec".
Reading "pk_pinv_dec".
CIF file read warning: CIF style sky130: units rescaled by factor of 5 / 1
Reading "pk_nand2_dec".
Reading "pk_nmos_m1_w0_740_sli_dactive".
Reading "pk_pmos_m10_w7_000_sli_dli_da_p".
Reading "pk_pinv".
Reading "pk_pmos_m1_w1_120_sli_dli".
Reading "pk_nmos_m1_w0_740_sactive_dli".
Reading "pk_nmos_m10_w7_000_sli_dli_da_p".
Reading "pk_contact_27".
Reading "pk_pmos_m3_w1_650_sli_dli_da_p".
Reading "pk_and3_dec".
Reading "pk_contact_8".
Reading "pk_pinv_dec_0".
Reading "pk_contact_9".
Reading "pk_nmos_m3_w1_680_sli_dli_da_p".
Reading "pk_pnand2".
Reading "pk_pdriver".
Reading "pk_nmos_m1_w2_880_sli_dli".
Reading "pk_contact_26".
Reading "pk_contact_28".
Reading "pk_contact_29".
Reading "pk_and2_dec".
Reading "pk_contact_14".
Reading "pk_pmos_m1_w0_550_sli_dli".
Reading "pk_contact_15".
Reading "pk_contact_16".
Reading "pk_pmos_m18_w2_000_sli_dli_da_p".
Reading "pk_nmos_m18_w2_000_sli_dli_da_p".
Reading "pk_pmos_m22_w2_000_sli_dli_da_p".
Reading "pk_nmos_m22_w2_000_sli_dli_da_p".
Reading "pk_pmos_m7_w2_000_sli_dli_da_p".
Reading "pk_nmos_m7_w1_680_sli_dli_da_p".
Reading "pk_cell_1rw_1r".
Reading "pk_pmos_m12_w2_000_sli_dli_da_p".
Reading "pk_nmos_m12_w2_000_sli_dli_da_p".
Reading "pk_pmos_m8_w2_000_sli_dli_da_p".
Reading "pk_nmos_m13_w2_000_sli_dli_da_p".
Reading "pk_pmos_m13_w2_000_sli_dli_da_p".
Reading "pk_replica_cell_1rw_1r".
Reading "pk_pinv_3".
Reading "pk_wordline_driver".
Reading "pk_nmos_m8_w1_680_sli_dli_da_p".
Reading "pk_precharge_0".
Reading "pk_pinv_2".
Reading "pk_pmos_m24_w2_000_sli_dli_da_p".
Reading "pk_pmos_m40_w2_000_sli_dli_da_p".
Reading "pk_pand2".
Reading "pk_pmos_m3_w2_000_sli_dli_da_p".
Reading "pk_single_level_column_mux_0".
Reading "pk_sense_amp".
Reading "pk_pinv_1".
Reading "pk_nmos_m1_w0_740_sactive_dactive".
Reading "pk_dff".
Reading "pk_single_level_column_mux".
Reading "pk_contact_19".
Reading "pk_contact_20".
Reading "pk_contact_21".
Reading "pk_contact_22".
Reading "pk_pmos_m5_w2_000_sli_dli_da_p".
Reading "pk_precharge_1".
Reading "pk_hierarchical_predecode2x4".
Reading "pk_hierarchical_predecode3x8".
    100 uses
Reading "pk_write_driver".
Reading "pk_col_cap_cell_1rw_1r".
Reading "pk_dummy_cell_1rw_1r".
Reading "pk_pinv_17".
Reading "pk_nmos_m3_w2_000_sli_dli_da_p".
Reading "pk_pmos_m4_w2_000_sli_dli_da_p".
Reading "pk_nmos_m4_w1_260_sli_dli_da_p".
Reading "pk_nmos_m24_w2_000_sli_dli_da_p".
Reading "pk_row_cap_cell_1rw_1r".
Reading "pk_nmos_m5_w1_680_sli_dli_da_p".
Reading "pk_nmos_m40_w2_000_sli_dli_da_p".
Reading "pk_nmos_m2_w1_260_sli_dli_da_p".
Reading "pk_pinv_16".
Reading "pk_pmos_m2_w1_650_sli_dli_da_p".
Reading "pk_bitcell_array".
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Reading "pk_pinv_19".
Reading "pk_pinv_10".
Reading "pk_precharge_array".
    100 uses
Reading "pk_sense_amp_array".
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Reading "pk_write_driver_array".
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Reading "pk_write_mask_and_array".
Reading "pk_single_level_column_mux_array".
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Reading "pk_pdriver_0".
Reading "pk_pinv_20".
Reading "pk_precharge_array_0".
    100 uses
Reading "pk_single_level_column_mux_array_0".
    100 uses
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Reading "pk_pinv_0".
Reading "pk_hierarchical_decoder".
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Reading "pk_pnand2_0".
Reading "pk_pinv_6".
Reading "pk_pinv_12".
Reading "pk_pinv_18".
Reading "pk_pnand3".
Reading "pk_pdriver_4".
Reading "pk_replica_column_0".
    100 uses
Reading "pk_pinv_14".
Reading "pk_pinv_7".
Reading "pk_pinv_8".
Reading "pk_pinv_9".
Reading "pk_pinv_11".
Reading "pk_wordline_driver_array".
    100 uses
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Reading "pk_pinv_13".
Reading "pk_dff_buf_0".
Reading "pk_replica_column".
    100 uses
Reading "pk_pdriver_3".
Reading "pk_row_cap_array_0".
    100 uses
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Reading "pk_dummy_array".
Reading "pk_col_cap_array".
    100 uses
Reading "pk_row_cap_array".
    100 uses
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Reading "pk_pinv_15".
Reading "pk_port_data".
Reading "pk_cr_1".
Reading "pk_contact_33".
Reading "pk_port_data_0".
Reading "pk_pinvbuf".
Reading "pk_pand2_0".
Reading "pk_pdriver_2".
Reading "pk_pand3_0".
Reading "pk_delay_chain".
    100 uses
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Reading "pk_pnand2_1".
Reading "pk_pdriver_5".
Reading "pk_contact_32".
Reading "pk_cr_0".
Reading "pk_replica_bitcell_array".
Reading "pk_port_address".
Reading "pk_pdriver_1".
Reading "pk_pand3".
Reading "pk_dff_buf_array".
Reading "pk_contact_34".
Reading "pk_cr_2".
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Reading "pk_col_addr_dff".
Reading "pk_control_logic_r".
Error while reading cell "pk_control_logic_r" (byte position 5739906): Warning:  Cell pk_control_logic_r boundary was redefined.
Error while reading cell "pk_control_logic_r" (byte position 5739906): Warning:  Cell pk_control_logic_r boundary was redefined.
Error while reading cell "pk_control_logic_r" (byte position 5739906): Warning:  Cell pk_control_logic_r boundary was redefined.
Error while reading cell "pk_control_logic_r" (byte position 5739906): Warning:  Cell pk_control_logic_r boundary was redefined.
Error while reading cell "pk_control_logic_r" (byte position 5739906): Warning:  Cell pk_control_logic_r boundary was redefined.
Reading "pk_bank".
    100 uses
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Reading "pk_control_logic_rw".
    100 uses
Reading "pk_row_addr_dff".
Reading "pk_wmask_dff".
Reading "pk_data_dff".
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Reading "pk_cr_3".
Reading "pk_sram_1rw1r_32_256_8_sky130".
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Reading "sram_1rw1r_32_256_8_sky130".
[INFO]: Zeroizing Origin
[INFO]: Current Box Values: 0 0 88934 189438
[INFO]: Saving .mag view With BBox Values: 0 0 88934 189438
[INFO]: GDS Write Complete
Generating LEF output /project/openlane/storage/runs/storage/results/magic/storage.lef for cell storage:
Diagnostic:  Write LEF header for cell storage
Diagnostic:  Writing LEF output for cell storage
Diagnostic:  Scale value is 0.005000
[INFO]: LEF Write Complete
[INFO]: MAGIC TAPEOUT STEP DONE
[INFO]: Running Magic Spice Export...

Magic 8.3 revision 64 - Compiled on Fri Oct  9 12:13:18 UTC 2020.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130: scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/project/openlane/storage/runs/storage/tmp/magic_spice.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
This action cannot be undone.
LEF read, Line 61 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 62 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 95 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 96 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 102 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 103 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 104 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 142 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 143 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 145 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 146 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 147 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 183 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 184 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 186 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 187 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 188 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 224 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 225 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 227 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 228 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 229 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 265 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 266 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 772 lines.
Reading LEF data from file /project/openlane/storage/../../lef/sram_1rw1r_32_256_8_sky130_lp1.lef.
This action cannot be undone.
LEF read: Processed 1143 lines.
Reading DEF data from file /project/openlane/storage/runs/storage/results/routing/storage.def.
This action cannot be undone.
  Processed 7 vias total.
  Processed 4931 subcell instances total.
  Processed 160 pins total.
  Processed 2 special nets total.
  Processed 158 nets total.
DEF read: Processed 15428 lines.
Extracting sram_1rw1r_32_256_8_sky130 into sram_1rw1r_32_256_8_sky130.ext:
Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext:
Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:
Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:
Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext:
Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext:
Extracting sky130_fd_sc_hd__decap_12 into sky130_fd_sc_hd__decap_12.ext:
Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:
Extracting sky130_fd_sc_hd__diode_2 into sky130_fd_sc_hd__diode_2.ext:
Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext:
Extracting storage into storage.ext:
exttospice finished.
Using technology "sky130A", version 20200508
[INFO]: Saving Magic Views in /project
[INFO]: Running Magic DRC...

Magic 8.3 revision 64 - Compiled on Fri Oct  9 12:13:18 UTC 2020.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130: scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic_drc.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
This action cannot be undone.
LEF read, Line 61 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 62 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 95 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 96 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 102 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 103 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 104 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 142 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 143 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 145 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 146 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 147 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 183 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 184 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 186 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 187 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 188 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 224 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 225 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 227 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 228 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 229 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 265 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 266 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 772 lines.
Reading LEF data from file /project/openlane/storage/../../lef/sram_1rw1r_32_256_8_sky130_lp1.lef.
This action cannot be undone.
LEF read: Processed 1143 lines.
Reading DEF data from file /project/openlane/storage/runs/storage/results/routing/storage.def.
This action cannot be undone.
  Processed 7 vias total.
  Processed 4931 subcell instances total.
  Processed 160 pins total.
  Processed 2 special nets total.
  Processed 158 nets total.
DEF read: Processed 15428 lines.
[INFO]: Loading storage

DRC style is now "drc(full)"
Loading DRC CIF style.
[INFO]: COUNT: 18
[INFO]: Should be divided by 3 or 4
[INFO]: DRC Checking DONE (/project/openlane/storage/runs/storage/logs/magic/magic.drc)
[INFO]: Saving mag view with DRC errors(/project/openlane/storage/runs/storage/results/magic/storage.drc.mag)
[INFO]: Saved
[INFO]: Running LVS...
[INFO]: /project/openlane/storage/runs/storage/results/magic/storage.spice against /project/openlane/storage/runs/storage/results/lvs/storage.lvs.powered.v
Netgen 1.5.157 compiled on Fri Oct  9 13:50:13 UTC 2020
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Generating JSON file result
Reading netlist file /project/openlane/storage/runs/storage/results/magic/storage.spice
Reading netlist file /project/openlane/storage/runs/storage/results/lvs/storage.lvs.powered.v
Warning:  A case-insensitive file has been read and so the	verilog file must be treated case-insensitive to match.
Creating placeholder cell definition for module sky130_fd_sc_hd__diode_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__fill_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_12.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__fill_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_8.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_6.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_3.
Creating placeholder cell definition for module sky130_fd_sc_hd__tapvpwrvgnd_1.
Creating placeholder cell definition for module sram_1rw1r_32_256_8_sky130.
Note:  Implicit pin clk1
Note:  Implicit pin csb1
Reading setup file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/netgen/sky130A_setup.tcl
Comparison output logged to file /project/openlane/storage/runs/storage/results/lvs/storage.lvs.log
Logging to file "/project/openlane/storage/runs/storage/results/lvs/storage.lvs.log" enabled
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__diode_2'
Circuit sky130_fd_sc_hd__diode_2 contains 0 device instances.
Circuit contains 0 nets, and 3 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__diode_2'
Circuit sky130_fd_sc_hd__diode_2 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__diode_2 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1'
Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances.
Circuit contains 0 nets, and 2 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1'
Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains no devices.
Contents of circuit 1:  Circuit: 'sram_1rw1r_32_256_8_sky130'
Circuit sram_1rw1r_32_256_8_sky130 contains 0 device instances.
Circuit contains 0 nets, and 123 disconnected pins.
Contents of circuit 2:  Circuit: 'sram_1rw1r_32_256_8_sky130'
Circuit sram_1rw1r_32_256_8_sky130 contains 0 device instances.
Circuit contains 0 nets.

Circuit sram_1rw1r_32_256_8_sky130 contains no devices.
Contents of circuit 1:  Circuit: 'storage'
Circuit storage contains 448 device instances.
  Class: sram_1rw1r_32_256_8_sky130 instances:   2
  Class: sky130_fd_sc_hd__diode_2 instances: 104
  Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 342
Circuit contains 202 nets.
Contents of circuit 2:  Circuit: 'storage'
Circuit storage contains 448 device instances.
  Class: sram_1rw1r_32_256_8_sky130 instances:   2
  Class: sky130_fd_sc_hd__diode_2 instances: 104
  Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 342
Circuit contains 202 nets.

Circuit 1 contains 448 devices, Circuit 2 contains 448 devices.
Circuit 1 contains 202 nets,    Circuit 2 contains 202 nets.

Circuits match with 42 symmetries.
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match with 42 symmetries.
Circuits match correctly.
Result: Circuits match uniquely.
Logging to file "/project/openlane/storage/runs/storage/results/lvs/storage.lvs.log" disabled
LVS Done.
LVS reports no net, device, pin, or property mismatches.

Total errors = 0
[INFO]: Running Antenna Checks...
[INFO]: Running OpenROAD Antenna Rule Checker...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/storage/runs/storage/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/storage/runs/storage/results/routing/storage.def
Notice 0: Design: storage
Notice 0:     Created 160 pins.
Notice 0:     Created 4931 components and 10208 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 158 nets and 304 connections.
Notice 0: Finished DEF file: /project/openlane/storage/runs/storage/results/routing/storage.def
Notice 0: Split top of 61 T shapes.
Number of pins violated: 0
Number of nets violated: 0
Total number of nets: 158
[INFO]: Generating Final Summary Report...
[SUCCESS]: Flow Completed Without Fatal Errors.

Submodule: user_id_programming

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/user_id_programming/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/user_id_programming/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/user_id_programming/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/user_id_programming/runs/user_id_programming
[WARNING]: Removing exisiting run /project/openlane/user_id_programming/runs/user_id_programming
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 0.0
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/user_id_programming/../../verilog/rtl/user_id_programming.v
Parsing Verilog input from `/project/openlane/user_id_programming/../../verilog/rtl/user_id_programming.v' to AST representation.
Generating RTLIL representation for module `\user_id_programming'.
Successfully finished Verilog frontend.

3. Executing HIERARCHY pass (managing design hierarchy).

3.1. Analyzing design hierarchy..
Top module:  \user_id_programming

3.2. Analyzing design hierarchy..
Top module:  \user_id_programming
Removed 0 unused modules.

4. Executing SYNTH pass.

4.1. Executing HIERARCHY pass (managing design hierarchy).

4.1.1. Analyzing design hierarchy..
Top module:  \user_id_programming

4.1.2. Analyzing design hierarchy..
Top module:  \user_id_programming
Removed 0 unused modules.

4.2. Executing PROC pass (convert processes to netlists).

4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

4.2.4. Executing PROC_INIT pass (extract init attributes).

4.2.5. Executing PROC_ARST pass (detect async resets in processes).

4.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).

4.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

4.2.8. Executing PROC_DFF pass (convert process syncs to FFs).

4.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.3. Executing FLATTEN pass (flatten design).

4.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.6. Executing CHECK pass (checking for obvious problems).
checking module user_id_programming..
found and reported 0 problems.

4.7. Executing OPT pass (performing simple optimizations).

4.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_id_programming..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_id_programming.
Performed a total of 0 changes.

4.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.7.6. Executing OPT_DFF pass (perform DFF optimizations).

4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.7.9. Finished OPT passes. (There is nothing left to do.)

4.8. Executing FSM pass (extract and optimize FSM).

4.8.1. Executing FSM_DETECT pass (finding FSMs in design).

4.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

4.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

4.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

4.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

4.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

4.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

4.9. Executing OPT pass (performing simple optimizations).

4.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_id_programming..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_id_programming.
Performed a total of 0 changes.

4.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.9.6. Executing OPT_DFF pass (perform DFF optimizations).

4.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.9.9. Finished OPT passes. (There is nothing left to do.)

4.10. Executing WREDUCE pass (reducing word size of cells).

4.11. Executing PEEPOPT pass (run peephole optimizers).

4.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module user_id_programming:
  created 0 $alu and 0 $macc cells.

4.14. Executing SHARE pass (SAT-based resource sharing).

4.15. Executing OPT pass (performing simple optimizations).

4.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_id_programming..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_id_programming.
Performed a total of 0 changes.

4.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.15.6. Executing OPT_DFF pass (perform DFF optimizations).

4.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.15.9. Finished OPT passes. (There is nothing left to do.)

4.16. Executing MEMORY pass.

4.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

4.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

4.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

4.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.18. Executing OPT pass (performing simple optimizations).

4.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.18.3. Executing OPT_DFF pass (perform DFF optimizations).

4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.18.5. Finished fast OPT passes.

4.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

4.20. Executing OPT pass (performing simple optimizations).

4.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_id_programming..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_id_programming.
Performed a total of 0 changes.

4.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.20.6. Executing OPT_SHARE pass.

4.20.7. Executing OPT_DFF pass (perform DFF optimizations).

4.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.20.10. Finished OPT passes. (There is nothing left to do.)

4.21. Executing TECHMAP pass (map to technology primitives).

4.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

4.21.2. Continuing TECHMAP pass.
No more expansions possible.


4.22. Executing OPT pass (performing simple optimizations).

4.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.22.3. Executing OPT_DFF pass (perform DFF optimizations).

4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.22.5. Finished fast OPT passes.

4.23. Executing ABC pass (technology mapping using ABC).

4.23.1. Extracting gate netlist of module `\user_id_programming' to `/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

4.24. Executing OPT pass (performing simple optimizations).

4.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

4.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

4.24.3. Executing OPT_DFF pass (perform DFF optimizations).

4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

4.24.5. Finished fast OPT passes.

4.25. Executing HIERARCHY pass (managing design hierarchy).

4.25.1. Analyzing design hierarchy..
Top module:  \user_id_programming

4.25.2. Analyzing design hierarchy..
Top module:  \user_id_programming
Removed 0 unused modules.

4.26. Printing statistics.

=== user_id_programming ===

   Number of wires:                  5
   Number of wire bits:             98
   Number of public wires:           5
   Number of public wire bits:      98
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     sky130_fd_sc_hd__conb_1        32

4.27. Executing CHECK pass (checking for obvious problems).
checking module user_id_programming..
found and reported 0 problems.

5. Executing SHARE pass (SAT-based resource sharing).

6. Executing OPT pass (performing simple optimizations).

6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_id_programming..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_id_programming.
Performed a total of 0 changes.

6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_id_programming'.
Removed a total of 0 cells.

6.6. Executing OPT_DFF pass (perform DFF optimizations).

6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_id_programming.

6.9. Finished OPT passes. (There is nothing left to do.)

7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..
Removed 0 unused cells and 1 unused wires.


8. Printing statistics.

=== user_id_programming ===

   Number of wires:                  4
   Number of wire bits:             66
   Number of public wires:           4
   Number of public wire bits:      66
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     sky130_fd_sc_hd__conb_1        32

9. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

9.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\user_id_programming':

10. Printing statistics.
[INFO]: ABC: WireLoad : S_2

=== user_id_programming ===

   Number of wires:                  4
   Number of wire bits:             66
   Number of public wires:           4
   Number of public wire bits:      66
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     sky130_fd_sc_hd__conb_1        32

11. Executing ABC pass (technology mapping using ABC).

11.1. Extracting gate netlist of module `\user_id_programming' to `/tmp/yosys-abc-k5jVAL/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

12. Executing SETUNDEF pass (replace undef values with defined constants).

13. Executing HILOMAP pass (mapping to constant drivers).

14. Executing SPLITNETS pass (splitting up multi-bit signals).

15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_id_programming..

16. Executing INSBUF pass (insert buffer cells for connected wires).

17. Executing CHECK pass (checking for obvious problems).
checking module user_id_programming..
found and reported 0 problems.

18. Printing statistics.

=== user_id_programming ===

   Number of wires:                 35
   Number of wire bits:             66
   Number of public wires:          35
   Number of public wire bits:      66
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 32
     sky130_fd_sc_hd__conb_1        32

   Chip area for module '\user_id_programming': 120.115200

19. Executing Verilog backend.
Dumping module `\user_id_programming'.

End of script. Logfile hash: 6e6443fcf4, CPU: user 1.25s system 0.08s, MEM: 43.53 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 48% 2x read_liberty (0 sec), 10% 1x proc_dff (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/user_id_programming/runs/user_id_programming/results/synthesis/user_id_programming.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_id_programming/runs/user_id_programming/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/user_id_programming/runs/user_id_programming/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Info: Added 9 rows of 53 sites.
[INFO] Extracting DIE_AREA and CORE_AREA from the floorplan
[INFO] Floorplanned on a die area of 0.0 0.0 35.545 46.265 (microns). Saving to /project/openlane/user_id_programming/runs/user_id_programming/reports/floorplan/verilog2def.die_area.rpt.
[INFO] Floorplanned on a core area of 5.52 10.88 29.9 35.36 (microns). Saving to /project/openlane/user_id_programming/runs/user_id_programming/reports/floorplan/verilog2def.core_area.rpt.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 24.38
[INFO]: Core area height: 24.479999999999997
[WARNING]: Current core area is too small for a power grid
[WARNING]: Minimizing the power grid!!!!
[INFO]: Changing layout from 0 to /project/openlane/user_id_programming/runs/user_id_programming/tmp/floorplan/verilog2def_openroad.def
[INFO]: Running IO Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_id_programming/runs/user_id_programming/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/user_id_programming/runs/user_id_programming/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_id_programming/runs/user_id_programming/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: user_id_programming
Notice 0:     Created 34 pins.
Notice 0:     Created 32 components and 128 component-terminals.
Notice 0:     Created 66 nets and 64 connections.
Notice 0: Finished DEF file: /project/openlane/user_id_programming/runs/user_id_programming/tmp/floorplan/verilog2def_openroad.def
#Macro blocks found: 0
Warning: using the default boundaries offset (5 microns)
Warning: using the default min distance between IO pins (2 tracks)
WARNING: force pin spread option has no effect when using random pin placement
 > Running IO placement
 * Num of slots          122
 * Num of I/O            34
 * Num of I/O w/sink     32
 * Num of I/O w/o sink   2
 * Slots Per Section     200
 * Slots Increase Factor 0.01
 * Usage Per Section     0.8
 * Usage Increase Factor 0.01
 * Force Pin Spread      1

WARNING: running random pin placement
RandomMode Even
 > IO placement done.
[INFO]: Changing layout from /project/openlane/user_id_programming/runs/user_id_programming/tmp/floorplan/verilog2def_openroad.def to /project/openlane/user_id_programming/runs/user_id_programming/tmp/floorplan/ioPlacer.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_id_programming/runs/user_id_programming/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/user_id_programming/runs/user_id_programming/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_id_programming/runs/user_id_programming/tmp/floorplan/ioPlacer.def
Notice 0: Design: user_id_programming
Notice 0:     Created 34 pins.
Notice 0:     Created 32 components and 128 component-terminals.
Notice 0:     Created 66 nets and 64 connections.
Notice 0: Finished DEF file: /project/openlane/user_id_programming/runs/user_id_programming/tmp/floorplan/ioPlacer.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 0
[INFO] #Original rows: 9
[INFO] #Cut rows: 0
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 18
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 5
Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/user_id_programming/runs/user_id_programming/tmp/floorplan/ioPlacer.def to /project/openlane/user_id_programming/runs/user_id_programming/results/floorplan/user_id_programming.floorplan.def
[INFO]: Running Placement...
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_id_programming/runs/user_id_programming/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/user_id_programming/runs/user_id_programming/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_id_programming/runs/user_id_programming/results/floorplan/user_id_programming.floorplan.def
Notice 0: Design: user_id_programming
Notice 0:     Created 34 pins.
Notice 0:     Created 55 components and 174 component-terminals.
Notice 0:     Created 66 nets and 64 connections.
Notice 0: Finished DEF file: /project/openlane/user_id_programming/runs/user_id_programming/results/floorplan/user_id_programming.floorplan.def
[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (29900, 35360)
[INFO] NumInstances = 55
[INFO] NumPlaceInstances = 32
[INFO] NumFixedInstances = 23
[INFO] NumDummyInstances = 0
[INFO] NumNets = 66
[INFO] NumPins = 98
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (35545, 46265)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (29900, 35360)
[INFO] CoreArea = 596822400
[INFO] NonPlaceInstsArea = 73820800
[INFO] PlaceInstsArea = 120115200
[INFO] Util(%) = 22.966507
[INFO] StdInstsArea = 120115200
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 7.69606e-08 HPWL: 1518430
[InitialPlace]  Iter: 2 CG Error: 0 HPWL: 329660
[InitialPlace]  Iter: 3 CG Error: 0 HPWL: 329660
[InitialPlace]  Iter: 4 CG Error: 0 HPWL: 329660
[InitialPlace]  Iter: 5 CG Error: 0 HPWL: 329660
[INFO] FillerInit: NumGCells = 55
[INFO] FillerInit: NumGNets = 66
[INFO] FillerInit: NumGPins = 98
[INFO] TargetDensity = 0.400000
[INFO] AveragePlaceInstArea = 3753600
[INFO] IdealBinArea = 9384000
[INFO] IdealBinCnt = 63
[INFO] TotalBinArea = 596822400
[INFO] BinCnt = (4, 4)
[INFO] BinSize = (6095, 6120)
[INFO] NumBins = 16
[ERROR] RePlAce diverged at initial iteration.
        Please tune the parameters again (REPL-5)
Error: RePlAce terminated with errors.
[ERROR]: Failure in global placement

    while executing
"global_placement_or"
    (procedure "run_placement" line 8)
    invoked from within
"run_placement"
    (procedure "run_non_interactive_mode" line 13)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: user_id_programming] Fehler 1

Submodule: user_proj_example

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example
[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
mergeLef.py : Merging LEFs
INVX4.lef: SITEs matched found: 0
INVX4.lef: MACROs matched found: 1
NOR2X1.lef: SITEs matched found: 0
NOR2X1.lef: MACROs matched found: 1
AOI21X1.lef: SITEs matched found: 0
AOI21X1.lef: MACROs matched found: 1
BUFX2.lef: SITEs matched found: 0
BUFX2.lef: MACROs matched found: 1
OR2X1.lef: SITEs matched found: 0
OR2X1.lef: MACROs matched found: 1
INVX2.lef: SITEs matched found: 0
INVX2.lef: MACROs matched found: 1
AND2X2.lef: SITEs matched found: 0
AND2X2.lef: MACROs matched found: 1
OR2X2.lef: SITEs matched found: 0
OR2X2.lef: MACROs matched found: 1
AND2X1.lef: SITEs matched found: 0
AND2X1.lef: MACROs matched found: 1
INVX1.lef: SITEs matched found: 0
INVX1.lef: MACROs matched found: 1
INV.lef: SITEs matched found: 0
INV.lef: MACROs matched found: 1
mergeLef.py : Merging LEFs complete
[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 3.68
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v
Parsing Verilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation.
Generating RTLIL representation for module `\AND2X1'.
Generating RTLIL representation for module `\AND2X2'.
Generating RTLIL representation for module `\OR2X1'.
Generating RTLIL representation for module `\OR2X2'.
Generating RTLIL representation for module `\NOR2X1'.
Generating RTLIL representation for module `\NOR2X2'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\INVX1'.
Generating RTLIL representation for module `\INVX2'.
Generating RTLIL representation for module `\INVX3'.
Generating RTLIL representation for module `\INVX4'.
Generating RTLIL representation for module `\BUFX1'.
Generating RTLIL representation for module `\BUFX2'.
Generating RTLIL representation for module `\AOI21X1'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/user_proj_example/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v
Parsing Verilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v
Parsing Verilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v' to AST representation.
Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:9.1-16.10.
Generating RTLIL representation for module `\AND2X1'.
Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:18.1-25.10.
Generating RTLIL representation for module `\AND2X2'.
Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:27.1-35.10.
Generating RTLIL representation for module `\OR2X1'.
Replacing existing blackbox module `\OR2X2' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:37.1-45.10.
Generating RTLIL representation for module `\OR2X2'.
Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:47.1-55.10.
Generating RTLIL representation for module `\NOR2X1'.
Replacing existing blackbox module `\NOR2X2' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:57.1-65.10.
Generating RTLIL representation for module `\NOR2X2'.
Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:67.1-73.10.
Generating RTLIL representation for module `\INV'.
Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:75.1-81.10.
Generating RTLIL representation for module `\INVX1'.
Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:82.1-88.10.
Generating RTLIL representation for module `\INVX2'.
Replacing existing blackbox module `\INVX3' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:89.1-95.10.
Generating RTLIL representation for module `\INVX3'.
Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:96.1-102.10.
Generating RTLIL representation for module `\INVX4'.
Replacing existing blackbox module `\BUFX1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:104.1-110.10.
Generating RTLIL representation for module `\BUFX1'.
Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:111.1-117.10.
Generating RTLIL representation for module `\BUFX2'.
Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:119.1-128.10.
Generating RTLIL representation for module `\AOI21X1'.
Successfully finished Verilog frontend.

6. Executing HIERARCHY pass (managing design hierarchy).

6.1. Analyzing design hierarchy..
Top module:  \user_proj_example

6.2. Analyzing design hierarchy..
Top module:  \user_proj_example
Removed 0 unused modules.

7. Executing SYNTH pass.

7.1. Executing HIERARCHY pass (managing design hierarchy).

7.1.1. Analyzing design hierarchy..
Top module:  \user_proj_example

7.1.2. Analyzing design hierarchy..
Top module:  \user_proj_example
Removed 0 unused modules.

7.2. Executing PROC pass (convert processes to netlists).

7.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

7.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

7.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

7.2.4. Executing PROC_INIT pass (extract init attributes).

7.2.5. Executing PROC_ARST pass (detect async resets in processes).

7.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).

7.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

7.2.8. Executing PROC_DFF pass (convert process syncs to FFs).

7.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

7.3. Executing FLATTEN pass (flatten design).

7.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.6. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [29] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [28] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [27] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [26] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [25] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [24] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [23] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [22] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [21] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [20] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [19] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [18] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [17] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [16] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [15] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [14] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [13] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [12] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [11] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [10] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [9] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [8] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [7] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [6] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [5] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [4] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [3] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [2] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [1] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [0] is used but has no driver.
Warning: Wire user_proj_example.\wbs_ack_o is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [126] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [125] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [124] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [123] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [122] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [121] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [120] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [119] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [118] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [117] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [116] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [115] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [114] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [113] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [112] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [111] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [110] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [109] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [108] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [107] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [106] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [105] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [104] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [103] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [102] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [101] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [100] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [99] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [98] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [97] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [96] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [95] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [94] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [93] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [92] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [91] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [90] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [89] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [88] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [87] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [86] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [85] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [84] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [83] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [82] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [81] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [80] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [79] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [78] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [77] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [76] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [75] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [74] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [73] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [72] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [71] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [70] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [69] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [68] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [67] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [66] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [65] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [64] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [63] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [62] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [61] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [60] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [59] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [57] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [56] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [55] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [54] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [53] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [52] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [51] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [50] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [49] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [48] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [47] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [46] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [45] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [44] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [43] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [42] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [41] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [40] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [39] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [38] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [37] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [36] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [35] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [34] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [33] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [32] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [31] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [30] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [29] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [28] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [27] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [26] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [25] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [24] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [23] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [22] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [21] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [18] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [17] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [15] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [13] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [10] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [6] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [3] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.
Warning: Wire user_proj_example.\io_out [37] is used but has no driver.
Warning: Wire user_proj_example.\io_out [36] is used but has no driver.
Warning: Wire user_proj_example.\io_out [35] is used but has no driver.
Warning: Wire user_proj_example.\io_out [34] is used but has no driver.
Warning: Wire user_proj_example.\io_out [33] is used but has no driver.
Warning: Wire user_proj_example.\io_out [32] is used but has no driver.
Warning: Wire user_proj_example.\io_out [31] is used but has no driver.
Warning: Wire user_proj_example.\io_out [30] is used but has no driver.
Warning: Wire user_proj_example.\io_out [29] is used but has no driver.
Warning: Wire user_proj_example.\io_out [27] is used but has no driver.
Warning: Wire user_proj_example.\io_out [26] is used but has no driver.
Warning: Wire user_proj_example.\io_out [24] is used but has no driver.
Warning: Wire user_proj_example.\io_out [23] is used but has no driver.
Warning: Wire user_proj_example.\io_out [21] is used but has no driver.
Warning: Wire user_proj_example.\io_out [20] is used but has no driver.
Warning: Wire user_proj_example.\io_out [18] is used but has no driver.
Warning: Wire user_proj_example.\io_out [16] is used but has no driver.
Warning: Wire user_proj_example.\io_out [14] is used but has no driver.
Warning: Wire user_proj_example.\io_out [12] is used but has no driver.
Warning: Wire user_proj_example.\io_out [10] is used but has no driver.
Warning: Wire user_proj_example.\io_out [8] is used but has no driver.
Warning: Wire user_proj_example.\io_out [7] is used but has no driver.
Warning: Wire user_proj_example.\io_out [6] is used but has no driver.
Warning: Wire user_proj_example.\io_out [4] is used but has no driver.
Warning: Wire user_proj_example.\io_out [3] is used but has no driver.
Warning: Wire user_proj_example.\io_out [1] is used but has no driver.
Warning: Wire user_proj_example.\io_out [0] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [37] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [36] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [35] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [34] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [33] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [32] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [31] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [30] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [29] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [28] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [27] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [26] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [25] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [24] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [23] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [22] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [21] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [20] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [19] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [18] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [17] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [16] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [15] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [14] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [13] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [12] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [11] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [10] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [9] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [8] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [7] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [6] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [5] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [4] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [3] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [2] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [1] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [0] is used but has no driver.
found and reported 226 problems.

7.7. Executing OPT pass (performing simple optimizations).

7.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

7.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.7.6. Executing OPT_DFF pass (perform DFF optimizations).

7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.7.9. Finished OPT passes. (There is nothing left to do.)

7.8. Executing FSM pass (extract and optimize FSM).

7.8.1. Executing FSM_DETECT pass (finding FSMs in design).

7.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

7.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

7.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

7.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

7.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

7.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

7.9. Executing OPT pass (performing simple optimizations).

7.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

7.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.9.6. Executing OPT_DFF pass (perform DFF optimizations).

7.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.9.9. Finished OPT passes. (There is nothing left to do.)

7.10. Executing WREDUCE pass (reducing word size of cells).

7.11. Executing PEEPOPT pass (run peephole optimizers).

7.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module user_proj_example:
  created 0 $alu and 0 $macc cells.

7.14. Executing SHARE pass (SAT-based resource sharing).

7.15. Executing OPT pass (performing simple optimizations).

7.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

7.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.15.6. Executing OPT_DFF pass (perform DFF optimizations).

7.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.15.9. Finished OPT passes. (There is nothing left to do.)

7.16. Executing MEMORY pass.

7.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

7.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

7.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

7.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

7.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.18. Executing OPT pass (performing simple optimizations).

7.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.


7.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.18.3. Executing OPT_DFF pass (perform DFF optimizations).

7.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.18.5. Finished fast OPT passes.

7.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

7.20. Executing OPT pass (performing simple optimizations).

7.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

7.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.20.6. Executing OPT_SHARE pass.

7.20.7. Executing OPT_DFF pass (perform DFF optimizations).

7.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.20.10. Finished OPT passes. (There is nothing left to do.)

7.21. Executing TECHMAP pass (map to technology primitives).

7.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

7.21.2. Continuing TECHMAP pass.
No more expansions possible.


7.22. Executing OPT pass (performing simple optimizations).

7.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.22.3. Executing OPT_DFF pass (perform DFF optimizations).

7.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.22.5. Finished fast OPT passes.

7.23. Executing ABC pass (technology mapping using ABC).

7.23.1. Extracting gate netlist of module `\user_proj_example' to `/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

7.24. Executing OPT pass (performing simple optimizations).

7.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

7.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

7.24.3. Executing OPT_DFF pass (perform DFF optimizations).

7.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

7.24.5. Finished fast OPT passes.

7.25. Executing HIERARCHY pass (managing design hierarchy).

7.25.1. Analyzing design hierarchy..
Top module:  \user_proj_example

7.25.2. Analyzing design hierarchy..
Top module:  \user_proj_example
Removed 0 unused modules.

7.26. Printing statistics.

=== user_proj_example ===

   Number of wires:                 24
   Number of wire bits:            612
   Number of public wires:          24
   Number of public wire bits:     612
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     BUFX2                           1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     NOR2X1                          1
     OR2X1                           1
     OR2X2                           1

7.27. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.

8. Executing SHARE pass (SAT-based resource sharing).

9. Executing OPT pass (performing simple optimizations).

9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.6. Executing OPT_DFF pass (perform DFF optimizations).

9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.9. Finished OPT passes. (There is nothing left to do.)

10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

11. Printing statistics.

=== user_proj_example ===

   Number of wires:                 24
   Number of wire bits:            612
   Number of public wires:          24
   Number of public wire bits:     612
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     BUFX2                           1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     NOR2X1                          1
     OR2X1                           1
     OR2X2                           1

12. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

12.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\user_proj_example':

13. Printing statistics.
[INFO]: ABC: WireLoad : S_2

=== user_proj_example ===

   Number of wires:                 24
   Number of wire bits:            612
   Number of public wires:          24
   Number of public wire bits:     612
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     BUFX2                           1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     NOR2X1                          1
     OR2X1                           1
     OR2X2                           1

14. Executing ABC pass (technology mapping using ABC).

14.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-o5B5Wf/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

15. Executing SETUNDEF pass (replace undef values with defined constants).

16. Executing HILOMAP pass (mapping to constant drivers).

17. Executing SPLITNETS pass (splitting up multi-bit signals).

18. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 0 unused cells and 226 unused wires.


19. Executing INSBUF pass (insert buffer cells for connected wires).

20. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.

21. Printing statistics.

=== user_proj_example ===

   Number of wires:                 24
   Number of wire bits:            612
   Number of public wires:          24
   Number of public wire bits:     612
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                237
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     BUFX2                           1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     NOR2X1                          1
     OR2X1                           1
     OR2X2                           1
     sky130_fd_sc_hd__conb_1       226

   Area for cell type \AND2X1 is unknown!
   Area for cell type \AND2X2 is unknown!
   Area for cell type \OR2X1 is unknown!
   Area for cell type \OR2X2 is unknown!
   Area for cell type \NOR2X1 is unknown!
   Area for cell type \INV is unknown!
   Area for cell type \INVX1 is unknown!
   Area for cell type \INVX2 is unknown!
   Area for cell type \INVX4 is unknown!
   Area for cell type \BUFX2 is unknown!
   Area for cell type \AOI21X1 is unknown!

   Chip area for module '\user_proj_example': 848.313600

22. Executing Verilog backend.
Dumping module `\user_proj_example'.

Warnings: 226 unique messages, 226 total
End of script. Logfile hash: e660afa8d2, CPU: user 1.66s system 0.06s, MEM: 43.58 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 50% 2x read_liberty (0 sec), 8% 1x proc_dff (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 706 module AND2X1 not found.  Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 713 module AND2X2 not found.  Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 720 module AOI21X1 not found.  Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 728 module BUFX2 not found.  Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 734 module INV not found.  Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 740 module INVX1 not found.  Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 746 module INVX2 not found.  Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 752 module INVX4 not found.  Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 758 module NOR2X1 not found.  Creating black box for NOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 765 module OR2X1 not found.  Creating black box for OR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 772 module OR2X2 not found.  Creating black box for OR2X2.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61084.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX4 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61136.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro NOR2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61199.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AOI21X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61273.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro BUFX2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61325.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro OR2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61388.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61440.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AND2X2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61503.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro OR2X2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61566.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AND2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61629.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61681.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INV references unkown site CORE
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 448 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 706 instance AND2X1 port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 706 instance AND2X1 port vdd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 713 instance AND2X2 port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 713 instance AND2X2 port vdd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 720 instance AOI21X1 port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 720 instance AOI21X1 port vdd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 728 instance BUFX2 port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 728 instance BUFX2 port vdd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 734 instance INV port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 734 instance INV port vdd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 740 instance INVX1 port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 740 instance INVX1 port vdd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 746 instance INVX2 port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 746 instance INVX2 port vdd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 752 instance INVX4 port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 752 instance INVX4 port vdd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 758 instance NOR2X1 port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 758 instance NOR2X1 port vdd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 765 instance OR2X1 port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 765 instance OR2X1 port vdd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 772 instance OR2X2 port gnd not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 772 instance OR2X2 port vdd not found.
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF master AND2X1 has no liberty cell.
Warning: LEF master AND2X2 has no liberty cell.
Warning: LEF master AOI21X1 has no liberty cell.
Warning: LEF master BUFX2 has no liberty cell.
Warning: LEF master INV has no liberty cell.
Warning: LEF master INVX1 has no liberty cell.
Warning: LEF master INVX2 has no liberty cell.
Warning: LEF master INVX4 has no liberty cell.
Warning: LEF master NOR2X1 has no liberty cell.
Warning: LEF master OR2X1 has no liberty cell.
Warning: LEF master OR2X2 has no liberty cell.
Info: Added 83 rows of 519 sites.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 238.95999999999998
[INFO]: Core area height: 228.24
[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
[INFO]: Running IO Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61084.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX4 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61136.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro NOR2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61199.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AOI21X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61273.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro BUFX2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61325.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro OR2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61388.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61440.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AND2X2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61503.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro OR2X2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61566.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AND2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61629.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef at line 61681.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INV references unkown site CORE
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 448 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: user_proj_example
Notice 0:     Created 612 pins.
Notice 0:     Created 237 components and 955 component-terminals.
Notice 0:     Created 612 nets and 255 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
#Macro blocks found: 0
Warning: using the default boundaries offset (5 microns)
Warning: using the default min distance between IO pins (2 tracks)
WARNING: force pin spread option has no effect when using random pin placement
 > Running IO placement
 * Num of slots          888
 * Num of I/O            612
 * Num of I/O w/sink     255
 * Num of I/O w/o sink   357
 * Slots Per Section     200
 * Slots Increase Factor 0.01
 * Usage Per Section     0.8
 * Usage Increase Factor 0.01
 * Force Pin Spread      1

WARNING: running random pin placement
RandomMode Even
 > IO placement done.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61084.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX4 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61136.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro NOR2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61199.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AOI21X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61273.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro BUFX2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61325.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro OR2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61388.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61440.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AND2X2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61503.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro OR2X2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61566.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AND2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61629.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61681.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INV references unkown site CORE
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 448 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
Notice 0: Design: user_proj_example
Notice 0:     Created 612 pins.
Notice 0:     Created 237 components and 955 component-terminals.
Notice 0:     Created 612 nets and 255 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (244260, 236640)
[INFO] NumInstances = 237
[INFO] NumPlaceInstances = 237
[INFO] NumFixedInstances = 0
[INFO] NumDummyInstances = 0
[INFO] NumNets = 612
[INFO] NumPins = 867
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (250000, 250000)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (244260, 236640)
[INFO] CoreArea = 53897942400
[INFO] NonPlaceInstsArea = 0
[INFO] PlaceInstsArea = 848313600
[INFO] Util(%) = 1.573926
[INFO] StdInstsArea = 848313600
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 1.14421e-07 HPWL: 63634510
[InitialPlace]  Iter: 2 CG Error: 2.11846e-08 HPWL: 6466281
[InitialPlace]  Iter: 3 CG Error: 8.54941e-08 HPWL: 6325092
[InitialPlace]  Iter: 4 CG Error: 2.93002e-08 HPWL: 6230376
[InitialPlace]  Iter: 5 CG Error: 2.7879e-08 HPWL: 6165956
[INFO] FillerInit: NumGCells = 2164
[INFO] FillerInit: NumGNets = 612
[INFO] FillerInit: NumGPins = 867
[INFO] TargetDensity = 0.150000
[INFO] AveragePlaceInstArea = 3579382
[INFO] IdealBinArea = 23862546
[INFO] IdealBinCnt = 2258
[INFO] TotalBinArea = 53897942400
[INFO] BinCnt = (64, 64)
[INFO] BinSize = (3731, 3528)
[INFO] NumBins = 4096
[NesterovSolve] Iter: 1 overflow: 0.279783 HPWL: 5556895
[NesterovSolve] Iter: 10 overflow: 0.27929 HPWL: 5488983
[NesterovSolve] Iter: 20 overflow: 0.279755 HPWL: 5466342
[NesterovSolve] Iter: 30 overflow: 0.279743 HPWL: 5466809
[NesterovSolve] Iter: 40 overflow: 0.279698 HPWL: 5467744
[NesterovSolve] Iter: 50 overflow: 0.279554 HPWL: 5470229
[NesterovSolve] Finished with Overflow: 0.279475
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from LEF macro
Warning: Liberty cell sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from LEF macro
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
[INFO]: Global placement was successful
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
[INFO]: Running Basic Macro Placement
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61084.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX4 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61136.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro NOR2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61199.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AOI21X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61273.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro BUFX2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61325.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro OR2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61388.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61440.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AND2X2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61503.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro OR2X2 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61566.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro AND2X1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61629.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INVX1 references unkown site CORE
Notice 0: Warning: WARNING (LEFPARS-2032): A SITE statement is defined before SYMMETRY statement.
To avoid this warning in the future, define SITE after SYMMETRY See file /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef at line 61681.

Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: error: undefined layer (metal2) referenced
Notice 0: warning: macro INV references unkown site CORE
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 448 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Warning: /project/openlane/user_proj_example/runs/user_proj_example/tmp/trimmed.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
Notice 0: Design: user_proj_example
Notice 0:     Created 612 pins.
Notice 0:     Created 237 components and 955 component-terminals.
Notice 0:     Created 612 nets and 255 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
[PROC] End Parsing Global Config
[PROC] Begin Extracting Macro Cells ...
[ERROR] Cannot find any macros in this design.
 (MAPL-3)
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_basic_mp.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/user_proj_example/logs/placement/basic_mp.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check openroad  log file
[ERROR]: Dumping to /project/openlane/user_proj_example/runs/user_proj_example/error.log

    while executing
"try_catch openroad -exit $::env(SCRIPTS_DIR)/openroad/or_basic_mp.tcl |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/placement/basic_mp.log"
    (procedure "basic_macro_placement" line 6)
    invoked from within
"basic_macro_placement"
    (procedure "run_floorplan" line 24)
    invoked from within
"run_floorplan"
    (procedure "run_non_interactive_mode" line 12)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: user_proj_example] Fehler 1

Submodule: user_project_wrapper

###############################################
/bin/sh: 1: [[: not found
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: rc4
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/user_project_wrapper/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/user_project_wrapper/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/user_project_wrapper/config.tcl
[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.
[INFO]: Current run directory is /project/openlane/user_project_wrapper/runs/user_project_wrapper
[WARNING]: Removing exisiting run /project/openlane/user_project_wrapper/runs/user_project_wrapper
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
mergeLef.py : Merging LEFs
user_proj_example.lef: SITEs matched found: 0
user_proj_example.lef: MACROs matched found: 1
mergeLef.py : Merging LEFs complete
[INFO]: Merging the following extra LEFs:  /project/openlane/user_project_wrapper/../../lef/user_proj_example.lef
padLefMacro.py : Padding technology lef file
Derived SITE width (microns): 0.46
Derived SITE height (microns): 5.44
Right cell padding (microns): 3.68
Left cell padding (microns): 0.0
Top cell padding (microns): 0.0
Bottom cell padding (microns): 0.0
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_4
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvgnd2_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_12
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_3
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_6
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_2
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tapvpwrvgnd_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__decap_8
Skipping LEF padding for MACRO  sky130_fd_sc_hd__tap_1
Skipping LEF padding for MACRO  sky130_fd_sc_hd__fill_2
padLefMacro.py : Finished
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v' to AST representation.
Generating RTLIL representation for module `\user_project_wrapper'.
Successfully finished Verilog frontend.

5. Executing HIERARCHY pass (managing design hierarchy).

5.1. Analyzing design hierarchy..
Top module:  \user_project_wrapper

5.2. Analyzing design hierarchy..
Top module:  \user_project_wrapper
Removed 0 unused modules.

6. Executing SYNTH pass.

6.1. Executing HIERARCHY pass (managing design hierarchy).

6.1.1. Analyzing design hierarchy..
Top module:  \user_project_wrapper

6.1.2. Analyzing design hierarchy..
Top module:  \user_project_wrapper
Removed 0 unused modules.

6.2. Executing PROC pass (convert processes to netlists).

6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

6.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

6.2.4. Executing PROC_INIT pass (extract init attributes).

6.2.5. Executing PROC_ARST pass (detect async resets in processes).

6.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).

6.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

6.2.8. Executing PROC_DFF pass (convert process syncs to FFs).

6.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

6.3. Executing FLATTEN pass (flatten design).

6.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.6. Executing CHECK pass (checking for obvious problems).
checking module user_project_wrapper..
found and reported 0 problems.

6.7. Executing OPT pass (performing simple optimizations).

6.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_project_wrapper..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_project_wrapper.
Performed a total of 0 changes.

6.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.7.6. Executing OPT_DFF pass (perform DFF optimizations).

6.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.7.9. Finished OPT passes. (There is nothing left to do.)

6.8. Executing FSM pass (extract and optimize FSM).

6.8.1. Executing FSM_DETECT pass (finding FSMs in design).

6.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

6.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

6.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

6.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

6.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

6.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

6.9. Executing OPT pass (performing simple optimizations).

6.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_project_wrapper..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_project_wrapper.
Performed a total of 0 changes.

6.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.9.6. Executing OPT_DFF pass (perform DFF optimizations).

6.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.9.9. Finished OPT passes. (There is nothing left to do.)

6.10. Executing WREDUCE pass (reducing word size of cells).

6.11. Executing PEEPOPT pass (run peephole optimizers).

6.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module user_project_wrapper:
  created 0 $alu and 0 $macc cells.

6.14. Executing SHARE pass (SAT-based resource sharing).

6.15. Executing OPT pass (performing simple optimizations).

6.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_project_wrapper..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_project_wrapper.
Performed a total of 0 changes.

6.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.15.6. Executing OPT_DFF pass (perform DFF optimizations).

6.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.15.9. Finished OPT passes. (There is nothing left to do.)

6.16. Executing MEMORY pass.

6.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

6.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

6.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

6.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

6.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.18. Executing OPT pass (performing simple optimizations).

6.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.18.3. Executing OPT_DFF pass (perform DFF optimizations).

6.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.18.5. Finished fast OPT passes.

6.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

6.20. Executing OPT pass (performing simple optimizations).

6.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_project_wrapper..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_project_wrapper.
Performed a total of 0 changes.

6.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.20.6. Executing OPT_SHARE pass.

6.20.7. Executing OPT_DFF pass (perform DFF optimizations).

6.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.20.10. Finished OPT passes. (There is nothing left to do.)

6.21. Executing TECHMAP pass (map to technology primitives).

6.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

6.21.2. Continuing TECHMAP pass.
No more expansions possible.


6.22. Executing OPT pass (performing simple optimizations).

6.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.22.3. Executing OPT_DFF pass (perform DFF optimizations).

6.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.22.5. Finished fast OPT passes.

6.23. Executing ABC pass (technology mapping using ABC).

6.23.1. Extracting gate netlist of module `\user_project_wrapper' to `/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

6.24. Executing OPT pass (performing simple optimizations).

6.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

6.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

6.24.3. Executing OPT_DFF pass (perform DFF optimizations).

6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

6.24.5. Finished fast OPT passes.

6.25. Executing HIERARCHY pass (managing design hierarchy).

6.25.1. Analyzing design hierarchy..
Top module:  \user_project_wrapper

6.25.2. Analyzing design hierarchy..
Top module:  \user_project_wrapper
Removed 0 unused modules.

6.26. Printing statistics.

=== user_project_wrapper ===

   Number of wires:                 26
   Number of wire bits:            644
   Number of public wires:          26
   Number of public wire bits:     644
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     user_proj_example               1

6.27. Executing CHECK pass (checking for obvious problems).
checking module user_project_wrapper..
found and reported 0 problems.

7. Executing SHARE pass (SAT-based resource sharing).

8. Executing OPT pass (performing simple optimizations).

8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_project_wrapper..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_project_wrapper.
Performed a total of 0 changes.

8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_project_wrapper'.
Removed a total of 0 cells.

8.6. Executing OPT_DFF pass (perform DFF optimizations).

8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_project_wrapper.

8.9. Finished OPT passes. (There is nothing left to do.)

9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

10. Printing statistics.

=== user_project_wrapper ===

   Number of wires:                 26
   Number of wire bits:            644
   Number of public wires:          26
   Number of public wire bits:     644
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     user_proj_example               1

11. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\user_project_wrapper':

12. Printing statistics.
[INFO]: ABC: WireLoad : S_2

=== user_project_wrapper ===

   Number of wires:                 26
   Number of wire bits:            644
   Number of public wires:          26
   Number of public wire bits:     644
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     user_proj_example               1

13. Executing ABC pass (technology mapping using ABC).

13.1. Extracting gate netlist of module `\user_project_wrapper' to `/tmp/yosys-abc-FH9jbe/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

14. Executing SETUNDEF pass (replace undef values with defined constants).

15. Executing HILOMAP pass (mapping to constant drivers).

16. Executing SPLITNETS pass (splitting up multi-bit signals).

17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

18. Executing INSBUF pass (insert buffer cells for connected wires).

19. Executing CHECK pass (checking for obvious problems).
checking module user_project_wrapper..
found and reported 0 problems.

20. Printing statistics.

=== user_project_wrapper ===

   Number of wires:                 26
   Number of wire bits:            644
   Number of public wires:          26
   Number of public wire bits:     644
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     user_proj_example               1

   Area for cell type \user_proj_example is unknown!

21. Executing Verilog backend.
Dumping module `\user_project_wrapper'.

End of script. Logfile hash: a37b80cdbf, CPU: user 0.43s system 0.00s, MEM: 14.89 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 24% 4x stat (0 sec), 24% 1x dfflibmap (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v, line 30 module user_proj_example not found.  Creating black box for mprj.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF master user_proj_example has no liberty cell.
Info: Added 1352 rows of 5845 sites.
[INFO]: Floorplanning was successful
[INFO]: Core area width: 2688.96
[INFO]: Core area height: 3678.24
[INFO]: Changing layout from 0 to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def
Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: user_project_wrapper
Notice 0:     Created 644 pins.
Notice 0:     Created 1 components and 614 component-terminals.
Notice 0:     Created 644 nets and 612 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def
Top-level design name: user_project_wrapper
Warning: Multiple regexes matched vssa1 . Those are vssa1$ and vssa1$
Only the first one is taken into consideration.
Warning: Multiple regexes matched vdda1 . Those are vdda1$ and vdda1$
Only the first one is taken into consideration.
Warning: Some pins weren't matched by the config file
Those are: ['analog_io[0]', 'analog_io[1]', 'analog_io[2]', 'analog_io[3]', 'analog_io[4]', 'analog_io[5]', 'analog_io[6]', 'analog_io[7]', 'analog_io[8]', 'analog_io[9]', 'analog_io[10]', 'analog_io[11]', 'analog_io[12]', 'analog_io[13]', 'analog_io[14]', 'analog_io[15]', 'analog_io[16]', 'analog_io[17]', 'analog_io[18]', 'analog_io[19]', 'analog_io[20]', 'analog_io[21]', 'analog_io[22]', 'analog_io[23]', 'analog_io[24]', 'analog_io[25]', 'analog_io[26]', 'analog_io[27]', 'analog_io[28]', 'analog_io[29]', 'analog_io[30]']
Assigning random sides to the above pins
Block boundaries: 0 0 2700000 3700000
Writing /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
[INFO]: Running Global Placement...
OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
Notice 0: Design: user_project_wrapper
Notice 0:     Created 644 pins.
Notice 0:     Created 1 components and 614 component-terminals.
Notice 0:     Created 644 nets and 612 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (2694220, 3688320)
[INFO] NumInstances = 1
[INFO] NumPlaceInstances = 1
[INFO] NumFixedInstances = 0
[INFO] NumDummyInstances = 0
[INFO] NumNets = 644
[INFO] NumPins = 1256
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (2700000, 3700000)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (2694220, 3688320)
[INFO] CoreArea = 9887532928000
[INFO] NonPlaceInstsArea = 0
[INFO] PlaceInstsArea = 62500000000
[INFO] Util(%) = 0.632109
[INFO] StdInstsArea = 0
[INFO] MacroInstsArea = 62500000000
[InitialPlace]  Iter: 1 CG Error: 0 HPWL: 1247797600
[InitialPlace]  Iter: 2 CG Error: 0 HPWL: 1358623820
[InitialPlace]  Iter: 3 CG Error: 0 HPWL: 1189149916
[InitialPlace]  Iter: 4 CG Error: 0 HPWL: 1047161837
[InitialPlace]  Iter: 5 CG Error: 0 HPWL: 964524465
[INFO] FillerInit: NumGCells = 1
[INFO] FillerInit: NumGNets = 644
[INFO] FillerInit: NumGPins = 1256
[INFO] TargetDensity = 0.001000
[INFO] AveragePlaceInstArea = 62500000000
[INFO] IdealBinArea = 62499994992640
[INFO] IdealBinCnt = 0
[INFO] TotalBinArea = 9887532928000
[INFO] BinCnt = (2048, 2048)
[INFO] BinSize = (1313, 1796)
[INFO] NumBins = 4194304
[NesterovSolve] Iter: 1 overflow: 0 HPWL: 800549360
[NesterovSolve] Iter: 10 overflow: 0 HPWL: 800549360
[NesterovSolve] Iter: 20 overflow: 0 HPWL: 800549360
[NesterovSolve] Iter: 30 overflow: 0 HPWL: 800549360
[ERROR] RePlAce divergence detected. 
        Please decrease init_density_penalty value (REPL-3)
Error: RePlAce terminated with errors.
[ERROR]: Failure in global placement

    while executing
"global_placement_or"
    (procedure "run_floorplan" line 19)
    invoked from within
"run_floorplan"
    (procedure "run_non_interactive_mode" line 12)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: user_project_wrapper] Fehler 1