philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts$ bash deploy2caravel.sh
Cleaning up old files
Copying files that were created by StdCellLib
Removing cells with DRC issues left
Checking AND2X1
Checking AND2X2
Checking AOI21X1
Checking AOI22X1
Checking BUFX2
Checking BUFX4
Removing cell with 2 DRC issues:
Checking CLKBUF1
Removing cell with 7 DRC issues:
Checking corr_XOR2X1
Error: Could not find DRC: /home/philipp/libresilicon/StdCellLib/corr_XOR2X1.drc No such file or directory
Removing cell with 1 DRC issues:
Checking HAX1
Checking INV
Checking INVX1
Checking INVX2
Checking INVX4
Checking INVX8
Checking LATCH
Removing cell with 1 DRC issues:
Checking MUX2X1
Checking NAND2X1
Checking NAND3X1
Checking NOR2X1
Checking NOR3X1
Removing cell with 60 DRC issues:
Checking OAI21X1
Checking OAI22X1
Checking OR2X1
Checking OR2X2
Removing cell with 7 DRC issues:
Checking XNOR2X1
Checking XOR2X1
Removing cell with 1 DRC issues:
Now cleaning up the files for Sky130
origlef: orig/AND2X1.lef
lef: AND2X1.lef
mag:../mag/AND2X1.mag
Extracting Obstruction information from ../mag/AND2X1.mag
AND2X1.lef
AND2X1.lef -> 5.76 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file AND2X1.lef.
This action cannot be undone.
LEF read: Processed 196 lines.
Generating LEF output AND2X1.lef for cell AND2X1:
Diagnostic: Write LEF header for cell AND2X1
Diagnostic: Writing LEF output for cell AND2X1
Diagnostic: Scale value is 0.010000
origlef: orig/AND2X2.lef
lef: AND2X2.lef
mag:../mag/AND2X2.mag
Extracting Obstruction information from ../mag/AND2X2.mag
AND2X2.lef
AND2X2.lef -> 5.76 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file AND2X2.lef.
This action cannot be undone.
LEF read: Processed 196 lines.
Generating LEF output AND2X2.lef for cell AND2X2:
Diagnostic: Write LEF header for cell AND2X2
Diagnostic: Writing LEF output for cell AND2X2
Diagnostic: Scale value is 0.010000
origlef: orig/AOI21X1.lef
lef: AOI21X1.lef
mag:../mag/AOI21X1.mag
Extracting Obstruction information from ../mag/AOI21X1.mag
AOI21X1.lef
AOI21X1.lef -> 5.76 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file AOI21X1.lef.
This action cannot be undone.
LEF read: Processed 212 lines.
Generating LEF output AOI21X1.lef for cell AOI21X1:
Diagnostic: Write LEF header for cell AOI21X1
Diagnostic: Writing LEF output for cell AOI21X1
Diagnostic: Scale value is 0.010000
origlef: orig/AOI22X1.lef
lef: AOI22X1.lef
mag:../mag/AOI22X1.mag
Extracting Obstruction information from ../mag/AOI22X1.mag
AOI22X1.lef
AOI22X1.lef -> 7.2 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file AOI22X1.lef.
This action cannot be undone.
LEF read: Processed 253 lines.
Generating LEF output AOI22X1.lef for cell AOI22X1:
Diagnostic: Write LEF header for cell AOI22X1
Diagnostic: Writing LEF output for cell AOI22X1
Diagnostic: Scale value is 0.010000
origlef: orig/BUFX2.lef
lef: BUFX2.lef
mag:../mag/BUFX2.mag
Extracting Obstruction information from ../mag/BUFX2.mag
BUFX2.lef
BUFX2.lef -> 4.32 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file BUFX2.lef.
This action cannot be undone.
LEF read: Processed 155 lines.
Generating LEF output BUFX2.lef for cell BUFX2:
Diagnostic: Write LEF header for cell BUFX2
Diagnostic: Writing LEF output for cell BUFX2
Diagnostic: Scale value is 0.010000
origlef: orig/HAX1.lef
lef: HAX1.lef
mag:../mag/HAX1.mag
Extracting Obstruction information from ../mag/HAX1.mag
HAX1.lef
HAX1.lef -> 15.84 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file HAX1.lef.
This action cannot be undone.
LEF read: Processed 396 lines.
Generating LEF output HAX1.lef for cell HAX1:
Diagnostic: Write LEF header for cell HAX1
Diagnostic: Writing LEF output for cell HAX1
Diagnostic: Scale value is 0.010000
origlef: orig/INV.lef
lef: INV.lef
mag:../mag/INV.mag
Extracting Obstruction information from ../mag/INV.mag
INV.lef
INV.lef -> 2.88 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file INV.lef.
This action cannot be undone.
LEF read: Processed 69 lines.
Generating LEF output INV.lef for cell INV:
Diagnostic: Write LEF header for cell INV
Diagnostic: Writing LEF output for cell INV
Diagnostic: Scale value is 0.010000
origlef: orig/INVX1.lef
lef: INVX1.lef
mag:../mag/INVX1.mag
Extracting Obstruction information from ../mag/INVX1.mag
INVX1.lef
INVX1.lef -> 2.88 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file INVX1.lef.
This action cannot be undone.
LEF read: Processed 69 lines.
Generating LEF output INVX1.lef for cell INVX1:
Diagnostic: Write LEF header for cell INVX1
Diagnostic: Writing LEF output for cell INVX1
Diagnostic: Scale value is 0.010000
origlef: orig/INVX2.lef
lef: INVX2.lef
mag:../mag/INVX2.mag
Extracting Obstruction information from ../mag/INVX2.mag
INVX2.lef
INVX2.lef -> 2.88 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file INVX2.lef.
This action cannot be undone.
LEF read: Processed 69 lines.
Generating LEF output INVX2.lef for cell INVX2:
Diagnostic: Write LEF header for cell INVX2
Diagnostic: Writing LEF output for cell INVX2
Diagnostic: Scale value is 0.010000
origlef: orig/INVX4.lef
lef: INVX4.lef
mag:../mag/INVX4.mag
Extracting Obstruction information from ../mag/INVX4.mag
INVX4.lef
INVX4.lef -> 4.32 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file INVX4.lef.
This action cannot be undone.
LEF read: Processed 169 lines.
Generating LEF output INVX4.lef for cell INVX4:
Diagnostic: Write LEF header for cell INVX4
Diagnostic: Writing LEF output for cell INVX4
Diagnostic: Scale value is 0.010000
origlef: orig/INVX8.lef
lef: INVX8.lef
mag:../mag/INVX8.mag
Extracting Obstruction information from ../mag/INVX8.mag
INVX8.lef
INVX8.lef -> 7.2 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file INVX8.lef.
This action cannot be undone.
LEF read: Processed 258 lines.
Generating LEF output INVX8.lef for cell INVX8:
Diagnostic: Write LEF header for cell INVX8
Diagnostic: Writing LEF output for cell INVX8
Diagnostic: Scale value is 0.010000
origlef: orig/MUX2X1.lef
lef: MUX2X1.lef
mag:../mag/MUX2X1.mag
Extracting Obstruction information from ../mag/MUX2X1.mag
MUX2X1.lef
MUX2X1.lef -> 8.64 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file MUX2X1.lef.
This action cannot be undone.
LEF read: Processed 258 lines.
Generating LEF output MUX2X1.lef for cell MUX2X1:
Diagnostic: Write LEF header for cell MUX2X1
Diagnostic: Writing LEF output for cell MUX2X1
Diagnostic: Scale value is 0.010000
origlef: orig/NAND2X1.lef
lef: NAND2X1.lef
mag:../mag/NAND2X1.mag
Extracting Obstruction information from ../mag/NAND2X1.mag
NAND2X1.lef
NAND2X1.lef -> 4.32 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file NAND2X1.lef.
This action cannot be undone.
LEF read: Processed 161 lines.
Generating LEF output NAND2X1.lef for cell NAND2X1:
Diagnostic: Write LEF header for cell NAND2X1
Diagnostic: Writing LEF output for cell NAND2X1
Diagnostic: Scale value is 0.010000
origlef: orig/NAND3X1.lef
lef: NAND3X1.lef
mag:../mag/NAND3X1.mag
Extracting Obstruction information from ../mag/NAND3X1.mag
NAND3X1.lef
NAND3X1.lef -> 5.76 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file NAND3X1.lef.
This action cannot be undone.
LEF read: Processed 199 lines.
Generating LEF output NAND3X1.lef for cell NAND3X1:
Diagnostic: Write LEF header for cell NAND3X1
Diagnostic: Writing LEF output for cell NAND3X1
Diagnostic: Scale value is 0.010000
origlef: orig/NOR2X1.lef
lef: NOR2X1.lef
mag:../mag/NOR2X1.mag
Extracting Obstruction information from ../mag/NOR2X1.mag
NOR2X1.lef
NOR2X1.lef -> 4.32 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file NOR2X1.lef.
This action cannot be undone.
LEF read: Processed 161 lines.
Generating LEF output NOR2X1.lef for cell NOR2X1:
Diagnostic: Write LEF header for cell NOR2X1
Diagnostic: Writing LEF output for cell NOR2X1
Diagnostic: Scale value is 0.010000
origlef: orig/OAI21X1.lef
lef: OAI21X1.lef
mag:../mag/OAI21X1.mag
Extracting Obstruction information from ../mag/OAI21X1.mag
OAI21X1.lef
OAI21X1.lef -> 5.76 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file OAI21X1.lef.
This action cannot be undone.
LEF read: Processed 210 lines.
Generating LEF output OAI21X1.lef for cell OAI21X1:
Diagnostic: Write LEF header for cell OAI21X1
Diagnostic: Writing LEF output for cell OAI21X1
Diagnostic: Scale value is 0.010000
origlef: orig/OAI22X1.lef
lef: OAI22X1.lef
mag:../mag/OAI22X1.mag
Extracting Obstruction information from ../mag/OAI22X1.mag
OAI22X1.lef
OAI22X1.lef -> 7.2 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file OAI22X1.lef.
This action cannot be undone.
LEF read: Processed 255 lines.
Generating LEF output OAI22X1.lef for cell OAI22X1:
Diagnostic: Write LEF header for cell OAI22X1
Diagnostic: Writing LEF output for cell OAI22X1
Diagnostic: Scale value is 0.010000
origlef: orig/OR2X1.lef
lef: OR2X1.lef
mag:../mag/OR2X1.mag
Extracting Obstruction information from ../mag/OR2X1.mag
OR2X1.lef
OR2X1.lef -> 5.76 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file OR2X1.lef.
This action cannot be undone.
LEF read: Processed 190 lines.
Generating LEF output OR2X1.lef for cell OR2X1:
Diagnostic: Write LEF header for cell OR2X1
Diagnostic: Writing LEF output for cell OR2X1
Diagnostic: Scale value is 0.010000
origlef: orig/XNOR2X1.lef
lef: XNOR2X1.lef
mag:../mag/XNOR2X1.mag
Extracting Obstruction information from ../mag/XNOR2X1.mag
XNOR2X1.lef
XNOR2X1.lef -> 10.08 3.33
Magic 8.3 revision 158 - Compiled on Mo 26 Apr 2021 00:02:04 CEST.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Input style sky130: scaleFactor=2, multiplier=2
Processing system .magicrc file
Using technology "sky130A", version 1.0.81-0-gb184e85
Reading LEF data from file XNOR2X1.lef.
This action cannot be undone.
LEF read: Processed 307 lines.
Generating LEF output XNOR2X1.lef for cell XNOR2X1:
Diagnostic: Write LEF header for cell XNOR2X1
Diagnostic: Writing LEF output for cell XNOR2X1
Diagnostic: Scale value is 0.010000
INFO: Reading base liberty: /home/philipp/libresilicon/StdCellLib/Catalog/libresilicon.libtemplate
INFO: Reading liberty: AND2X1.lib
INFO: Reading liberty: AND2X2.lib
INFO: Reading liberty: AOI21X1.lib
INFO: Reading liberty: AOI22X1.lib
INFO: Reading liberty: BUFX2.lib
INFO: Reading liberty: HAX1.lib
INFO: Reading liberty: INV.lib
INFO: Reading liberty: INVX1.lib
INFO: Reading liberty: INVX2.lib
INFO: Reading liberty: INVX4.lib
INFO: Reading liberty: INVX8.lib
INFO: Reading liberty: MUX2X1.lib
INFO: Reading liberty: NAND2X1.lib
INFO: Reading liberty: NAND3X1.lib
INFO: Reading liberty: NOR2X1.lib
INFO: Reading liberty: OAI21X1.lib
INFO: Reading liberty: OAI22X1.lib
INFO: Reading liberty: OR2X1.lib
INFO: Reading liberty: XNOR2X1.lib
INFO: Add group: cell(AND2X1)
INFO: Add group: cell(AND2X2)
INFO: Add group: cell(AOI21X1)
INFO: Add group: cell(AOI22X1)
INFO: Add group: cell(BUFX2)
INFO: Add group: cell(HAX1)
INFO: Add group: cell(INV)
INFO: Add group: cell(INVX1)
INFO: Add group: cell(INVX2)
INFO: Add group: cell(INVX4)
INFO: Add group: cell(INVX8)
INFO: Add group: cell(MUX2X1)
INFO: Add group: cell(NAND2X1)
INFO: Add group: cell(NAND3X1)
INFO: Add group: cell(NOR2X1)
INFO: Add group: cell(OAI21X1)
INFO: Add group: cell(OAI22X1)
INFO: Add group: cell(OR2X1)
INFO: Add group: cell(XNOR2X1)
INFO: Number of cells in base: 19, number of cells in output: 19
INFO: Write liberty: libresilicon.lib
Now generating the demo wafer, the macro placement and the test-bench
Now building the Caravel user-project
cd openlane && make user_proj_example
make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird betreten
###############################################
[INFO]:
___ ____ ___ ____ _ ____ ____ ___
/ \ | \ / _]| \ | | / || \ / _]
| || o ) [_ | _ || | | o || _ | / [_
| O || _/ _]| | || |___ | || | || _]
| || | | [_ | | || || _ || | || [_
\___/ |__| |_____||__|__||_____||__|__||__|__||_____|
[INFO]: Version: v0.15
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/pdk-ls
[INFO]: PDK: sky130A
[INFO]: Setting PDKPATH to /media/philipp/Daten/skywater/pdk-ls/sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_ls
[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl
[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example
[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example
[INFO]: Preparing LEF Files
[INFO]: Extracting the number of available metal layers from /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef
[INFO]: The number of available metal layers is 6
[INFO]: The available metal layers are li1 met1 met2 met3 met4 met5
[INFO]: Merging LEF Files...
mergeLef.py : Merging LEFs
sky130_fd_sc_ls.lef: SITEs matched found: 0
sky130_fd_sc_ls.lef: MACROs matched found: 399
mergeLef.py : Merging LEFs complete
mergeLef.py : Merging LEFs
NAND3X1.lef: SITEs matched found: 0
NAND3X1.lef: MACROs matched found: 1
INVX8.lef: SITEs matched found: 0
INVX8.lef: MACROs matched found: 1
OAI21X1.lef: SITEs matched found: 0
OAI21X1.lef: MACROs matched found: 1
INVX4.lef: SITEs matched found: 0
INVX4.lef: MACROs matched found: 1
OAI22X1.lef: SITEs matched found: 0
OAI22X1.lef: MACROs matched found: 1
NOR2X1.lef: SITEs matched found: 0
NOR2X1.lef: MACROs matched found: 1
HAX1.lef: SITEs matched found: 0
HAX1.lef: MACROs matched found: 1
AOI21X1.lef: SITEs matched found: 0
AOI21X1.lef: MACROs matched found: 1
MUX2X1.lef: SITEs matched found: 0
MUX2X1.lef: MACROs matched found: 1
BUFX2.lef: SITEs matched found: 0
BUFX2.lef: MACROs matched found: 1
OR2X1.lef: SITEs matched found: 0
OR2X1.lef: MACROs matched found: 1
NAND2X1.lef: SITEs matched found: 0
NAND2X1.lef: MACROs matched found: 1
INVX2.lef: SITEs matched found: 0
INVX2.lef: MACROs matched found: 1
AND2X2.lef: SITEs matched found: 0
AND2X2.lef: MACROs matched found: 1
AOI22X1.lef: SITEs matched found: 0
AOI22X1.lef: MACROs matched found: 1
XNOR2X1.lef: SITEs matched found: 0
XNOR2X1.lef: MACROs matched found: 1
AND2X1.lef: SITEs matched found: 0
AND2X1.lef: MACROs matched found: 1
INVX1.lef: SITEs matched found: 0
INVX1.lef: MACROs matched found: 1
INV.lef: SITEs matched found: 0
INV.lef: MACROs matched found: 1
mergeLef.py : Merging LEFs complete
[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX8.lef /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/HAX1.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef
[INFO]: Trimming Liberty...
[INFO]: Generating Exclude List...
[INFO]: Storing configs into config.tcl ...
[INFO]: Preparation complete
[INFO]: Running Synthesis...
[INFO]: current step index: 1
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
Reading /project/openlane/user_proj_example/runs/user_proj_example/tmp/sky130_fd_sc_ls__tt_025C_1v80.no_pg.lib as a blackbox
1. Executing Liberty frontend.
Imported 386 cell types from liberty file.
2. Executing Liberty frontend.
Imported 19 cell types from liberty file.
3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation.
Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:10.1-19.10.
Generating RTLIL representation for module `\AND2X1'.
Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:21.1-30.10.
Generating RTLIL representation for module `\AND2X2'.
Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:32.1-42.10.
Generating RTLIL representation for module `\AOI21X1'.
Replacing existing blackbox module `\AOI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:44.1-55.10.
Generating RTLIL representation for module `\AOI22X1'.
Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:57.1-65.10.
Generating RTLIL representation for module `\BUFX2'.
Replacing existing blackbox module `\HAX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:67.1-77.10.
Generating RTLIL representation for module `\HAX1'.
Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:79.1-87.10.
Generating RTLIL representation for module `\INV'.
Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:89.1-97.10.
Generating RTLIL representation for module `\INVX1'.
Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:99.1-107.10.
Generating RTLIL representation for module `\INVX2'.
Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:109.1-117.10.
Generating RTLIL representation for module `\INVX4'.
Replacing existing blackbox module `\INVX8' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:119.1-127.10.
Generating RTLIL representation for module `\INVX8'.
Replacing existing blackbox module `\MUX2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:129.1-139.10.
Generating RTLIL representation for module `\MUX2X1'.
Replacing existing blackbox module `\NAND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:141.1-150.10.
Generating RTLIL representation for module `\NAND2X1'.
Replacing existing blackbox module `\NAND3X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:152.1-162.10.
Generating RTLIL representation for module `\NAND3X1'.
Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:164.1-173.10.
Generating RTLIL representation for module `\NOR2X1'.
Replacing existing blackbox module `\OAI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:175.1-185.10.
Generating RTLIL representation for module `\OAI21X1'.
Replacing existing blackbox module `\OAI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:187.1-198.10.
Generating RTLIL representation for module `\OAI22X1'.
Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:200.1-209.10.
Generating RTLIL representation for module `\OR2X1'.
Replacing existing blackbox module `\XNOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:211.1-220.10.
Generating RTLIL representation for module `\XNOR2X1'.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../caravel/verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
Successfully finished Verilog frontend.
6. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/hierarchy.dot'.
Dumping module user_proj_example to page 1.
7. Executing HIERARCHY pass (managing design hierarchy).
7.1. Analyzing design hierarchy..
Top module: \user_proj_example
7.2. Analyzing design hierarchy..
Top module: \user_proj_example
Removed 0 unused modules.
8. Executing TRIBUF pass.
9. Executing SYNTH pass.
9.1. Executing HIERARCHY pass (managing design hierarchy).
9.1.1. Analyzing design hierarchy..
Top module: \user_proj_example
9.1.2. Analyzing design hierarchy..
Top module: \user_proj_example
Removed 0 unused modules.
9.2. Executing PROC pass (convert processes to netlists).
9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
9.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
9.2.4. Executing PROC_INIT pass (extract init attributes).
9.2.5. Executing PROC_ARST pass (detect async resets in processes).
9.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
9.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
9.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
9.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
9.3. Executing FLATTEN pass (flatten design).
9.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.6. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver.
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Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.
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Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.
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Warning: Wire user_proj_example.\la_data_out [52] is used but has no driver.
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Warning: Wire user_proj_example.\la_data_out [39] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [38] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [37] is used but has no driver.
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Warning: Wire user_proj_example.\la_data_out [33] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [32] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [31] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [30] is used but has no driver.
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Warning: Wire user_proj_example.\la_data_out [28] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [27] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [26] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [25] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [24] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [23] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [22] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [17] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [13] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.
Warning: Wire user_proj_example.\io_out [36] is used but has no driver.
Warning: Wire user_proj_example.\io_out [35] is used but has no driver.
Warning: Wire user_proj_example.\io_out [33] is used but has no driver.
Warning: Wire user_proj_example.\io_out [32] is used but has no driver.
Warning: Wire user_proj_example.\io_out [31] is used but has no driver.
Warning: Wire user_proj_example.\io_out [29] is used but has no driver.
Warning: Wire user_proj_example.\io_out [27] is used but has no driver.
Warning: Wire user_proj_example.\io_out [25] is used but has no driver.
Warning: Wire user_proj_example.\io_out [23] is used but has no driver.
Warning: Wire user_proj_example.\io_out [21] is used but has no driver.
Warning: Wire user_proj_example.\io_out [18] is used but has no driver.
Warning: Wire user_proj_example.\io_out [17] is used but has no driver.
Warning: Wire user_proj_example.\io_out [15] is used but has no driver.
Warning: Wire user_proj_example.\io_out [13] is used but has no driver.
Warning: Wire user_proj_example.\io_out [12] is used but has no driver.
Warning: Wire user_proj_example.\io_out [11] is used but has no driver.
Warning: Wire user_proj_example.\io_out [10] is used but has no driver.
Warning: Wire user_proj_example.\io_out [8] is used but has no driver.
Warning: Wire user_proj_example.\io_out [7] is used but has no driver.
Warning: Wire user_proj_example.\io_out [6] is used but has no driver.
Warning: Wire user_proj_example.\io_out [4] is used but has no driver.
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Warning: Wire user_proj_example.\io_out [1] is used but has no driver.
Warning: Wire user_proj_example.\io_out [0] is used but has no driver.
found and reported 179 problems.
9.7. Executing OPT pass (performing simple optimizations).
9.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.7.6. Executing OPT_DFF pass (perform DFF optimizations).
9.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.7.9. Finished OPT passes. (There is nothing left to do.)
9.8. Executing FSM pass (extract and optimize FSM).
9.8.1. Executing FSM_DETECT pass (finding FSMs in design).
9.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
9.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
9.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
9.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
9.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
9.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
9.9. Executing OPT pass (performing simple optimizations).
9.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.9.6. Executing OPT_DFF pass (perform DFF optimizations).
9.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.9.9. Finished OPT passes. (There is nothing left to do.)
9.10. Executing WREDUCE pass (reducing word size of cells).
9.11. Executing PEEPOPT pass (run peephole optimizers).
9.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module user_proj_example:
created 0 $alu and 0 $macc cells.
9.14. Executing SHARE pass (SAT-based resource sharing).
9.15. Executing OPT pass (performing simple optimizations).
9.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.15.6. Executing OPT_DFF pass (perform DFF optimizations).
9.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.15.9. Finished OPT passes. (There is nothing left to do.)
9.16. Executing MEMORY pass.
9.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
9.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
9.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
9.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
9.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.18. Executing OPT pass (performing simple optimizations).
9.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
<suppressed ~87 debug messages>
9.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.18.3. Executing OPT_DFF pass (perform DFF optimizations).
9.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.18.5. Finished fast OPT passes.
9.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
9.20. Executing OPT pass (performing simple optimizations).
9.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.20.6. Executing OPT_SHARE pass.
9.20.7. Executing OPT_DFF pass (perform DFF optimizations).
9.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.20.10. Finished OPT passes. (There is nothing left to do.)
9.21. Executing TECHMAP pass (map to technology primitives).
9.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
9.21.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~67 debug messages>
9.22. Executing OPT pass (performing simple optimizations).
9.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.22.3. Executing OPT_DFF pass (perform DFF optimizations).
9.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.22.5. Finished fast OPT passes.
9.23. Executing ABC pass (technology mapping using ABC).
9.23.1. Extracting gate netlist of module `\user_proj_example' to `<abc-temp-dir>/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
9.24. Executing OPT pass (performing simple optimizations).
9.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.24.3. Executing OPT_DFF pass (perform DFF optimizations).
9.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.24.5. Finished fast OPT passes.
9.25. Executing HIERARCHY pass (managing design hierarchy).
9.25.1. Analyzing design hierarchy..
Top module: \user_proj_example
9.25.2. Analyzing design hierarchy..
Top module: \user_proj_example
Removed 0 unused modules.
9.26. Printing statistics.
=== user_proj_example ===
Number of wires: 16
Number of wire bits: 604
Number of public wires: 16
Number of public wire bits: 604
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 19
AND2X1 1
AND2X2 1
AOI21X1 1
AOI22X1 1
BUFX2 1
HAX1 1
INV 1
INVX1 1
INVX2 1
INVX4 1
INVX8 1
MUX2X1 1
NAND2X1 1
NAND3X1 1
NOR2X1 1
OAI21X1 1
OAI22X1 1
OR2X1 1
XNOR2X1 1
9.27. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.
10. Executing SHARE pass (SAT-based resource sharing).
11. Executing OPT pass (performing simple optimizations).
11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
11.6. Executing OPT_DFF pass (perform DFF optimizations).
11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
11.9. Finished OPT passes. (There is nothing left to do.)
12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
13. Printing statistics.
=== user_proj_example ===
Number of wires: 16
Number of wire bits: 604
Number of public wires: 16
Number of public wire bits: 604
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 19
AND2X1 1
AND2X2 1
AOI21X1 1
AOI22X1 1
BUFX2 1
HAX1 1
INV 1
INVX1 1
INVX2 1
INVX4 1
INVX8 1
MUX2X1 1
NAND2X1 1
NAND3X1 1
NOR2X1 1
OAI21X1 1
OAI22X1 1
OR2X1 1
XNOR2X1 1
mapping tbuf
14. Executing TECHMAP pass (map to technology primitives).
14.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/tribuff_map.v
Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/tribuff_map.v' to AST representation.
Generating RTLIL representation for module `\$_TBUF_'.
Successfully finished Verilog frontend.
14.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
15. Executing SIMPLEMAP pass (map simple cells to gate primitives).
16. Executing MUXCOVER pass (mapping to wider MUXes).
Covering MUX trees in module user_proj_example..
Treeifying 0 MUXes:
Finished treeification: Found 0 trees.
Covering trees:
Added a total of 0 decoder MUXes.
<suppressed ~1 debug messages>
17. Executing TECHMAP pass (map to technology primitives).
17.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux4_map.v
Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux4_map.v' to AST representation.
Generating RTLIL representation for module `\$_MUX4_'.
Successfully finished Verilog frontend.
17.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
18. Executing SIMPLEMAP pass (map simple cells to gate primitives).
19. Executing TECHMAP pass (map to technology primitives).
19.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux2_map.v
Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/mux2_map.v' to AST representation.
Generating RTLIL representation for module `\$_MUX_'.
Successfully finished Verilog frontend.
19.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
20. Executing SIMPLEMAP pass (map simple cells to gate primitives).
21. Executing TECHMAP pass (map to technology primitives).
21.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/latch_map.v
Parsing Verilog input from `/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/sky130_fd_sc_ls/latch_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Successfully finished Verilog frontend.
21.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
22. Executing SIMPLEMAP pass (map simple cells to gate primitives).
23. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell sky130_fd_sc_ls__dfxtp_2 (noninv, pins=3, area=28.77) is a direct match for cell type $_DFF_P_.
cell sky130_fd_sc_ls__dfrtp_2 (noninv, pins=4, area=38.36) is a direct match for cell type $_DFF_PN0_.
cell sky130_fd_sc_ls__dfstp_2 (noninv, pins=4, area=39.96) is a direct match for cell type $_DFF_PN1_.
cell sky130_fd_sc_ls__dfbbn_2 (noninv, pins=6, area=47.95) is a direct match for cell type $_DFFSR_NNN_.
final dff cell mappings:
unmapped dff cell: $_DFF_N_
\sky130_fd_sc_ls__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
unmapped dff cell: $_DFF_NN0_
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\sky130_fd_sc_ls__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
\sky130_fd_sc_ls__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
\sky130_fd_sc_ls__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
unmapped dff cell: $_DFFSR_PNN_
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
23.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\user_proj_example':
24. Printing statistics.
=== user_proj_example ===
Number of wires: 16
Number of wire bits: 604
Number of public wires: 16
Number of public wire bits: 604
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 19
AND2X1 1
AND2X2 1
AOI21X1 1
AOI22X1 1
BUFX2 1
HAX1 1
INV 1
INVX1 1
INVX2 1
INVX4 1
INVX8 1
MUX2X1 1
NAND2X1 1
NAND3X1 1
NOR2X1 1
OAI21X1 1
OAI22X1 1
OR2X1 1
XNOR2X1 1
[INFO]: ABC: WireLoad : S_4
25. Executing ABC pass (technology mapping using ABC).
25.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-90moWU/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
26. Executing SETUNDEF pass (replace undef values with defined constants).
27. Executing HILOMAP pass (mapping to constant drivers).
28. Executing SPLITNETS pass (splitting up multi-bit signals).
29. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 0 unused cells and 217 unused wires.
<suppressed ~1 debug messages>
30. Executing INSBUF pass (insert buffer cells for connected wires).
31. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.
32. Printing statistics.
=== user_proj_example ===
Number of wires: 16
Number of wire bits: 604
Number of public wires: 16
Number of public wire bits: 604
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 236
AND2X1 1
AND2X2 1
AOI21X1 1
AOI22X1 1
BUFX2 1
HAX1 1
INV 1
INVX1 1
INVX2 1
INVX4 1
INVX8 1
MUX2X1 1
NAND2X1 1
NAND3X1 1
NOR2X1 1
OAI21X1 1
OAI22X1 1
OR2X1 1
XNOR2X1 1
sky130_fd_sc_ls__conb_1 217
Area for cell type \AND2X1 is unknown!
Area for cell type \AND2X2 is unknown!
Area for cell type \AOI21X1 is unknown!
Area for cell type \AOI22X1 is unknown!
Area for cell type \BUFX2 is unknown!
Area for cell type \HAX1 is unknown!
Area for cell type \INV is unknown!
Area for cell type \INVX1 is unknown!
Area for cell type \INVX2 is unknown!
Area for cell type \INVX4 is unknown!
Area for cell type \INVX8 is unknown!
Area for cell type \MUX2X1 is unknown!
Area for cell type \NAND2X1 is unknown!
Area for cell type \NAND3X1 is unknown!
Area for cell type \NOR2X1 is unknown!
Area for cell type \OAI21X1 is unknown!
Area for cell type \OAI22X1 is unknown!
Area for cell type \OR2X1 is unknown!
Area for cell type \XNOR2X1 is unknown!
Chip area for module '\user_proj_example': 1040.558400
33. Executing Verilog backend.
Dumping module `\user_proj_example'.
Warnings: 179 unique messages, 179 total
End of script. Logfile hash: 032ba45d54, CPU: user 22.19s system 0.75s, MEM: 386.59 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 37% 4x read_liberty (8 sec), 37% 4x stat (8 sec), 21% 1x dfflibmap (4 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v
[INFO]: Running Static Timing Analysis...
[INFO]: current step index: 2
OpenSTA 2.3.0 38b40303a8 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details.
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 671, module AND2X1 not found. Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 676, module AND2X2 not found. Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 681, module AOI21X1 not found. Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 687, module AOI22X1 not found. Creating black box for AOI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 694, module BUFX2 not found. Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 698, module HAX1 not found. Creating black box for HAX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 704, module INV not found. Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 708, module INVX1 not found. Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 712, module INVX2 not found. Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 716, module INVX4 not found. Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 720, module INVX8 not found. Creating black box for INVX8.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 724, module MUX2X1 not found. Creating black box for MUX2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 730, module NAND2X1 not found. Creating black box for NAND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 735, module NAND3X1 not found. Creating black box for NAND3X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 741, module NOR2X1 not found. Creating black box for NOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 746, module OAI21X1 not found. Creating black box for OAI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 752, module OAI22X1 not found. Creating black box for OAI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 759, module OR2X1 not found. Creating black box for OR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v line 764, module XNOR2X1 not found. Creating black box for XNOR2X1.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.02205
set_load $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
[INFO]: current step index: 3
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
[WARNING ORD-1000] LEF master AND2X1 has no liberty cell.
[WARNING ORD-1000] LEF master AND2X2 has no liberty cell.
[WARNING ORD-1000] LEF master AOI21X1 has no liberty cell.
[WARNING ORD-1000] LEF master AOI22X1 has no liberty cell.
[WARNING ORD-1000] LEF master BUFX2 has no liberty cell.
[WARNING ORD-1000] LEF master HAX1 has no liberty cell.
[WARNING ORD-1000] LEF master INV has no liberty cell.
[WARNING ORD-1000] LEF master INVX1 has no liberty cell.
[WARNING ORD-1000] LEF master INVX2 has no liberty cell.
[WARNING ORD-1000] LEF master INVX4 has no liberty cell.
[WARNING ORD-1000] LEF master INVX8 has no liberty cell.
[WARNING ORD-1000] LEF master MUX2X1 has no liberty cell.
[WARNING ORD-1000] LEF master NAND2X1 has no liberty cell.
[WARNING ORD-1000] LEF master NAND3X1 has no liberty cell.
[WARNING ORD-1000] LEF master NOR2X1 has no liberty cell.
[WARNING ORD-1000] LEF master OAI21X1 has no liberty cell.
[WARNING ORD-1000] LEF master OAI22X1 has no liberty cell.
[WARNING ORD-1000] LEF master OR2X1 has no liberty cell.
[WARNING ORD-1000] LEF master XNOR2X1 has no liberty cell.
[INFO IFP-0001] Added 82 rows of 601 sites.
[INFO]: Core area width: 288.48
[INFO]: Core area height: 273.36
[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def
[INFO]: current step index: 4
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 236 components and 1400 component-terminals.
Notice 0: Created 604 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def
Top-level design name: user_proj_example
Block boundaries: 0 0 300000 300000
Writing /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/3-verilog2def_openroad.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def
[INFO]: Manual Macro Placement...
[INFO]: current step index: 5
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 236 components and 1400 component-terminals.
Notice 0: Created 604 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def
Placing the following macros:
{'AND2X1': ['38400', '23310', 'N'], 'AND2X2': ['38400', '29970', 'N'], 'AOI21X1': ['38400', '36630', 'N'], 'AOI22X1': ['38400', '43290', 'N'], 'BUFX2': ['38400', '49950', 'N'], 'HAX1': ['38400', '56610', 'N'], 'INV': ['38400', '63270', 'N'], 'INVX1': ['38400', '69930', 'N'], 'INVX2': ['38400', '76590', 'N'], 'INVX4': ['38400', '83250', 'N'], 'INVX8': ['38400', '89910', 'N'], 'MUX2X1': ['38400', '96570', 'N'], 'NAND2X1': ['38400', '103230', 'N'], 'NAND3X1': ['38400', '109890', 'N'], 'NOR2X1': ['38400', '116550', 'N'], 'OAI21X1': ['38400', '123210', 'N'], 'OAI22X1': ['38400', '129870', 'N'], 'OR2X1': ['38400', '136530', 'N'], 'XNOR2X1': ['38400', '143190', 'N']}
Design name: user_proj_example
Placing AND2X1
Placing AND2X2
Placing AOI21X1
Placing AOI22X1
Placing BUFX2
Placing HAX1
Placing INV
Placing INVX1
Placing INVX2
Placing INVX4
Placing INVX8
Placing MUX2X1
Placing NAND2X1
Placing NAND3X1
Placing NOR2X1
Placing OAI21X1
Placing OAI22X1
Placing OR2X1
Placing XNOR2X1
Successfully placed 19 instances
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def
[INFO]: Running Tap/Decap Insertion...
[INFO]: current step index: 6
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 236 components and 1400 component-terminals.
Notice 0: Created 604 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def
Step 1: Cut rows...
[INFO TAP-0001] Macro blocks found: 0
[INFO TAP-0002] #Original rows: 82
[INFO TAP-0003] #Cut rows: 0
Step 2: Insert endcaps...
[INFO TAP-0004] #Endcaps inserted: 164
Step 3: Insert tapcells...
[INFO TAP-0005] #Tapcells inserted: 882
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/4-ioPlacer.macro_placement.def to /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO]: Taking a Screenshot of the Layout Using Klayout...
[INFO]: current step index: 7
Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def.png'
Done
[INFO]: Screenshot taken.
[INFO]: Power planning the following nets
[INFO]: Power: vccd1 vccd2 vdda1 vdda2
[INFO]: Ground: vssd1 vssd2 vssa1 vssa2
[INFO]: Generating PDN...
[INFO]: current step index: 8
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 1282 components and 3820 component-terminals.
Notice 0: Created 604 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_proj_example
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Layer: met1 - width: 0.480 pitch: 3.330 offset: 0.000
Straps
Layer: met4 - width: 1.600 pitch: 153.600 offset: 16.320
Connect: {met1 met4}
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vccd1 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vccd1.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (22.080um, 10.800um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (175.680um, 10.800um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (175.680um, 10.800um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (175.680um, 151.200um).
[INFO PSM-0031] Number of nodes on net vccd1 = 2876.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vccd1.
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vssd1 is not explicitly set.
[WARNING PSM-0021] Using voltage 0.000V for ground network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vssd1.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (98.880um, 10.800um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (98.880um, 10.800um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (252.480um, 10.800um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (252.480um, 151.200um).
[INFO PSM-0031] Number of nodes on net vssd1 = 2810.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vssd1.
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def
[INFO]: Generating PDN...
[INFO]: current step index: 9
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def
Notice 0: Design: user_proj_example
Notice 0: Created 606 pins.
Notice 0: Created 1282 components and 3820 component-terminals.
Notice 0: Created 2 special nets and 0 connections.
Notice 0: Created 604 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_proj_example
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Straps
Layer: met4 - width: 1.600 pitch: 153.600 offset: 19.620
Connect:
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vccd2 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vccd2.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (21.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (172.800um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).
[INFO PSM-0031] Number of nodes on net vccd2 = 3.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vccd2.
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vssd2 is not explicitly set.
[WARNING PSM-0021] Using voltage 0.000V for ground network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vssd2.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (97.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (253.800um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (253.800um, 149.850um).
[INFO PSM-0031] Number of nodes on net vssd2 = 3.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vssd2.
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/8-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def
[INFO]: Generating PDN...
[INFO]: current step index: 10
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def
Notice 0: Design: user_proj_example
Notice 0: Created 608 pins.
Notice 0: Created 1282 components and 3820 component-terminals.
Notice 0: Created 4 special nets and 0 connections.
Notice 0: Created 604 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_proj_example
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Straps
Layer: met4 - width: 1.600 pitch: 153.600 offset: 22.920
Connect:
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vdda1 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vdda1.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (27.000um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (178.200um, 149.850um).
[INFO PSM-0031] Number of nodes on net vdda1 = 2.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vdda1.
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vssa1 is not explicitly set.
[WARNING PSM-0021] Using voltage 0.000V for ground network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vssa1.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).
[INFO PSM-0031] Number of nodes on net vssa1 = 3.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vssa1.
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/9-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def
[INFO]: Generating PDN...
[INFO]: current step index: 11
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def
Notice 0: Design: user_proj_example
Notice 0: Created 610 pins.
Notice 0: Created 1282 components and 3820 component-terminals.
Notice 0: Created 6 special nets and 0 connections.
Notice 0: Created 604 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_proj_example
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Straps
Layer: met4 - width: 1.600 pitch: 153.600 offset: 26.220
Connect:
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vdda2 is not explicitly set.
[WARNING PSM-0022] Using voltage 0.000V for VDD network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vdda2.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (27.000um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (183.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (183.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (183.600um, 149.850um).
[INFO PSM-0031] Number of nodes on net vdda2 = 3.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vdda2.
[WARNING PSM-0016] Voltage pad location (vsrc) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vssa2 is not explicitly set.
[WARNING PSM-0021] Using voltage 0.000V for ground network.
[INFO PSM-0026] Creating G matrix.
[INFO PSM-0028] Extracting power stripes on net vssa2.
[WARNING PSM-0030] Vsrc location at (5.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (102.600um, 149.850um).
[WARNING PSM-0030] Vsrc location at (145.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (108.000um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 13.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).
[WARNING PSM-0030] Vsrc location at (285.760um, 153.320um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (259.200um, 149.850um).
[INFO PSM-0031] Number of nodes on net vssa2 = 3.
[INFO PSM-0037] G matrix created sucessfully.
[INFO PSM-0040] Connection between all PDN nodes established in net vssa2.
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/10-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def
[INFO]: Running Placement...
[WARNING]: Performing Random Global Placement...
[INFO]: current step index: 12
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 1282 components and 3820 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 604 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def
Design name: user_proj_example
Core Area Boundaries: 5760 13320 294240 286380
Number of instances 1282
Placed 217 instances
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/11-pdn.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-replace.def
[INFO]: Skipping OpenPhySyn Timing Optimizations.
[INFO]: Running Resizer Design Optimizations...
[INFO]: Generating Exclude List...
[INFO]: Creating ::env(DONT_USE_CELLS)...
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/tmp/resizer.lib line 33, default_operating_condition ss_100C_1v60 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-replace.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 1282 components and 3820 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 604 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-replace.def
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.02205
set_load $cap_load [all_outputs]
[INFO RSZ-0027] Inserted 367 input buffers.
[INFO RSZ-0028] Inserted 237 output buffers.
[INFO RSZ-0039] Resized 274 instances.
Design Stats
--------------------------------
total instances 1886
multi row instances 0
fixed instances 1065
nets 1216
design area 78772.3 u^2
fixed area 2846.8 u^2
movable area 4953.4 u^2
utilization 7 %
utilization padded 15 %
rows 82
row height 3.3 u
Placement Analysis
--------------------------------
total displacement 12648.7 u
average displacement 6.7 u
max displacement 77.1 u
original HPWL 72993.0 u
legalized HPWL 77740.4 u
delta HPWL 7 %
[INFO DPL-0020] Mirrored 287 instances
[INFO DPL-0021] HPWL before 77740.4 u
[INFO DPL-0022] HPWL after 77565.1 u
[INFO DPL-0023] HPWL delta -0.2 %
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-replace.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def
[INFO]: Writing Verilog...
[INFO]: current step index: 13
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 1886 components and 7444 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 1208 nets and 1485 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def
[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v
[INFO]: Running Static Timing Analysis...
[INFO]: current step index: 14
OpenSTA 2.3.0 38b40303a8 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details.
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 50, module AND2X1 not found. Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 53, module AND2X2 not found. Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 56, module AOI21X1 not found. Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 60, module AOI22X1 not found. Creating black box for AOI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 65, module BUFX2 not found. Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 67, module HAX1 not found. Creating black box for HAX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 71, module INV not found. Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 73, module INVX1 not found. Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 75, module INVX2 not found. Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 77, module INVX4 not found. Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 79, module INVX8 not found. Creating black box for INVX8.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 81, module MUX2X1 not found. Creating black box for MUX2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 85, module NAND2X1 not found. Creating black box for NAND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 88, module NAND3X1 not found. Creating black box for NAND3X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 92, module NOR2X1 not found. Creating black box for NOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 95, module OAI21X1 not found. Creating black box for OAI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 99, module OAI22X1 not found. Creating black box for OAI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 104, module OR2X1 not found. Creating black box for OR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 107, module XNOR2X1 not found. Creating black box for XNOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 491, module sky130_fd_sc_ls__tapvpwrvgnd_1 not found. Creating black box for PHY_164.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.02205
set_load $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Running Detailed Placement...
[INFO]: current step index: 15
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 1886 components and 7444 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 1208 nets and 1485 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def
Design Stats
--------------------------------
total instances 1886
multi row instances 0
fixed instances 1065
nets 1216
design area 78772.3 u^2
fixed area 2846.8 u^2
movable area 4953.4 u^2
utilization 7 %
utilization padded 13 %
rows 82
row height 3.3 u
Placement Analysis
--------------------------------
total displacement 0.0 u
average displacement 0.0 u
max displacement 0.0 u
original HPWL 77565.1 u
legalized HPWL 77740.4 u
delta HPWL 0 %
[INFO DPL-0020] Mirrored 287 instances
[INFO DPL-0021] HPWL before 77740.4 u
[INFO DPL-0022] HPWL after 77565.1 u
[INFO DPL-0023] HPWL delta -0.2 %
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/12-resizer.def to /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def to /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
[INFO]: Taking a Screenshot of the Layout Using Klayout...
[INFO]: current step index: 16
Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def.png'
Done
[INFO]: Screenshot taken.
[INFO]: current step index: 17
[INFO]: Running Resizer Timing Optimizations...
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/tmp/resizer.lib line 33, default_operating_condition ss_100C_1v60 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 1886 components and 7444 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 1208 nets and 1485 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.02205
set_load $cap_load [all_outputs]
[WARNING STA-0357] virtual clock can not be propagated.
[INFO RSZ-0033] No hold violations found.
Design Stats
--------------------------------
total instances 1886
multi row instances 0
fixed instances 1065
nets 1216
design area 78772.3 u^2
fixed area 2846.8 u^2
movable area 4953.4 u^2
utilization 7 %
utilization padded 15 %
rows 82
row height 3.3 u
Placement Analysis
--------------------------------
total displacement 0.0 u
average displacement 0.0 u
max displacement 0.0 u
original HPWL 77565.1 u
legalized HPWL 77740.4 u
delta HPWL 0 %
[INFO DPL-0020] Mirrored 287 instances
[INFO DPL-0021] HPWL before 77740.4 u
[INFO DPL-0022] HPWL after 77565.1 u
[INFO DPL-0023] HPWL delta -0.2 %
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def
[INFO]: Writing Verilog...
[INFO]: current step index: 18
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 1886 components and 7444 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 1208 nets and 1485 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def
[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v
[INFO]: Running Static Timing Analysis...
[INFO]: current step index: 19
OpenSTA 2.3.0 38b40303a8 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details.
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 50, module AND2X1 not found. Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 53, module AND2X2 not found. Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 56, module AOI21X1 not found. Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 60, module AOI22X1 not found. Creating black box for AOI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 65, module BUFX2 not found. Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 67, module HAX1 not found. Creating black box for HAX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 71, module INV not found. Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 73, module INVX1 not found. Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 75, module INVX2 not found. Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 77, module INVX4 not found. Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 79, module INVX8 not found. Creating black box for INVX8.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 81, module MUX2X1 not found. Creating black box for MUX2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 85, module NAND2X1 not found. Creating black box for NAND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 88, module NAND3X1 not found. Creating black box for NAND3X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 92, module NOR2X1 not found. Creating black box for NOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 95, module OAI21X1 not found. Creating black box for OAI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 99, module OAI22X1 not found. Creating black box for OAI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 104, module OR2X1 not found. Creating black box for OR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 107, module XNOR2X1 not found. Creating black box for XNOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v line 491, module sky130_fd_sc_ls__tapvpwrvgnd_1 not found. Creating black box for PHY_164.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.02205
set_load $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Routing...
[INFO]: Running Global Routing...
[INFO]: current step index: 20
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__tt_025C_1v80.lib line 32, default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 1886 components and 7444 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 1208 nets and 1485 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def
Min routing layer: 2
Max routing layer: 6
Global adjustment: 0.0
Unidirectional routing: true
Grid origin: (0, 0)
[INFO GRT-0004] #DB Obstructions: 0
[INFO GRT-0005] #DB Obstacles: 22949
[INFO GRT-0006] #DB Macros: 0
[INFO GRT-0017] Found 0 clock nets
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 2
[INFO GRT-0018] Processing 16674 obstacles on layer 1
[INFO GRT-0019] Processing 4578 obstacles on layer 2
[INFO GRT-0022] Processing 16 obstacles on layer 5
[INFO GRT-0020] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 9586, WIRELEN1 : 0
[INFO] NumSeg : 836
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 9586, WIRELEN1 : 9586
[INFO] NumSeg : 836
[INFO] NumShift: 0
[Overflow Report] Total hCap : 46142
[Overflow Report] Total vCap : 36068
[Overflow Report] Total Usage : 9586
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
Second L Route
[Overflow Report] Total hCap : 46142
[Overflow Report] Total vCap : 36068
[Overflow Report] Total Usage : 9586
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
First Z Route
[Overflow Report] Total hCap : 46142
[Overflow Report] Total vCap : 36068
[Overflow Report] Total Usage : 9586
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
[INFO] LV routing round 0, enlarge 10
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage : 9586
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
[INFO] LV routing round 1, enlarge 15
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage : 9586
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
[INFO] LV routing round 2, enlarge 20
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage : 9586
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
Usage checked
Maze routing finished
[INFO] P3 runtime: 0.000000 sec
[INFO] Final 2D results:
[Overflow Report] total Usage : 9586
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 0.020000 sec
Post Processing Begins
Post Processsing finished
Starting via filling
[INFO] Via related to pin nodes 2672
[INFO] Via related stiner nodes 0
Via filling finished
Final usage/overflow report:
[INFO] Usage per layer:
Layer 1 usage: 0
Layer 2 usage: 3548
Layer 3 usage: 5804
Layer 4 usage: 216
Layer 5 usage: 18
Layer 6 usage: 0
[INFO] Capacity per layer:
Layer 1 capacity: 0
Layer 2 capacity: 27862
Layer 3 capacity: 24920
Layer 4 capacity: 15000
Layer 5 capacity: 11148
Layer 6 capacity: 3280
[INFO] Use percentage per layer:
Layer 1 use percentage: 0.0%
Layer 2 use percentage: 12.73%
Layer 3 use percentage: 23.29%
Layer 4 use percentage: 1.44%
Layer 5 use percentage: 0.16%
Layer 6 use percentage: 0.00%
[INFO] Overflow per layer:
Layer 1 overflow: 0
Layer 2 overflow: 0
Layer 3 overflow: 0
Layer 4 overflow: 0
Layer 5 overflow: 0
Layer 6 overflow: 0
[Overflow Report] Total Usage : 9586
[Overflow Report] Total Capacity: 82210
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
[INFO] Final usage : 9586
[INFO] Final number of vias : 3210
[INFO] Final usage 3D : 19216
[INFO GRT-0018] Total wirelength: 91879 um
Repairing antennas...
[WARNING GRT-0025] No OR_DEFAULT vias defined
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
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Notice 0: Split top of 1 T shapes.
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Notice 0: Split top of 1 T shapes.
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Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
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Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
Notice 0: Split top of 1 T shapes.
[INFO GRT-0012] #Antenna violations: 122
Design Stats
--------------------------------
total instances 2126
multi row instances 0
fixed instances 1524
nets 1216
design area 78772.3 u^2
fixed area 4859.1 u^2
movable area 3708.3 u^2
utilization 5 %
utilization padded 5 %
rows 82
row height 3.3 u
Placement Analysis
--------------------------------
total displacement 0.0 u
average displacement 0.0 u
max displacement 0.0 u
original HPWL 77825.6 u
legalized HPWL 77941.7 u
delta HPWL 0 %
[WARNING DPL-0005] Overlap check failed (9).
[INFO GRT-0015] 240 diodes inserted
Min routing layer: 2
Max routing layer: 6
Global adjustment: 0.0
Unidirectional routing: true
Grid origin: (0, 0)
[INFO GRT-0004] #DB Obstructions: 0
[INFO GRT-0005] #DB Obstacles: 24389
[INFO GRT-0006] #DB Macros: 0
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 5
[INFO GRT-0018] Processing 17394 obstacles on layer 1
[INFO GRT-0019] Processing 5058 obstacles on layer 2
[INFO GRT-0022] Processing 16 obstacles on layer 5
[INFO GRT-0020] Reducing resources of layer 1 by 99%
[INFO GRT-0009] #Nets to reroute: 396
[WARNING UKN-0000] Underflow in reduce
[WARNING UKN-0000] cap, reducedCap: 15, 16
[WARNING UKN-0000] Underflow in reduce
[WARNING UKN-0000] cap, reducedCap: 14, 15
[WARNING UKN-0000] Underflow in reduce
[WARNING UKN-0000] cap, reducedCap: 16, 17
[WARNING UKN-0000] Underflow in reduce
[WARNING UKN-0000] cap, reducedCap: 16, 17
[WARNING UKN-0000] Underflow in reduce
[WARNING UKN-0000] cap, reducedCap: 15, 17
[WARNING UKN-0000] Underflow in reduce
[WARNING UKN-0000] cap, reducedCap: 13, 16
[WARNING UKN-0000] Underflow in reduce
[WARNING UKN-0000] cap, reducedCap: 14, 15
Final usage/overflow report:
[Overflow Report] Total Usage : 8478
[Overflow Report] Total Capacity: 81357
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
[INFO] Final usage : 8478
[INFO] Final number of vias : 1627
[INFO] Final usage 3D : 13359
[WARNING DPL-0005] Overlap check failed (9).
[INFO GRT-0014] Num routed nets: 897
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ss_100C_1v60.lib line 33, default_operating_condition ss_100C_1v60 not found.
Warning: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/lib/sky130_fd_sc_ls__ff_n40C_1v95.lib line 32, default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.02205
set_load $cap_load [all_outputs]
No paths found.
No paths found.
No paths found.
wns 0.00
tns 0.00
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/17-resizer_timing.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def
[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.guide
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.guide to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.guide
[INFO]: Current Def is /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def
[INFO]: Current Guide is /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.guide
[INFO]: Running Fill Insertion...
[INFO]: current step index: 21
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 2126 components and 8644 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 1208 nets and 1725 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def
[INFO DPL-0001] Placed 7223 filler instances.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/20-fastroute.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/21-addspacers.def
[INFO]: Writing Verilog...
[INFO]: current step index: 22
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/21-addspacers.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 9349 components and 37536 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 1208 nets and 1725 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/21-addspacers.def
[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_preroute.v
[INFO]: Running Detailed Routing...
[INFO]: current step index: 23
reading lef ...
units: 1000
#layers: 13
#macros: 418
#vias: 25
#viarulegen: 25
reading def ...
design: user_proj_example
die area: ( 0 0 ) ( 300000 300000 )
trackPts: 12
defvias: 3
#components: 9349
#terminals: 620
#snets: 8
#nets: 1208
reading guide ...
#guides: 4658
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
Layer mcon
default via: L1M1_PR_MR
Layer via
default via: M1M2_PR
Layer via2
default via: via2_FR
Layer via3
default via: M3M4_PR_M
Layer via4
default via: via4_FR
Writing reference output def...
libcell analysis ...
instance analysis ...
#unique instances = 49
init region query ...
complete FR_MASTERSLICE
complete FR_VIA
complete li1
complete mcon
complete met1
complete via
complete met2
complete via2
complete met3
complete via3
complete met4
complete via4
complete met5
FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 78070
mcon shape region query size = 98078
met1 shape region query size = 19670
via shape region query size = 664
met2 shape region query size = 936
via2 shape region query size = 664
met3 shape region query size = 332
via3 shape region query size = 664
met4 shape region query size = 198
via4 shape region query size = 0
met5 shape region query size = 0
start pin access
complete 92 pins
complete 43 unique inst patterns
complete 837 groups
Expt1 runtime (pin-level access point gen): 2.82195
Expt2 runtime (design-level access pattern gen): 0.184966
#scanned instances = 9349
#unique instances = 49
#stdCellGenAp = 636
#stdCellValidPlanarAp = 233
#stdCellValidViaAp = 463
#stdCellPinNoAp = 0
#stdCellPinCnt = 1485
#instTermValidViaApCnt = 0
#macroGenAp = 0
#macroValidPlanarAp = 0
#macroValidViaAp = 0
#macroNoAp = 0
complete pin access
cpu time = 00:00:05, elapsed time = 00:00:03, memory = 28.22 (MB), peak = 30.30 (MB)
post process guides ...
GCELLGRID X 0 DO 41 STEP 7200 ;
GCELLGRID Y 0 DO 41 STEP 7200 ;
complete FR_MASTERSLICE
complete FR_VIA
complete li1
complete mcon
complete met1
complete via
complete met2
complete via2
complete met3
complete via3
complete met4
complete via4
complete met5
building cmap ...
init guide query ...
complete FR_MASTERSLICE (guide)
complete FR_VIA (guide)
complete li1 (guide)
complete mcon (guide)
complete met1 (guide)
complete via (guide)
complete met2 (guide)
complete via2 (guide)
complete met3 (guide)
complete via3 (guide)
complete met4 (guide)
complete via4 (guide)
complete met5 (guide)
FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 1151
mcon guide region query size = 0
met1 guide region query size = 1314
via guide region query size = 0
met2 guide region query size = 1310
via2 guide region query size = 0
met3 guide region query size = 38
via3 guide region query size = 0
met4 guide region query size = 13
via4 guide region query size = 0
met5 guide region query size = 4
init gr pin query ...
start track assignment
Done with 2474 vertical wires in 1 frboxes and 1356 horizontal wires in 1 frboxes.
Done with 588 vertical wires in 1 frboxes and 310 horizontal wires in 1 frboxes.
complete track assignment
cpu time = 00:00:01, elapsed time = 00:00:01, memory = 45.75 (MB), peak = 51.53 (MB)
post processing ...
start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 46.79 (MB), peak = 51.53 (MB)
start detail routing ...
start 0th optimization iteration ...
completing 10% with 0 violations
elapsed time = 00:00:02, memory = 89.00 (MB)
completing 20% with 0 violations
elapsed time = 00:00:04, memory = 96.52 (MB)
completing 30% with 141 violations
elapsed time = 00:00:05, memory = 83.41 (MB)
completing 40% with 141 violations
elapsed time = 00:00:06, memory = 86.14 (MB)
completing 50% with 141 violations
elapsed time = 00:00:06, memory = 86.25 (MB)
completing 60% with 166 violations
elapsed time = 00:00:08, memory = 89.52 (MB)
completing 70% with 166 violations
elapsed time = 00:00:10, memory = 98.07 (MB)
completing 80% with 258 violations
elapsed time = 00:00:11, memory = 84.21 (MB)
completing 90% with 258 violations
elapsed time = 00:00:11, memory = 84.66 (MB)
completing 100% with 262 violations
elapsed time = 00:00:12, memory = 48.64 (MB)
number of violations = 262
cpu time = 00:00:23, elapsed time = 00:00:13, memory = 49.71 (MB), peak = 396.94 (MB)
total wire length = 77484 um
total wire length on LAYER li1 = 46 um
total wire length on LAYER met1 = 24271 um
total wire length on LAYER met2 = 48407 um
total wire length on LAYER met3 = 2682 um
total wire length on LAYER met4 = 1304 um
total wire length on LAYER met5 = 770 um
total number of vias = 3243
up-via summary (total 3243):
-----------------------
FR_MASTERSLICE 0
li1 1396
met1 1721
met2 98
met3 20
met4 8
-----------------------
3243
start 1st optimization iteration ...
completing 10% with 262 violations
elapsed time = 00:00:00, memory = 80.64 (MB)
completing 20% with 262 violations
elapsed time = 00:00:01, memory = 85.68 (MB)
completing 30% with 262 violations
elapsed time = 00:00:02, memory = 90.39 (MB)
completing 40% with 220 violations
elapsed time = 00:00:03, memory = 90.93 (MB)
completing 50% with 220 violations
elapsed time = 00:00:03, memory = 91.43 (MB)
completing 60% with 194 violations
elapsed time = 00:00:04, memory = 86.13 (MB)
completing 70% with 194 violations
elapsed time = 00:00:06, memory = 94.37 (MB)
completing 80% with 194 violations
elapsed time = 00:00:07, memory = 94.45 (MB)
completing 90% with 168 violations
elapsed time = 00:00:09, memory = 103.11 (MB)
completing 100% with 156 violations
elapsed time = 00:00:13, memory = 50.08 (MB)
number of violations = 156
cpu time = 00:00:24, elapsed time = 00:00:14, memory = 49.92 (MB), peak = 397.09 (MB)
total wire length = 77406 um
total wire length on LAYER li1 = 29 um
total wire length on LAYER met1 = 24208 um
total wire length on LAYER met2 = 48362 um
total wire length on LAYER met3 = 2702 um
total wire length on LAYER met4 = 1334 um
total wire length on LAYER met5 = 768 um
total number of vias = 3253
up-via summary (total 3253):
-----------------------
FR_MASTERSLICE 0
li1 1372
met1 1743
met2 102
met3 28
met4 8
-----------------------
3253
start 2nd optimization iteration ...
completing 10% with 156 violations
elapsed time = 00:00:00, memory = 54.30 (MB)
completing 20% with 156 violations
elapsed time = 00:00:00, memory = 74.69 (MB)
completing 30% with 156 violations
elapsed time = 00:00:00, memory = 76.87 (MB)
completing 40% with 156 violations
elapsed time = 00:00:00, memory = 80.21 (MB)
completing 50% with 156 violations
elapsed time = 00:00:01, memory = 89.70 (MB)
completing 60% with 174 violations
elapsed time = 00:00:04, memory = 77.33 (MB)
completing 70% with 174 violations
elapsed time = 00:00:04, memory = 83.78 (MB)
completing 80% with 174 violations
elapsed time = 00:00:05, memory = 84.03 (MB)
completing 90% with 171 violations
elapsed time = 00:00:06, memory = 99.23 (MB)
completing 100% with 144 violations
elapsed time = 00:00:12, memory = 68.73 (MB)
number of violations = 144
cpu time = 00:00:21, elapsed time = 00:00:12, memory = 61.01 (MB), peak = 407.49 (MB)
total wire length = 77432 um
total wire length on LAYER li1 = 42 um
total wire length on LAYER met1 = 24272 um
total wire length on LAYER met2 = 48382 um
total wire length on LAYER met3 = 2659 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3231
up-via summary (total 3231):
-----------------------
FR_MASTERSLICE 0
li1 1389
met1 1724
met2 90
met3 20
met4 8
-----------------------
3231
start 3rd optimization iteration ...
completing 10% with 144 violations
elapsed time = 00:00:00, memory = 97.87 (MB)
completing 20% with 144 violations
elapsed time = 00:00:01, memory = 105.86 (MB)
completing 30% with 58 violations
elapsed time = 00:00:02, memory = 75.04 (MB)
completing 40% with 58 violations
elapsed time = 00:00:03, memory = 79.80 (MB)
completing 50% with 58 violations
elapsed time = 00:00:03, memory = 79.95 (MB)
completing 60% with 47 violations
elapsed time = 00:00:03, memory = 93.21 (MB)
completing 70% with 47 violations
elapsed time = 00:00:04, memory = 94.50 (MB)
completing 80% with 5 violations
elapsed time = 00:00:04, memory = 77.09 (MB)
completing 90% with 5 violations
elapsed time = 00:00:04, memory = 77.21 (MB)
completing 100% with 5 violations
elapsed time = 00:00:04, memory = 77.21 (MB)
number of violations = 5
cpu time = 00:00:08, elapsed time = 00:00:05, memory = 77.21 (MB), peak = 422.16 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24019 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 4th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 86.23 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 86.75 (MB)
completing 30% with 5 violations
elapsed time = 00:00:01, memory = 76.61 (MB)
completing 40% with 5 violations
elapsed time = 00:00:02, memory = 79.23 (MB)
completing 50% with 5 violations
elapsed time = 00:00:02, memory = 79.23 (MB)
completing 60% with 5 violations
elapsed time = 00:00:02, memory = 79.49 (MB)
completing 70% with 5 violations
elapsed time = 00:00:02, memory = 79.75 (MB)
completing 80% with 5 violations
elapsed time = 00:00:03, memory = 79.75 (MB)
completing 90% with 5 violations
elapsed time = 00:00:03, memory = 79.75 (MB)
completing 100% with 5 violations
elapsed time = 00:00:03, memory = 79.75 (MB)
number of violations = 5
cpu time = 00:00:06, elapsed time = 00:00:04, memory = 82.75 (MB), peak = 424.44 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24019 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 5th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 82.75 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 82.96 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 82.96 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 82.96 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 82.96 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 82.96 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 89.14 (MB)
completing 80% with 5 violations
elapsed time = 00:00:02, memory = 90.76 (MB)
completing 90% with 5 violations
elapsed time = 00:00:02, memory = 81.45 (MB)
completing 100% with 5 violations
elapsed time = 00:00:02, memory = 81.60 (MB)
number of violations = 5
cpu time = 00:00:06, elapsed time = 00:00:03, memory = 81.60 (MB), peak = 424.44 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24019 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 6th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 81.60 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 81.71 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 81.73 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 81.73 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 81.99 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 81.99 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 86.39 (MB)
completing 80% with 5 violations
elapsed time = 00:00:01, memory = 86.47 (MB)
completing 90% with 5 violations
elapsed time = 00:00:02, memory = 81.59 (MB)
completing 100% with 5 violations
elapsed time = 00:00:02, memory = 82.36 (MB)
number of violations = 5
cpu time = 00:00:05, elapsed time = 00:00:03, memory = 82.36 (MB), peak = 424.44 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24019 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 7th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 82.36 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 82.38 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 82.54 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 82.54 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 83.31 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 83.47 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 83.47 (MB)
completing 80% with 5 violations
elapsed time = 00:00:01, memory = 83.47 (MB)
completing 90% with 5 violations
elapsed time = 00:00:02, memory = 87.84 (MB)
completing 100% with 5 violations
elapsed time = 00:00:02, memory = 88.06 (MB)
number of violations = 5
cpu time = 00:00:05, elapsed time = 00:00:03, memory = 87.80 (MB), peak = 429.41 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24019 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 8th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 87.80 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 87.80 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 87.86 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 87.86 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 87.86 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 87.86 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 87.86 (MB)
completing 80% with 5 violations
elapsed time = 00:00:01, memory = 87.86 (MB)
completing 90% with 5 violations
elapsed time = 00:00:02, memory = 95.59 (MB)
completing 100% with 5 violations
elapsed time = 00:00:02, memory = 77.71 (MB)
number of violations = 5
cpu time = 00:00:05, elapsed time = 00:00:03, memory = 77.71 (MB), peak = 429.41 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24019 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 9th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 78.23 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 86.73 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 86.82 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 86.82 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 86.92 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 86.92 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 86.92 (MB)
completing 80% with 5 violations
elapsed time = 00:00:01, memory = 86.92 (MB)
completing 90% with 5 violations
elapsed time = 00:00:02, memory = 96.45 (MB)
completing 100% with 5 violations
elapsed time = 00:00:04, memory = 62.67 (MB)
number of violations = 5
cpu time = 00:00:07, elapsed time = 00:00:05, memory = 62.67 (MB), peak = 429.41 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24019 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 10th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 92.05 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 95.32 (MB)
completing 30% with 5 violations
elapsed time = 00:00:02, memory = 80.01 (MB)
completing 40% with 5 violations
elapsed time = 00:00:02, memory = 83.99 (MB)
completing 50% with 5 violations
elapsed time = 00:00:02, memory = 84.23 (MB)
completing 60% with 5 violations
elapsed time = 00:00:02, memory = 84.23 (MB)
completing 70% with 5 violations
elapsed time = 00:00:03, memory = 84.23 (MB)
completing 80% with 5 violations
elapsed time = 00:00:03, memory = 84.23 (MB)
completing 90% with 5 violations
elapsed time = 00:00:03, memory = 84.23 (MB)
completing 100% with 5 violations
elapsed time = 00:00:03, memory = 84.45 (MB)
number of violations = 5
cpu time = 00:00:06, elapsed time = 00:00:04, memory = 84.45 (MB), peak = 429.41 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24020 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 11th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 85.48 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 85.86 (MB)
completing 30% with 5 violations
elapsed time = 00:00:01, memory = 86.37 (MB)
completing 40% with 5 violations
elapsed time = 00:00:01, memory = 86.37 (MB)
completing 50% with 5 violations
elapsed time = 00:00:02, memory = 86.37 (MB)
completing 60% with 5 violations
elapsed time = 00:00:02, memory = 86.48 (MB)
completing 70% with 5 violations
elapsed time = 00:00:02, memory = 86.48 (MB)
completing 80% with 5 violations
elapsed time = 00:00:02, memory = 86.48 (MB)
completing 90% with 5 violations
elapsed time = 00:00:03, memory = 86.56 (MB)
completing 100% with 5 violations
elapsed time = 00:00:03, memory = 86.56 (MB)
number of violations = 5
cpu time = 00:00:06, elapsed time = 00:00:04, memory = 85.94 (MB), peak = 429.41 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24020 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 12th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 85.94 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 85.94 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 85.94 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 85.94 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 85.94 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 85.94 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 89.03 (MB)
completing 80% with 5 violations
elapsed time = 00:00:01, memory = 89.20 (MB)
completing 90% with 5 violations
elapsed time = 00:00:02, memory = 83.89 (MB)
completing 100% with 5 violations
elapsed time = 00:00:02, memory = 84.14 (MB)
number of violations = 5
cpu time = 00:00:05, elapsed time = 00:00:03, memory = 84.14 (MB), peak = 429.41 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24020 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 13th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 84.14 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 84.29 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 84.29 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 84.80 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 85.00 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 85.00 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 86.28 (MB)
completing 80% with 5 violations
elapsed time = 00:00:01, memory = 86.33 (MB)
completing 90% with 5 violations
elapsed time = 00:00:02, memory = 82.25 (MB)
completing 100% with 5 violations
elapsed time = 00:00:02, memory = 82.76 (MB)
number of violations = 5
cpu time = 00:00:05, elapsed time = 00:00:03, memory = 82.76 (MB), peak = 429.41 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24020 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 14th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 82.76 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 82.81 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 82.81 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 82.81 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 83.58 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 83.58 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 83.71 (MB)
completing 80% with 5 violations
elapsed time = 00:00:01, memory = 83.71 (MB)
completing 90% with 5 violations
elapsed time = 00:00:02, memory = 87.82 (MB)
completing 100% with 5 violations
elapsed time = 00:00:02, memory = 87.84 (MB)
number of violations = 5
cpu time = 00:00:05, elapsed time = 00:00:03, memory = 87.59 (MB), peak = 429.41 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24020 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 15th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 87.59 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 87.66 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 87.83 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 87.83 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 87.99 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 88.19 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 88.19 (MB)
completing 80% with 5 violations
elapsed time = 00:00:01, memory = 88.19 (MB)
completing 90% with 5 violations
elapsed time = 00:00:02, memory = 88.44 (MB)
completing 100% with 5 violations
elapsed time = 00:00:02, memory = 89.21 (MB)
number of violations = 5
cpu time = 00:00:05, elapsed time = 00:00:03, memory = 88.44 (MB), peak = 430.21 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24020 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 16th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 88.44 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 88.48 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 88.48 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 88.48 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 88.55 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 88.55 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 88.55 (MB)
completing 80% with 5 violations
elapsed time = 00:00:01, memory = 88.55 (MB)
completing 90% with 5 violations
elapsed time = 00:00:02, memory = 97.06 (MB)
completing 100% with 5 violations
elapsed time = 00:00:04, memory = 77.75 (MB)
number of violations = 5
cpu time = 00:00:07, elapsed time = 00:00:05, memory = 77.75 (MB), peak = 430.21 (MB)
total wire length = 77447 um
total wire length on LAYER li1 = 41 um
total wire length on LAYER met1 = 24020 um
total wire length on LAYER met2 = 48406 um
total wire length on LAYER met3 = 2903 um
total wire length on LAYER met4 = 1306 um
total wire length on LAYER met5 = 769 um
total number of vias = 3295
up-via summary (total 3295):
-----------------------
FR_MASTERSLICE 0
li1 1390
met1 1763
met2 114
met3 20
met4 8
-----------------------
3295
start 17th optimization iteration ...
completing 10% with 5 violations
elapsed time = 00:00:00, memory = 81.36 (MB)
completing 20% with 5 violations
elapsed time = 00:00:00, memory = 86.26 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 86.47 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 86.47 (MB)
completing 50% with 5 violations
elapsed time = 00:00:01, memory = 86.47 (MB)
completing 60% with 5 violations
elapsed time = 00:00:01, memory = 86.47 (MB)
completing 70% with 5 violations
elapsed time = 00:00:01, memory = 86.67 (MB)
completing 80% with 5 violations
elapsed time = 00:00:02, memory = 87.23 (MB)
completing 90% with 0 violations
elapsed time = 00:00:02, memory = 83.65 (MB)
completing 100% with 0 violations
elapsed time = 00:00:03, memory = 83.67 (MB)
number of violations = 0
cpu time = 00:00:06, elapsed time = 00:00:03, memory = 80.67 (MB), peak = 430.21 (MB)
total wire length = 77424 um
total wire length on LAYER li1 = 28 um
total wire length on LAYER met1 = 23948 um
total wire length on LAYER met2 = 48367 um
total wire length on LAYER met3 = 2968 um
total wire length on LAYER met4 = 1342 um
total wire length on LAYER met5 = 769 um
total number of vias = 3288
up-via summary (total 3288):
-----------------------
FR_MASTERSLICE 0
li1 1380
met1 1756
met2 120
met3 24
met4 8
-----------------------
3288
start 25th optimization iteration ...
completing 10% with 0 violations
elapsed time = 00:00:00, memory = 80.67 (MB)
completing 20% with 0 violations
elapsed time = 00:00:00, memory = 80.67 (MB)
completing 30% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 40% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 50% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 60% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 70% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 80% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 90% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
completing 100% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
number of violations = 0
cpu time = 00:00:04, elapsed time = 00:00:02, memory = 80.90 (MB), peak = 430.21 (MB)
total wire length = 77424 um
total wire length on LAYER li1 = 28 um
total wire length on LAYER met1 = 23948 um
total wire length on LAYER met2 = 48367 um
total wire length on LAYER met3 = 2968 um
total wire length on LAYER met4 = 1342 um
total wire length on LAYER met5 = 769 um
total number of vias = 3288
up-via summary (total 3288):
-----------------------
FR_MASTERSLICE 0
li1 1380
met1 1756
met2 120
met3 24
met4 8
-----------------------
3288
start 33rd optimization iteration ...
completing 10% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 20% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 30% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 40% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 50% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 60% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 70% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 80% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
completing 90% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
completing 100% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
number of violations = 0
cpu time = 00:00:05, elapsed time = 00:00:02, memory = 80.90 (MB), peak = 430.21 (MB)
total wire length = 77424 um
total wire length on LAYER li1 = 28 um
total wire length on LAYER met1 = 23948 um
total wire length on LAYER met2 = 48367 um
total wire length on LAYER met3 = 2968 um
total wire length on LAYER met4 = 1342 um
total wire length on LAYER met5 = 769 um
total number of vias = 3288
up-via summary (total 3288):
-----------------------
FR_MASTERSLICE 0
li1 1380
met1 1756
met2 120
met3 24
met4 8
-----------------------
3288
start 41st optimization iteration ...
completing 10% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 20% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 30% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 40% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 50% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 60% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 70% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 80% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
completing 90% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
completing 100% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
number of violations = 0
cpu time = 00:00:05, elapsed time = 00:00:02, memory = 80.90 (MB), peak = 430.21 (MB)
total wire length = 77424 um
total wire length on LAYER li1 = 28 um
total wire length on LAYER met1 = 23948 um
total wire length on LAYER met2 = 48367 um
total wire length on LAYER met3 = 2968 um
total wire length on LAYER met4 = 1342 um
total wire length on LAYER met5 = 769 um
total number of vias = 3288
up-via summary (total 3288):
-----------------------
FR_MASTERSLICE 0
li1 1380
met1 1756
met2 120
met3 24
met4 8
-----------------------
3288
start 49th optimization iteration ...
completing 10% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 20% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 30% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 40% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 50% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 60% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 70% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
completing 80% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
completing 90% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
completing 100% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
number of violations = 0
cpu time = 00:00:05, elapsed time = 00:00:02, memory = 80.90 (MB), peak = 430.21 (MB)
total wire length = 77424 um
total wire length on LAYER li1 = 28 um
total wire length on LAYER met1 = 23948 um
total wire length on LAYER met2 = 48367 um
total wire length on LAYER met3 = 2968 um
total wire length on LAYER met4 = 1342 um
total wire length on LAYER met5 = 769 um
total number of vias = 3288
up-via summary (total 3288):
-----------------------
FR_MASTERSLICE 0
li1 1380
met1 1756
met2 120
met3 24
met4 8
-----------------------
3288
start 57th optimization iteration ...
completing 10% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 20% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 30% with 0 violations
elapsed time = 00:00:00, memory = 80.90 (MB)
completing 40% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 50% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 60% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 70% with 0 violations
elapsed time = 00:00:01, memory = 80.90 (MB)
completing 80% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
completing 90% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
completing 100% with 0 violations
elapsed time = 00:00:02, memory = 80.90 (MB)
number of violations = 0
cpu time = 00:00:05, elapsed time = 00:00:02, memory = 80.90 (MB), peak = 430.21 (MB)
total wire length = 77424 um
total wire length on LAYER li1 = 28 um
total wire length on LAYER met1 = 23948 um
total wire length on LAYER met2 = 48367 um
total wire length on LAYER met3 = 2968 um
total wire length on LAYER met4 = 1342 um
total wire length on LAYER met5 = 769 um
total number of vias = 3288
up-via summary (total 3288):
-----------------------
FR_MASTERSLICE 0
li1 1380
met1 1756
met2 120
met3 24
met4 8
-----------------------
3288
complete detail routing
total wire length = 77424 um
total wire length on LAYER li1 = 28 um
total wire length on LAYER met1 = 23948 um
total wire length on LAYER met2 = 48367 um
total wire length on LAYER met3 = 2968 um
total wire length on LAYER met4 = 1342 um
total wire length on LAYER met5 = 769 um
total number of vias = 3288
up-via summary (total 3288):
-----------------------
FR_MASTERSLICE 0
li1 1380
met1 1756
met2 120
met3 24
met4 8
-----------------------
3288
cpu time = 00:03:13, elapsed time = 00:01:56, memory = 80.90 (MB), peak = 430.21 (MB)
post processing ...
Runtime taken (hrt): 124.351
[INFO]: No DRC violations after detailed routing.
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/21-addspacers.def to /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
[INFO]: Taking a Screenshot of the Layout Using Klayout...
[INFO]: current step index: 24
Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def.png'
Done
[INFO]: Screenshot taken.
[INFO]: Calculating Runtime From the Start...
[INFO]: Routing completed for user_proj_example/15-06_07-02 in 0h7m12s
[INFO]: Writing Powered Verilog...
[INFO]: current step index: 25
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
Notice 0: Design: user_proj_example
Notice 0: Created 620 pins.
Notice 0: Created 9349 components and 37536 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 1208 nets and 1725 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
Top-level design name: user_proj_example
Default power net: vccd1
Default ground net: vssd1
Found a total of 4 power ports.
Found a total of 4 ground ports.
Modified power connections of 9349 cells (Remaining: 0 ).
[INFO]: Writing Verilog...
[INFO]: current step index: 26
OpenROAD 0.9.0 1415572a73
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 418 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/25-user_proj_example.powered.def
Notice 0: Design: user_proj_example
Notice 0: Created 612 pins.
Notice 0: Created 9349 components and 37536 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 1210 nets and 37319 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/25-user_proj_example.powered.def
[INFO]: Yosys won't attempt to rewrite verilog, and the OpenROAD output will be used as is.
[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_preroute.v to /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.powered.v
[INFO]: Running Magic to generate various views...
[INFO]: Streaming out GDS II...
[INFO]: current step index: 27
Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(): scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic/mag_gds.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef.
This action cannot be undone.
LEF read, Line 64 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 77 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 98 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 99 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 111 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 137 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 138 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 155 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 174 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 191 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 227 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 246 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 263 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 769 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef.
This action cannot be undone.
LEF read: Processed 142 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX8.lef.
This action cannot be undone.
LEF read: Processed 166 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef.
This action cannot be undone.
LEF read: Processed 153 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX4.lef.
This action cannot be undone.
LEF read: Processed 117 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef.
This action cannot be undone.
LEF read: Processed 187 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef.
This action cannot be undone.
LEF read: Processed 114 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/HAX1.lef.
This action cannot be undone.
LEF read: Processed 328 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef.
This action cannot be undone.
LEF read: Processed 155 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef.
This action cannot be undone.
LEF read: Processed 202 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef.
This action cannot be undone.
LEF read: Processed 128 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef.
This action cannot be undone.
LEF read: Processed 156 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef.
This action cannot be undone.
LEF read: Processed 115 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX2.lef.
This action cannot be undone.
LEF read: Processed 62 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef.
This action cannot be undone.
LEF read: Processed 158 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef.
This action cannot be undone.
LEF read: Processed 185 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef.
This action cannot be undone.
LEF read: Processed 243 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef.
This action cannot be undone.
LEF read: Processed 158 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX1.lef.
This action cannot be undone.
LEF read: Processed 62 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INV.lef.
This action cannot be undone.
LEF read: Processed 62 lines.
Reading DEF data from file /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def.
This action cannot be undone.
Processed 5 vias total.
Processed 9349 subcell instances total.
Processed 620 pins total.
Processed 8 special nets total.
Processed 1208 nets total.
DEF read: Processed 21701 lines.
Root cell box:
width x height ( llx, lly ), ( urx, ury ) area (units^2)
microns: 300.00 x 300.00 ( 0.00, 0.00 ), ( 300.00, 300.00) 90000.00
lambda: 30000.00 x 30000.00 ( 0.00, 0.00 ), ( 30000.00, 30000.00) 900000000.00
internal: 60000 x 60000 ( 0, 0 ), ( 60000, 60000) 3600000000
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "HAX1".
Warning: cell HAX1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "INVX8".
Warning: cell INVX8 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "AND2X2".
Warning: cell AND2X2 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "XNOR2X1".
Warning: cell XNOR2X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "OAI22X1".
Warning: cell OAI22X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "AOI21X1".
Warning: cell AOI21X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "NAND2X1".
Warning: cell NAND2X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "OAI21X1".
Warning: cell OAI21X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "INV".
Warning: cell INV already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "AOI22X1".
Warning: cell AOI22X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "OR2X1".
Warning: cell OR2X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "INVX1".
Warning: cell INVX1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "NOR2X1".
Warning: cell NOR2X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "MUX2X1".
Warning: cell MUX2X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "BUFX2".
Warning: cell BUFX2 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "AND2X1".
Warning: cell AND2X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "NAND3X1".
Warning: cell NAND3X1 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "INVX2".
Warning: cell INVX2 already existed before reading GDS!
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 6.0
Library name: LIB
Reading "INVX4".
Warning: cell INVX4 already existed before reading GDS!
Generating output for cell sky130_fd_sc_ls__decap_4
Generating output for cell sky130_fd_sc_ls__clkbuf_1
Generating output for cell sky130_fd_sc_ls__decap_8
Generating output for cell sky130_fd_sc_ls__tapvpwrvgnd_1
Generating output for cell sky130_fd_sc_ls__fill_diode_2
Generating output for cell sky130_fd_sc_ls__fill_1
Generating output for cell sky130_fd_sc_ls__conb_1
Generating output for cell sky130_fd_sc_ls__buf_1
Generating output for cell sky130_fd_sc_ls__diode_2
Generating output for cell sky130_fd_sc_ls__clkbuf_2
Generating output for cell AND2X1
Generating output for cell AND2X2
Generating output for cell AOI21X1
Generating output for cell AOI22X1
Generating output for cell BUFX2
Generating output for cell HAX1
Generating output for cell INV
Generating output for cell INVX1
Generating output for cell INVX2
Generating output for cell INVX4
Generating output for cell INVX8
Generating output for cell MUX2X1
Generating output for cell NAND2X1
Generating output for cell NAND3X1
Generating output for cell NOR2X1
Generating output for cell OAI21X1
Generating output for cell OAI22X1
Generating output for cell OR2X1
Generating output for cell XNOR2X1
Generating output for cell sky130_fd_sc_ls__buf_2
Generating output for cell sky130_fd_sc_ls__clkbuf_4
Generating output for cell user_proj_example
[INFO]: GDS Write Complete
[INFO]: Taking a Screenshot of the Layout Using Klayout...
[INFO]: current step index: 28
Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds
[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds
[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds.png'
Done
[INFO]: Screenshot taken.
[INFO]: current step index: 29
Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(): scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic/gds_pointers.tcl" from command line.
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 3.0
Library name: user_proj_example
Reading "sky130_fd_sc_ls__decap_4".
CIF file read warning: CIF style sky130(): units rescaled by factor of 5 / 1
Reading "sky130_fd_sc_ls__clkbuf_1".
Reading "sky130_fd_sc_ls__decap_8".
Reading "sky130_fd_sc_ls__tapvpwrvgnd_1".
Reading "sky130_fd_sc_ls__fill_diode_2".
Reading "sky130_fd_sc_ls__fill_1".
Reading "sky130_fd_sc_ls__conb_1".
Reading "sky130_fd_sc_ls__buf_1".
Reading "sky130_fd_sc_ls__diode_2".
Reading "sky130_fd_sc_ls__clkbuf_2".
Reading "AND2X1".
Reading "AND2X2".
Reading "AOI21X1".
Reading "AOI22X1".
Reading "BUFX2".
Reading "HAX1".
Reading "INV".
Reading "INVX1".
Reading "INVX2".
Reading "INVX4".
Reading "INVX8".
Reading "MUX2X1".
Reading "NAND2X1".
Reading "NAND3X1".
Reading "NOR2X1".
Reading "OAI21X1".
Reading "OAI22X1".
Reading "OR2X1".
Reading "XNOR2X1".
Reading "sky130_fd_sc_ls__buf_2".
Reading "sky130_fd_sc_ls__clkbuf_4".
Reading "user_proj_example".
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[INFO]: Wrote /project/openlane/user_proj_example/runs/user_proj_example/tmp/magic/magic_gds_ptrs.mag including GDS pointers.
[INFO]: current step index: 30
Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(): scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic/lef.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef.
This action cannot be undone.
LEF read, Line 64 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 77 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 98 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 99 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 111 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 137 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 138 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 155 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 174 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 191 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 227 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 246 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 263 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 769 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef.
This action cannot be undone.
LEF read: Processed 142 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX8.lef.
This action cannot be undone.
LEF read: Processed 166 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef.
This action cannot be undone.
LEF read: Processed 153 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX4.lef.
This action cannot be undone.
LEF read: Processed 117 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef.
This action cannot be undone.
LEF read: Processed 187 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef.
This action cannot be undone.
LEF read: Processed 114 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/HAX1.lef.
This action cannot be undone.
LEF read: Processed 328 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef.
This action cannot be undone.
LEF read: Processed 155 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef.
This action cannot be undone.
LEF read: Processed 202 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef.
This action cannot be undone.
LEF read: Processed 128 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef.
This action cannot be undone.
LEF read: Processed 156 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef.
This action cannot be undone.
LEF read: Processed 115 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX2.lef.
This action cannot be undone.
LEF read: Processed 62 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef.
This action cannot be undone.
LEF read: Processed 158 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef.
This action cannot be undone.
LEF read: Processed 185 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef.
This action cannot be undone.
LEF read: Processed 243 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef.
This action cannot be undone.
LEF read: Processed 158 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX1.lef.
This action cannot be undone.
LEF read: Processed 62 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INV.lef.
This action cannot be undone.
LEF read: Processed 62 lines.
user_proj_example: 10000 rects
user_proj_example: 20000 rects
user_proj_example: 30000 rects
Processing timestamp mismatches: XNOR2X1, OR2X1, OAI22X1, OAI21X1, NOR2X1, NAND3X1, NAND2X1, MUX2X1, INVX8, INVX4, INVX2, INVX1, INV, HAX1, BUFX2, AOI22X1, AOI21X1, AND2X2, AND2X1.
[INFO]: Writing abstract LEF
Generating LEF output /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.lef for cell user_proj_example:
Diagnostic: Write LEF header for cell user_proj_example
Diagnostic: Writing LEF output for cell user_proj_example
Warning: Parent cell lists instance of "sky130_fd_sc_ls__decap_4" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__decap_4.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__decap_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__decap_8" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__decap_8.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__decap_8.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__fill_1" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__fill_1.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__fill_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__fill_diode_2" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__fill_diode_2.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__fill_diode_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__clkbuf_4" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__clkbuf_4.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__clkbuf_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__tapvpwrvgnd_1" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__tapvpwrvgnd_1.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__tapvpwrvgnd_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__clkbuf_1" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__clkbuf_1.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__clkbuf_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__clkbuf_2" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__clkbuf_2.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__clkbuf_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__diode_2" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__diode_2.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__diode_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__buf_2" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__buf_2.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__buf_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__conb_1" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__conb_1.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__conb_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_ls__buf_1" at bad file path /project/openlane/user_proj_example/runs/user_proj_example/results/magic/sky130_fd_sc_ls__buf_1.mag.
The cell exists in the search paths at /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/maglef/sky130_fd_sc_ls__buf_1.mag.
The discovered version will be used.
Diagnostic: Scale value is 0.005000
Processing timestamp mismatches: sky130_fd_sc_ls__buf_1, sky130_fd_sc_ls__conb_1, sky130_fd_sc_ls__buf_2, sky130_fd_sc_ls__diode_2, sky130_fd_sc_ls__clkbuf_2, sky130_fd_sc_ls__clkbuf_1, sky130_fd_sc_ls__tapvpwrvgnd_1, sky130_fd_sc_ls__clkbuf_4, sky130_fd_sc_ls__fill_diode_2, sky130_fd_sc_ls__fill_1, sky130_fd_sc_ls__decap_8, sky130_fd_sc_ls__decap_4.
[INFO]: LEF Write Complete
Using technology "sky130A", version 1.0.156-0-g7e29496
[INFO]: current step index: 31
Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(): scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic/maglef.tcl" from command line.
Reading LEF data from file /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.lef.
This action cannot be undone.
LEF read: Processed 5246 lines.
[INFO]: DONE GENERATING MAGLEF VIEW
[INFO]: Running Klayout to re-generate GDS-II...
[INFO]: Streaming out GDS II...
[INFO]: current step index: 32
Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
Using DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
Design Name: user_proj_example
Output GDS will be: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds
Extra GDSes:
/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/gds/sky130_fd_sc_ls.gds /project/openlane/user_proj_example/../../cells/gds/HAX1.gds /project/openlane/user_proj_example/../../cells/gds/INVX8.gds /project/openlane/user_proj_example/../../cells/gds/AND2X2.gds /project/openlane/user_proj_example/../../cells/gds/XNOR2X1.gds /project/openlane/user_proj_example/../../cells/gds/OAI22X1.gds /project/openlane/user_proj_example/../../cells/gds/AOI21X1.gds /project/openlane/user_proj_example/../../cells/gds/NAND2X1.gds /project/openlane/user_proj_example/../../cells/gds/OAI21X1.gds /project/openlane/user_proj_example/../../cells/gds/INV.gds /project/openlane/user_proj_example/../../cells/gds/AOI22X1.gds /project/openlane/user_proj_example/../../cells/gds/OR2X1.gds /project/openlane/user_proj_example/../../cells/gds/INVX1.gds /project/openlane/user_proj_example/../../cells/gds/NOR2X1.gds /project/openlane/user_proj_example/../../cells/gds/MUX2X1.gds /project/openlane/user_proj_example/../../cells/gds/BUFX2.gds /project/openlane/user_proj_example/../../cells/gds/AND2X1.gds /project/openlane/user_proj_example/../../cells/gds/NAND3X1.gds /project/openlane/user_proj_example/../../cells/gds/INVX2.gds /project/openlane/user_proj_example/../../cells/gds/INVX4.gds
[INFO] Clearing cells...
[INFO] Merging GDS files...
/media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/gds/sky130_fd_sc_ls.gds
/project/openlane/user_proj_example/../../cells/gds/HAX1.gds
/project/openlane/user_proj_example/../../cells/gds/INVX8.gds
/project/openlane/user_proj_example/../../cells/gds/AND2X2.gds
/project/openlane/user_proj_example/../../cells/gds/XNOR2X1.gds
/project/openlane/user_proj_example/../../cells/gds/OAI22X1.gds
/project/openlane/user_proj_example/../../cells/gds/AOI21X1.gds
/project/openlane/user_proj_example/../../cells/gds/NAND2X1.gds
/project/openlane/user_proj_example/../../cells/gds/OAI21X1.gds
/project/openlane/user_proj_example/../../cells/gds/INV.gds
/project/openlane/user_proj_example/../../cells/gds/AOI22X1.gds
/project/openlane/user_proj_example/../../cells/gds/OR2X1.gds
/project/openlane/user_proj_example/../../cells/gds/INVX1.gds
/project/openlane/user_proj_example/../../cells/gds/NOR2X1.gds
/project/openlane/user_proj_example/../../cells/gds/MUX2X1.gds
/project/openlane/user_proj_example/../../cells/gds/BUFX2.gds
/project/openlane/user_proj_example/../../cells/gds/AND2X1.gds
/project/openlane/user_proj_example/../../cells/gds/NAND3X1.gds
/project/openlane/user_proj_example/../../cells/gds/INVX2.gds
/project/openlane/user_proj_example/../../cells/gds/INVX4.gds
[INFO] Copying toplevel cell 'user_proj_example'
WARNING: no fill config file specified
[INFO] Checking for missing GDS...
[INFO] All LEF cells have matching GDS cells
[INFO] Writing out GDS '/project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds'
Done
[INFO]: Back-up GDS-II streamed out.
[INFO]: Taking a Screenshot of the Layout Using Klayout...
[INFO]: current step index: 33
Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds
[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds
[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds.png'
Done
[INFO]: Screenshot taken.
[INFO]: Running XOR on the layouts using Klayout...
[INFO]: current step index: 34
First Layout: /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds
Second Layout: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds
Design Name: user_proj_example
Output GDS will be: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.gds
Reading /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds ..
Reading /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds ..
--- Running XOR for 122/16 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.340s
XOR differences: 118
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 235/4 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.040s
XOR differences: 1
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 236/0 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.690s
XOR differences: 6
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 237/0 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.030s
XOR differences: 1
"_output" in: xor.drc:41
Elapsed: 0.040s
--- Running XOR for 64/16 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.330s
XOR differences: 155
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 64/20 ---
"_input" in: xor.drc:38
Elapsed: 0.040s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.630s
XOR differences: 35
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 64/5 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.150s
XOR differences: 0
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 64/59 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.140s
XOR differences: 0
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 65/20 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.850s
XOR differences: 14965
"_output" in: xor.drc:41
Elapsed: 0.040s
--- Running XOR for 65/44 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.100s
XOR differences: 1905
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 66/15 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.020s
"^" in: xor.drc:38
Elapsed: 0.060s
XOR differences: 853
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 66/20 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 1.910s
XOR differences: 17664
"_output" in: xor.drc:41
Elapsed: 0.040s
--- Running XOR for 66/44 ---
"_input" in: xor.drc:38
Elapsed: 0.020s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 2.910s
XOR differences: 99204
"_output" in: xor.drc:41
Elapsed: 0.110s
--- Running XOR for 67/16 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.260s
XOR differences: 16690
"_output" in: xor.drc:41
Elapsed: 0.040s
--- Running XOR for 67/20 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 4.540s
XOR differences: 2487
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 67/44 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 2.290s
XOR differences: 55639
"_output" in: xor.drc:41
Elapsed: 0.070s
--- Running XOR for 67/5 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.070s
XOR differences: 0
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 68/16 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.020s
"^" in: xor.drc:38
Elapsed: 0.610s
XOR differences: 179
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 68/20 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 1.270s
XOR differences: 1714
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 68/44 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.100s
XOR differences: 4839
"_output" in: xor.drc:41
Elapsed: 0.040s
--- Running XOR for 68/5 ---
"_input" in: xor.drc:38
Elapsed: 0.020s
"_input" in: xor.drc:38
Elapsed: 0.040s
"^" in: xor.drc:38
Elapsed: 0.170s
XOR differences: 0
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 69/16 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.040s
"^" in: xor.drc:38
Elapsed: 0.050s
XOR differences: 978
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 69/20 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.310s
XOR differences: 2019
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 69/44 ---
"_input" in: xor.drc:38
Elapsed: 0.020s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.050s
XOR differences: 1568
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 69/5 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.030s
XOR differences: 0
"_output" in: xor.drc:41
Elapsed: 0.090s
--- Running XOR for 70/20 ---
"_input" in: xor.drc:38
Elapsed: 0.020s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.060s
XOR differences: 463
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 70/44 ---
"_input" in: xor.drc:38
Elapsed: 0.040s
"_input" in: xor.drc:38
Elapsed: 0.020s
"^" in: xor.drc:38
Elapsed: 0.060s
XOR differences: 1376
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 71/16 ---
"_input" in: xor.drc:38
Elapsed: 0.040s
"_input" in: xor.drc:38
Elapsed: 0.020s
"^" in: xor.drc:38
Elapsed: 0.050s
XOR differences: 31
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 71/20 ---
"_input" in: xor.drc:38
Elapsed: 0.040s
"_input" in: xor.drc:38
Elapsed: 0.020s
"^" in: xor.drc:38
Elapsed: 0.060s
XOR differences: 59
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 71/44 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.040s
XOR differences: 16
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 71/5 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.030s
XOR differences: 0
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 72/20 ---
"_input" in: xor.drc:38
Elapsed: 0.040s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.040s
XOR differences: 16
"_output" in: xor.drc:41
Elapsed: 0.040s
--- Running XOR for 78/44 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.370s
XOR differences: 6551
"_output" in: xor.drc:41
Elapsed: 0.040s
--- Running XOR for 81/23 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.050s
XOR differences: 431
"_output" in: xor.drc:41
Elapsed: 0.040s
--- Running XOR for 81/4 ---
"_input" in: xor.drc:38
Elapsed: 0.020s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.650s
XOR differences: 6
"_output" in: xor.drc:41
Elapsed: 0.030s
--- Running XOR for 83/44 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.160s
XOR differences: 0
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 93/44 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.650s
XOR differences: 939
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 94/20 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.630s
XOR differences: 890
"_output" in: xor.drc:41
Elapsed: 0.020s
--- Running XOR for 95/20 ---
"_input" in: xor.drc:38
Elapsed: 0.040s
"_input" in: xor.drc:38
Elapsed: 0.030s
"^" in: xor.drc:38
Elapsed: 0.320s
XOR differences: 1587
"_output" in: xor.drc:41
Elapsed: 0.030s
Writing layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.gds ..
Total run time: 25.820s
[INFO]: Taking a Screenshot of the Layout Using Klayout...
[INFO]: current step index: 35
Using Techfile: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
Using layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.gds
[INFO] Reading tech file: /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.tech/klayout/sky130A.lyt
[INFO] Reading Layout file: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.gds
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=2411190, record number=149364, cell=XOR)
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=12647654, record number=758709, cell=XOR)
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=12693574, record number=758714, cell=XOR)
[INFO] Writing out PNG screenshot '/project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.gds.png'
Done
[INFO]: Screenshot taken.
[INFO]: current step index: 36
First Layout: /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds
Second Layout: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds
Design Name: user_proj_example
Output GDS will be: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.xml
Reading /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.gds ..
Reading /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.gds ..
--- Running XOR for 122/16 ---
"_input" in: xor.drc:38
Elapsed: 0.030s
"_input" in: xor.drc:38
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XOR differences: 118
"_output" in: xor.drc:40
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--- Running XOR for 235/4 ---
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XOR differences: 1
"_output" in: xor.drc:40
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--- Running XOR for 236/0 ---
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"_input" in: xor.drc:38
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XOR differences: 6
"_output" in: xor.drc:40
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--- Running XOR for 237/0 ---
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"_input" in: xor.drc:38
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XOR differences: 1
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--- Running XOR for 64/16 ---
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XOR differences: 155
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--- Running XOR for 64/20 ---
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XOR differences: 35
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--- Running XOR for 64/5 ---
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XOR differences: 0
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--- Running XOR for 64/59 ---
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--- Running XOR for 65/20 ---
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XOR differences: 14965
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--- Running XOR for 65/44 ---
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XOR differences: 17664
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XOR differences: 99204
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XOR differences: 16690
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--- Running XOR for 67/20 ---
"_input" in: xor.drc:38
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XOR differences: 2487
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--- Running XOR for 67/44 ---
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XOR differences: 55639
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--- Running XOR for 67/5 ---
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XOR differences: 0
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--- Running XOR for 68/16 ---
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XOR differences: 179
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XOR differences: 1714
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--- Running XOR for 68/44 ---
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XOR differences: 4839
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--- Running XOR for 68/5 ---
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XOR differences: 0
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--- Running XOR for 69/16 ---
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XOR differences: 978
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--- Running XOR for 69/20 ---
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XOR differences: 2019
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--- Running XOR for 69/44 ---
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XOR differences: 1568
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XOR differences: 0
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XOR differences: 463
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XOR differences: 1376
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XOR differences: 31
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XOR differences: 0
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XOR differences: 16
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XOR differences: 6551
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--- Running XOR for 81/23 ---
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XOR differences: 431
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--- Running XOR for 81/4 ---
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XOR differences: 6
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--- Running XOR for 83/44 ---
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"_input" in: xor.drc:38
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XOR differences: 0
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--- Running XOR for 93/44 ---
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XOR differences: 939
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--- Running XOR for 94/20 ---
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XOR differences: 890
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--- Running XOR for 95/20 ---
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"^" in: xor.drc:38
Elapsed: 0.320s
XOR differences: 1587
"_output" in: xor.drc:40
Elapsed: 0.030s
Writing report database: /project/openlane/user_proj_example/runs/user_proj_example/results/klayout/user_proj_example.xor.xml ..
Total run time: 42.900s
[INFO]: Klayout XOR Complete
[INFO]: Running Magic Spice Export from LEF...
[INFO]: current step index: 37
Magic 8.3 revision 145 - Compiled on Mon Mar 22 04:21:56 UTC 2021.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(): scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/project/openlane/user_proj_example/runs/user_proj_example/tmp/magic_spice.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/pdk-ls/sky130A/libs.ref/sky130_fd_sc_ls/techlef/sky130_fd_sc_ls.tlef.
This action cannot be undone.
LEF read, Line 64 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 77 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 98 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 99 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 111 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 137 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 138 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 155 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 174 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 191 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 227 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 246 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
LEF read, Line 263 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 769 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef.
This action cannot be undone.
LEF read: Processed 142 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX8.lef.
This action cannot be undone.
LEF read: Processed 166 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef.
This action cannot be undone.
LEF read: Processed 153 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX4.lef.
This action cannot be undone.
LEF read: Processed 117 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef.
This action cannot be undone.
LEF read: Processed 187 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef.
This action cannot be undone.
LEF read: Processed 114 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/HAX1.lef.
This action cannot be undone.
LEF read: Processed 328 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef.
This action cannot be undone.
LEF read: Processed 155 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef.
This action cannot be undone.
LEF read: Processed 202 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef.
This action cannot be undone.
LEF read: Processed 128 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef.
This action cannot be undone.
LEF read: Processed 156 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef.
This action cannot be undone.
LEF read: Processed 115 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX2.lef.
This action cannot be undone.
LEF read: Processed 62 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef.
This action cannot be undone.
LEF read: Processed 158 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef.
This action cannot be undone.
LEF read: Processed 185 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef.
This action cannot be undone.
LEF read: Processed 243 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef.
This action cannot be undone.
LEF read: Processed 158 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX1.lef.
This action cannot be undone.
LEF read: Processed 62 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INV.lef.
This action cannot be undone.
LEF read: Processed 62 lines.
Reading DEF data from file /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def.
This action cannot be undone.
Processed 5 vias total.
Processed 9349 subcell instances total.
Processed 620 pins total.
Processed 8 special nets total.
Processed 1208 nets total.
DEF read: Processed 21701 lines.
Processing user_proj_example
Extracting sky130_fd_sc_ls__clkbuf_4 into sky130_fd_sc_ls__clkbuf_4.ext:
Extracting sky130_fd_sc_ls__buf_2 into sky130_fd_sc_ls__buf_2.ext:
Extracting XNOR2X1 into XNOR2X1.ext:
Extracting OR2X1 into OR2X1.ext:
Extracting OAI22X1 into OAI22X1.ext:
Extracting OAI21X1 into OAI21X1.ext:
Extracting NOR2X1 into NOR2X1.ext:
Extracting NAND3X1 into NAND3X1.ext:
Extracting NAND2X1 into NAND2X1.ext:
Extracting MUX2X1 into MUX2X1.ext:
Extracting INVX8 into INVX8.ext:
Extracting INVX4 into INVX4.ext:
Extracting INVX2 into INVX2.ext:
Extracting INVX1 into INVX1.ext:
Extracting INV into INV.ext:
Extracting HAX1 into HAX1.ext:
Extracting BUFX2 into BUFX2.ext:
Extracting AOI22X1 into AOI22X1.ext:
Extracting AOI21X1 into AOI21X1.ext:
Extracting AND2X2 into AND2X2.ext:
Extracting AND2X1 into AND2X1.ext:
Extracting sky130_fd_sc_ls__clkbuf_2 into sky130_fd_sc_ls__clkbuf_2.ext:
Extracting sky130_fd_sc_ls__diode_2 into sky130_fd_sc_ls__diode_2.ext:
Extracting sky130_fd_sc_ls__buf_1 into sky130_fd_sc_ls__buf_1.ext:
Extracting sky130_fd_sc_ls__conb_1 into sky130_fd_sc_ls__conb_1.ext:
Extracting sky130_fd_sc_ls__fill_1 into sky130_fd_sc_ls__fill_1.ext:
Extracting sky130_fd_sc_ls__fill_diode_2 into sky130_fd_sc_ls__fill_diode_2.ext:
Extracting sky130_fd_sc_ls__tapvpwrvgnd_1 into sky130_fd_sc_ls__tapvpwrvgnd_1.ext:
Extracting sky130_fd_sc_ls__decap_8 into sky130_fd_sc_ls__decap_8.ext:
Extracting sky130_fd_sc_ls__clkbuf_1 into sky130_fd_sc_ls__clkbuf_1.ext:
Extracting sky130_fd_sc_ls__decap_4 into sky130_fd_sc_ls__decap_4.ext:
Extracting user_proj_example into user_proj_example.ext:
user_proj_example: 5 fatal errors
Total of 5 errors (check feedback entries).
exttospice finished.
Using technology "sky130A", version 1.0.156-0-g7e29496
[ERROR]: There are illegal overlaps (e.g., routes over obstructions) in your design.
[ERROR]: See /project/openlane/user_proj_example/runs/user_proj_example/logs/magic/37-magic_ext2spice.feedback.txt for more.
[INFO]: Calculating Runtime From the Start...
[INFO]: Flow failed for user_proj_example/15-06_07-02 in 0h10m12s
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: user_proj_example
Run Directory: /project/openlane/user_proj_example/runs/user_proj_example
Source not found.
----------------------------------------
LVS Summary:
Source: /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs_parsed.gds.log
Source not found.
----------------------------------------
Antenna Summary:
No antenna report found.
[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv
[ERROR]: Flow Failed.
while executing
"quit_on_illegal_overlaps -log [index_file $::env(magic_log_file_tag)_ext2$extract_type.feedback.txt 0]"
(procedure "run_magic_spice_export" line 63)
invoked from within
"run_magic_spice_export"
(procedure "run_non_interactive_mode" line 38)
invoked from within
"run_non_interactive_mode {*}$argv"
invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
puts_info "Running interactively"
if { [info exists arg_values(-file)..."
(file "/openLANE_flow/flow.tcl" line 223)
make[1]: *** [Makefile:43: user_proj_example] Error 1
make[1]: Verzeichnis „/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/openlane“ wird verlassen
make: *** [Makefile:71: user_proj_example] Error 2
Deployment done.
philipp@philippina:/media/philipp/Daten/skywater/caravel_stdcelllib_stdcells_project/scripts$