[INFO]:
___ ____ ___ ____ _ ____ ____ ___
/ \ | \ / _]| \ | | / || \ / _]
| || o ) [_ | _ || | | o || _ | / [_
| O || _/ _]| | || |___ | || | || _]
| || | | [_ | | || || _ || | || [_
\___/ |__| |_____||__|__||_____||__|__||__|__||_____|
[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl
[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A
[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl
[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example
[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX8.lef /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef /project/openlane/user_proj_example/../../cells/lef/XOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX4.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/HAX1.lef /project/openlane/user_proj_example/../../cells/lef/LATCH.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/NOR3X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X2.lef /project/openlane/user_proj_example/../../cells/lef/TBUFX2.lef /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef /project/openlane/user_proj_example/../../cells/lef/CLKBUF1.lef /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/TBUFX1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef
[INFO]: Trimming Liberty...
[INFO]: Running Synthesis...
Reading /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib as a blackbox
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
1. Executing Liberty frontend.
Imported 428 cell types from liberty file.
2. Executing Liberty frontend.
Imported 24 cell types from liberty file.
3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation.
Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:9.1-16.10.
Generating RTLIL representation for module `\AND2X1'.
Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:18.1-25.10.
Generating RTLIL representation for module `\AND2X2'.
Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:27.1-35.10.
Generating RTLIL representation for module `\OR2X1'.
Replacing existing blackbox module `\OR2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:37.1-45.10.
Generating RTLIL representation for module `\OR2X2'.
Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:47.1-55.10.
Generating RTLIL representation for module `\NOR2X1'.
Generating RTLIL representation for module `\NOR2X2'.
Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:67.1-73.10.
Generating RTLIL representation for module `\INV'.
Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:75.1-81.10.
Generating RTLIL representation for module `\INVX1'.
Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:82.1-88.10.
Generating RTLIL representation for module `\INVX2'.
Generating RTLIL representation for module `\INVX3'.
Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:96.1-102.10.
Generating RTLIL representation for module `\INVX4'.
Generating RTLIL representation for module `\BUFX1'.
Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:111.1-117.10.
Generating RTLIL representation for module `\BUFX2'.
Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:119.1-128.10.
Generating RTLIL representation for module `\AOI21X1'.
Successfully finished Verilog frontend.
Successfully finished Verilog frontend.
/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:47: Warning: Identifier `\vccd1' is implicitly declared.
/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:48: Warning: Identifier `\vssd1' is implicitly declared.
Successfully finished Verilog frontend.
Successfully finished Verilog frontend.
Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.
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Warning: Wire user_proj_example.\io_oeb [7] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [6] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [5] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [4] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [3] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [2] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [1] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [0] is used but has no driver.
found and reported 226 problems.
9.7. Executing OPT pass (performing simple optimizations).
9.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.7.6. Executing OPT_DFF pass (perform DFF optimizations).
9.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.7.9. Finished OPT passes. (There is nothing left to do.)
9.8. Executing FSM pass (extract and optimize FSM).
9.8.1. Executing FSM_DETECT pass (finding FSMs in design).
9.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
9.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
9.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
9.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
9.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
9.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
9.9. Executing OPT pass (performing simple optimizations).
9.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.9.6. Executing OPT_DFF pass (perform DFF optimizations).
9.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.9.9. Finished OPT passes. (There is nothing left to do.)
9.10. Executing WREDUCE pass (reducing word size of cells).
9.11. Executing PEEPOPT pass (run peephole optimizers).
9.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module user_proj_example:
created 0 $alu and 0 $macc cells.
9.14. Executing SHARE pass (SAT-based resource sharing).
9.15. Executing OPT pass (performing simple optimizations).
9.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.15.6. Executing OPT_DFF pass (perform DFF optimizations).
9.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.15.9. Finished OPT passes. (There is nothing left to do.)
9.16. Executing MEMORY pass.
9.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
9.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
9.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
9.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
9.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.18. Executing OPT pass (performing simple optimizations).
9.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.18.3. Executing OPT_DFF pass (perform DFF optimizations).
9.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.18.5. Finished fast OPT passes.
9.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
9.20. Executing OPT pass (performing simple optimizations).
9.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
9.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
9.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.20.6. Executing OPT_SHARE pass.
9.20.7. Executing OPT_DFF pass (perform DFF optimizations).
9.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.20.10. Finished OPT passes. (There is nothing left to do.)
9.21. Executing TECHMAP pass (map to technology primitives).
9.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
9.22.5. Finished fast OPT passes.
9.23. Executing ABC pass (technology mapping using ABC).
9.23.1. Extracting gate netlist of module `\user_proj_example' to `/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
9.24. Executing OPT pass (performing simple optimizations).
9.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
9.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
9.24.3. Executing OPT_DFF pass (perform DFF optimizations).
9.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
9.24.5. Finished fast OPT passes.
9.25. Executing HIERARCHY pass (managing design hierarchy).
9.25.1. Analyzing design hierarchy..
Top module: \user_proj_example
9.25.2. Analyzing design hierarchy..
Top module: \user_proj_example
Removed 0 unused modules.
9.26. Printing statistics.
=== user_proj_example ===
Number of wires: 18
Number of wire bits: 606
Number of public wires: 18
Number of public wire bits: 606
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 11
AND2X1 1
AND2X2 1
AOI21X1 1
BUFX2 1
INV 1
INVX1 1
INVX2 1
INVX4 1
NOR2X1 1
OR2X1 1
OR2X2 1
9.27. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.
10. Executing SHARE pass (SAT-based resource sharing).
11. Executing OPT pass (performing simple optimizations).
11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
11.6. Executing OPT_DFF pass (perform DFF optimizations).
11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
11.9. Finished OPT passes. (There is nothing left to do.)
12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
13. Printing statistics.
=== user_proj_example ===
Number of wires: 18
Number of wire bits: 606
Number of public wires: 18
Number of public wire bits: 606
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 11
AND2X1 1
AND2X2 1
AOI21X1 1
BUFX2 1
INV 1
INVX1 1
INVX2 1
INVX4 1
NOR2X1 1
OR2X1 1
OR2X2 1
14. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
final dff cell mappings:
unmapped dff cell: $_DFF_N_
\sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
unmapped dff cell: $_DFF_NN0_
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
\sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
\sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
unmapped dff cell: $_DFFSR_PNN_
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
14.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\user_proj_example':
15. Printing statistics.
[INFO]: ABC: WireLoad : S_2
=== user_proj_example ===
Number of wires: 18
Number of wire bits: 606
Number of public wires: 18
Number of public wire bits: 606
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 11
AND2X1 1
AND2X2 1
AOI21X1 1
BUFX2 1
INV 1
INVX1 1
INVX2 1
INVX4 1
NOR2X1 1
OR2X1 1
OR2X2 1
16. Executing ABC pass (technology mapping using ABC).
16.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-5ylwHI/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
17. Executing SETUNDEF pass (replace undef values with defined constants).
18. Executing HILOMAP pass (mapping to constant drivers).
19. Executing SPLITNETS pass (splitting up multi-bit signals).
20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 0 unused cells and 226 unused wires.
21. Executing INSBUF pass (insert buffer cells for connected wires).
22. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.
23. Printing statistics.
=== user_proj_example ===
Number of wires: 18
Number of wire bits: 606
Number of public wires: 18
Number of public wire bits: 606
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 237
AND2X1 1
AND2X2 1
AOI21X1 1
BUFX2 1
INV 1
INVX1 1
INVX2 1
INVX4 1
NOR2X1 1
OR2X1 1
OR2X2 1
sky130_fd_sc_hd__conb_1 226
Area for cell type \AND2X1 is unknown!
Area for cell type \AND2X2 is unknown!
Area for cell type \AOI21X1 is unknown!
Area for cell type \BUFX2 is unknown!
Area for cell type \INV is unknown!
Area for cell type \INVX1 is unknown!
Area for cell type \INVX2 is unknown!
Area for cell type \INVX4 is unknown!
Area for cell type \NOR2X1 is unknown!
Area for cell type \OR2X1 is unknown!
Area for cell type \OR2X2 is unknown!
Chip area for module '\user_proj_example': 848.313600
24. Executing Verilog backend.
Dumping module `\user_proj_example'.
Warnings: 228 unique messages, 228 total
End of script. Logfile hash: cc041fd0b5, CPU: user 1.95s system 0.08s, MEM: 44.25 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 32% 4x read_liberty (0 sec), 31% 4x stat (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3
This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details.
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 700 module AND2X1 not found. Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 707 module AND2X2 not found. Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 714 module AOI21X1 not found. Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 722 module BUFX2 not found. Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 728 module INV not found. Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 734 module INVX1 not found. Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 740 module INVX2 not found. Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 746 module INVX4 not found. Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 752 module NOR2X1 not found. Creating black box for NOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 759 module OR2X1 not found. Creating black box for OR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 766 module OR2X2 not found. Creating black box for OR2X2.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
Warning: base.sdc, 1 port '0' not found.
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 0.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 0.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
Warning: base.sdc, 8 port '0' not found.
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 11 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 464 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell
Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell
Warning: LEF master AND2X1 has no liberty cell.
Warning: LEF master AND2X2 has no liberty cell.
Warning: LEF master AOI21X1 has no liberty cell.
Warning: LEF master BUFX2 has no liberty cell.
Warning: LEF master INV has no liberty cell.
Warning: LEF master INVX1 has no liberty cell.
Warning: LEF master INVX2 has no liberty cell.
Warning: LEF master INVX4 has no liberty cell.
Warning: LEF master NOR2X1 has no liberty cell.
Warning: LEF master OR2X1 has no liberty cell.
Warning: LEF master OR2X2 has no liberty cell.
Info: Added 212 rows of 1280 sites.
[INFO]: Core area width: 588.96
[INFO]: Core area height: 578.24
[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: Created 11 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 464 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 237 components and 955 component-terminals.
Notice 0: Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
Top-level design name: user_proj_example
Block boundaries: 0 0 600000 600000
Writing /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
[INFO]: Manual Macro Placement...
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: Created 11 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 464 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 237 components and 955 component-terminals.
Notice 0: Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
Placing the following macros:
{'AND2X1': ['50000', '10000', 'N'], 'AND2X2': ['50000', '20000', 'N'], 'AOI21X1': ['50000', '30000', 'N'], 'BUFX2': ['50000', '40000', 'N'], 'INV': ['50000', '50000', 'N'], 'INVX1': ['50000', '60000', 'N'], 'INVX2': ['50000', '70000', 'N'], 'INVX4': ['50000', '80000', 'N'], 'NOR2X1': ['50000', '90000', 'N'], 'OR2X1': ['50000', '100000', 'N'], 'OR2X2': ['50000', '110000', 'N']}
Design name: user_proj_example
Placing AND2X1
Placing AND2X2
Placing AOI21X1
Placing BUFX2
Placing INV
Placing INVX1
Placing INVX2
Placing INVX4
Placing NOR2X1
Placing OR2X1
Placing OR2X2
Successfully placed 11 instances
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def
[INFO]: Running Tap/Decap Insertion...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 11 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 464 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 237 components and 955 component-terminals.
Notice 0: Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 0
[INFO] #Original rows: 212
[INFO] #Cut rows: 0
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 424
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 4387
Running tapcell... Done!
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def to /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO]: Running Placement...
[WARNING]: Performing Random Global Placement...
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 5048 components and 10577 component-terminals.
Notice 0: Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
Design name: user_proj_example
Core Area Boundaries: 5520 10880 594320 587520
Number of instances 5048
Placed 226 instances
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
[INFO]: Running OpenPhySyn Timing Optimization...
[INFO]: Trimming Liberty...
[OpenPhySyn] [2020-11-29 03:11:15.624] [info] Loaded 6 transforms.
[OpenPhySyn] [2020-11-29 03:11:18.327] [info] OpenPhySyn: 1.8.1
Warning: /project/openlane/user_proj_example/runs/user_proj_example/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 11 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 464 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 5048 components and 10577 component-terminals.
Notice 0: Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
Warning: base.sdc, 1 port '0' not found.
[INFO]: Setting output delay to: 0.0
[INFO]: Setting input delay to: 0.0
Warning: base.sdc, 8 port '0' not found.
[INFO]: Setting load to: 0.01765
=============== Initial Reports =============
No paths found.
Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Initial area: 79284 um2
OpenPhySyn timing repair:
[OpenPhySyn] [2020-11-29 03:12:26.007] [info] Invoking repair_timing transform
[OpenPhySyn] [2020-11-29 03:12:26.030] [info] Buffer library: sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_1
[OpenPhySyn] [2020-11-29 03:12:26.030] [info] Inverter library: None
[OpenPhySyn] [2020-11-29 03:12:26.030] [info] Buffering: enabled
[OpenPhySyn] [2020-11-29 03:12:26.030] [info] Driver sizing: enabled
[OpenPhySyn] [2020-11-29 03:12:26.030] [info] Pin-swapping: enabled
[OpenPhySyn] [2020-11-29 03:12:26.030] [info] Mode: Timing-Driven
[OpenPhySyn] [2020-11-29 03:12:26.030] [info] Iteration 1
[OpenPhySyn] [2020-11-29 03:12:26.147] [info] No more violations or cannot find more optimal buffer
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Runtime: 0s
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Buffers: 0
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Resize up: 0
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Resize down: 0
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Pin Swap: 0
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Buffered nets: 0
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Fanout violations: 0
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Transition violations: 0
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Capacitance violations: 0
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Slack gain: 0.0
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Initial area: 7928
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] New area: 7928
[OpenPhySyn] [2020-11-29 03:12:26.148] [info] Finished repair_timing transform (0)
Added/updated 0 cells
=============== Final Reports =============
No paths found.
Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Final area: 79284 um2
Export optimized design
[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 11 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 464 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 5048 components and 10577 component-terminals.
Notice 0: Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3
This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details.
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 34 module AND2X1 not found. Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 39 module AND2X2 not found. Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 44 module AOI21X1 not found. Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 50 module BUFX2 not found. Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 54 module INV not found. Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 58 module INVX1 not found. Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 62 module INVX2 not found. Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 66 module INVX4 not found. Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 70 module NOR2X1 not found. Creating black box for NOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 75 module OR2X1 not found. Creating black box for OR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 80 module OR2X2 not found. Creating black box for OR2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 735 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for PHY_424.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
Warning: base.sdc, 1 port '0' not found.
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 0.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 0.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
Warning: base.sdc, 8 port '0' not found.
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Running Detailed Placement...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: Created 11 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 464 library cells
Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
Notice 0: Design: user_proj_example
Notice 0: Created 604 pins.
Notice 0: Created 5048 components and 10577 component-terminals.
Notice 0: Created 606 nets and 277 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
Warning: could not find power special net
Design Stats
--------------------------------
total instances 5048
multi row instances 0
fixed instances 4822
nets 606
design area 339525.6 u^2
fixed area 7080.5 u^2
movable area 848.3 u^2
utilization 0 %
utilization padded 0 %
rows 212
row height 2.7 u
Placement Analysis
--------------------------------
total displacement 371.0 u
average displacement 0.1 u
max displacement 4.1 u
original HPWL 130256.7 u
legalized HPWL 130092.4 u
delta HPWL -0 %
Warning: Site check failed (11).
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_opendp.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/user_proj_example/logs/placement/opendp.log"
[ERROR]: Last 10 lines:
child process exited abnormally
[ERROR]: Please check openroad log file
[ERROR]: Dumping to /project/openlane/user_proj_example/runs/user_proj_example/error.log