Submodule: user_proj_example

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[INFO]: ___ ____ ___ ____ _ ____ ____ ___ / \ | \ / _]| \ | | / || \ / _] | || o ) [_ | _ || | | o || _ | / [_ | O || _/ _]| | || |___ | || | || _] | || | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____|

[INFO]: Version: rc4

[INFO]: Running non-interactively

[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl

[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl

[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A

[INFO]: PDK: sky130A

[INFO]: Standard Cell Library: sky130_fd_sc_hd

[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl

[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.

[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example

[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example

[INFO]: Preparing LEF Files

mergeLef.py : Merging LEFs sky130_fd_sc_hd.lef: SITEs matched found: 0 sky130_fd_sc_hd.lef: MACROs matched found: 437 mergeLef.py : Merging LEFs complete mergeLef.py : Merging LEFs INVX4.lef: SITEs matched found: 0 INVX4.lef: MACROs matched found: 1 NOR2X1.lef: SITEs matched found: 0 NOR2X1.lef: MACROs matched found: 1 AOI21X1.lef: SITEs matched found: 0 AOI21X1.lef: MACROs matched found: 1 BUFX2.lef: SITEs matched found: 0 BUFX2.lef: MACROs matched found: 1 OR2X1.lef: SITEs matched found: 0 OR2X1.lef: MACROs matched found: 1 INVX2.lef: SITEs matched found: 0 INVX2.lef: MACROs matched found: 1 AND2X2.lef: SITEs matched found: 0 AND2X2.lef: MACROs matched found: 1 OR2X2.lef: SITEs matched found: 0 OR2X2.lef: MACROs matched found: 1 AND2X1.lef: SITEs matched found: 0 AND2X1.lef: MACROs matched found: 1 INVX1.lef: SITEs matched found: 0 INVX1.lef: MACROs matched found: 1 INV.lef: SITEs matched found: 0 INV.lef: MACROs matched found: 1 mergeLef.py : Merging LEFs complete

[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X2.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef

padLefMacro.py : Padding technology lef file Derived SITE width (microns): 0.46 Derived SITE height (microns): 5.44 Right cell padding (microns): 3.68 Left cell padding (microns): 0.0 Top cell padding (microns): 0.0 Bottom cell padding (microns): 0.0 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_4 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvgnd2_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_12 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_3 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_6 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_2 Skipping LEF padding for MACRO sky130_fd_sc_hd__tapvpwrvgnd_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__decap_8 Skipping LEF padding for MACRO sky130_fd_sc_hd__tap_1 Skipping LEF padding for MACRO sky130_fd_sc_hd__fill_2

padLefMacro.py : Finished

[INFO]: Trimming Liberty...

[INFO]: Preparation complete

[INFO]: Running Synthesis...

/----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. 1. Executing Liberty frontend. Imported 428 cell types from liberty file. 2. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v Parsing Verilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation. Generating RTLIL representation for module `\AND2X1'. Generating RTLIL representation for module `\AND2X2'. Generating RTLIL representation for module `\OR2X1'. Generating RTLIL representation for module `\OR2X2'. Generating RTLIL representation for module `\NOR2X1'. Generating RTLIL representation for module `\NOR2X2'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\INVX1'. Generating RTLIL representation for module `\INVX2'. Generating RTLIL representation for module `\INVX3'. Generating RTLIL representation for module `\INVX4'. Generating RTLIL representation for module `\BUFX1'. Generating RTLIL representation for module `\BUFX2'. Generating RTLIL representation for module `\AOI21X1'.

Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/defines.v Parsing Verilog input from `/project/openlane/user_proj_example/../../verilog/rtl/defines.v' to AST representation.

Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v Parsing Verilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation. Generating RTLIL representation for module `\user_proj_example'.

Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v Parsing Verilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v' to AST representation. Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:9.1-16.10. Generating RTLIL representation for module `\AND2X1'. Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:18.1-25.10. Generating RTLIL representation for module `\AND2X2'. Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:27.1-35.10. Generating RTLIL representation for module `\OR2X1'. Replacing existing blackbox module `\OR2X2' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:37.1-45.10. Generating RTLIL representation for module `\OR2X2'. Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:47.1-55.10. Generating RTLIL representation for module `\NOR2X1'. Replacing existing blackbox module `\NOR2X2' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:57.1-65.10. Generating RTLIL representation for module `\NOR2X2'. Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:67.1-73.10. Generating RTLIL representation for module `\INV'. Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:75.1-81.10. Generating RTLIL representation for module `\INVX1'. Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:82.1-88.10. Generating RTLIL representation for module `\INVX2'. Replacing existing blackbox module `\INVX3' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:89.1-95.10. Generating RTLIL representation for module `\INVX3'. Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:96.1-102.10. Generating RTLIL representation for module `\INVX4'. Replacing existing blackbox module `\BUFX1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:104.1-110.10. Generating RTLIL representation for module `\BUFX1'. Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:111.1-117.10. Generating RTLIL representation for module `\BUFX2'. Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog/rtl/user_proj_cells.v:119.1-128.10. Generating RTLIL representation for module `\AOI21X1'.

Successfully finished Verilog frontend.

6. Executing HIERARCHY pass (managing design hierarchy). 6.1. Analyzing design hierarchy.. Top module: \user_proj_example 6.2. Analyzing design hierarchy.. Top module: \user_proj_example Removed 0 unused modules. 7. Executing SYNTH pass. 7.1. Executing HIERARCHY pass (managing design hierarchy). 7.1.1. Analyzing design hierarchy.. Top module: \user_proj_example 7.1.2. Analyzing design hierarchy.. Top module: \user_proj_example Removed 0 unused modules. 7.2. Executing PROC pass (convert processes to netlists). 7.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 7.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 7.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 7.2.4. Executing PROC_INIT pass (extract init attributes). 7.2.5. Executing PROC_ARST pass (detect async resets in processes). 7.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). 7.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). 7.2.8. Executing PROC_DFF pass (convert process syncs to FFs). 7.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 7.3. Executing FLATTEN pass (flatten design). 7.4. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 7.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 7.6. Executing CHECK pass (checking for obvious problems). checking module user_proj_example..

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found and reported 226 problems. 7.7. Executing OPT pass (performing simple optimizations). 7.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 7.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \user_proj_example.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \user_proj_example. Performed a total of 0 changes. 7.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.7.6. Executing OPT_DFF pass (perform DFF optimizations). 7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 7.7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example.

7.7.9. Finished OPT passes. (There is nothing left to do.)

7.8. Executing FSM pass (extract and optimize FSM). 7.8.1. Executing FSM_DETECT pass (finding FSMs in design). 7.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). 7.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). 7.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 7.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). 7.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 7.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 7.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 7.9. Executing OPT pass (performing simple optimizations). 7.9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 7.9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \user_proj_example.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 7.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \user_proj_example. Performed a total of 0 changes. 7.9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.9.6. Executing OPT_DFF pass (perform DFF optimizations). 7.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 7.9.8. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example.

7.9.9. Finished OPT passes. (There is nothing left to do.)

7.10. Executing WREDUCE pass (reducing word size of cells). 7.11. Executing PEEPOPT pass (run peephole optimizers). 7.12. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 7.13. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module user_proj_example: created 0 $alu and 0 $macc cells. 7.14. Executing SHARE pass (SAT-based resource sharing). 7.15. Executing OPT pass (performing simple optimizations). 7.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 7.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \user_proj_example.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 7.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \user_proj_example. Performed a total of 0 changes. 7.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.15.6. Executing OPT_DFF pass (perform DFF optimizations). 7.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 7.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example.

7.15.9. Finished OPT passes. (There is nothing left to do.)

7.16. Executing MEMORY pass. 7.16.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 7.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 7.16.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 7.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 7.16.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 7.16.6. Executing MEMORY_COLLECT pass (generating $mem cells). 7.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 7.18. Executing OPT pass (performing simple optimizations). 7.18.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 7.18.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.18.3. Executing OPT_DFF pass (perform DFF optimizations). 7.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example..

7.18.5. Finished fast OPT passes.

7.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 7.20. Executing OPT pass (performing simple optimizations). 7.20.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 7.20.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \user_proj_example.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 7.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \user_proj_example. Performed a total of 0 changes. 7.20.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.20.6. Executing OPT_SHARE pass. 7.20.7. Executing OPT_DFF pass (perform DFF optimizations). 7.20.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 7.20.9. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example.

7.20.10. Finished OPT passes. (There is nothing left to do.)

7.21. Executing TECHMAP pass (map to technology primitives). 7.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'.

Successfully finished Verilog frontend.

7.21.2. Continuing TECHMAP pass. No more expansions possible. 7.22. Executing OPT pass (performing simple optimizations). 7.22.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 7.22.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.22.3. Executing OPT_DFF pass (perform DFF optimizations). 7.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example..

7.22.5. Finished fast OPT passes.

7.23. Executing ABC pass (technology mapping using ABC). 7.23.1. Extracting gate netlist of module `\user_proj_example' to `/input.blif'.. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 7.24. Executing OPT pass (performing simple optimizations). 7.24.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 7.24.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 7.24.3. Executing OPT_DFF pass (perform DFF optimizations). 7.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example..

7.24.5. Finished fast OPT passes.

7.25. Executing HIERARCHY pass (managing design hierarchy). 7.25.1. Analyzing design hierarchy.. Top module: \user_proj_example 7.25.2. Analyzing design hierarchy.. Top module: \user_proj_example Removed 0 unused modules. 7.26. Printing statistics. === user_proj_example === Number of wires: 24 Number of wire bits: 612 Number of public wires: 24 Number of public wire bits: 612 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 11 AND2X1 1 AND2X2 1 AOI21X1 1 BUFX2 1 INV 1 INVX1 1 INVX2 1 INVX4 1 NOR2X1 1 OR2X1 1 OR2X2 1 7.27. Executing CHECK pass (checking for obvious problems). checking module user_proj_example.. found and reported 0 problems. 8. Executing SHARE pass (SAT-based resource sharing). 9. Executing OPT pass (performing simple optimizations). 9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \user_proj_example.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \user_proj_example. Performed a total of 0 changes. 9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 9.6. Executing OPT_DFF pass (perform DFF optimizations). 9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 9.8. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example.

9.9. Finished OPT passes. (There is nothing left to do.)

10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 11. Printing statistics. === user_proj_example === Number of wires: 24 Number of wire bits: 612 Number of public wires: 24 Number of public wire bits: 612 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 11 AND2X1 1 AND2X2 1 AOI21X1 1 BUFX2 1 INV 1 INVX1 1 INVX2 1 INVX4 1 NOR2X1 1 OR2X1 1 OR2X2 1 12. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_. cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_. cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_. cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_. final dff cell mappings: unmapped dff cell: $_DFF_N_ \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q)); unmapped dff cell: $_DFF_NN0_ unmapped dff cell: $_DFF_NN1_ unmapped dff cell: $_DFF_NP0_ unmapped dff cell: $_DFF_NP1_ \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R)); \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R)); unmapped dff cell: $_DFF_PP0_ unmapped dff cell: $_DFF_PP1_ \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); unmapped dff cell: $_DFFSR_NNP_ unmapped dff cell: $_DFFSR_NPN_ unmapped dff cell: $_DFFSR_NPP_ unmapped dff cell: $_DFFSR_PNN_ unmapped dff cell: $_DFFSR_PNP_ unmapped dff cell: $_DFFSR_PPN_ unmapped dff cell: $_DFFSR_PPP_ 12.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Mapping DFF cells in module `\user_proj_example': 13. Printing statistics. [INFO]: ABC: WireLoad : S_2 === user_proj_example === Number of wires: 24 Number of wire bits: 612 Number of public wires: 24 Number of public wire bits: 612 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 11 AND2X1 1 AND2X2 1 AOI21X1 1 BUFX2 1 INV 1 INVX1 1 INVX2 1 INVX4 1 NOR2X1 1 OR2X1 1 OR2X2 1 14. Executing ABC pass (technology mapping using ABC). 14.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-T61ekw/input.blif'.. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 15. Executing SETUNDEF pass (replace undef values with defined constants). 16. Executing HILOMAP pass (mapping to constant drivers). 17. Executing SPLITNETS pass (splitting up multi-bit signals). 18. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. Removed 0 unused cells and 226 unused wires. 19. Executing INSBUF pass (insert buffer cells for connected wires). 20. Executing CHECK pass (checking for obvious problems). checking module user_proj_example.. found and reported 0 problems. 21. Printing statistics. === user_proj_example === Number of wires: 24 Number of wire bits: 612 Number of public wires: 24 Number of public wire bits: 612 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 237 AND2X1 1 AND2X2 1 AOI21X1 1 BUFX2 1 INV 1 INVX1 1 INVX2 1 INVX4 1 NOR2X1 1 OR2X1 1 OR2X2 1 sky130_fd_sc_hd__conb_1 226 Area for cell type \AND2X1 is unknown! Area for cell type \AND2X2 is unknown! Area for cell type \OR2X1 is unknown! Area for cell type \OR2X2 is unknown! Area for cell type \NOR2X1 is unknown! Area for cell type \INV is unknown! Area for cell type \INVX1 is unknown! Area for cell type \INVX2 is unknown! Area for cell type \INVX4 is unknown! Area for cell type \BUFX2 is unknown! Area for cell type \AOI21X1 is unknown! Chip area for module '\user_proj_example': 848.313600 22. Executing Verilog backend. Dumping module `\user_proj_example'.

Warnings: 226 unique messages, 226 total

End of script. Logfile hash: 5340fb9b7c, CPU: user 1.43s system 0.05s, MEM: 43.46 MB peak Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) Time spent: 45% 2x read_liberty (0 sec), 10% 1x proc_dff (0 sec), ...

[INFO]: Changing netlist from 0 to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v

[INFO]: Running Static Timing Analysis...

OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc. License GPLv3: GNU GPL version 3 This is free software, and you are free to change and redistribute it under certain conditions; type `show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 706 module AND2X1 not found. Creating black box for AND2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 713 module AND2X2 not found. Creating black box for AND2X2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 720 module AOI21X1 not found. Creating black box for AOI21X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 728 module BUFX2 not found. Creating black box for BUFX2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 734 module INV not found. Creating black box for INV.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 740 module INVX1 not found. Creating black box for INVX1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 746 module INVX2 not found. Creating black box for INVX2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 752 module INVX4 not found. Creating black box for INVX4.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 758 module NOR2X1 not found. Creating black box for NOR2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 765 module OR2X1 not found. Creating black box for OR2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 772 module OR2X2 not found. Creating black box for OR2X2.

create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)

Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable

tns 0.00 wns 0.00

[INFO]: Synthesis was successful

[INFO]: Running Floorplanning...

[INFO]: Running Initial Floorplanning...

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.

Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef

Notice 0: warning: macro INVX4 references unkown site CORE

Notice 0: warning: macro NOR2X1 references unkown site CORE

Notice 0: warning: macro AOI21X1 references unkown site CORE

Notice 0: warning: macro BUFX2 references unkown site CORE

Notice 0: warning: macro OR2X1 references unkown site CORE

Notice 0: warning: macro INVX2 references unkown site CORE

Notice 0: warning: macro AND2X2 references unkown site CORE

Notice 0: warning: macro OR2X2 references unkown site CORE

Notice 0: warning: macro AND2X1 references unkown site CORE

Notice 0: warning: macro INVX1 references unkown site CORE

Notice 0: warning: macro INV references unkown site CORE

Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 448 library cells

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 706 instance AND2X1 port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 706 instance AND2X1 port vdd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 713 instance AND2X2 port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 713 instance AND2X2 port vdd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 720 instance AOI21X1 port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 720 instance AOI21X1 port vdd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 728 instance BUFX2 port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 728 instance BUFX2 port vdd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 734 instance INV port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 734 instance INV port vdd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 740 instance INVX1 port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 740 instance INVX1 port vdd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 746 instance INVX2 port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 746 instance INVX2 port vdd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 752 instance INVX4 port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 752 instance INVX4 port vdd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 758 instance NOR2X1 port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 758 instance NOR2X1 port vdd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 765 instance OR2X1 port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 765 instance OR2X1 port vdd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 772 instance OR2X2 port gnd not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 772 instance OR2X2 port vdd not found.

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF master AND2X1 has no liberty cell.

Warning: LEF master AND2X2 has no liberty cell.

Warning: LEF master AOI21X1 has no liberty cell.

Warning: LEF master BUFX2 has no liberty cell.

Warning: LEF master INV has no liberty cell.

Warning: LEF master INVX1 has no liberty cell.

Warning: LEF master INVX2 has no liberty cell.

Warning: LEF master INVX4 has no liberty cell.

Warning: LEF master NOR2X1 has no liberty cell.

Warning: LEF master OR2X1 has no liberty cell.

Warning: LEF master OR2X2 has no liberty cell.

Info: Added 83 rows of 519 sites.

[INFO]: Floorplanning was successful

[INFO]: Core area width: 238.95999999999998

[INFO]: Core area height: 228.24

[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def

[INFO]: Running IO Placement...

OpenROAD 0.9.0 e582f2522b This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef

Notice 0: warning: macro INVX4 references unkown site CORE

Notice 0: warning: macro NOR2X1 references unkown site CORE

Notice 0: warning: macro AOI21X1 references unkown site CORE

Notice 0: warning: macro BUFX2 references unkown site CORE

Notice 0: warning: macro OR2X1 references unkown site CORE

Notice 0: warning: macro INVX2 references unkown site CORE

Notice 0: warning: macro AND2X2 references unkown site CORE

Notice 0: warning: macro OR2X2 references unkown site CORE

Notice 0: warning: macro AND2X1 references unkown site CORE

Notice 0: warning: macro INVX1 references unkown site CORE

Notice 0: warning: macro INV references unkown site CORE

Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 448 library cells

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef

Notice 0: Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def Notice 0: Design: user_proj_example Notice 0: Created 612 pins. Notice 0: Created 237 components and 955 component-terminals. Notice 0: Created 612 nets and 255 connections.

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def

#Macro blocks found: 0

Warning: using the default boundaries offset (5 microns)

Warning: using the default min distance between IO pins (2 tracks)

WARNING: force pin spread option has no effect when using random pin placement

> Running IO placement * Num of slots 888 * Num of I/O 612 * Num of I/O w/sink 255 * Num of I/O w/o sink 357 * Slots Per Section 200 * Slots Increase Factor 0.01 * Usage Per Section 0.8 * Usage Increase Factor 0.01 * Force Pin Spread 1

WARNING: running random pin placement

RandomMode Even > IO placement done.

[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def

[INFO]: Running Global Placement...

Notice 0: warning: macro INVX4 references unkown site CORE

Notice 0: warning: macro NOR2X1 references unkown site CORE

Notice 0: warning: macro AOI21X1 references unkown site CORE

Notice 0: warning: macro BUFX2 references unkown site CORE

Notice 0: warning: macro OR2X1 references unkown site CORE

Notice 0: warning: macro INVX2 references unkown site CORE

Notice 0: warning: macro AND2X2 references unkown site CORE

Notice 0: warning: macro OR2X2 references unkown site CORE

Notice 0: warning: macro AND2X1 references unkown site CORE

Notice 0: warning: macro INVX1 references unkown site CORE

Notice 0: warning: macro INV references unkown site CORE

Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 448 library cells

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef

Notice 0: Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def Notice 0: Design: user_proj_example Notice 0: Created 612 pins. Notice 0: Created 237 components and 955 component-terminals. Notice 0: Created 612 nets and 255 connections.

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def

[INFO] DBU = 1000 [INFO] SiteSize = (460, 2720) [INFO] CoreAreaLxLy = (5520, 10880) [INFO] CoreAreaUxUy = (244260, 236640) [INFO] NumInstances = 237 [INFO] NumPlaceInstances = 237 [INFO] NumFixedInstances = 0 [INFO] NumDummyInstances = 0 [INFO] NumNets = 612 [INFO] NumPins = 867 [INFO] DieAreaLxLy = (0, 0) [INFO] DieAreaUxUy = (250000, 250000) [INFO] CoreAreaLxLy = (5520, 10880) [INFO] CoreAreaUxUy = (244260, 236640) [INFO] CoreArea = 53897942400 [INFO] NonPlaceInstsArea = 0 [INFO] PlaceInstsArea = 848313600 [INFO] Util(%) = 1.573926 [INFO] StdInstsArea = 848313600 [INFO] MacroInstsArea = 0

[InitialPlace] Iter: 1 CG Error: 7.37699e-08 HPWL: 63634510

[InitialPlace] Iter: 2 CG Error: 4.84044e-08 HPWL: 107627079

[InitialPlace] Iter: 3 CG Error: 5.00031e-08 HPWL: 111376086

[InitialPlace] Iter: 4 CG Error: 1.83147e-08 HPWL: 113224409

[InitialPlace] Iter: 5 CG Error: 7.05902e-10 HPWL: 113647784

[INFO] FillerInit: NumGCells = 2164 [INFO] FillerInit: NumGNets = 612 [INFO] FillerInit: NumGPins = 867 [INFO] TargetDensity = 0.150000 [INFO] AveragePlaceInstArea = 3579382 [INFO] IdealBinArea = 23862546 [INFO] IdealBinCnt = 2258 [INFO] TotalBinArea = 53897942400 [INFO] BinCnt = (64, 64) [INFO] BinSize = (3731, 3528) [INFO] NumBins = 4096

[ERROR] RePlAce diverged at initial iteration.

Please tune the parameters again (REPL-5)

Error: RePlAce terminated with errors.

[ERROR]: Failure in global placement

while executing "global_placement_or" (procedure "run_floorplan" line 19) invoked from within "run_floorplan" (procedure "run_non_interactive_mode" line 12) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { puts_info "Running interactively" if { [info exists arg_values(-file)..." (file "/openLANE_flow/flow.tcl" line 164) make: *** [Makefile:26: user_proj_example] Fehler 1

Reports:

Submodule: user_proj_example