Reports:

Submodule: user_proj_example

user_proj_example/runs/user_proj_example/logs/synthesis/yosys.log

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Liberty frontend.
Imported 25 cell types from liberty file.

3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation.
Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:10.1-17.10.
Generating RTLIL representation for module `\AND2X1'.
Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:19.1-26.10.
Generating RTLIL representation for module `\AND2X2'.
Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:28.1-36.10.
Generating RTLIL representation for module `\AOI21X1'.
Replacing existing blackbox module `\AOI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:38.1-47.10.
Generating RTLIL representation for module `\AOI22X1'.
Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:49.1-55.10.
Generating RTLIL representation for module `\BUFX2'.
Replacing existing blackbox module `\BUFX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:57.1-63.10.
Generating RTLIL representation for module `\BUFX4'.
Replacing existing blackbox module `\CLKBUF1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:65.1-71.10.
Generating RTLIL representation for module `\CLKBUF1'.
Replacing existing blackbox module `\HAX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:73.1-81.10.
Generating RTLIL representation for module `\HAX1'.
Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:83.1-89.10.
Generating RTLIL representation for module `\INV'.
Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:91.1-97.10.
Generating RTLIL representation for module `\INVX1'.
Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:99.1-105.10.
Generating RTLIL representation for module `\INVX2'.
Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:107.1-113.10.
Generating RTLIL representation for module `\INVX4'.
Replacing existing blackbox module `\INVX8' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:115.1-121.10.
Generating RTLIL representation for module `\INVX8'.
Replacing existing blackbox module `\LATCH' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:123.1-130.10.
Generating RTLIL representation for module `\LATCH'.
Replacing existing blackbox module `\MUX2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:132.1-140.10.
Generating RTLIL representation for module `\MUX2X1'.
Replacing existing blackbox module `\NAND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:142.1-149.10.
Generating RTLIL representation for module `\NAND2X1'.
Replacing existing blackbox module `\NAND3X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:151.1-159.10.
Generating RTLIL representation for module `\NAND3X1'.
Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:161.1-168.10.
Generating RTLIL representation for module `\NOR2X1'.
Replacing existing blackbox module `\NOR3X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:170.1-178.10.
Generating RTLIL representation for module `\NOR3X1'.
Replacing existing blackbox module `\OAI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:180.1-188.10.
Generating RTLIL representation for module `\OAI21X1'.
Replacing existing blackbox module `\OAI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:190.1-199.10.
Generating RTLIL representation for module `\OAI22X1'.
Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:201.1-208.10.
Generating RTLIL representation for module `\OR2X1'.
Replacing existing blackbox module `\OR2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:210.1-217.10.
Generating RTLIL representation for module `\OR2X2'.
Replacing existing blackbox module `\XNOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:219.1-226.10.
Generating RTLIL representation for module `\XNOR2X1'.
Replacing existing blackbox module `\XOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:228.1-235.10.
Generating RTLIL representation for module `\XOR2X1'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
Successfully finished Verilog frontend.

6. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/hierarchy.dot'.
Dumping module user_proj_example to page 1.

7. Executing HIERARCHY pass (managing design hierarchy).

7.1. Analyzing design hierarchy..
Top module:  \user_proj_example

7.2. Analyzing design hierarchy..
Top module:  \user_proj_example
Removed 0 unused modules.

8. Executing TRIBUF pass.

9. Executing SYNTH pass.

9.1. Executing HIERARCHY pass (managing design hierarchy).

9.1.1. Analyzing design hierarchy..
Top module:  \user_proj_example

9.1.2. Analyzing design hierarchy..
Top module:  \user_proj_example
Removed 0 unused modules.

9.2. Executing PROC pass (convert processes to netlists).

9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

9.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

9.2.4. Executing PROC_INIT pass (extract init attributes).

9.2.5. Executing PROC_ARST pass (detect async resets in processes).

9.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).

9.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

9.2.8. Executing PROC_DFF pass (convert process syncs to FFs).

9.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

9.3. Executing FLATTEN pass (flatten design).

9.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.6. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [29] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [28] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [27] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [26] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [25] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [24] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [23] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [22] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [21] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [20] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [19] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [18] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [17] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [16] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [15] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [14] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [13] is used but has no driver.
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Warning: Wire user_proj_example.\wbs_dat_o [0] is used but has no driver.
Warning: Wire user_proj_example.\wbs_ack_o is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [126] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [125] is used but has no driver.
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Warning: Wire user_proj_example.\la_data_out [67] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [66] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [65] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [64] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [63] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [62] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [61] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [60] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [59] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [57] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [56] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [55] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [54] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [53] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [52] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [51] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [50] is used but has no driver.
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Warning: Wire user_proj_example.\la_data_out [47] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [46] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [45] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [44] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [43] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [42] is used but has no driver.
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Warning: Wire user_proj_example.\la_data_out [36] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [34] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [33] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [31] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [30] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [28] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [27] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [25] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [24] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [23] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [22] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [18] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [15] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.
Warning: Wire user_proj_example.\io_out [36] is used but has no driver.
Warning: Wire user_proj_example.\io_out [35] is used but has no driver.
Warning: Wire user_proj_example.\io_out [33] is used but has no driver.
Warning: Wire user_proj_example.\io_out [31] is used but has no driver.
Warning: Wire user_proj_example.\io_out [29] is used but has no driver.
Warning: Wire user_proj_example.\io_out [27] is used but has no driver.
Warning: Wire user_proj_example.\io_out [25] is used but has no driver.
Warning: Wire user_proj_example.\io_out [22] is used but has no driver.
Warning: Wire user_proj_example.\io_out [21] is used but has no driver.
Warning: Wire user_proj_example.\io_out [19] is used but has no driver.
Warning: Wire user_proj_example.\io_out [17] is used but has no driver.
Warning: Wire user_proj_example.\io_out [15] is used but has no driver.
Warning: Wire user_proj_example.\io_out [13] is used but has no driver.
Warning: Wire user_proj_example.\io_out [12] is used but has no driver.
Warning: Wire user_proj_example.\io_out [11] is used but has no driver.
Warning: Wire user_proj_example.\io_out [10] is used but has no driver.
Warning: Wire user_proj_example.\io_out [8] is used but has no driver.
Warning: Wire user_proj_example.\io_out [7] is used but has no driver.
Warning: Wire user_proj_example.\io_out [6] is used but has no driver.
Warning: Wire user_proj_example.\io_out [4] is used but has no driver.
Warning: Wire user_proj_example.\io_out [3] is used but has no driver.
Warning: Wire user_proj_example.\io_out [1] is used but has no driver.
Warning: Wire user_proj_example.\io_out [0] is used but has no driver.
found and reported 173 problems.

9.7. Executing OPT pass (performing simple optimizations).

9.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

9.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

9.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.7.6. Executing OPT_DFF pass (perform DFF optimizations).

9.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.7.9. Finished OPT passes. (There is nothing left to do.)

9.8. Executing FSM pass (extract and optimize FSM).

9.8.1. Executing FSM_DETECT pass (finding FSMs in design).

9.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

9.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

9.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

9.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

9.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

9.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

9.9. Executing OPT pass (performing simple optimizations).

9.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

9.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

9.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.9.6. Executing OPT_DFF pass (perform DFF optimizations).

9.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.9.9. Finished OPT passes. (There is nothing left to do.)

9.10. Executing WREDUCE pass (reducing word size of cells).

9.11. Executing PEEPOPT pass (run peephole optimizers).

9.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module user_proj_example:
  created 0 $alu and 0 $macc cells.

9.14. Executing SHARE pass (SAT-based resource sharing).

9.15. Executing OPT pass (performing simple optimizations).

9.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

9.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

9.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.15.6. Executing OPT_DFF pass (perform DFF optimizations).

9.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.15.9. Finished OPT passes. (There is nothing left to do.)

9.16. Executing MEMORY pass.

9.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

9.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

9.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

9.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

9.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.18. Executing OPT pass (performing simple optimizations).

9.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.


9.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.18.3. Executing OPT_DFF pass (perform DFF optimizations).

9.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.18.5. Finished fast OPT passes.

9.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

9.20. Executing OPT pass (performing simple optimizations).

9.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

9.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

9.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.20.6. Executing OPT_SHARE pass.

9.20.7. Executing OPT_DFF pass (perform DFF optimizations).

9.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.20.10. Finished OPT passes. (There is nothing left to do.)

9.21. Executing TECHMAP pass (map to technology primitives).

9.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

9.21.2. Continuing TECHMAP pass.
No more expansions possible.


9.22. Executing OPT pass (performing simple optimizations).

9.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.22.3. Executing OPT_DFF pass (perform DFF optimizations).

9.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.22.5. Finished fast OPT passes.

9.23. Executing ABC pass (technology mapping using ABC).

9.23.1. Extracting gate netlist of module `\user_proj_example' to `/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

9.24. Executing OPT pass (performing simple optimizations).

9.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

9.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

9.24.3. Executing OPT_DFF pass (perform DFF optimizations).

9.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

9.24.5. Finished fast OPT passes.

9.25. Executing HIERARCHY pass (managing design hierarchy).

9.25.1. Analyzing design hierarchy..
Top module:  \user_proj_example

9.25.2. Analyzing design hierarchy..
Top module:  \user_proj_example
Removed 0 unused modules.

9.26. Printing statistics.

=== user_proj_example ===

   Number of wires:                 16
   Number of wire bits:            604
   Number of public wires:          16
   Number of public wire bits:     604
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 25
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     AOI22X1                         1
     BUFX2                           1
     BUFX4                           1
     CLKBUF1                         1
     HAX1                            1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     INVX8                           1
     LATCH                           1
     MUX2X1                          1
     NAND2X1                         1
     NAND3X1                         1
     NOR2X1                          1
     NOR3X1                          1
     OAI21X1                         1
     OAI22X1                         1
     OR2X1                           1
     OR2X2                           1
     XNOR2X1                         1
     XOR2X1                          1

9.27. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.

10. Executing SHARE pass (SAT-based resource sharing).

11. Executing OPT pass (performing simple optimizations).

11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.

11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.

11.6. Executing OPT_DFF pass (perform DFF optimizations).

11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.

11.9. Finished OPT passes. (There is nothing left to do.)

12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..

13. Printing statistics.

=== user_proj_example ===

   Number of wires:                 16
   Number of wire bits:            604
   Number of public wires:          16
   Number of public wire bits:     604
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 25
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     AOI22X1                         1
     BUFX2                           1
     BUFX4                           1
     CLKBUF1                         1
     HAX1                            1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     INVX8                           1
     LATCH                           1
     MUX2X1                          1
     NAND2X1                         1
     NAND3X1                         1
     NOR2X1                          1
     NOR3X1                          1
     OAI21X1                         1
     OAI22X1                         1
     OR2X1                           1
     OR2X2                           1
     XNOR2X1                         1
     XOR2X1                          1

14. Executing TECHMAP pass (map to technology primitives).

14.1. Executing Verilog-2005 frontend: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v
Parsing Verilog input from `/media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation.
Generating RTLIL representation for module `\$_TBUF_'.
Successfully finished Verilog frontend.

14.2. Continuing TECHMAP pass.
No more expansions possible.


15. Executing SIMPLEMAP pass (map simple cells to gate primitives).

16. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

16.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\user_proj_example':

17. Printing statistics.

=== user_proj_example ===

   Number of wires:                 16
   Number of wire bits:            604
   Number of public wires:          16
   Number of public wire bits:     604
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 25
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     AOI22X1                         1
     BUFX2                           1
     BUFX4                           1
     CLKBUF1                         1
     HAX1                            1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     INVX8                           1
     LATCH                           1
     MUX2X1                          1
     NAND2X1                         1
     NAND3X1                         1
     NOR2X1                          1
     NOR3X1                          1
     OAI21X1                         1
     OAI22X1                         1
     OR2X1                           1
     OR2X2                           1
     XNOR2X1                         1
     XOR2X1                          1

18. Executing ABC pass (technology mapping using ABC).

18.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-09T7To/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

19. Executing SETUNDEF pass (replace undef values with defined constants).

20. Executing HILOMAP pass (mapping to constant drivers).

21. Executing SPLITNETS pass (splitting up multi-bit signals).

22. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 0 unused cells and 211 unused wires.


23. Executing INSBUF pass (insert buffer cells for connected wires).

24. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
found and reported 0 problems.

25. Printing statistics.

=== user_proj_example ===

   Number of wires:                 16
   Number of wire bits:            604
   Number of public wires:          16
   Number of public wire bits:     604
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                236
     AND2X1                          1
     AND2X2                          1
     AOI21X1                         1
     AOI22X1                         1
     BUFX2                           1
     BUFX4                           1
     CLKBUF1                         1
     HAX1                            1
     INV                             1
     INVX1                           1
     INVX2                           1
     INVX4                           1
     INVX8                           1
     LATCH                           1
     MUX2X1                          1
     NAND2X1                         1
     NAND3X1                         1
     NOR2X1                          1
     NOR3X1                          1
     OAI21X1                         1
     OAI22X1                         1
     OR2X1                           1
     OR2X2                           1
     XNOR2X1                         1
     XOR2X1                          1
     sky130_fd_sc_hd__conb_1       211

   Area for cell type \AND2X1 is unknown!
   Area for cell type \AND2X2 is unknown!
   Area for cell type \AOI21X1 is unknown!
   Area for cell type \AOI22X1 is unknown!
   Area for cell type \BUFX2 is unknown!
   Area for cell type \BUFX4 is unknown!
   Area for cell type \CLKBUF1 is unknown!
   Area for cell type \HAX1 is unknown!
   Area for cell type \INV is unknown!
   Area for cell type \INVX1 is unknown!
   Area for cell type \INVX2 is unknown!
   Area for cell type \INVX4 is unknown!
   Area for cell type \INVX8 is unknown!
   Area for cell type \LATCH is unknown!
   Area for cell type \MUX2X1 is unknown!
   Area for cell type \NAND2X1 is unknown!
   Area for cell type \NAND3X1 is unknown!
   Area for cell type \NOR2X1 is unknown!
   Area for cell type \NOR3X1 is unknown!
   Area for cell type \OAI21X1 is unknown!
   Area for cell type \OAI22X1 is unknown!
   Area for cell type \OR2X1 is unknown!
   Area for cell type \OR2X2 is unknown!
   Area for cell type \XNOR2X1 is unknown!
   Area for cell type \XOR2X1 is unknown!

   Chip area for module '\user_proj_example': 792.009600

26. Executing Verilog backend.
Dumping module `\user_proj_example'.

Warnings: 173 unique messages, 173 total
End of script. Logfile hash: c056460d8c, CPU: user 2.22s system 0.20s, MEM: 44.50 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 33% 4x read_liberty (0 sec), 30% 4x stat (0 sec), ...
user_proj_example/runs/user_proj_example/logs/synthesis/opensta.log
OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 653 module AND2X1 not found.  Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 658 module AND2X2 not found.  Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 663 module AOI21X1 not found.  Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 669 module AOI22X1 not found.  Creating black box for AOI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 676 module BUFX2 not found.  Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 680 module BUFX4 not found.  Creating black box for BUFX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 684 module CLKBUF1 not found.  Creating black box for CLKBUF1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 688 module HAX1 not found.  Creating black box for HAX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 694 module INV not found.  Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 698 module INVX1 not found.  Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 702 module INVX2 not found.  Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 706 module INVX4 not found.  Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 710 module INVX8 not found.  Creating black box for INVX8.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 714 module LATCH not found.  Creating black box for LATCH.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 719 module MUX2X1 not found.  Creating black box for MUX2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 725 module NAND2X1 not found.  Creating black box for NAND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 730 module NAND3X1 not found.  Creating black box for NAND3X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 736 module NOR2X1 not found.  Creating black box for NOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 741 module NOR3X1 not found.  Creating black box for NOR3X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 747 module OAI21X1 not found.  Creating black box for OAI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 753 module OAI22X1 not found.  Creating black box for OAI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 760 module OR2X1 not found.  Creating black box for OR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 765 module OR2X2 not found.  Creating black box for OR2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 770 module XNOR2X1 not found.  Creating black box for XNOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 775 module XOR2X1 not found.  Creating black box for XOR2X1.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 0.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 0.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
user_proj_example/runs/user_proj_example/logs/floorplan/verilog2def.openroad.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Warning: LEF master AND2X1 has no liberty cell.
Warning: LEF master AND2X2 has no liberty cell.
Warning: LEF master AOI21X1 has no liberty cell.
Warning: LEF master AOI22X1 has no liberty cell.
Warning: LEF master BUFX2 has no liberty cell.
Warning: LEF master BUFX4 has no liberty cell.
Warning: LEF master CLKBUF1 has no liberty cell.
Warning: LEF master HAX1 has no liberty cell.
Warning: LEF master INV has no liberty cell.
Warning: LEF master INVX1 has no liberty cell.
Warning: LEF master INVX2 has no liberty cell.
Warning: LEF master INVX4 has no liberty cell.
Warning: LEF master INVX8 has no liberty cell.
Warning: LEF master LATCH has no liberty cell.
Warning: LEF master MUX2X1 has no liberty cell.
Warning: LEF master NAND2X1 has no liberty cell.
Warning: LEF master NAND3X1 has no liberty cell.
Warning: LEF master NOR2X1 has no liberty cell.
Warning: LEF master NOR3X1 has no liberty cell.
Warning: LEF master OAI21X1 has no liberty cell.
Warning: LEF master OAI22X1 has no liberty cell.
Warning: LEF master OR2X1 has no liberty cell.
Warning: LEF master OR2X2 has no liberty cell.
Warning: LEF master XNOR2X1 has no liberty cell.
Warning: LEF master XOR2X1 has no liberty cell.
Info: Added 102 rows of 628 sites.
user_proj_example/runs/user_proj_example/logs/floorplan/place_io_ol.log
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 236 components and 1393 component-terminals.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
Top-level design name: user_proj_example
Block boundaries: 0 0 300000 300000
Writing /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
user_proj_example/runs/user_proj_example/logs/macro_placement.log
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 236 components and 1393 component-terminals.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def
Placing the following macros:
{'AND2X1': ['40480', '13600', 'N'], 'AND2X2': ['40480', '19040', 'N'], 'AOI21X1': ['40480', '24480', 'N'], 'AOI22X1': ['40480', '29920', 'N'], 'BUFX2': ['40480', '35360', 'N'], 'BUFX4': ['40480', '40800', 'N'], 'CLKBUF1': ['40480', '46240', 'N'], 'HAX1': ['40480', '51680', 'N'], 'INV': ['40480', '57120', 'N'], 'INVX1': ['40480', '62560', 'N'], 'INVX2': ['40480', '68000', 'N'], 'INVX4': ['40480', '73440', 'N'], 'INVX8': ['40480', '78880', 'N'], 'LATCH': ['40480', '84320', 'N'], 'MUX2X1': ['40480', '89760', 'N'], 'NAND2X1': ['40480', '95200', 'N'], 'NAND3X1': ['40480', '100640', 'N'], 'NOR2X1': ['40480', '106080', 'N'], 'NOR3X1': ['40480', '111520', 'N'], 'OAI21X1': ['40480', '116960', 'N'], 'OAI22X1': ['40480', '122400', 'N'], 'OR2X1': ['40480', '127840', 'N'], 'OR2X2': ['40480', '133280', 'N'], 'XNOR2X1': ['40480', '138720', 'N'], 'XOR2X1': ['40480', '144160', 'N']}
Design name: user_proj_example
Placing AND2X1
Placing AND2X2
Placing AOI21X1
Placing AOI22X1
Placing BUFX2
Placing BUFX4
Placing CLKBUF1
Placing HAX1
Placing INV
Placing INVX1
Placing INVX2
Placing INVX4
Placing INVX8
Placing LATCH
Placing MUX2X1
Placing NAND2X1
Placing NAND3X1
Placing NOR2X1
Placing NOR3X1
Placing OAI21X1
Placing OAI22X1
Placing OR2X1
Placing OR2X2
Placing XNOR2X1
Placing XOR2X1
Successfully placed 25 instances
user_proj_example/runs/user_proj_example/logs/floorplan/tapcell.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 236 components and 1393 component-terminals.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 0
[INFO] #Original rows: 102
[INFO] #Cut rows: 0
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 204
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 1040
Running tapcell... Done!
user_proj_example/runs/user_proj_example/logs/floorplan/pdn.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
Notice 0: Design: user_proj_example
Notice 0:     Created 604 pins.
Notice 0:     Created 1480 components and 4289 component-terminals.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_proj_example
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
    Stdcell Rails
      Layer: met1 -  width: 0.480  pitch: 2.720  offset: 0.000 
    Straps
      Layer: met4 -  width: 1.600  pitch: 153.600  offset: 16.320 
    Connect: {met1 met4}
Type: macro, macro_1
    Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
    Straps
    Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
user_proj_example/runs/user_proj_example/logs/placement/replace.log
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/pdn.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 1480 components and 4289 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/pdn.def
Design name: user_proj_example
Core Area Boundaries: 5520 10880 294400 288320
Number of instances 1480
Placed 211 instances
user_proj_example/runs/user_proj_example/logs/placement/openphysyn.log
[OpenPhySyn] [2020-12-19 00:25:39.919] [info] Loaded 6 transforms.
[OpenPhySyn] [2020-12-19 00:25:42.099] [info] OpenPhySyn: 1.8.1
Warning: /project/openlane/user_proj_example/runs/user_proj_example/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 1480 components and 4289 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def
[INFO]: Setting output delay to: 0.0
[INFO]: Setting input delay to: 0.0
[INFO]: Setting load to: 0.01765
=============== Initial Reports =============
No paths found.
Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Initial area: 33057 um2
OpenPhySyn timing repair:
[OpenPhySyn] [2020-12-19 00:25:42.547] [info] Invoking repair_timing transform
[OpenPhySyn] [2020-12-19 00:25:42.565] [info] Buffer library: sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8
[OpenPhySyn] [2020-12-19 00:25:42.565] [info] Inverter library: None
[OpenPhySyn] [2020-12-19 00:25:42.565] [info] Buffering: enabled
[OpenPhySyn] [2020-12-19 00:25:42.565] [info] Driver sizing: enabled
[OpenPhySyn] [2020-12-19 00:25:42.565] [info] Pin-swapping: enabled
[OpenPhySyn] [2020-12-19 00:25:42.565] [info] Mode: Timing-Driven
[OpenPhySyn] [2020-12-19 00:25:42.565] [info] Iteration 1
[OpenPhySyn] [2020-12-19 00:25:42.737] [info] No more violations or cannot find more optimal buffer
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Runtime: 0s
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Buffers: 0
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Resize up: 0
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Resize down: 0
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Pin Swap: 0
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Buffered nets: 0
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Fanout violations: 0
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Transition violations: 0
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Capacitance violations: 0
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Slack gain: 0.0
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Initial area: 3306
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] New area: 3306
[OpenPhySyn] [2020-12-19 00:25:42.738] [info] Finished repair_timing transform (0)
Added/updated 0 cells
=============== Final Reports =============
No paths found.
Capacitance violations: 0
Transition violations: 0
wns 0.00
tns 0.00
Final area: 33057 um2
Export optimized design
user_proj_example/runs/user_proj_example/logs/synthesis/opensta_post_openphysyn.log
OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 38 module AND2X1 not found.  Creating black box for AND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 41 module AND2X2 not found.  Creating black box for AND2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 44 module AOI21X1 not found.  Creating black box for AOI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 48 module AOI22X1 not found.  Creating black box for AOI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 53 module BUFX2 not found.  Creating black box for BUFX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 55 module BUFX4 not found.  Creating black box for BUFX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 57 module CLKBUF1 not found.  Creating black box for CLKBUF1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 59 module HAX1 not found.  Creating black box for HAX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 63 module INV not found.  Creating black box for INV.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 65 module INVX1 not found.  Creating black box for INVX1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 67 module INVX2 not found.  Creating black box for INVX2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 69 module INVX4 not found.  Creating black box for INVX4.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 71 module INVX8 not found.  Creating black box for INVX8.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 73 module LATCH not found.  Creating black box for LATCH.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 76 module MUX2X1 not found.  Creating black box for MUX2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 80 module NAND2X1 not found.  Creating black box for NAND2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 83 module NAND3X1 not found.  Creating black box for NAND3X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 87 module NOR2X1 not found.  Creating black box for NOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 90 module NOR3X1 not found.  Creating black box for NOR3X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 94 module OAI21X1 not found.  Creating black box for OAI21X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 98 module OAI22X1 not found.  Creating black box for OAI22X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 103 module OR2X1 not found.  Creating black box for OR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 106 module OR2X2 not found.  Creating black box for OR2X2.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 109 module XNOR2X1 not found.  Creating black box for XNOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 112 module XOR2X1 not found.  Creating black box for XOR2X1.
Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 530 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found.  Creating black box for PHY_204.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 0.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 0.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
user_proj_example/runs/user_proj_example/logs/cts/cts.log
SKIPPED!
user_proj_example/runs/user_proj_example/logs/placement/opendp.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 1480 components and 4289 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def
Design Stats
--------------------------------
total instances          1480
multi row instances         0
fixed instances          1269
nets                      606
design area           80146.9 u^2
fixed area             2513.7 u^2
movable area            792.0 u^2
utilization                 1 %
utilization padded          1 %
rows                      102
row height                2.7 u

Placement Analysis
--------------------------------
total displacement      370.1 u
average displacement      0.2 u
max displacement          5.2 u
original HPWL         72949.9 u
legalized HPWL        72762.0 u
delta HPWL                 -0 %

user_proj_example/runs/user_proj_example/logs/routing/fastroute.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 1480 components and 4289 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 6
[PARAMS] Global adjustment: 0
[PARAMS] Unidirectional routing: 1
[PARAMS] Grid origin: (-1, -1)
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 10798
[INFO] #DB Macros: 0
[INFO] Found 0 clock nets
[INFO] Minimum degree: 2
[INFO] Maximum degree: 2
[INFO] Processing 6650 obstacles on layer 1
[INFO] Processing 3450 obstacles on layer 2
[INFO] Processing 4 obstacles on layer 5
[INFO] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 9853, WIRELEN1 : 0
[INFO] NumSeg  : 288
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 9853, WIRELEN1 : 9853
[INFO] NumSeg  : 288
[INFO] NumShift: 0
[Overflow Report] Total hCap    : 53446
[Overflow Report] Total vCap    : 39908
[Overflow Report] Total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Second L Route
[Overflow Report] Total hCap    : 53446
[Overflow Report] Total vCap    : 39908
[Overflow Report] Total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

First Z Route
[Overflow Report] Total hCap    : 53446
[Overflow Report] Total vCap    : 39908
[Overflow Report] Total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 0, enlarge 10 
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 1, enlarge 15 
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 2, enlarge 20 
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Usage checked
Maze routing finished
[INFO] P3 runtime: 0.000000 sec
[INFO] Final 2D results: 
[Overflow Report] total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 0.000000 sec
Post Processing Begins 
Post Processsing finished
 Starting via filling
[INFO] Via related to pin nodes 765
[INFO] Via related stiner nodes 0
Via filling finished

Final usage/overflow report: 
[INFO] Usage per layer: 
    Layer 1 usage: 0
    Layer 2 usage: 3789
    Layer 3 usage: 6045
    Layer 4 usage: 19
    Layer 5 usage: 0
    Layer 6 usage: 0

[INFO] Capacity per layer: 
    Layer 1 capacity: 0
    Layer 2 capacity: 31690
    Layer 3 capacity: 27300
    Layer 4 capacity: 18186
    Layer 5 capacity: 12608
    Layer 6 capacity: 3570

[INFO] Use percentage per layer: 
    Layer 1 use percentage: 0.0%
    Layer 2 use percentage: 11.96%
    Layer 3 use percentage: 22.14%
    Layer 4 use percentage: 0.10%
    Layer 5 use percentage: 0.00%
    Layer 6 use percentage: 0.00%

[INFO] Overflow per layer: 
    Layer 1 overflow: 0
    Layer 2 overflow: 0
    Layer 3 overflow: 0
    Layer 4 overflow: 0
    Layer 5 overflow: 0
    Layer 6 overflow: 0

[Overflow Report] Total Usage   : 9853
[Overflow Report] Total Capacity: 93354
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] Final usage          : 9853
[INFO] Final number of vias : 1150
[INFO] Final usage 3D       : 13303
[INFO] Total wirelength: 78301 um
Notice 0: Split top of 1 T shapes.
Repairing antennas...
[WARNING]No OR_DEFAULT vias defined
[INFO] #Antenna violations: 0
[INFO] Num routed nets: 288
user_proj_example/runs/user_proj_example/logs/routing/fastroute_post_antenna.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 1480 components and 4289 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 6
[PARAMS] Global adjustment: 0
[PARAMS] Unidirectional routing: 1
[PARAMS] Grid origin: (-1, -1)
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 10798
[INFO] #DB Macros: 0
[INFO] Found 0 clock nets
[INFO] Minimum degree: 2
[INFO] Maximum degree: 2
[INFO] Processing 6650 obstacles on layer 1
[INFO] Processing 3450 obstacles on layer 2
[INFO] Processing 4 obstacles on layer 5
[INFO] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 9853, WIRELEN1 : 0
[INFO] NumSeg  : 288
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 9853, WIRELEN1 : 9853
[INFO] NumSeg  : 288
[INFO] NumShift: 0
[Overflow Report] Total hCap    : 53446
[Overflow Report] Total vCap    : 39908
[Overflow Report] Total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Second L Route
[Overflow Report] Total hCap    : 53446
[Overflow Report] Total vCap    : 39908
[Overflow Report] Total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

First Z Route
[Overflow Report] Total hCap    : 53446
[Overflow Report] Total vCap    : 39908
[Overflow Report] Total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 0, enlarge 10 
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 1, enlarge 15 
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 2, enlarge 20 
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Usage checked
Maze routing finished
[INFO] P3 runtime: 0.010000 sec
[INFO] Final 2D results: 
[Overflow Report] total Usage   : 9853
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 0.010000 sec
Post Processing Begins 
Post Processsing finished
 Starting via filling
[INFO] Via related to pin nodes 765
[INFO] Via related stiner nodes 0
Via filling finished

Final usage/overflow report: 
[INFO] Usage per layer: 
    Layer 1 usage: 0
    Layer 2 usage: 3789
    Layer 3 usage: 6045
    Layer 4 usage: 19
    Layer 5 usage: 0
    Layer 6 usage: 0

[INFO] Capacity per layer: 
    Layer 1 capacity: 0
    Layer 2 capacity: 31690
    Layer 3 capacity: 27300
    Layer 4 capacity: 18186
    Layer 5 capacity: 12608
    Layer 6 capacity: 3570

[INFO] Use percentage per layer: 
    Layer 1 use percentage: 0.0%
    Layer 2 use percentage: 11.96%
    Layer 3 use percentage: 22.14%
    Layer 4 use percentage: 0.10%
    Layer 5 use percentage: 0.00%
    Layer 6 use percentage: 0.00%

[INFO] Overflow per layer: 
    Layer 1 overflow: 0
    Layer 2 overflow: 0
    Layer 3 overflow: 0
    Layer 4 overflow: 0
    Layer 5 overflow: 0
    Layer 6 overflow: 0

[Overflow Report] Total Usage   : 9853
[Overflow Report] Total Capacity: 93354
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] Final usage          : 9853
[INFO] Final number of vias : 1150
[INFO] Final usage 3D       : 13303
[INFO] Total wirelength: 78301 um
[INFO] Num routed nets: 288
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 0.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 0.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
user_proj_example/runs/user_proj_example/logs/routing/addspacers.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 1480 components and 4289 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/fastroute.def
Placed 5638 filler instances.
user_proj_example/runs/user_proj_example/logs/routing/tritonRoute.log

reading lef ...

units:       1000
#layers:     13
#macros:     463
#vias:       25
#viarulegen: 25

reading def ...

design:      user_proj_example
die area:    ( 0 0 ) ( 300000 300000 )
trackPts:    12
defvias:     3
#components: 7118
#terminals:  606
#snets:      2
#nets:       604

reading guide ...

#guides:     1292
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
#unique instances = 45

init region query ...
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 39246
mcon shape region query size = 127398
met1 shape region query size = 14932
via shape region query size = 824
met2 shape region query size = 1016
via2 shape region query size = 824
met3 shape region query size = 412
via3 shape region query size = 824
met4 shape region query size = 212
via4 shape region query size = 0
met5 shape region query size = 0


start pin access
  complete 81 pins
  complete 39 unique inst patterns
  complete 236 groups
Expt1 runtime (pin-level access point gen): 1.02415
Expt2 runtime (design-level access pattern gen): 0.215494
#scanned instances     = 7118
#unique  instances     = 45
#stdCellGenAp          = 468
#stdCellValidPlanarAp  = 282
#stdCellValidViaAp     = 439
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 288
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0

complete pin access
cpu time = 00:00:02, elapsed time = 00:00:01, memory = 25.75 (MB), peak = 29.11 (MB)

post process guides ...
GCELLGRID X -1 DO 43 STEP 6900 ;
GCELLGRID Y -1 DO 43 STEP 6900 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 211
mcon guide region query size = 0
met1 guide region query size = 427
via guide region query size = 0
met2 guide region query size = 530
via2 guide region query size = 0
met3 guide region query size = 2
via3 guide region query size = 0
met4 guide region query size = 0
via4 guide region query size = 0
met5 guide region query size = 0

init gr pin query ...


start track assignment
Done with 741 vertical wires in 1 frboxes and 429 horizontal wires in 1 frboxes.
Done with 184 vertical wires in 1 frboxes and 108 horizontal wires in 1 frboxes.

complete track assignment
cpu time = 00:00:01, elapsed time = 00:00:01, memory = 34.78 (MB), peak = 55.39 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 35.85 (MB), peak = 55.39 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:02, memory = 74.51 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:03, memory = 77.23 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:03, memory = 77.25 (MB)
    completing 40% with 700 violations
    elapsed time = 00:00:06, memory = 76.93 (MB)
    completing 50% with 700 violations
    elapsed time = 00:00:07, memory = 78.89 (MB)
    completing 60% with 737 violations
    elapsed time = 00:00:11, memory = 79.32 (MB)
    completing 70% with 737 violations
    elapsed time = 00:00:12, memory = 81.14 (MB)
    completing 80% with 737 violations
    elapsed time = 00:00:13, memory = 82.33 (MB)
    completing 90% with 896 violations
    elapsed time = 00:00:15, memory = 82.13 (MB)
    completing 100% with 617 violations
    elapsed time = 00:00:16, memory = 44.41 (MB)
  number of violations = 617
cpu time = 00:00:27, elapsed time = 00:00:17, memory = 42.21 (MB), peak = 392.45 (MB)
total wire length = 72590 um
total wire length on LAYER li1 = 5 um
total wire length on LAYER met1 = 26120 um
total wire length on LAYER met2 = 46131 um
total wire length on LAYER met3 = 333 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1275
up-via summary (total 1275):

-----------------------
 FR_MASTERSLICE       0
            li1     219
           met1    1028
           met2      28
           met3       0
           met4       0
-----------------------
                   1275


start 1st optimization iteration ...
    completing 10% with 617 violations
    elapsed time = 00:00:00, memory = 77.02 (MB)
    completing 20% with 617 violations
    elapsed time = 00:00:01, memory = 78.04 (MB)
    completing 30% with 617 violations
    elapsed time = 00:00:03, memory = 78.30 (MB)
    completing 40% with 462 violations
    elapsed time = 00:00:04, memory = 84.20 (MB)
    completing 50% with 462 violations
    elapsed time = 00:00:04, memory = 84.71 (MB)
    completing 60% with 420 violations
    elapsed time = 00:00:06, memory = 78.34 (MB)
    completing 70% with 420 violations
    elapsed time = 00:00:07, memory = 81.28 (MB)
    completing 80% with 420 violations
    elapsed time = 00:00:08, memory = 81.28 (MB)
    completing 90% with 304 violations
    elapsed time = 00:00:10, memory = 85.54 (MB)
    completing 100% with 299 violations
    elapsed time = 00:00:10, memory = 44.80 (MB)
  number of violations = 299
cpu time = 00:00:19, elapsed time = 00:00:11, memory = 41.91 (MB), peak = 392.45 (MB)
total wire length = 72468 um
total wire length on LAYER li1 = 8 um
total wire length on LAYER met1 = 25900 um
total wire length on LAYER met2 = 46125 um
total wire length on LAYER met3 = 434 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1255
up-via summary (total 1255):

-----------------------
 FR_MASTERSLICE       0
            li1     221
           met1     996
           met2      38
           met3       0
           met4       0
-----------------------
                   1255


start 2nd optimization iteration ...
    completing 10% with 299 violations
    elapsed time = 00:00:00, memory = 62.79 (MB)
    completing 20% with 299 violations
    elapsed time = 00:00:01, memory = 82.12 (MB)
    completing 30% with 299 violations
    elapsed time = 00:00:02, memory = 82.18 (MB)
    completing 40% with 299 violations
    elapsed time = 00:00:04, memory = 85.71 (MB)
    completing 50% with 299 violations
    elapsed time = 00:00:04, memory = 87.49 (MB)
    completing 60% with 314 violations
    elapsed time = 00:00:05, memory = 57.79 (MB)
    completing 70% with 314 violations
    elapsed time = 00:00:06, memory = 86.16 (MB)
    completing 80% with 314 violations
    elapsed time = 00:00:08, memory = 86.69 (MB)
    completing 90% with 296 violations
    elapsed time = 00:00:10, memory = 88.16 (MB)
    completing 100% with 296 violations
    elapsed time = 00:00:11, memory = 46.03 (MB)
  number of violations = 296
cpu time = 00:00:19, elapsed time = 00:00:12, memory = 42.06 (MB), peak = 392.45 (MB)
total wire length = 72463 um
total wire length on LAYER li1 = 9 um
total wire length on LAYER met1 = 25783 um
total wire length on LAYER met2 = 46113 um
total wire length on LAYER met3 = 557 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1277
up-via summary (total 1277):

-----------------------
 FR_MASTERSLICE       0
            li1     223
           met1     998
           met2      56
           met3       0
           met4       0
-----------------------
                   1277


start 3rd optimization iteration ...
    completing 10% with 296 violations
    elapsed time = 00:00:01, memory = 88.20 (MB)
    completing 20% with 296 violations
    elapsed time = 00:00:03, memory = 91.44 (MB)
    completing 30% with 296 violations
    elapsed time = 00:00:03, memory = 91.46 (MB)
    completing 40% with 245 violations
    elapsed time = 00:00:05, memory = 93.25 (MB)
    completing 50% with 245 violations
    elapsed time = 00:00:07, memory = 93.25 (MB)
    completing 60% with 192 violations
    elapsed time = 00:00:11, memory = 92.08 (MB)
    completing 70% with 192 violations
    elapsed time = 00:00:13, memory = 92.34 (MB)
    completing 80% with 192 violations
    elapsed time = 00:00:14, memory = 92.60 (MB)
    completing 90% with 146 violations
    elapsed time = 00:00:16, memory = 97.98 (MB)
    completing 100% with 100 violations
    elapsed time = 00:00:17, memory = 46.22 (MB)
  number of violations = 100
cpu time = 00:00:28, elapsed time = 00:00:18, memory = 45.18 (MB), peak = 392.45 (MB)
total wire length = 72454 um
total wire length on LAYER li1 = 23 um
total wire length on LAYER met1 = 25771 um
total wire length on LAYER met2 = 46057 um
total wire length on LAYER met3 = 602 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1387
up-via summary (total 1387):

-----------------------
 FR_MASTERSLICE       0
            li1     235
           met1    1088
           met2      64
           met3       0
           met4       0
-----------------------
                   1387


start 4th optimization iteration ...
    completing 10% with 100 violations
    elapsed time = 00:00:01, memory = 81.78 (MB)
    completing 20% with 100 violations
    elapsed time = 00:00:02, memory = 87.81 (MB)
    completing 30% with 100 violations
    elapsed time = 00:00:02, memory = 89.37 (MB)
    completing 40% with 93 violations
    elapsed time = 00:00:04, memory = 91.25 (MB)
    completing 50% with 93 violations
    elapsed time = 00:00:05, memory = 91.35 (MB)
    completing 60% with 72 violations
    elapsed time = 00:00:06, memory = 75.07 (MB)
    completing 70% with 72 violations
    elapsed time = 00:00:08, memory = 91.61 (MB)
    completing 80% with 72 violations
    elapsed time = 00:00:09, memory = 93.68 (MB)
    completing 90% with 57 violations
    elapsed time = 00:00:11, memory = 97.12 (MB)
    completing 100% with 52 violations
    elapsed time = 00:00:14, memory = 48.00 (MB)
  number of violations = 52
cpu time = 00:00:20, elapsed time = 00:00:15, memory = 44.94 (MB), peak = 392.45 (MB)
total wire length = 72460 um
total wire length on LAYER li1 = 23 um
total wire length on LAYER met1 = 25778 um
total wire length on LAYER met2 = 46050 um
total wire length on LAYER met3 = 607 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1409
up-via summary (total 1409):

-----------------------
 FR_MASTERSLICE       0
            li1     235
           met1    1108
           met2      66
           met3       0
           met4       0
-----------------------
                   1409


start 5th optimization iteration ...
    completing 10% with 52 violations
    elapsed time = 00:00:00, memory = 60.15 (MB)
    completing 20% with 52 violations
    elapsed time = 00:00:01, memory = 88.39 (MB)
    completing 30% with 52 violations
    elapsed time = 00:00:02, memory = 88.69 (MB)
    completing 40% with 46 violations
    elapsed time = 00:00:03, memory = 69.65 (MB)
    completing 50% with 46 violations
    elapsed time = 00:00:04, memory = 73.10 (MB)
    completing 60% with 39 violations
    elapsed time = 00:00:05, memory = 76.41 (MB)
    completing 70% with 39 violations
    elapsed time = 00:00:06, memory = 93.40 (MB)
    completing 80% with 39 violations
    elapsed time = 00:00:08, memory = 94.43 (MB)
    completing 90% with 37 violations
    elapsed time = 00:00:09, memory = 85.22 (MB)
    completing 100% with 30 violations
    elapsed time = 00:00:10, memory = 70.51 (MB)
  number of violations = 30
cpu time = 00:00:14, elapsed time = 00:00:11, memory = 69.45 (MB), peak = 415.72 (MB)
total wire length = 72469 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25735 um
total wire length on LAYER met2 = 46046 um
total wire length on LAYER met3 = 661 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1435
up-via summary (total 1435):

-----------------------
 FR_MASTERSLICE       0
            li1     241
           met1    1120
           met2      74
           met3       0
           met4       0
-----------------------
                   1435


start 6th optimization iteration ...
    completing 10% with 30 violations
    elapsed time = 00:00:00, memory = 62.30 (MB)
    completing 20% with 30 violations
    elapsed time = 00:00:01, memory = 82.25 (MB)
    completing 30% with 30 violations
    elapsed time = 00:00:01, memory = 83.91 (MB)
    completing 40% with 28 violations
    elapsed time = 00:00:02, memory = 64.61 (MB)
    completing 50% with 28 violations
    elapsed time = 00:00:02, memory = 83.46 (MB)
    completing 60% with 25 violations
    elapsed time = 00:00:03, memory = 65.32 (MB)
    completing 70% with 25 violations
    elapsed time = 00:00:04, memory = 86.35 (MB)
    completing 80% with 25 violations
    elapsed time = 00:00:04, memory = 87.12 (MB)
    completing 90% with 25 violations
    elapsed time = 00:00:05, memory = 76.57 (MB)
    completing 100% with 16 violations
    elapsed time = 00:00:05, memory = 63.94 (MB)
  number of violations = 16
cpu time = 00:00:09, elapsed time = 00:00:06, memory = 63.05 (MB), peak = 415.72 (MB)
total wire length = 72472 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25736 um
total wire length on LAYER met2 = 46041 um
total wire length on LAYER met3 = 668 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1449
up-via summary (total 1449):

-----------------------
 FR_MASTERSLICE       0
            li1     241
           met1    1124
           met2      84
           met3       0
           met4       0
-----------------------
                   1449


start 7th optimization iteration ...
    completing 10% with 16 violations
    elapsed time = 00:00:00, memory = 67.18 (MB)
    completing 20% with 16 violations
    elapsed time = 00:00:00, memory = 77.78 (MB)
    completing 30% with 16 violations
    elapsed time = 00:00:01, memory = 78.81 (MB)
    completing 40% with 14 violations
    elapsed time = 00:00:02, memory = 70.30 (MB)
    completing 50% with 14 violations
    elapsed time = 00:00:02, memory = 83.92 (MB)
    completing 60% with 9 violations
    elapsed time = 00:00:03, memory = 63.37 (MB)
    completing 70% with 9 violations
    elapsed time = 00:00:03, memory = 73.94 (MB)
    completing 80% with 9 violations
    elapsed time = 00:00:03, memory = 78.32 (MB)
    completing 90% with 6 violations
    elapsed time = 00:00:04, memory = 74.11 (MB)
    completing 100% with 4 violations
    elapsed time = 00:00:04, memory = 65.31 (MB)
  number of violations = 4
cpu time = 00:00:08, elapsed time = 00:00:05, memory = 64.90 (MB), peak = 415.72 (MB)
total wire length = 72476 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25716 um
total wire length on LAYER met2 = 46041 um
total wire length on LAYER met3 = 693 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1463
up-via summary (total 1463):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1    1134
           met2      90
           met3       0
           met4       0
-----------------------
                   1463


start 8th optimization iteration ...
    completing 10% with 4 violations
    elapsed time = 00:00:00, memory = 66.96 (MB)
    completing 20% with 4 violations
    elapsed time = 00:00:00, memory = 74.18 (MB)
    completing 30% with 4 violations
    elapsed time = 00:00:00, memory = 74.44 (MB)
    completing 40% with 1 violations
    elapsed time = 00:00:00, memory = 74.98 (MB)
    completing 50% with 1 violations
    elapsed time = 00:00:01, memory = 75.48 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:01, memory = 67.19 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:01, memory = 71.83 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:01, memory = 73.89 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:02, memory = 74.15 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:02, memory = 74.24 (MB)
  number of violations = 0
cpu time = 00:00:05, elapsed time = 00:00:03, memory = 74.24 (MB), peak = 420.48 (MB)
total wire length = 72477 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25714 um
total wire length on LAYER met2 = 46042 um
total wire length on LAYER met3 = 695 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1467
up-via summary (total 1467):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1    1136
           met2      92
           met3       0
           met4       0
-----------------------
                   1467


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 74.24 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 74.24 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 74.50 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 74.50 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:01, memory = 74.50 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:01, memory = 74.50 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:01, memory = 74.63 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:01, memory = 74.63 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:02, memory = 74.63 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:02, memory = 74.63 (MB)
  number of violations = 0
cpu time = 00:00:03, elapsed time = 00:00:02, memory = 74.63 (MB), peak = 420.48 (MB)
total wire length = 72477 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25714 um
total wire length on LAYER met2 = 46042 um
total wire length on LAYER met3 = 695 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1467
up-via summary (total 1467):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1    1136
           met2      92
           met3       0
           met4       0
-----------------------
                   1467


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 74.63 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 74.63 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 74.63 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 74.63 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:02, memory = 74.86 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:02, memory = 74.86 (MB)
  number of violations = 0
cpu time = 00:00:04, elapsed time = 00:00:02, memory = 74.86 (MB), peak = 420.48 (MB)
total wire length = 72477 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25714 um
total wire length on LAYER met2 = 46042 um
total wire length on LAYER met3 = 695 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1467
up-via summary (total 1467):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1    1136
           met2      92
           met3       0
           met4       0
-----------------------
                   1467


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:02, memory = 74.86 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:02, memory = 74.86 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:03, memory = 74.86 (MB)
  number of violations = 0
cpu time = 00:00:04, elapsed time = 00:00:03, memory = 74.86 (MB), peak = 420.48 (MB)
total wire length = 72477 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25714 um
total wire length on LAYER met2 = 46042 um
total wire length on LAYER met3 = 695 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1467
up-via summary (total 1467):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1    1136
           met2      92
           met3       0
           met4       0
-----------------------
                   1467


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:02, memory = 74.86 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:02, memory = 74.86 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:03, memory = 74.86 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:03, memory = 74.86 (MB)
  number of violations = 0
cpu time = 00:00:04, elapsed time = 00:00:03, memory = 74.86 (MB), peak = 420.48 (MB)
total wire length = 72477 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25714 um
total wire length on LAYER met2 = 46042 um
total wire length on LAYER met3 = 695 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1467
up-via summary (total 1467):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1    1136
           met2      92
           met3       0
           met4       0
-----------------------
                   1467


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:02, memory = 74.86 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:02, memory = 74.86 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:03, memory = 74.86 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:03, memory = 74.86 (MB)
  number of violations = 0
cpu time = 00:00:04, elapsed time = 00:00:03, memory = 74.86 (MB), peak = 420.48 (MB)
total wire length = 72477 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25714 um
total wire length on LAYER met2 = 46042 um
total wire length on LAYER met3 = 695 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1467
up-via summary (total 1467):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1    1136
           met2      92
           met3       0
           met4       0
-----------------------
                   1467


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 74.86 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:01, memory = 74.86 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:02, memory = 74.86 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:02, memory = 74.86 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:03, memory = 74.86 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:03, memory = 74.86 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:04, memory = 74.86 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:04, memory = 74.86 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:05, memory = 74.86 (MB)
  number of violations = 0
cpu time = 00:00:05, elapsed time = 00:00:05, memory = 74.86 (MB), peak = 420.48 (MB)
total wire length = 72477 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25714 um
total wire length on LAYER met2 = 46042 um
total wire length on LAYER met3 = 695 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1467
up-via summary (total 1467):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1    1136
           met2      92
           met3       0
           met4       0
-----------------------
                   1467


complete detail routing
total wire length = 72477 um
total wire length on LAYER li1 = 25 um
total wire length on LAYER met1 = 25714 um
total wire length on LAYER met2 = 46042 um
total wire length on LAYER met3 = 695 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 1467
up-via summary (total 1467):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1    1136
           met2      92
           met3       0
           met4       0
-----------------------
                   1467

cpu time = 00:03:02, elapsed time = 00:02:03, memory = 74.86 (MB), peak = 420.48 (MB)

post processing ...

Runtime taken (hrt): 128.607
user_proj_example/runs/user_proj_example/logs/lvs/write_powered_verilog.log
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 7118 components and 26841 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
Top-level design name: user_proj_example
Found port VPWR of type SIGNAL
Found port VGND of type SIGNAL
Power net:  VPWR
Ground net: VGND
Modified power connections of 7118 cells (Remaining: 0 ).
user_proj_example/runs/user_proj_example/logs/write_verilog.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/user_proj_example.powered.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 7118 components and 26841 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 606 nets and 26630 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/routing/user_proj_example.powered.def
user_proj_example/runs/user_proj_example/logs/synthesis/yosys_rewrite_verilog.log

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.powered.v
Parsing Verilog input from `/project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.powered.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
Successfully finished Verilog frontend.

2. Executing Verilog backend.
Dumping module `\user_proj_example'.

End of script. Logfile hash: ea355d6045, CPU: user 18.45s system 0.11s, MEM: 66.08 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 87% 2x write_verilog (16 sec), 12% 2x read_verilog (2 sec)
user_proj_example/runs/user_proj_example/logs/magic/magic.log

Magic 8.3 revision 92 - Compiled on Sat Dec  5 17:44:54 UTC 2020.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130: scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic/mag_lef_gds.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
This action cannot be undone.
LEF read, Line 77 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 78 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 111 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 112 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 118 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 119 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 120 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 159 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 160 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 162 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 163 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 164 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 200 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 201 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 203 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 204 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 205 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 241 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 242 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 244 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 245 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 282 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 283 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 789 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef.
This action cannot be undone.
LEF read: Processed 79 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX8.lef.
This action cannot be undone.
LEF read: Processed 75 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef.
This action cannot be undone.
LEF read: Processed 78 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX4.lef.
This action cannot be undone.
LEF read: Processed 65 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef.
This action cannot be undone.
LEF read: Processed 92 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/XOR2X1.lef.
This action cannot be undone.
LEF read: Processed 88 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/BUFX4.lef.
This action cannot be undone.
LEF read: Processed 57 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef.
This action cannot be undone.
LEF read: Processed 68 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/HAX1.lef.
This action cannot be undone.
LEF read: Processed 104 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/LATCH.lef.
This action cannot be undone.
LEF read: Processed 76 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef.
This action cannot be undone.
LEF read: Processed 79 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef.
This action cannot be undone.
LEF read: Processed 77 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef.
This action cannot be undone.
LEF read: Processed 51 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef.
This action cannot be undone.
LEF read: Processed 64 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef.
This action cannot be undone.
LEF read: Processed 68 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX2.lef.
This action cannot be undone.
LEF read: Processed 53 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NOR3X1.lef.
This action cannot be undone.
LEF read: Processed 91 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef.
This action cannot be undone.
LEF read: Processed 64 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OR2X2.lef.
This action cannot be undone.
LEF read: Processed 60 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef.
This action cannot be undone.
LEF read: Processed 90 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/CLKBUF1.lef.
This action cannot be undone.
LEF read: Processed 61 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef.
This action cannot be undone.
LEF read: Processed 68 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef.
This action cannot be undone.
LEF read: Processed 64 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX1.lef.
This action cannot be undone.
LEF read: Processed 53 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INV.lef.
This action cannot be undone.
LEF read: Processed 53 lines.
Reading DEF data from file /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def.
This action cannot be undone.
  Processed 5 vias total.
  Processed 7118 subcell instances total.
  Processed 606 pins total.
  Processed 2 special nets total.
  Processed 604 nets total.
DEF read: Processed 14595 lines.
[INFO]: Zeroizing Origin
[INFO]: Current Box Values: 0 0 59856 60000
[INFO]: Writing abstract LEF
Generating LEF output /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.lef for cell user_proj_example:
Diagnostic:  Write LEF header for cell user_proj_example
Diagnostic:  Writing LEF output for cell user_proj_example
Diagnostic:  Scale value is 0.005000
[INFO]: LEF Write Complete

Library written using GDS-II Release 6.0
Library name: LIB
Reading "XOR2X1".
Warning:  cell XOR2X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "HAX1".
Warning:  cell HAX1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "INVX8".
Warning:  cell INVX8 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "AND2X2".
Warning:  cell AND2X2 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "NOR3X1".
Warning:  cell NOR3X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "XNOR2X1".
Warning:  cell XNOR2X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "OAI22X1".
Warning:  cell OAI22X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "AOI21X1".
Warning:  cell AOI21X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "NAND2X1".
Warning:  cell NAND2X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "OR2X2".
Warning:  cell OR2X2 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "OAI21X1".
Warning:  cell OAI21X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "INV".
Warning:  cell INV already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "AOI22X1".
Warning:  cell AOI22X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "OR2X1".
Warning:  cell OR2X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "INVX1".
Warning:  cell INVX1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "NOR2X1".
Warning:  cell NOR2X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "MUX2X1".
Warning:  cell MUX2X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "LATCH".
Warning:  cell LATCH already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "BUFX2".
Warning:  cell BUFX2 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "BUFX4".
Warning:  cell BUFX4 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "AND2X1".
Warning:  cell AND2X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "NAND3X1".
Warning:  cell NAND3X1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "INVX2".
Warning:  cell INVX2 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "CLKBUF1".
Warning:  cell CLKBUF1 already existed before reading GDS!

Library written using GDS-II Release 6.0
Library name: LIB
Reading "INVX4".
Warning:  cell INVX4 already existed before reading GDS!
   Writing cell user_proj_example
   Writing cell sky130_fd_sc_hd__decap_12
   Writing cell sky130_fd_sc_hd__decap_3
   Writing cell sky130_fd_sc_hd__decap_4
   Writing cell sky130_fd_sc_hd__tapvpwrvgnd_1
   Writing cell sky130_fd_sc_hd__fill_2
   Writing cell sky130_fd_sc_hd__decap_8
   Writing cell sky130_fd_sc_hd__decap_6
   Writing cell AND2X1
   Writing cell sky130_fd_sc_hd__fill_1
   Writing cell sky130_fd_sc_hd__conb_1
   Writing cell AND2X2
   Writing cell AOI21X1
   Writing cell AOI22X1
   Writing cell BUFX2
   Writing cell BUFX4
   Writing cell CLKBUF1
   Writing cell HAX1
   Writing cell INV
   Writing cell INVX1
   Writing cell INVX2
   Writing cell INVX4
   Writing cell INVX8
   Writing cell LATCH
   Writing cell MUX2X1
   Writing cell NAND2X1
   Writing cell NAND3X1
   Writing cell NOR2X1
   Writing cell NOR3X1
   Writing cell OAI21X1
   Writing cell OAI22X1
   Writing cell OR2X1
   Writing cell OR2X2
   Writing cell XNOR2X1
   Writing cell XOR2X1
[INFO]: GDS Write Complete
user_proj_example/runs/user_proj_example/logs/magic/magic.maglef.log

Magic 8.3 revision 92 - Compiled on Sat Dec  5 17:44:54 UTC 2020.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130: scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic/maglef.tcl" from command line.
Reading LEF data from file /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.lef.
This action cannot be undone.
LEF read: Processed 4542 lines.
[INFO]: DONE GENERATING MAGLEF VIEW
user_proj_example/runs/user_proj_example/logs/magic/magic_spice.log

Magic 8.3 revision 92 - Compiled on Sat Dec  5 17:44:54 UTC 2020.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130: scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/project/openlane/user_proj_example/runs/user_proj_example/tmp/magic_spice.tcl" from command line.
Reading LEF data from file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
This action cannot be undone.
LEF read, Line 77 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 78 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 111 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 112 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 118 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 119 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 120 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 159 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 160 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 162 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 163 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 164 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 200 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 201 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 203 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 204 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 205 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 241 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 242 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 244 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 245 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 282 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 283 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 789 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef.
This action cannot be undone.
LEF read: Processed 79 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX8.lef.
This action cannot be undone.
LEF read: Processed 75 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef.
This action cannot be undone.
LEF read: Processed 78 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX4.lef.
This action cannot be undone.
LEF read: Processed 65 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef.
This action cannot be undone.
LEF read: Processed 92 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/XOR2X1.lef.
This action cannot be undone.
LEF read: Processed 88 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/BUFX4.lef.
This action cannot be undone.
LEF read: Processed 57 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef.
This action cannot be undone.
LEF read: Processed 68 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/HAX1.lef.
This action cannot be undone.
LEF read: Processed 104 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/LATCH.lef.
This action cannot be undone.
LEF read: Processed 76 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef.
This action cannot be undone.
LEF read: Processed 79 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef.
This action cannot be undone.
LEF read: Processed 77 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef.
This action cannot be undone.
LEF read: Processed 51 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef.
This action cannot be undone.
LEF read: Processed 64 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef.
This action cannot be undone.
LEF read: Processed 68 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX2.lef.
This action cannot be undone.
LEF read: Processed 53 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/NOR3X1.lef.
This action cannot be undone.
LEF read: Processed 91 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef.
This action cannot be undone.
LEF read: Processed 64 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/OR2X2.lef.
This action cannot be undone.
LEF read: Processed 60 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef.
This action cannot be undone.
LEF read: Processed 90 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/CLKBUF1.lef.
This action cannot be undone.
LEF read: Processed 61 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef.
This action cannot be undone.
LEF read: Processed 68 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef.
This action cannot be undone.
LEF read: Processed 64 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INVX1.lef.
This action cannot be undone.
LEF read: Processed 53 lines.
Reading LEF data from file /project/openlane/user_proj_example/../../cells/lef/INV.lef.
This action cannot be undone.
LEF read: Processed 53 lines.
Reading DEF data from file /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def.
This action cannot be undone.
  Processed 5 vias total.
  Processed 7118 subcell instances total.
  Processed 606 pins total.
  Processed 2 special nets total.
  Processed 604 nets total.
DEF read: Processed 14595 lines.
Extracting XOR2X1 into XOR2X1.ext:
Extracting XNOR2X1 into XNOR2X1.ext:
Extracting OR2X2 into OR2X2.ext:
Extracting OR2X1 into OR2X1.ext:
Extracting OAI22X1 into OAI22X1.ext:
Extracting OAI21X1 into OAI21X1.ext:
Extracting NOR3X1 into NOR3X1.ext:
Extracting NOR2X1 into NOR2X1.ext:
Extracting NAND3X1 into NAND3X1.ext:
Extracting NAND2X1 into NAND2X1.ext:
Extracting MUX2X1 into MUX2X1.ext:
Extracting LATCH into LATCH.ext:
Extracting INVX8 into INVX8.ext:
Extracting INVX4 into INVX4.ext:
Extracting INVX2 into INVX2.ext:
Extracting INVX1 into INVX1.ext:
Extracting INV into INV.ext:
Extracting HAX1 into HAX1.ext:
Extracting CLKBUF1 into CLKBUF1.ext:
Extracting BUFX4 into BUFX4.ext:
Extracting BUFX2 into BUFX2.ext:
Extracting AOI22X1 into AOI22X1.ext:
Extracting AOI21X1 into AOI21X1.ext:
Extracting AND2X2 into AND2X2.ext:
Extracting sky130_fd_sc_hd__conb_1 into sky130_fd_sc_hd__conb_1.ext:
Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext:
Extracting AND2X1 into AND2X1.ext:
Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:
Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext:
Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext:
Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:
Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:
Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext:
Extracting sky130_fd_sc_hd__decap_12 into sky130_fd_sc_hd__decap_12.ext:
Extracting user_proj_example into user_proj_example.ext:
exttospice finished.
Using technology "sky130A", version 1.0.81-0-gb184e85
user_proj_example/runs/user_proj_example/logs/magic/magic.drc.log

Magic 8.3 revision 92 - Compiled on Sat Dec  5 17:44:54 UTC 2020.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130: scaleFactor=2, multiplier=2
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/openLANE_flow/scripts/magic/drc.tcl" from command line.

Library written using GDS-II Release 3.0
Library name: user_proj_example
Reading "sky130_fd_sc_hd__decap_12".
Error while reading cell "sky130_fd_sc_hd__decap_12" (byte position 150): Unknown layer/datatype in boundary, layer=236 type=0
Reading "sky130_fd_sc_hd__decap_3".
Error while reading cell "sky130_fd_sc_hd__decap_3" (byte position 4284): Unknown layer/datatype in boundary, layer=236 type=0
Reading "sky130_fd_sc_hd__decap_4".
Error while reading cell "sky130_fd_sc_hd__decap_4" (byte position 6946): Unknown layer/datatype in boundary, layer=236 type=0
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
Reading "sky130_fd_sc_hd__fill_2".
Reading "sky130_fd_sc_hd__decap_8".
Error while reading cell "sky130_fd_sc_hd__decap_8" (byte position 12830): Unknown layer/datatype in boundary, layer=236 type=0
Reading "sky130_fd_sc_hd__decap_6".
Error while reading cell "sky130_fd_sc_hd__decap_6" (byte position 16356): Unknown layer/datatype in boundary, layer=236 type=0
Reading "AND2X1".
Reading "sky130_fd_sc_hd__fill_1".
Reading "sky130_fd_sc_hd__conb_1".
Error while reading cell "sky130_fd_sc_hd__conb_1" (byte position 26634): Unknown layer/datatype in boundary, layer=236 type=0
Reading "AND2X2".
Reading "AOI21X1".
Reading "AOI22X1".
Reading "BUFX2".
Reading "BUFX4".
Reading "CLKBUF1".
Reading "HAX1".
Reading "INV".
Reading "INVX1".
Reading "INVX2".
Reading "INVX4".
Reading "INVX8".
Reading "LATCH".
Reading "MUX2X1".
Reading "NAND2X1".
Reading "NAND3X1".
Reading "NOR2X1".
Reading "NOR3X1".
Reading "OAI21X1".
Reading "OAI22X1".
Reading "OR2X1".
Reading "OR2X2".
Reading "XNOR2X1".
Reading "XOR2X1".
Reading "user_proj_example".
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[INFO]: Loading user_proj_example

DRC style is now "drc(full)"
Loading DRC CIF style.
[INFO]: COUNT: 4773
[INFO]: Should be divided by 3 or 4
[INFO]: DRC Checking DONE (/project/openlane/user_proj_example/runs/user_proj_example/logs/magic/magic.drc)
[INFO]: Saving mag view with DRC errors(/project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.drc.mag)
[INFO]: Saved
user_proj_example/runs/user_proj_example/logs/lvs/lvs.log
Netgen 1.5.158 compiled on Sat Dec  5 19:50:01 UTC 2020
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Generating JSON file result
Reading netlist file /project/openlane/user_proj_example/runs/user_proj_example/results/magic/user_proj_example.spice
Reading netlist file /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.powered.v
Warning:  A case-insensitive file has been read and so the	verilog file must be treated case-insensitive to match.
Creating placeholder cell definition for module AND2X1.
Creating placeholder cell definition for module AND2X2.
Creating placeholder cell definition for module AOI21X1.
Creating placeholder cell definition for module AOI22X1.
Creating placeholder cell definition for module BUFX2.
Creating placeholder cell definition for module BUFX4.
Creating placeholder cell definition for module CLKBUF1.
Creating placeholder cell definition for module sky130_fd_sc_hd__fill_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_12.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_6.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_8.
Creating placeholder cell definition for module sky130_fd_sc_hd__fill_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_3.
Creating placeholder cell definition for module HAX1.
Creating placeholder cell definition for module INV.
Creating placeholder cell definition for module INVX1.
Creating placeholder cell definition for module INVX2.
Creating placeholder cell definition for module INVX4.
Creating placeholder cell definition for module INVX8.
Creating placeholder cell definition for module LATCH.
Creating placeholder cell definition for module MUX2X1.
Creating placeholder cell definition for module NAND2X1.
Creating placeholder cell definition for module NAND3X1.
Creating placeholder cell definition for module NOR2X1.
Creating placeholder cell definition for module NOR3X1.
Creating placeholder cell definition for module OAI21X1.
Creating placeholder cell definition for module OAI22X1.
Creating placeholder cell definition for module OR2X1.
Creating placeholder cell definition for module OR2X2.
Creating placeholder cell definition for module sky130_fd_sc_hd__tapvpwrvgnd_1.
Creating placeholder cell definition for module XNOR2X1.
Creating placeholder cell definition for module XOR2X1.
Creating placeholder cell definition for module sky130_fd_sc_hd__conb_1.
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
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Note:  Implicit pin HI
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Note:  Implicit pin HI
Note:  Implicit pin HI
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Note:  Implicit pin HI
Note:  Implicit pin HI
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Note:  Implicit pin HI
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Note:  Implicit pin HI
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Note:  Implicit pin HI
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Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
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Note:  Implicit pin HI
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Note:  Implicit pin HI
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Note:  Implicit pin HI
Note:  Implicit pin HI
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Note:  Implicit pin HI
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Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
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Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
Note:  Implicit pin HI
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Note:  Implicit pin HI
Note:  Implicit pin HI
Reading setup file /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.tech/netgen/sky130A_setup.tcl
Comparison output logged to file /project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.log
Logging to file "/project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.log" enabled
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1'
Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances.
Circuit contains 0 nets, and 2 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1'
Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains no devices.
Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__conb_1'
Circuit sky130_fd_sc_hd__conb_1 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__conb_1'
Circuit sky130_fd_sc_hd__conb_1 contains 0 device instances.
Circuit contains 0 nets.

Circuit sky130_fd_sc_hd__conb_1 contains no devices.
Contents of circuit 1:  Circuit: 'NAND2X1'
Circuit NAND2X1 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'NAND2X1'
Circuit NAND2X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit NAND2X1 contains no devices.
Contents of circuit 1:  Circuit: 'XNOR2X1'
Circuit XNOR2X1 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'XNOR2X1'
Circuit XNOR2X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit XNOR2X1 contains no devices.
Contents of circuit 1:  Circuit: 'AOI21X1'
Circuit AOI21X1 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'AOI21X1'
Circuit AOI21X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit AOI21X1 contains no devices.
Contents of circuit 1:  Circuit: 'XOR2X1'
Circuit XOR2X1 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'XOR2X1'
Circuit XOR2X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit XOR2X1 contains no devices.
Contents of circuit 1:  Circuit: 'LATCH'
Circuit LATCH contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'LATCH'
Circuit LATCH contains 0 device instances.
Circuit contains 0 nets.

Circuit LATCH contains no devices.
Contents of circuit 1:  Circuit: 'INVX1'
Circuit INVX1 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'INVX1'
Circuit INVX1 contains 0 device instances.
Circuit contains 0 nets.

Circuit INVX1 contains no devices.
Contents of circuit 1:  Circuit: 'INVX2'
Circuit INVX2 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'INVX2'
Circuit INVX2 contains 0 device instances.
Circuit contains 0 nets.

Circuit INVX2 contains no devices.
Contents of circuit 1:  Circuit: 'NOR2X1'
Circuit NOR2X1 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'NOR2X1'
Circuit NOR2X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit NOR2X1 contains no devices.
Contents of circuit 1:  Circuit: 'INVX4'
Circuit INVX4 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'INVX4'
Circuit INVX4 contains 0 device instances.
Circuit contains 0 nets.

Circuit INVX4 contains no devices.
Contents of circuit 1:  Circuit: 'OR2X1'
Circuit OR2X1 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'OR2X1'
Circuit OR2X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit OR2X1 contains no devices.
Contents of circuit 1:  Circuit: 'OR2X2'
Circuit OR2X2 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'OR2X2'
Circuit OR2X2 contains 0 device instances.
Circuit contains 0 nets.

Circuit OR2X2 contains no devices.
Contents of circuit 1:  Circuit: 'INVX8'
Circuit INVX8 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'INVX8'
Circuit INVX8 contains 0 device instances.
Circuit contains 0 nets.

Circuit INVX8 contains no devices.
Contents of circuit 1:  Circuit: 'OAI22X1'
Circuit OAI22X1 contains 0 device instances.
Circuit contains 0 nets, and 7 disconnected pins.
Contents of circuit 2:  Circuit: 'OAI22X1'
Circuit OAI22X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit OAI22X1 contains no devices.
Contents of circuit 1:  Circuit: 'BUFX2'
Circuit BUFX2 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'BUFX2'
Circuit BUFX2 contains 0 device instances.
Circuit contains 0 nets.

Circuit BUFX2 contains no devices.
Contents of circuit 1:  Circuit: 'NAND3X1'
Circuit NAND3X1 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'NAND3X1'
Circuit NAND3X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit NAND3X1 contains no devices.
Contents of circuit 1:  Circuit: 'INV'
Circuit INV contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'INV'
Circuit INV contains 0 device instances.
Circuit contains 0 nets.

Circuit INV contains no devices.
Contents of circuit 1:  Circuit: 'BUFX4'
Circuit BUFX4 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'BUFX4'
Circuit BUFX4 contains 0 device instances.
Circuit contains 0 nets.

Circuit BUFX4 contains no devices.
Contents of circuit 1:  Circuit: 'AOI22X1'
Circuit AOI22X1 contains 0 device instances.
Circuit contains 0 nets, and 7 disconnected pins.
Contents of circuit 2:  Circuit: 'AOI22X1'
Circuit AOI22X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit AOI22X1 contains no devices.
Contents of circuit 1:  Circuit: 'NOR3X1'
Circuit NOR3X1 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'NOR3X1'
Circuit NOR3X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit NOR3X1 contains no devices.
Contents of circuit 1:  Circuit: 'CLKBUF1'
Circuit CLKBUF1 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'CLKBUF1'
Circuit CLKBUF1 contains 0 device instances.
Circuit contains 0 nets.

Circuit CLKBUF1 contains no devices.
Contents of circuit 1:  Circuit: 'MUX2X1'
Circuit MUX2X1 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'MUX2X1'
Circuit MUX2X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit MUX2X1 contains no devices.
Contents of circuit 1:  Circuit: 'AND2X1'
Circuit AND2X1 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'AND2X1'
Circuit AND2X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit AND2X1 contains no devices.
Contents of circuit 1:  Circuit: 'AND2X2'
Circuit AND2X2 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'AND2X2'
Circuit AND2X2 contains 0 device instances.
Circuit contains 0 nets.

Circuit AND2X2 contains no devices.
Contents of circuit 1:  Circuit: 'OAI21X1'
Circuit OAI21X1 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'OAI21X1'
Circuit OAI21X1 contains 0 device instances.
Circuit contains 0 nets.

Circuit OAI21X1 contains no devices.
Contents of circuit 1:  Circuit: 'HAX1'
Circuit HAX1 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'HAX1'
Circuit HAX1 contains 0 device instances.
Circuit contains 0 nets.

Circuit HAX1 contains no devices.
Contents of circuit 1:  Circuit: 'user_proj_example'
Circuit user_proj_example contains 1276 device instances.
  Class: NOR3X1                instances:   1
  Class: OR2X1                 instances:   1
  Class: OR2X2                 instances:   1
  Class: MUX2X1                instances:   1
  Class: AOI22X1               instances:   1
  Class: NOR2X1                instances:   1
  Class: INV                   instances:   1
  Class: LATCH                 instances:   1
  Class: sky130_fd_sc_hd__conb_1 instances: 211
  Class: NAND3X1               instances:   1
  Class: HAX1                  instances:   1
  Class: OAI22X1               instances:   1
  Class: XOR2X1                instances:   1
  Class: AOI21X1               instances:   1
  Class: NAND2X1               instances:   1
  Class: OAI21X1               instances:   1
  Class: XNOR2X1               instances:   1
  Class: BUFX2                 instances:   1
  Class: BUFX4                 instances:   1
  Class: AND2X1                instances:   1
  Class: AND2X2                instances:   1
  Class: CLKBUF1               instances:   1
  Class: INVX1                 instances:   1
  Class: INVX2                 instances:   1
  Class: INVX4                 instances:   1
  Class: INVX8                 instances:   1
  Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 1040
Circuit contains 501 nets, and 316 disconnected pins.
Contents of circuit 2:  Circuit: 'user_proj_example'
Circuit user_proj_example contains 1276 device instances.
  Class: NOR3X1                instances:   1
  Class: OR2X1                 instances:   1
  Class: OR2X2                 instances:   1
  Class: MUX2X1                instances:   1
  Class: AOI22X1               instances:   1
  Class: NOR2X1                instances:   1
  Class: INV                   instances:   1
  Class: LATCH                 instances:   1
  Class: sky130_fd_sc_hd__conb_1 instances: 211
  Class: NAND3X1               instances:   1
  Class: HAX1                  instances:   1
  Class: OAI22X1               instances:   1
  Class: XOR2X1                instances:   1
  Class: AOI21X1               instances:   1
  Class: NAND2X1               instances:   1
  Class: OAI21X1               instances:   1
  Class: XNOR2X1               instances:   1
  Class: BUFX2                 instances:   1
  Class: BUFX4                 instances:   1
  Class: AND2X1                instances:   1
  Class: AND2X2                instances:   1
  Class: CLKBUF1               instances:   1
  Class: INVX1                 instances:   1
  Class: INVX2                 instances:   1
  Class: INVX4                 instances:   1
  Class: INVX8                 instances:   1
  Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 1040
Circuit contains 290 nets, and 504 disconnected pins.

Circuit 1 contains 1276 devices, Circuit 2 contains 1276 devices.
Circuit 1 contains 290 nets,    Circuit 2 contains 290 nets.

Circuits match with 3 symmetries.
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match with 3 symmetries.
Circuits match correctly.
Result: Circuits match uniquely.
Logging to file "/project/openlane/user_proj_example/runs/user_proj_example/results/lvs/user_proj_example.lvs.log" disabled
LVS Done.
user_proj_example/runs/user_proj_example/logs/routing/or_antenna.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 463 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
Notice 0: Design: user_proj_example
Notice 0:     Created 606 pins.
Notice 0:     Created 7118 components and 26841 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 604 nets and 288 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
Number of pins violated: 0
Number of nets violated: 0
Total number of nets: 604

Submodule: user_project_wrapper

user_project_wrapper/runs/user_project_wrapper/logs/synthesis/yosys.log

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v' to AST representation.
Generating RTLIL representation for module `\user_project_wrapper'.
Successfully finished Verilog frontend.

5. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/hierarchy.dot'.
Dumping module user_project_wrapper to page 1.

6. Executing HIERARCHY pass (managing design hierarchy).

6.1. Analyzing design hierarchy..
Top module:  \user_project_wrapper

6.2. Analyzing design hierarchy..
Top module:  \user_project_wrapper
Removed 0 unused modules.

7. Printing statistics.

=== user_project_wrapper ===

   Number of wires:                 18
   Number of wire bits:            636
   Number of public wires:          18
   Number of public wire bits:     636
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     user_proj_example               1

8. Executing SPLITNETS pass (splitting up multi-bit signals).

9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..

10. Executing CHECK pass (checking for obvious problems).
checking module user_project_wrapper..
found and reported 0 problems.

11. Printing statistics.

=== user_project_wrapper ===

   Number of wires:                 18
   Number of wire bits:            636
   Number of public wires:          18
   Number of public wire bits:     636
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     user_proj_example               1

   Area for cell type \user_proj_example is unknown!

12. Executing Verilog backend.
Dumping module `\user_project_wrapper'.

End of script. Logfile hash: 97b1761aab, CPU: user 0.11s system 0.03s, MEM: 13.07 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 64% 2x stat (0 sec), 12% 8x read_verilog (0 sec), ...
user_project_wrapper/runs/user_project_wrapper/logs/synthesis/opensta.log
OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v, line 22 module user_proj_example not found.  Creating black box for mprj.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
tns 0.00
wns 0.00
user_project_wrapper/runs/user_project_wrapper/logs/floorplan/verilog2def.openroad.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Warning: LEF master user_proj_example has no liberty cell.
Info: Added 1286 rows of 6323 sites.
user_project_wrapper/runs/user_project_wrapper/logs/floorplan/place_io_ol.log
Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: user_project_wrapper
Notice 0:     Created 636 pins.
Notice 0:     Created 1 components and 606 component-terminals.
Notice 0:     Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def
Top-level design name: user_project_wrapper
Block boundaries: 0 0 2920000 3520000
Writing /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
user_project_wrapper/runs/user_project_wrapper/logs/macro_placement.log
Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
Notice 0: Design: user_project_wrapper
Notice 0:     Created 1240 pins.
Notice 0:     Created 1 components and 606 component-terminals.
Notice 0:     Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
Placing the following macros:
{'mprj': ['1175000', '1700000', 'N']}
Design name: user_project_wrapper
Placing mprj
Successfully placed 1 instances
user_project_wrapper/runs/user_project_wrapper/logs/floorplan/tapcell.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def
Notice 0: Design: user_project_wrapper
Notice 0:     Created 644 pins.
Notice 0:     Created 1 components and 606 component-terminals.
Notice 0:     Created 644 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 1
[INFO] #Original rows: 1286
[INFO] #Cut rows: 118
Step 2: Insert endcaps...
[INFO] #Endcaps inserted: 2808
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 131884
Running tapcell... Done!
user_project_wrapper/runs/user_project_wrapper/logs/floorplan/pdn.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/floorplan/user_project_wrapper.floorplan.def
Notice 0: Design: user_project_wrapper
Notice 0: 		Created 100000 Insts
Notice 0:     Created 644 pins.
Notice 0:     Created 134693 components and 275606 component-terminals.
Notice 0:     Created 644 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/floorplan/user_project_wrapper.floorplan.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_project_wrapper
[INFO] [PDNG-0009] Reading technology data
[ERROR] [PDNG-0037] Cannot find pin VDD on instance mprj (user_proj_example)
[ERROR] [PDNG-0037] Cannot find pin vdd on instance mprj (user_proj_example)
[ERROR] [PDNG-0037] Cannot find pin VSS on instance mprj (user_proj_example)
[ERROR] [PDNG-0037] Cannot find pin gnd on instance mprj (user_proj_example)
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
    Core Rings
      Layer: met4 -  width: 3.000  spacing: 1.700  core_offset: 14.000 
      Layer: met5 -  width: 3.000  spacing: 1.700  core_offset: 14.000 
    Stdcell Rails
      Layer: met1 -  width: 0.480  pitch: 2.720  offset: 0.000 
    Straps
      Layer: met4 -  width: 3.000  pitch: 180.000  offset: 0.000 
      Layer: met5 -  width: 3.000  pitch: 180.000  offset: 0.000 
    Connect: {met1 met4} {met4 met5}
Type: macro, macro_1
    Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
    Straps
    Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[WARN] [PDNG-0041] No via added at (5.52 10.64 7.02 11.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 16.08 7.02 16.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 21.52 7.02 22.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 26.96 7.02 27.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 32.4 7.02 32.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 37.84 7.02 38.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 43.28 7.02 43.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 48.72 7.02 49.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 54.16 7.02 54.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 59.6 7.02 60.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 65.04 7.02 65.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 70.48 7.02 70.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 75.92 7.02 76.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 81.36 7.02 81.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 86.8 7.02 87.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 92.24 7.02 92.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 97.68 7.02 98.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 103.12 7.02 103.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 108.56 7.02 109.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 114.0 7.02 114.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 119.44 7.02 119.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 124.88 7.02 125.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 130.32 7.02 130.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 135.76 7.02 136.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 141.2 7.02 141.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 146.64 7.02 147.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 152.08 7.02 152.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 157.52 7.02 158.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 162.96 7.02 163.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 168.4 7.02 168.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 173.84 7.02 174.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 179.28 7.02 179.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 184.72 7.02 185.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 190.16 7.02 190.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 195.6 7.02 196.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 201.04 7.02 201.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 206.48 7.02 206.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 211.92 7.02 212.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 217.36 7.02 217.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 222.8 7.02 223.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 228.24 7.02 228.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 233.68 7.02 234.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 239.12 7.02 239.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 244.56 7.02 245.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 250.0 7.02 250.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 255.44 7.02 255.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 260.88 7.02 261.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 266.32 7.02 266.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 271.76 7.02 272.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 277.2 7.02 277.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 282.64 7.02 283.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 288.08 7.02 288.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 293.52 7.02 294.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 298.96 7.02 299.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 304.4 7.02 304.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 309.84 7.02 310.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 315.28 7.02 315.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 320.72 7.02 321.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 326.16 7.02 326.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 331.6 7.02 332.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 337.04 7.02 337.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 342.48 7.02 342.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 347.92 7.02 348.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 353.36 7.02 353.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 358.8 7.02 359.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 364.24 7.02 364.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 369.68 7.02 370.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 375.12 7.02 375.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 380.56 7.02 381.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 386.0 7.02 386.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 391.44 7.02 391.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 396.88 7.02 397.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 402.32 7.02 402.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 407.76 7.02 408.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 413.2 7.02 413.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 418.64 7.02 419.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 424.08 7.02 424.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 429.52 7.02 430.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 434.96 7.02 435.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 440.4 7.02 440.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 445.84 7.02 446.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 451.28 7.02 451.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 456.72 7.02 457.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 462.16 7.02 462.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 467.6 7.02 468.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 473.04 7.02 473.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 478.48 7.02 478.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 483.92 7.02 484.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 489.36 7.02 489.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 494.8 7.02 495.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 500.24 7.02 500.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 505.68 7.02 506.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 511.12 7.02 511.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 516.56 7.02 517.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 522.0 7.02 522.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 527.44 7.02 527.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 532.88 7.02 533.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 538.32 7.02 538.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 543.76 7.02 544.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 549.2 7.02 549.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 554.64 7.02 555.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 560.08 7.02 560.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 565.52 7.02 566.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 570.96 7.02 571.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 576.4 7.02 576.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 581.84 7.02 582.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 587.28 7.02 587.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 592.72 7.02 593.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 598.16 7.02 598.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 603.6 7.02 604.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 609.04 7.02 609.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 614.48 7.02 614.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 619.92 7.02 620.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 625.36 7.02 625.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 630.8 7.02 631.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 636.24 7.02 636.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 641.68 7.02 642.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 647.12 7.02 647.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 652.56 7.02 653.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 658.0 7.02 658.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 663.44 7.02 663.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 668.88 7.02 669.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 674.32 7.02 674.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 679.76 7.02 680.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 685.2 7.02 685.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 690.64 7.02 691.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 696.08 7.02 696.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 701.52 7.02 702.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 706.96 7.02 707.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 712.4 7.02 712.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 717.84 7.02 718.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 723.28 7.02 723.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 728.72 7.02 729.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 734.16 7.02 734.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 739.6 7.02 740.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 745.04 7.02 745.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 750.48 7.02 750.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 755.92 7.02 756.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 761.36 7.02 761.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 766.8 7.02 767.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 772.24 7.02 772.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 777.68 7.02 778.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 783.12 7.02 783.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 788.56 7.02 789.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 794.0 7.02 794.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 799.44 7.02 799.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 804.88 7.02 805.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 810.32 7.02 810.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 815.76 7.02 816.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 821.2 7.02 821.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 826.64 7.02 827.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 832.08 7.02 832.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 837.52 7.02 838.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 842.96 7.02 843.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 848.4 7.02 848.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 853.84 7.02 854.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 859.28 7.02 859.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 864.72 7.02 865.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 870.16 7.02 870.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 875.6 7.02 876.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 881.04 7.02 881.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 886.48 7.02 886.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 891.92 7.02 892.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 897.36 7.02 897.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 902.8 7.02 903.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 908.24 7.02 908.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 913.68 7.02 914.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 919.12 7.02 919.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 924.56 7.02 925.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 930.0 7.02 930.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 935.44 7.02 935.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 940.88 7.02 941.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 946.32 7.02 946.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 951.76 7.02 952.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 957.2 7.02 957.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 962.64 7.02 963.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 968.08 7.02 968.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 973.52 7.02 974.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 978.96 7.02 979.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 984.4 7.02 984.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 989.84 7.02 990.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 995.28 7.02 995.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1000.72 7.02 1001.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1006.16 7.02 1006.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1011.6 7.02 1012.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1017.04 7.02 1017.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1022.48 7.02 1022.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1027.92 7.02 1028.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1033.36 7.02 1033.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1038.8 7.02 1039.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1044.24 7.02 1044.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1049.68 7.02 1050.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1055.12 7.02 1055.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1060.56 7.02 1061.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1066.0 7.02 1066.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1071.44 7.02 1071.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1076.88 7.02 1077.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1082.32 7.02 1082.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1087.76 7.02 1088.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1093.2 7.02 1093.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1098.64 7.02 1099.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1104.08 7.02 1104.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1109.52 7.02 1110.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1114.96 7.02 1115.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1120.4 7.02 1120.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1125.84 7.02 1126.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1131.28 7.02 1131.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1136.72 7.02 1137.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1142.16 7.02 1142.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1147.6 7.02 1148.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1153.04 7.02 1153.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1158.48 7.02 1158.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1163.92 7.02 1164.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1169.36 7.02 1169.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1174.8 7.02 1175.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1180.24 7.02 1180.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1185.68 7.02 1186.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1191.12 7.02 1191.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1196.56 7.02 1197.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1202.0 7.02 1202.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1207.44 7.02 1207.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1212.88 7.02 1213.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1218.32 7.02 1218.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1223.76 7.02 1224.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1229.2 7.02 1229.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1234.64 7.02 1235.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1240.08 7.02 1240.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1245.52 7.02 1246.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1250.96 7.02 1251.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1256.4 7.02 1256.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1261.84 7.02 1262.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1267.28 7.02 1267.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1272.72 7.02 1273.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1278.16 7.02 1278.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1283.6 7.02 1284.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1289.04 7.02 1289.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1294.48 7.02 1294.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1299.92 7.02 1300.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1305.36 7.02 1305.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1310.8 7.02 1311.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1316.24 7.02 1316.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1321.68 7.02 1322.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1327.12 7.02 1327.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1332.56 7.02 1333.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1338.0 7.02 1338.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1343.44 7.02 1343.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1348.88 7.02 1349.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1354.32 7.02 1354.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1359.76 7.02 1360.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1365.2 7.02 1365.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1370.64 7.02 1371.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1376.08 7.02 1376.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1381.52 7.02 1382.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1386.96 7.02 1387.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1392.4 7.02 1392.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1397.84 7.02 1398.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1403.28 7.02 1403.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1408.72 7.02 1409.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1414.16 7.02 1414.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1419.6 7.02 1420.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1425.04 7.02 1425.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1430.48 7.02 1430.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1435.92 7.02 1436.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1441.36 7.02 1441.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1446.8 7.02 1447.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1452.24 7.02 1452.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1457.68 7.02 1458.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1463.12 7.02 1463.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1468.56 7.02 1469.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1474.0 7.02 1474.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1479.44 7.02 1479.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1484.88 7.02 1485.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1490.32 7.02 1490.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1495.76 7.02 1496.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1501.2 7.02 1501.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1506.64 7.02 1507.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1512.08 7.02 1512.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1517.52 7.02 1518.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1522.96 7.02 1523.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1528.4 7.02 1528.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1533.84 7.02 1534.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1539.28 7.02 1539.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1544.72 7.02 1545.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1550.16 7.02 1550.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1555.6 7.02 1556.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1561.04 7.02 1561.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1566.48 7.02 1566.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1571.92 7.02 1572.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1577.36 7.02 1577.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1582.8 7.02 1583.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1588.24 7.02 1588.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1593.68 7.02 1594.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1599.12 7.02 1599.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1604.56 7.02 1605.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1610.0 7.02 1610.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1615.44 7.02 1615.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1620.88 7.02 1621.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1626.32 7.02 1626.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1631.76 7.02 1632.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1637.2 7.02 1637.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1642.64 7.02 1643.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1648.08 7.02 1648.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1653.52 7.02 1654.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1658.96 7.02 1659.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1664.4 7.02 1664.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1669.84 7.02 1670.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1675.28 7.02 1675.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1680.72 7.02 1681.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1686.16 7.02 1686.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1691.6 7.02 1692.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1697.04 7.02 1697.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1702.48 7.02 1702.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1707.92 7.02 1708.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1713.36 7.02 1713.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1718.8 7.02 1719.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1724.24 7.02 1724.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1729.68 7.02 1730.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1735.12 7.02 1735.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1740.56 7.02 1741.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1746.0 7.02 1746.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1751.44 7.02 1751.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1756.88 7.02 1757.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1762.32 7.02 1762.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1767.76 7.02 1768.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1773.2 7.02 1773.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1778.64 7.02 1779.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1784.08 7.02 1784.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1789.52 7.02 1790.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1794.96 7.02 1795.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1800.4 7.02 1800.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1805.84 7.02 1806.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1811.28 7.02 1811.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1816.72 7.02 1817.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1822.16 7.02 1822.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1827.6 7.02 1828.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1833.04 7.02 1833.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1838.48 7.02 1838.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1843.92 7.02 1844.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1849.36 7.02 1849.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1854.8 7.02 1855.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1860.24 7.02 1860.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1865.68 7.02 1866.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1871.12 7.02 1871.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1876.56 7.02 1877.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1882.0 7.02 1882.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1887.44 7.02 1887.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1892.88 7.02 1893.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1898.32 7.02 1898.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1903.76 7.02 1904.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1909.2 7.02 1909.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1914.64 7.02 1915.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1920.08 7.02 1920.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1925.52 7.02 1926.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1930.96 7.02 1931.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1936.4 7.02 1936.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1941.84 7.02 1942.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1947.28 7.02 1947.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1952.72 7.02 1953.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1958.16 7.02 1958.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1963.6 7.02 1964.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1969.04 7.02 1969.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1974.48 7.02 1974.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1979.92 7.02 1980.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1985.36 7.02 1985.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1990.8 7.02 1991.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1996.24 7.02 1996.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2001.68 7.02 2002.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2007.12 7.02 2007.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2012.56 7.02 2013.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2018.0 7.02 2018.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2023.44 7.02 2023.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2028.88 7.02 2029.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2034.32 7.02 2034.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2039.76 7.02 2040.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2045.2 7.02 2045.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2050.64 7.02 2051.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2056.08 7.02 2056.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2061.52 7.02 2062.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2066.96 7.02 2067.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2072.4 7.02 2072.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2077.84 7.02 2078.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2083.28 7.02 2083.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2088.72 7.02 2089.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2094.16 7.02 2094.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2099.6 7.02 2100.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2105.04 7.02 2105.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2110.48 7.02 2110.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2115.92 7.02 2116.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2121.36 7.02 2121.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2126.8 7.02 2127.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2132.24 7.02 2132.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2137.68 7.02 2138.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2143.12 7.02 2143.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2148.56 7.02 2149.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2154.0 7.02 2154.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2159.44 7.02 2159.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2164.88 7.02 2165.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2170.32 7.02 2170.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2175.76 7.02 2176.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2181.2 7.02 2181.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2186.64 7.02 2187.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2192.08 7.02 2192.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2197.52 7.02 2198.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2202.96 7.02 2203.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2208.4 7.02 2208.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2213.84 7.02 2214.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2219.28 7.02 2219.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2224.72 7.02 2225.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2230.16 7.02 2230.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2235.6 7.02 2236.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2241.04 7.02 2241.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2246.48 7.02 2246.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2251.92 7.02 2252.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2257.36 7.02 2257.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2262.8 7.02 2263.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2268.24 7.02 2268.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2273.68 7.02 2274.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2279.12 7.02 2279.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2284.56 7.02 2285.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2290.0 7.02 2290.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2295.44 7.02 2295.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2300.88 7.02 2301.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2306.32 7.02 2306.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2311.76 7.02 2312.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2317.2 7.02 2317.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2322.64 7.02 2323.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2328.08 7.02 2328.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2333.52 7.02 2334.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2338.96 7.02 2339.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2344.4 7.02 2344.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2349.84 7.02 2350.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2355.28 7.02 2355.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2360.72 7.02 2361.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2366.16 7.02 2366.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2371.6 7.02 2372.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2377.04 7.02 2377.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2382.48 7.02 2382.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2387.92 7.02 2388.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2393.36 7.02 2393.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2398.8 7.02 2399.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2404.24 7.02 2404.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2409.68 7.02 2410.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2415.12 7.02 2415.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2420.56 7.02 2421.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2426.0 7.02 2426.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2431.44 7.02 2431.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2436.88 7.02 2437.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2442.32 7.02 2442.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2447.76 7.02 2448.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2453.2 7.02 2453.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2458.64 7.02 2459.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2464.08 7.02 2464.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2469.52 7.02 2470.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2474.96 7.02 2475.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2480.4 7.02 2480.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2485.84 7.02 2486.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2491.28 7.02 2491.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2496.72 7.02 2497.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2502.16 7.02 2502.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2507.6 7.02 2508.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2513.04 7.02 2513.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2518.48 7.02 2518.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2523.92 7.02 2524.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2529.36 7.02 2529.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2534.8 7.02 2535.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2540.24 7.02 2540.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2545.68 7.02 2546.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2551.12 7.02 2551.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2556.56 7.02 2557.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2562.0 7.02 2562.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2567.44 7.02 2567.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2572.88 7.02 2573.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2578.32 7.02 2578.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2583.76 7.02 2584.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2589.2 7.02 2589.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2594.64 7.02 2595.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2600.08 7.02 2600.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2605.52 7.02 2606.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2610.96 7.02 2611.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2616.4 7.02 2616.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2621.84 7.02 2622.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2627.28 7.02 2627.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2632.72 7.02 2633.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2638.16 7.02 2638.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2643.6 7.02 2644.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2649.04 7.02 2649.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2654.48 7.02 2654.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2659.92 7.02 2660.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2665.36 7.02 2665.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2670.8 7.02 2671.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2676.24 7.02 2676.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2681.68 7.02 2682.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2687.12 7.02 2687.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2692.56 7.02 2693.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2698.0 7.02 2698.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2703.44 7.02 2703.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2708.88 7.02 2709.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2714.32 7.02 2714.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2719.76 7.02 2720.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2725.2 7.02 2725.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2730.64 7.02 2731.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2736.08 7.02 2736.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2741.52 7.02 2742.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2746.96 7.02 2747.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2752.4 7.02 2752.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2757.84 7.02 2758.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2763.28 7.02 2763.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2768.72 7.02 2769.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2774.16 7.02 2774.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2779.6 7.02 2780.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2785.04 7.02 2785.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2790.48 7.02 2790.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2795.92 7.02 2796.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2801.36 7.02 2801.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2806.8 7.02 2807.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2812.24 7.02 2812.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2817.68 7.02 2818.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2823.12 7.02 2823.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2828.56 7.02 2829.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2834.0 7.02 2834.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2839.44 7.02 2839.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2844.88 7.02 2845.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2850.32 7.02 2850.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2855.76 7.02 2856.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2861.2 7.02 2861.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2866.64 7.02 2867.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2872.08 7.02 2872.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2877.52 7.02 2878.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2882.96 7.02 2883.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2888.4 7.02 2888.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2893.84 7.02 2894.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2899.28 7.02 2899.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2904.72 7.02 2905.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2910.16 7.02 2910.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2915.6 7.02 2916.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2921.04 7.02 2921.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2926.48 7.02 2926.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2931.92 7.02 2932.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2937.36 7.02 2937.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2942.8 7.02 2943.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2948.24 7.02 2948.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2953.68 7.02 2954.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2959.12 7.02 2959.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2964.56 7.02 2965.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2970.0 7.02 2970.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2975.44 7.02 2975.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2980.88 7.02 2981.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2986.32 7.02 2986.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2991.76 7.02 2992.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2997.2 7.02 2997.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3002.64 7.02 3003.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3008.08 7.02 3008.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3013.52 7.02 3014.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3018.96 7.02 3019.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3024.4 7.02 3024.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3029.84 7.02 3030.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3035.28 7.02 3035.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3040.72 7.02 3041.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3046.16 7.02 3046.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3051.6 7.02 3052.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3057.04 7.02 3057.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3062.48 7.02 3062.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3067.92 7.02 3068.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3073.36 7.02 3073.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3078.8 7.02 3079.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3084.24 7.02 3084.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3089.68 7.02 3090.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3095.12 7.02 3095.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3100.56 7.02 3101.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3106.0 7.02 3106.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3111.44 7.02 3111.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3116.88 7.02 3117.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3122.32 7.02 3122.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3127.76 7.02 3128.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3133.2 7.02 3133.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3138.64 7.02 3139.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3144.08 7.02 3144.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3149.52 7.02 3150.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3154.96 7.02 3155.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3160.4 7.02 3160.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3165.84 7.02 3166.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3171.28 7.02 3171.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3176.72 7.02 3177.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3182.16 7.02 3182.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3187.6 7.02 3188.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3193.04 7.02 3193.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3198.48 7.02 3198.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3203.92 7.02 3204.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3209.36 7.02 3209.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3214.8 7.02 3215.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3220.24 7.02 3220.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3225.68 7.02 3226.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3231.12 7.02 3231.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3236.56 7.02 3237.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3242.0 7.02 3242.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3247.44 7.02 3247.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3252.88 7.02 3253.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3258.32 7.02 3258.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3263.76 7.02 3264.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3269.2 7.02 3269.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3274.64 7.02 3275.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3280.08 7.02 3280.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3285.52 7.02 3286.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3290.96 7.02 3291.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3296.4 7.02 3296.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3301.84 7.02 3302.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3307.28 7.02 3307.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3312.72 7.02 3313.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3318.16 7.02 3318.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3323.6 7.02 3324.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3329.04 7.02 3329.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3334.48 7.02 3334.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3339.92 7.02 3340.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3345.36 7.02 3345.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3350.8 7.02 3351.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3356.24 7.02 3356.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3361.68 7.02 3362.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3367.12 7.02 3367.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3372.56 7.02 3373.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3378.0 7.02 3378.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3383.44 7.02 3383.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3388.88 7.02 3389.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3394.32 7.02 3394.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3399.76 7.02 3400.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3405.2 7.02 3405.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3410.64 7.02 3411.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3416.08 7.02 3416.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3421.52 7.02 3422.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3426.96 7.02 3427.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3432.4 7.02 3432.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3437.84 7.02 3438.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3443.28 7.02 3443.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3448.72 7.02 3449.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3454.16 7.02 3454.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3459.6 7.02 3460.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3465.04 7.02 3465.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3470.48 7.02 3470.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3475.92 7.02 3476.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3481.36 7.02 3481.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3486.8 7.02 3487.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3492.24 7.02 3492.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3497.68 7.02 3498.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3503.12 7.02 3503.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3508.56 7.02 3509.04) because the full width of met4 (3.0) is not covered by the overlap
[INFO] [PDNG-0010] Inserting macro grid for 1 macros
[INFO] [PDNG-0034]   - grid for instance mprj
[INFO] [PDNG-0015] Writing to database
user_project_wrapper/runs/user_project_wrapper/logs/placement/replace.log
Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
Notice 0: Design: user_project_wrapper
Notice 0: 		Created 100000 Insts
Notice 0:     Created 646 pins.
Notice 0:     Created 134693 components and 275606 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 644 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
Design name: user_project_wrapper
Core Area Boundaries: 5520 10880 2914100 3508800
Number of instances 134693
Placed 0 instances
user_project_wrapper/runs/user_project_wrapper/logs/placement/opendp.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/placement/replace.def
Notice 0: Design: user_project_wrapper
Notice 0: 		Created 100000 Insts
Notice 0:     Created 646 pins.
Notice 0:     Created 134693 components and 275606 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 644 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/placement/replace.def
Design Stats
--------------------------------
total instances        134693
multi row instances         0
fixed instances        134693
nets                      646
design area          10173980.2 u^2
fixed area           179438.0 u^2
movable area              0.0 u^2
utilization                 0 %
utilization padded          0 %
rows                     1286
row height                2.7 u

Placement Analysis
--------------------------------
total displacement        0.0 u
average displacement      0.0 u
max displacement          0.0 u
original HPWL        1434198.3 u
legalized HPWL       1434198.3 u
delta HPWL                  0 %

user_project_wrapper/runs/user_project_wrapper/logs/cts/cts.log
SKIPPED!
user_project_wrapper/runs/user_project_wrapper/logs/routing/fastroute.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/placement/user_project_wrapper.placement.def
Notice 0: Design: user_project_wrapper
Notice 0: 		Created 100000 Insts
Notice 0:     Created 646 pins.
Notice 0:     Created 134693 components and 275606 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 644 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/placement/user_project_wrapper.placement.def
[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 6
[PARAMS] Global adjustment: 0
[PARAMS] Unidirectional routing: 1
[PARAMS] Grid origin: (-1, -1)
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 825280
[INFO] #DB Macros: 1
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VPWR has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[WARNING] Net VGND has wires outside die area
[INFO] Found 0 clock nets
[WARNING] Pin analog_io[0] is outside die area
[WARNING] Pin analog_io[10] is outside die area
[WARNING] Pin analog_io[11] is outside die area
[WARNING] Pin analog_io[12] is outside die area
[WARNING] Pin analog_io[13] is outside die area
[WARNING] Pin analog_io[14] is outside die area
[WARNING] Pin analog_io[15] is outside die area
[WARNING] Pin analog_io[16] is outside die area
[WARNING] Pin analog_io[17] is outside die area
[WARNING] Pin analog_io[18] is outside die area
[WARNING] Pin analog_io[19] is outside die area
[WARNING] Pin analog_io[1] is outside die area
[WARNING] Pin analog_io[20] is outside die area
[WARNING] Pin analog_io[21] is outside die area
[WARNING] Pin analog_io[22] is outside die area
[WARNING] Pin analog_io[23] is outside die area
[WARNING] Pin analog_io[24] is outside die area
[WARNING] Pin analog_io[25] is outside die area
[WARNING] Pin analog_io[26] is outside die area
[WARNING] Pin analog_io[27] is outside die area
[WARNING] Pin analog_io[28] is outside die area
[WARNING] Pin analog_io[29] is outside die area
[WARNING] Pin analog_io[2] is outside die area
[WARNING] Pin analog_io[30] is outside die area
[WARNING] Pin analog_io[3] is outside die area
[WARNING] Pin analog_io[4] is outside die area
[WARNING] Pin analog_io[5] is outside die area
[WARNING] Pin analog_io[6] is outside die area
[WARNING] Pin analog_io[7] is outside die area
[WARNING] Pin analog_io[8] is outside die area
[WARNING] Pin analog_io[9] is outside die area
[WARNING] Pin io_in[0] is outside die area
[WARNING] Pin io_in[10] is outside die area
[WARNING] Pin io_in[11] is outside die area
[WARNING] Pin io_in[12] is outside die area
[WARNING] Pin io_in[13] is outside die area
[WARNING] Pin io_in[14] is outside die area
[WARNING] Pin io_in[15] is outside die area
[WARNING] Pin io_in[16] is outside die area
[WARNING] Pin io_in[17] is outside die area
[WARNING] Pin io_in[18] is outside die area
[WARNING] Pin io_in[19] is outside die area
[WARNING] Pin io_in[1] is outside die area
[WARNING] Pin io_in[20] is outside die area
[WARNING] Pin io_in[21] is outside die area
[WARNING] Pin io_in[22] is outside die area
[WARNING] Pin io_in[23] is outside die area
[WARNING] Pin io_in[24] is outside die area
[WARNING] Pin io_in[25] is outside die area
[WARNING] Pin io_in[26] is outside die area
[WARNING] Pin io_in[27] is outside die area
[WARNING] Pin io_in[28] is outside die area
[WARNING] Pin io_in[29] is outside die area
[WARNING] Pin io_in[2] is outside die area
[WARNING] Pin io_in[30] is outside die area
[WARNING] Pin io_in[31] is outside die area
[WARNING] Pin io_in[32] is outside die area
[WARNING] Pin io_in[33] is outside die area
[WARNING] Pin io_in[34] is outside die area
[WARNING] Pin io_in[35] is outside die area
[WARNING] Pin io_in[36] is outside die area
[WARNING] Pin io_in[37] is outside die area
[WARNING] Pin io_in[3] is outside die area
[WARNING] Pin io_in[4] is outside die area
[WARNING] Pin io_in[5] is outside die area
[WARNING] Pin io_in[6] is outside die area
[WARNING] Pin io_in[7] is outside die area
[WARNING] Pin io_in[8] is outside die area
[WARNING] Pin io_in[9] is outside die area
[WARNING] Pin io_oeb[0] is outside die area
[WARNING] Pin io_oeb[10] is outside die area
[WARNING] Pin io_oeb[11] is outside die area
[WARNING] Pin io_oeb[12] is outside die area
[WARNING] Pin io_oeb[13] is outside die area
[WARNING] Pin io_oeb[14] is outside die area
[WARNING] Pin io_oeb[15] is outside die area
[WARNING] Pin io_oeb[16] is outside die area
[WARNING] Pin io_oeb[17] is outside die area
[WARNING] Pin io_oeb[18] is outside die area
[WARNING] Pin io_oeb[19] is outside die area
[WARNING] Pin io_oeb[1] is outside die area
[WARNING] Pin io_oeb[20] is outside die area
[WARNING] Pin io_oeb[21] is outside die area
[WARNING] Pin io_oeb[22] is outside die area
[WARNING] Pin io_oeb[23] is outside die area
[WARNING] Pin io_oeb[24] is outside die area
[WARNING] Pin io_oeb[25] is outside die area
[WARNING] Pin io_oeb[26] is outside die area
[WARNING] Pin io_oeb[27] is outside die area
[WARNING] Pin io_oeb[28] is outside die area
[WARNING] Pin io_oeb[29] is outside die area
[WARNING] Pin io_oeb[2] is outside die area
[WARNING] Pin io_oeb[30] is outside die area
[WARNING] Pin io_oeb[31] is outside die area
[WARNING] Pin io_oeb[32] is outside die area
[WARNING] Pin io_oeb[33] is outside die area
[WARNING] Pin io_oeb[34] is outside die area
[WARNING] Pin io_oeb[35] is outside die area
[WARNING] Pin io_oeb[36] is outside die area
[WARNING] Pin io_oeb[37] is outside die area
[WARNING] Pin io_oeb[3] is outside die area
[WARNING] Pin io_oeb[4] is outside die area
[WARNING] Pin io_oeb[5] is outside die area
[WARNING] Pin io_oeb[6] is outside die area
[WARNING] Pin io_oeb[7] is outside die area
[WARNING] Pin io_oeb[8] is outside die area
[WARNING] Pin io_oeb[9] is outside die area
[WARNING] Pin io_out[0] is outside die area
[WARNING] Pin io_out[10] is outside die area
[WARNING] Pin io_out[11] is outside die area
[WARNING] Pin io_out[12] is outside die area
[WARNING] Pin io_out[13] is outside die area
[WARNING] Pin io_out[14] is outside die area
[WARNING] Pin io_out[15] is outside die area
[WARNING] Pin io_out[16] is outside die area
[WARNING] Pin io_out[17] is outside die area
[WARNING] Pin io_out[18] is outside die area
[WARNING] Pin io_out[19] is outside die area
[WARNING] Pin io_out[1] is outside die area
[WARNING] Pin io_out[20] is outside die area
[WARNING] Pin io_out[21] is outside die area
[WARNING] Pin io_out[22] is outside die area
[WARNING] Pin io_out[23] is outside die area
[WARNING] Pin io_out[24] is outside die area
[WARNING] Pin io_out[25] is outside die area
[WARNING] Pin io_out[26] is outside die area
[WARNING] Pin io_out[27] is outside die area
[WARNING] Pin io_out[28] is outside die area
[WARNING] Pin io_out[29] is outside die area
[WARNING] Pin io_out[2] is outside die area
[WARNING] Pin io_out[30] is outside die area
[WARNING] Pin io_out[31] is outside die area
[WARNING] Pin io_out[32] is outside die area
[WARNING] Pin io_out[33] is outside die area
[WARNING] Pin io_out[34] is outside die area
[WARNING] Pin io_out[35] is outside die area
[WARNING] Pin io_out[36] is outside die area
[WARNING] Pin io_out[37] is outside die area
[WARNING] Pin io_out[3] is outside die area
[WARNING] Pin io_out[4] is outside die area
[WARNING] Pin io_out[5] is outside die area
[WARNING] Pin io_out[6] is outside die area
[WARNING] Pin io_out[7] is outside die area
[WARNING] Pin io_out[8] is outside die area
[WARNING] Pin io_out[9] is outside die area
[WARNING] Pin la_data_in[0] is outside die area
[WARNING] Pin la_data_in[100] is outside die area
[WARNING] Pin la_data_in[101] is outside die area
[WARNING] Pin la_data_in[102] is outside die area
[WARNING] Pin la_data_in[103] is outside die area
[WARNING] Pin la_data_in[104] is outside die area
[WARNING] Pin la_data_in[105] is outside die area
[WARNING] Pin la_data_in[106] is outside die area
[WARNING] Pin la_data_in[107] is outside die area
[WARNING] Pin la_data_in[108] is outside die area
[WARNING] Pin la_data_in[109] is outside die area
[WARNING] Pin la_data_in[10] is outside die area
[WARNING] Pin la_data_in[110] is outside die area
[WARNING] Pin la_data_in[111] is outside die area
[WARNING] Pin la_data_in[112] is outside die area
[WARNING] Pin la_data_in[113] is outside die area
[WARNING] Pin la_data_in[114] is outside die area
[WARNING] Pin la_data_in[115] is outside die area
[WARNING] Pin la_data_in[116] is outside die area
[WARNING] Pin la_data_in[117] is outside die area
[WARNING] Pin la_data_in[118] is outside die area
[WARNING] Pin la_data_in[119] is outside die area
[WARNING] Pin la_data_in[11] is outside die area
[WARNING] Pin la_data_in[120] is outside die area
[WARNING] Pin la_data_in[121] is outside die area
[WARNING] Pin la_data_in[122] is outside die area
[WARNING] Pin la_data_in[123] is outside die area
[WARNING] Pin la_data_in[124] is outside die area
[WARNING] Pin la_data_in[125] is outside die area
[WARNING] Pin la_data_in[126] is outside die area
[WARNING] Pin la_data_in[127] is outside die area
[WARNING] Pin la_data_in[12] is outside die area
[WARNING] Pin la_data_in[13] is outside die area
[WARNING] Pin la_data_in[14] is outside die area
[WARNING] Pin la_data_in[15] is outside die area
[WARNING] Pin la_data_in[16] is outside die area
[WARNING] Pin la_data_in[17] is outside die area
[WARNING] Pin la_data_in[18] is outside die area
[WARNING] Pin la_data_in[19] is outside die area
[WARNING] Pin la_data_in[1] is outside die area
[WARNING] Pin la_data_in[20] is outside die area
[WARNING] Pin la_data_in[21] is outside die area
[WARNING] Pin la_data_in[22] is outside die area
[WARNING] Pin la_data_in[23] is outside die area
[WARNING] Pin la_data_in[24] is outside die area
[WARNING] Pin la_data_in[25] is outside die area
[WARNING] Pin la_data_in[26] is outside die area
[WARNING] Pin la_data_in[27] is outside die area
[WARNING] Pin la_data_in[28] is outside die area
[WARNING] Pin la_data_in[29] is outside die area
[WARNING] Pin la_data_in[2] is outside die area
[WARNING] Pin la_data_in[30] is outside die area
[WARNING] Pin la_data_in[31] is outside die area
[WARNING] Pin la_data_in[32] is outside die area
[WARNING] Pin la_data_in[33] is outside die area
[WARNING] Pin la_data_in[34] is outside die area
[WARNING] Pin la_data_in[35] is outside die area
[WARNING] Pin la_data_in[36] is outside die area
[WARNING] Pin la_data_in[37] is outside die area
[WARNING] Pin la_data_in[38] is outside die area
[WARNING] Pin la_data_in[39] is outside die area
[WARNING] Pin la_data_in[3] is outside die area
[WARNING] Pin la_data_in[40] is outside die area
[WARNING] Pin la_data_in[41] is outside die area
[WARNING] Pin la_data_in[42] is outside die area
[WARNING] Pin la_data_in[43] is outside die area
[WARNING] Pin la_data_in[44] is outside die area
[WARNING] Pin la_data_in[45] is outside die area
[WARNING] Pin la_data_in[46] is outside die area
[WARNING] Pin la_data_in[47] is outside die area
[WARNING] Pin la_data_in[48] is outside die area
[WARNING] Pin la_data_in[49] is outside die area
[WARNING] Pin la_data_in[4] is outside die area
[WARNING] Pin la_data_in[50] is outside die area
[WARNING] Pin la_data_in[51] is outside die area
[WARNING] Pin la_data_in[52] is outside die area
[WARNING] Pin la_data_in[53] is outside die area
[WARNING] Pin la_data_in[54] is outside die area
[WARNING] Pin la_data_in[55] is outside die area
[WARNING] Pin la_data_in[56] is outside die area
[WARNING] Pin la_data_in[57] is outside die area
[WARNING] Pin la_data_in[58] is outside die area
[WARNING] Pin la_data_in[59] is outside die area
[WARNING] Pin la_data_in[5] is outside die area
[WARNING] Pin la_data_in[60] is outside die area
[WARNING] Pin la_data_in[61] is outside die area
[WARNING] Pin la_data_in[62] is outside die area
[WARNING] Pin la_data_in[63] is outside die area
[WARNING] Pin la_data_in[64] is outside die area
[WARNING] Pin la_data_in[65] is outside die area
[WARNING] Pin la_data_in[66] is outside die area
[WARNING] Pin la_data_in[67] is outside die area
[WARNING] Pin la_data_in[68] is outside die area
[WARNING] Pin la_data_in[69] is outside die area
[WARNING] Pin la_data_in[6] is outside die area
[WARNING] Pin la_data_in[70] is outside die area
[WARNING] Pin la_data_in[71] is outside die area
[WARNING] Pin la_data_in[72] is outside die area
[WARNING] Pin la_data_in[73] is outside die area
[WARNING] Pin la_data_in[74] is outside die area
[WARNING] Pin la_data_in[75] is outside die area
[WARNING] Pin la_data_in[76] is outside die area
[WARNING] Pin la_data_in[77] is outside die area
[WARNING] Pin la_data_in[78] is outside die area
[WARNING] Pin la_data_in[79] is outside die area
[WARNING] Pin la_data_in[7] is outside die area
[WARNING] Pin la_data_in[80] is outside die area
[WARNING] Pin la_data_in[81] is outside die area
[WARNING] Pin la_data_in[82] is outside die area
[WARNING] Pin la_data_in[83] is outside die area
[WARNING] Pin la_data_in[84] is outside die area
[WARNING] Pin la_data_in[85] is outside die area
[WARNING] Pin la_data_in[86] is outside die area
[WARNING] Pin la_data_in[87] is outside die area
[WARNING] Pin la_data_in[88] is outside die area
[WARNING] Pin la_data_in[89] is outside die area
[WARNING] Pin la_data_in[8] is outside die area
[WARNING] Pin la_data_in[90] is outside die area
[WARNING] Pin la_data_in[91] is outside die area
[WARNING] Pin la_data_in[92] is outside die area
[WARNING] Pin la_data_in[93] is outside die area
[WARNING] Pin la_data_in[94] is outside die area
[WARNING] Pin la_data_in[95] is outside die area
[WARNING] Pin la_data_in[96] is outside die area
[WARNING] Pin la_data_in[97] is outside die area
[WARNING] Pin la_data_in[98] is outside die area
[WARNING] Pin la_data_in[99] is outside die area
[WARNING] Pin la_data_in[9] is outside die area
[WARNING] Pin la_data_out[0] is outside die area
[WARNING] Pin la_data_out[100] is outside die area
[WARNING] Pin la_data_out[101] is outside die area
[WARNING] Pin la_data_out[102] is outside die area
[WARNING] Pin la_data_out[103] is outside die area
[WARNING] Pin la_data_out[104] is outside die area
[WARNING] Pin la_data_out[105] is outside die area
[WARNING] Pin la_data_out[106] is outside die area
[WARNING] Pin la_data_out[107] is outside die area
[WARNING] Pin la_data_out[108] is outside die area
[WARNING] Pin la_data_out[109] is outside die area
[WARNING] Pin la_data_out[10] is outside die area
[WARNING] Pin la_data_out[110] is outside die area
[WARNING] Pin la_data_out[111] is outside die area
[WARNING] Pin la_data_out[112] is outside die area
[WARNING] Pin la_data_out[113] is outside die area
[WARNING] Pin la_data_out[114] is outside die area
[WARNING] Pin la_data_out[115] is outside die area
[WARNING] Pin la_data_out[116] is outside die area
[WARNING] Pin la_data_out[117] is outside die area
[WARNING] Pin la_data_out[118] is outside die area
[WARNING] Pin la_data_out[119] is outside die area
[WARNING] Pin la_data_out[11] is outside die area
[WARNING] Pin la_data_out[120] is outside die area
[WARNING] Pin la_data_out[121] is outside die area
[WARNING] Pin la_data_out[122] is outside die area
[WARNING] Pin la_data_out[123] is outside die area
[WARNING] Pin la_data_out[124] is outside die area
[WARNING] Pin la_data_out[125] is outside die area
[WARNING] Pin la_data_out[126] is outside die area
[WARNING] Pin la_data_out[127] is outside die area
[WARNING] Pin la_data_out[12] is outside die area
[WARNING] Pin la_data_out[13] is outside die area
[WARNING] Pin la_data_out[14] is outside die area
[WARNING] Pin la_data_out[15] is outside die area
[WARNING] Pin la_data_out[16] is outside die area
[WARNING] Pin la_data_out[17] is outside die area
[WARNING] Pin la_data_out[18] is outside die area
[WARNING] Pin la_data_out[19] is outside die area
[WARNING] Pin la_data_out[1] is outside die area
[WARNING] Pin la_data_out[20] is outside die area
[WARNING] Pin la_data_out[21] is outside die area
[WARNING] Pin la_data_out[22] is outside die area
[WARNING] Pin la_data_out[23] is outside die area
[WARNING] Pin la_data_out[24] is outside die area
[WARNING] Pin la_data_out[25] is outside die area
[WARNING] Pin la_data_out[26] is outside die area
[WARNING] Pin la_data_out[27] is outside die area
[WARNING] Pin la_data_out[28] is outside die area
[WARNING] Pin la_data_out[29] is outside die area
[WARNING] Pin la_data_out[2] is outside die area
[WARNING] Pin la_data_out[30] is outside die area
[WARNING] Pin la_data_out[31] is outside die area
[WARNING] Pin la_data_out[32] is outside die area
[WARNING] Pin la_data_out[33] is outside die area
[WARNING] Pin la_data_out[34] is outside die area
[WARNING] Pin la_data_out[35] is outside die area
[WARNING] Pin la_data_out[36] is outside die area
[WARNING] Pin la_data_out[37] is outside die area
[WARNING] Pin la_data_out[38] is outside die area
[WARNING] Pin la_data_out[39] is outside die area
[WARNING] Pin la_data_out[3] is outside die area
[WARNING] Pin la_data_out[40] is outside die area
[WARNING] Pin la_data_out[41] is outside die area
[WARNING] Pin la_data_out[42] is outside die area
[WARNING] Pin la_data_out[43] is outside die area
[WARNING] Pin la_data_out[44] is outside die area
[WARNING] Pin la_data_out[45] is outside die area
[WARNING] Pin la_data_out[46] is outside die area
[WARNING] Pin la_data_out[47] is outside die area
[WARNING] Pin la_data_out[48] is outside die area
[WARNING] Pin la_data_out[49] is outside die area
[WARNING] Pin la_data_out[4] is outside die area
[WARNING] Pin la_data_out[50] is outside die area
[WARNING] Pin la_data_out[51] is outside die area
[WARNING] Pin la_data_out[52] is outside die area
[WARNING] Pin la_data_out[53] is outside die area
[WARNING] Pin la_data_out[54] is outside die area
[WARNING] Pin la_data_out[55] is outside die area
[WARNING] Pin la_data_out[56] is outside die area
[WARNING] Pin la_data_out[57] is outside die area
[WARNING] Pin la_data_out[58] is outside die area
[WARNING] Pin la_data_out[59] is outside die area
[WARNING] Pin la_data_out[5] is outside die area
[WARNING] Pin la_data_out[60] is outside die area
[WARNING] Pin la_data_out[61] is outside die area
[WARNING] Pin la_data_out[62] is outside die area
[WARNING] Pin la_data_out[63] is outside die area
[WARNING] Pin la_data_out[64] is outside die area
[WARNING] Pin la_data_out[65] is outside die area
[WARNING] Pin la_data_out[66] is outside die area
[WARNING] Pin la_data_out[67] is outside die area
[WARNING] Pin la_data_out[68] is outside die area
[WARNING] Pin la_data_out[69] is outside die area
[WARNING] Pin la_data_out[6] is outside die area
[WARNING] Pin la_data_out[70] is outside die area
[WARNING] Pin la_data_out[71] is outside die area
[WARNING] Pin la_data_out[72] is outside die area
[WARNING] Pin la_data_out[73] is outside die area
[WARNING] Pin la_data_out[74] is outside die area
[WARNING] Pin la_data_out[75] is outside die area
[WARNING] Pin la_data_out[76] is outside die area
[WARNING] Pin la_data_out[77] is outside die area
[WARNING] Pin la_data_out[78] is outside die area
[WARNING] Pin la_data_out[79] is outside die area
[WARNING] Pin la_data_out[7] is outside die area
[WARNING] Pin la_data_out[80] is outside die area
[WARNING] Pin la_data_out[81] is outside die area
[WARNING] Pin la_data_out[82] is outside die area
[WARNING] Pin la_data_out[83] is outside die area
[WARNING] Pin la_data_out[84] is outside die area
[WARNING] Pin la_data_out[85] is outside die area
[WARNING] Pin la_data_out[86] is outside die area
[WARNING] Pin la_data_out[87] is outside die area
[WARNING] Pin la_data_out[88] is outside die area
[WARNING] Pin la_data_out[89] is outside die area
[WARNING] Pin la_data_out[8] is outside die area
[WARNING] Pin la_data_out[90] is outside die area
[WARNING] Pin la_data_out[91] is outside die area
[WARNING] Pin la_data_out[92] is outside die area
[WARNING] Pin la_data_out[93] is outside die area
[WARNING] Pin la_data_out[94] is outside die area
[WARNING] Pin la_data_out[95] is outside die area
[WARNING] Pin la_data_out[96] is outside die area
[WARNING] Pin la_data_out[97] is outside die area
[WARNING] Pin la_data_out[98] is outside die area
[WARNING] Pin la_data_out[99] is outside die area
[WARNING] Pin la_data_out[9] is outside die area
[WARNING] Pin la_oen[0] is outside die area
[WARNING] Pin la_oen[100] is outside die area
[WARNING] Pin la_oen[101] is outside die area
[WARNING] Pin la_oen[102] is outside die area
[WARNING] Pin la_oen[103] is outside die area
[WARNING] Pin la_oen[104] is outside die area
[WARNING] Pin la_oen[105] is outside die area
[WARNING] Pin la_oen[106] is outside die area
[WARNING] Pin la_oen[107] is outside die area
[WARNING] Pin la_oen[108] is outside die area
[WARNING] Pin la_oen[109] is outside die area
[WARNING] Pin la_oen[10] is outside die area
[WARNING] Pin la_oen[110] is outside die area
[WARNING] Pin la_oen[111] is outside die area
[WARNING] Pin la_oen[112] is outside die area
[WARNING] Pin la_oen[113] is outside die area
[WARNING] Pin la_oen[114] is outside die area
[WARNING] Pin la_oen[115] is outside die area
[WARNING] Pin la_oen[116] is outside die area
[WARNING] Pin la_oen[117] is outside die area
[WARNING] Pin la_oen[118] is outside die area
[WARNING] Pin la_oen[119] is outside die area
[WARNING] Pin la_oen[11] is outside die area
[WARNING] Pin la_oen[120] is outside die area
[WARNING] Pin la_oen[121] is outside die area
[WARNING] Pin la_oen[122] is outside die area
[WARNING] Pin la_oen[123] is outside die area
[WARNING] Pin la_oen[124] is outside die area
[WARNING] Pin la_oen[125] is outside die area
[WARNING] Pin la_oen[126] is outside die area
[WARNING] Pin la_oen[127] is outside die area
[WARNING] Pin la_oen[12] is outside die area
[WARNING] Pin la_oen[13] is outside die area
[WARNING] Pin la_oen[14] is outside die area
[WARNING] Pin la_oen[15] is outside die area
[WARNING] Pin la_oen[16] is outside die area
[WARNING] Pin la_oen[17] is outside die area
[WARNING] Pin la_oen[18] is outside die area
[WARNING] Pin la_oen[19] is outside die area
[WARNING] Pin la_oen[1] is outside die area
[WARNING] Pin la_oen[20] is outside die area
[WARNING] Pin la_oen[21] is outside die area
[WARNING] Pin la_oen[22] is outside die area
[WARNING] Pin la_oen[23] is outside die area
[WARNING] Pin la_oen[24] is outside die area
[WARNING] Pin la_oen[25] is outside die area
[WARNING] Pin la_oen[26] is outside die area
[WARNING] Pin la_oen[27] is outside die area
[WARNING] Pin la_oen[28] is outside die area
[WARNING] Pin la_oen[29] is outside die area
[WARNING] Pin la_oen[2] is outside die area
[WARNING] Pin la_oen[30] is outside die area
[WARNING] Pin la_oen[31] is outside die area
[WARNING] Pin la_oen[32] is outside die area
[WARNING] Pin la_oen[33] is outside die area
[WARNING] Pin la_oen[34] is outside die area
[WARNING] Pin la_oen[35] is outside die area
[WARNING] Pin la_oen[36] is outside die area
[WARNING] Pin la_oen[37] is outside die area
[WARNING] Pin la_oen[38] is outside die area
[WARNING] Pin la_oen[39] is outside die area
[WARNING] Pin la_oen[3] is outside die area
[WARNING] Pin la_oen[40] is outside die area
[WARNING] Pin la_oen[41] is outside die area
[WARNING] Pin la_oen[42] is outside die area
[WARNING] Pin la_oen[43] is outside die area
[WARNING] Pin la_oen[44] is outside die area
[WARNING] Pin la_oen[45] is outside die area
[WARNING] Pin la_oen[46] is outside die area
[WARNING] Pin la_oen[47] is outside die area
[WARNING] Pin la_oen[48] is outside die area
[WARNING] Pin la_oen[49] is outside die area
[WARNING] Pin la_oen[4] is outside die area
[WARNING] Pin la_oen[50] is outside die area
[WARNING] Pin la_oen[51] is outside die area
[WARNING] Pin la_oen[52] is outside die area
[WARNING] Pin la_oen[53] is outside die area
[WARNING] Pin la_oen[54] is outside die area
[WARNING] Pin la_oen[55] is outside die area
[WARNING] Pin la_oen[56] is outside die area
[WARNING] Pin la_oen[57] is outside die area
[WARNING] Pin la_oen[58] is outside die area
[WARNING] Pin la_oen[59] is outside die area
[WARNING] Pin la_oen[5] is outside die area
[WARNING] Pin la_oen[60] is outside die area
[WARNING] Pin la_oen[61] is outside die area
[WARNING] Pin la_oen[62] is outside die area
[WARNING] Pin la_oen[63] is outside die area
[WARNING] Pin la_oen[64] is outside die area
[WARNING] Pin la_oen[65] is outside die area
[WARNING] Pin la_oen[66] is outside die area
[WARNING] Pin la_oen[67] is outside die area
[WARNING] Pin la_oen[68] is outside die area
[WARNING] Pin la_oen[69] is outside die area
[WARNING] Pin la_oen[6] is outside die area
[WARNING] Pin la_oen[70] is outside die area
[WARNING] Pin la_oen[71] is outside die area
[WARNING] Pin la_oen[72] is outside die area
[WARNING] Pin la_oen[73] is outside die area
[WARNING] Pin la_oen[74] is outside die area
[WARNING] Pin la_oen[75] is outside die area
[WARNING] Pin la_oen[76] is outside die area
[WARNING] Pin la_oen[77] is outside die area
[WARNING] Pin la_oen[78] is outside die area
[WARNING] Pin la_oen[79] is outside die area
[WARNING] Pin la_oen[7] is outside die area
[WARNING] Pin la_oen[80] is outside die area
[WARNING] Pin la_oen[81] is outside die area
[WARNING] Pin la_oen[82] is outside die area
[WARNING] Pin la_oen[83] is outside die area
[WARNING] Pin la_oen[84] is outside die area
[WARNING] Pin la_oen[85] is outside die area
[WARNING] Pin la_oen[86] is outside die area
[WARNING] Pin la_oen[87] is outside die area
[WARNING] Pin la_oen[88] is outside die area
[WARNING] Pin la_oen[89] is outside die area
[WARNING] Pin la_oen[8] is outside die area
[WARNING] Pin la_oen[90] is outside die area
[WARNING] Pin la_oen[91] is outside die area
[WARNING] Pin la_oen[92] is outside die area
[WARNING] Pin la_oen[93] is outside die area
[WARNING] Pin la_oen[94] is outside die area
[WARNING] Pin la_oen[95] is outside die area
[WARNING] Pin la_oen[96] is outside die area
[WARNING] Pin la_oen[97] is outside die area
[WARNING] Pin la_oen[98] is outside die area
[WARNING] Pin la_oen[99] is outside die area
[WARNING] Pin la_oen[9] is outside die area
[WARNING] Pin user_clock2 is outside die area
[WARNING] Pin wb_clk_i is outside die area
[WARNING] Pin wb_rst_i is outside die area
[WARNING] Pin wbs_ack_o is outside die area
[WARNING] Pin wbs_adr_i[0] is outside die area
[WARNING] Pin wbs_adr_i[10] is outside die area
[WARNING] Pin wbs_adr_i[11] is outside die area
[WARNING] Pin wbs_adr_i[12] is outside die area
[WARNING] Pin wbs_adr_i[13] is outside die area
[WARNING] Pin wbs_adr_i[14] is outside die area
[WARNING] Pin wbs_adr_i[15] is outside die area
[WARNING] Pin wbs_adr_i[16] is outside die area
[WARNING] Pin wbs_adr_i[17] is outside die area
[WARNING] Pin wbs_adr_i[18] is outside die area
[WARNING] Pin wbs_adr_i[19] is outside die area
[WARNING] Pin wbs_adr_i[1] is outside die area
[WARNING] Pin wbs_adr_i[20] is outside die area
[WARNING] Pin wbs_adr_i[21] is outside die area
[WARNING] Pin wbs_adr_i[22] is outside die area
[WARNING] Pin wbs_adr_i[23] is outside die area
[WARNING] Pin wbs_adr_i[24] is outside die area
[WARNING] Pin wbs_adr_i[25] is outside die area
[WARNING] Pin wbs_adr_i[26] is outside die area
[WARNING] Pin wbs_adr_i[27] is outside die area
[WARNING] Pin wbs_adr_i[28] is outside die area
[WARNING] Pin wbs_adr_i[29] is outside die area
[WARNING] Pin wbs_adr_i[2] is outside die area
[WARNING] Pin wbs_adr_i[30] is outside die area
[WARNING] Pin wbs_adr_i[31] is outside die area
[WARNING] Pin wbs_adr_i[3] is outside die area
[WARNING] Pin wbs_adr_i[4] is outside die area
[WARNING] Pin wbs_adr_i[5] is outside die area
[WARNING] Pin wbs_adr_i[6] is outside die area
[WARNING] Pin wbs_adr_i[7] is outside die area
[WARNING] Pin wbs_adr_i[8] is outside die area
[WARNING] Pin wbs_adr_i[9] is outside die area
[WARNING] Pin wbs_cyc_i is outside die area
[WARNING] Pin wbs_dat_i[0] is outside die area
[WARNING] Pin wbs_dat_i[10] is outside die area
[WARNING] Pin wbs_dat_i[11] is outside die area
[WARNING] Pin wbs_dat_i[12] is outside die area
[WARNING] Pin wbs_dat_i[13] is outside die area
[WARNING] Pin wbs_dat_i[14] is outside die area
[WARNING] Pin wbs_dat_i[15] is outside die area
[WARNING] Pin wbs_dat_i[16] is outside die area
[WARNING] Pin wbs_dat_i[17] is outside die area
[WARNING] Pin wbs_dat_i[18] is outside die area
[WARNING] Pin wbs_dat_i[19] is outside die area
[WARNING] Pin wbs_dat_i[1] is outside die area
[WARNING] Pin wbs_dat_i[20] is outside die area
[WARNING] Pin wbs_dat_i[21] is outside die area
[WARNING] Pin wbs_dat_i[22] is outside die area
[WARNING] Pin wbs_dat_i[23] is outside die area
[WARNING] Pin wbs_dat_i[24] is outside die area
[WARNING] Pin wbs_dat_i[25] is outside die area
[WARNING] Pin wbs_dat_i[26] is outside die area
[WARNING] Pin wbs_dat_i[27] is outside die area
[WARNING] Pin wbs_dat_i[28] is outside die area
[WARNING] Pin wbs_dat_i[29] is outside die area
[WARNING] Pin wbs_dat_i[2] is outside die area
[WARNING] Pin wbs_dat_i[30] is outside die area
[WARNING] Pin wbs_dat_i[31] is outside die area
[WARNING] Pin wbs_dat_i[3] is outside die area
[WARNING] Pin wbs_dat_i[4] is outside die area
[WARNING] Pin wbs_dat_i[5] is outside die area
[WARNING] Pin wbs_dat_i[6] is outside die area
[WARNING] Pin wbs_dat_i[7] is outside die area
[WARNING] Pin wbs_dat_i[8] is outside die area
[WARNING] Pin wbs_dat_i[9] is outside die area
[WARNING] Pin wbs_dat_o[0] is outside die area
[WARNING] Pin wbs_dat_o[10] is outside die area
[WARNING] Pin wbs_dat_o[11] is outside die area
[WARNING] Pin wbs_dat_o[12] is outside die area
[WARNING] Pin wbs_dat_o[13] is outside die area
[WARNING] Pin wbs_dat_o[14] is outside die area
[WARNING] Pin wbs_dat_o[15] is outside die area
[WARNING] Pin wbs_dat_o[16] is outside die area
[WARNING] Pin wbs_dat_o[17] is outside die area
[WARNING] Pin wbs_dat_o[18] is outside die area
[WARNING] Pin wbs_dat_o[19] is outside die area
[WARNING] Pin wbs_dat_o[1] is outside die area
[WARNING] Pin wbs_dat_o[20] is outside die area
[WARNING] Pin wbs_dat_o[21] is outside die area
[WARNING] Pin wbs_dat_o[22] is outside die area
[WARNING] Pin wbs_dat_o[23] is outside die area
[WARNING] Pin wbs_dat_o[24] is outside die area
[WARNING] Pin wbs_dat_o[25] is outside die area
[WARNING] Pin wbs_dat_o[26] is outside die area
[WARNING] Pin wbs_dat_o[27] is outside die area
[WARNING] Pin wbs_dat_o[28] is outside die area
[WARNING] Pin wbs_dat_o[29] is outside die area
[WARNING] Pin wbs_dat_o[2] is outside die area
[WARNING] Pin wbs_dat_o[30] is outside die area
[WARNING] Pin wbs_dat_o[31] is outside die area
[WARNING] Pin wbs_dat_o[3] is outside die area
[WARNING] Pin wbs_dat_o[4] is outside die area
[WARNING] Pin wbs_dat_o[5] is outside die area
[WARNING] Pin wbs_dat_o[6] is outside die area
[WARNING] Pin wbs_dat_o[7] is outside die area
[WARNING] Pin wbs_dat_o[8] is outside die area
[WARNING] Pin wbs_dat_o[9] is outside die area
[WARNING] Pin wbs_sel_i[0] is outside die area
[WARNING] Pin wbs_sel_i[1] is outside die area
[WARNING] Pin wbs_sel_i[2] is outside die area
[WARNING] Pin wbs_sel_i[3] is outside die area
[WARNING] Pin wbs_stb_i is outside die area
[WARNING] Pin wbs_we_i is outside die area
[WARNING] Pin vccd1 is outside die area
[WARNING] Pin vssd1 is outside die area
[WARNING] Pin vccd2 is outside die area
[WARNING] Pin vssd2 is outside die area
[WARNING] Pin vdda1 is outside die area
[WARNING] Pin vssa1 is outside die area
[WARNING] Pin vdda2 is outside die area
[WARNING] Pin vssa2 is outside die area
[INFO] Minimum degree: 2
[INFO] Maximum degree: 2
[INFO] Processing 544385 obstacles on layer 1
[INFO] Processing 270789 obstacles on layer 2
[INFO] Processing 880 obstacles on layer 3
[INFO] Processing 1 obstacles on layer 4
[INFO] Processing 44 obstacles on layer 5
[INFO] Processing 43 obstacles on layer 6
[INFO] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 205149, WIRELEN1 : 0
[INFO] NumSeg  : 604
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 205149, WIRELEN1 : 205149
[INFO] NumSeg  : 604
[INFO] NumShift: 0
[Overflow Report] Total hCap    : 6290104
[Overflow Report] Total vCap    : 4649592
[Overflow Report] Total Usage   : 205149
[Overflow Report] Max H Overflow: 91
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 91
[Overflow Report] Num Overflow e: 611
[Overflow Report] H   Overflow  : 25039
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 25039

Second L Route
[Overflow Report] Total hCap    : 6290104
[Overflow Report] Total vCap    : 4649592
[Overflow Report] Total Usage   : 205149
[Overflow Report] Max H Overflow: 91
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 91
[Overflow Report] Num Overflow e: 611
[Overflow Report] H   Overflow  : 25039
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 25039

First Z Route
[Overflow Report] Total hCap    : 6290104
[Overflow Report] Total vCap    : 4649592
[Overflow Report] Total Usage   : 205149
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 0, enlarge 10 
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage   : 205149
[Overflow Report] Max H Overflow: 144
[Overflow Report] Max V Overflow: 3
[Overflow Report] Max Overflow  : 144
[Overflow Report] Num Overflow e: 488
[Overflow Report] H   Overflow  : 24566
[Overflow Report] V   Overflow  : 243
[Overflow Report] Final Overflow: 24809

[INFO] LV routing round 1, enlarge 15 
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage   : 205149
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] LV routing round 2, enlarge 20 
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage   : 205149
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Usage checked
Maze routing finished
[INFO] P3 runtime: 0.100000 sec
[INFO] Final 2D results: 
[Overflow Report] total Usage   : 205149
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 2.830000 sec
Post Processing Begins 
Post Processsing finished
 Starting via filling
[INFO] Via related to pin nodes 2234
[INFO] Via related stiner nodes 0
Via filling finished

Final usage/overflow report: 
[INFO] Usage per layer: 
    Layer 1 usage: 0
    Layer 2 usage: 63884
    Layer 3 usage: 133729
    Layer 4 usage: 5345
    Layer 5 usage: 2191
    Layer 6 usage: 0

[INFO] Capacity per layer: 
    Layer 1 capacity: 0
    Layer 2 capacity: 3724811
    Layer 3 capacity: 3202246
    Layer 4 capacity: 2136122
    Layer 5 capacity: 1447346
    Layer 6 capacity: 429171

[INFO] Use percentage per layer: 
    Layer 1 use percentage: 0.0%
    Layer 2 use percentage: 1.72%
    Layer 3 use percentage: 4.18%
    Layer 4 use percentage: 0.25%
    Layer 5 use percentage: 0.15%
    Layer 6 use percentage: 0.00%

[INFO] Overflow per layer: 
    Layer 1 overflow: 0
    Layer 2 overflow: 0
    Layer 3 overflow: 0
    Layer 4 overflow: 0
    Layer 5 overflow: 0
    Layer 6 overflow: 0

[Overflow Report] Total Usage   : 205149
[Overflow Report] Total Capacity: 10939696
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] Final usage          : 205149
[INFO] Final number of vias : 3396
[INFO] Final usage 3D       : 215337
[INFO] Total wirelength: 1451725 um
[INFO] Num routed nets: 604
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
user_project_wrapper/runs/user_project_wrapper/logs/routing/addspacers.log
SKIPPED!
user_project_wrapper/runs/user_project_wrapper/logs/write_verilog.log
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.

Notice 0: Reading LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 439 library cells
Notice 0: Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/addspacers.def
Notice 0: Design: user_project_wrapper
Notice 0: 		Created 100000 Insts
Notice 0:     Created 646 pins.
Notice 0:     Created 134693 components and 275606 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 644 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/addspacers.def
user_project_wrapper/runs/user_project_wrapper/logs/routing/tritonRoute.log

reading lef ...

units:       1000
#layers:     13
#macros:     439
#vias:       25
#viarulegen: 25

reading def ...
defIn read 10000 components
defIn read 20000 components
defIn read 30000 components
defIn read 40000 components
defIn read 50000 components
defIn read 60000 components
defIn read 70000 components
defIn read 80000 components
defIn read 90000 components
defIn read 100000 components

design:      user_project_wrapper
die area:    ( 0 0 ) ( 2920000 3520000 )
trackPts:    12
defvias:     5
#components: 134693
#terminals:  646
#snets:      2
#nets:       644

reading guide ...

#guides:     3745
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
  complete 10000 instances
  complete 20000 instances
  complete 30000 instances
  complete 40000 instances
  complete 50000 instances
  complete 60000 instances
  complete 70000 instances
  complete 80000 instances
  complete 90000 instances
  complete 100000 instances
#unique instances = 7

init region query ...
  complete 10000 insts
  complete 20000 insts
  complete 30000 insts
  complete 40000 insts
  complete 50000 insts
  complete 60000 insts
  complete 70000 insts
  complete 80000 insts
  complete 90000 insts
  complete 100000 insts
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 544385
mcon shape region query size = 280616
met1 shape region query size = 291147
via shape region query size = 183222
met2 shape region query size = 42123
via2 shape region query size = 142506
met3 shape region query size = 40826
via3 shape region query size = 142506
met4 shape region query size = 21201
via4 shape region query size = 1582
met5 shape region query size = 836


start pin access
  complete 100 pins
  complete 200 pins
  complete 300 pins
  complete 400 pins
  complete 500 pins
  complete 600 pins
  complete 604 pins
  complete 4 unique inst patterns
  complete 0 groups
Expt1 runtime (pin-level access point gen): 7.62652
Expt2 runtime (design-level access pattern gen): 0.0120805
#scanned instances     = 134693
#unique  instances     = 7
#stdCellGenAp          = 0
#stdCellValidPlanarAp  = 0
#stdCellValidViaAp     = 0
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 0
#instTermValidViaApCnt = 0
#macroGenAp            = 3624
#macroValidPlanarAp    = 3624
#macroValidViaAp       = 0
#macroNoAp             = 0

complete pin access
cpu time = 00:00:08, elapsed time = 00:00:07, memory = 167.73 (MB), peak = 167.84 (MB)

post process guides ...
GCELLGRID X -1 DO 510 STEP 6900 ;
GCELLGRID Y -1 DO 423 STEP 6900 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 0
mcon guide region query size = 0
met1 guide region query size = 682
via guide region query size = 0
met2 guide region query size = 1759
via2 guide region query size = 0
met3 guide region query size = 123
via3 guide region query size = 0
met4 guide region query size = 14
via4 guide region query size = 0
met5 guide region query size = 0

init gr pin query ...


start track assignment
Done with 1773 vertical wires in 9 frboxes and 805 horizontal wires in 11 frboxes.
Done with 607 vertical wires in 9 frboxes and 36 horizontal wires in 11 frboxes.

complete track assignment
cpu time = 00:00:07, elapsed time = 00:00:05, memory = 346.30 (MB), peak = 346.61 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 369.04 (MB), peak = 369.07 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:27, memory = 394.84 (MB)
    completing 20% with 0 violations
    elapsed time = 00:01:24, memory = 406.60 (MB)
    completing 30% with 8075 violations
    elapsed time = 00:01:42, memory = 414.97 (MB)
    completing 40% with 8075 violations
    elapsed time = 00:02:14, memory = 415.02 (MB)
    completing 50% with 6020 violations
    elapsed time = 00:02:31, memory = 417.33 (MB)
    completing 60% with 5963 violations
    elapsed time = 00:02:48, memory = 417.55 (MB)
    completing 70% with 5963 violations
    elapsed time = 00:03:21, memory = 417.55 (MB)
    completing 80% with 8777 violations
    elapsed time = 00:03:41, memory = 422.80 (MB)
    completing 90% with 8777 violations
    elapsed time = 00:04:17, memory = 422.80 (MB)
    completing 100% with 1773 violations
    elapsed time = 00:04:41, memory = 422.86 (MB)
  number of violations = 1773
cpu time = 00:07:06, elapsed time = 00:04:42, memory = 414.45 (MB), peak = 692.50 (MB)
total wire length = 1432719 um
total wire length on LAYER li1 = 254 um
total wire length on LAYER met1 = 440605 um
total wire length on LAYER met2 = 938425 um
total wire length on LAYER met3 = 38503 um
total wire length on LAYER met4 = 14930 um
total wire length on LAYER met5 = 0 um
total number of vias = 2507
up-via summary (total 2507):

-----------------------
 FR_MASTERSLICE       0
            li1     170
           met1    2122
           met2     187
           met3      28
           met4       0
-----------------------
                   2507


start 1st optimization iteration ...
    completing 10% with 1773 violations
    elapsed time = 00:00:28, memory = 414.45 (MB)
    completing 20% with 1773 violations
    elapsed time = 00:00:52, memory = 414.45 (MB)
    completing 30% with 1386 violations
    elapsed time = 00:01:09, memory = 415.73 (MB)
    completing 40% with 1386 violations
    elapsed time = 00:01:44, memory = 415.82 (MB)
    completing 50% with 1592 violations
    elapsed time = 00:02:01, memory = 415.94 (MB)
    completing 60% with 1610 violations
    elapsed time = 00:02:13, memory = 415.94 (MB)
    completing 70% with 1610 violations
    elapsed time = 00:02:33, memory = 415.94 (MB)
    completing 80% with 1417 violations
    elapsed time = 00:02:50, memory = 416.71 (MB)
    completing 90% with 1417 violations
    elapsed time = 00:03:22, memory = 416.72 (MB)
    completing 100% with 1635 violations
    elapsed time = 00:03:35, memory = 416.72 (MB)
  number of violations = 1635
cpu time = 00:04:56, elapsed time = 00:03:36, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433302 um
total wire length on LAYER li1 = 484 um
total wire length on LAYER met1 = 440448 um
total wire length on LAYER met2 = 938573 um
total wire length on LAYER met3 = 38870 um
total wire length on LAYER met4 = 14926 um
total wire length on LAYER met5 = 0 um
total number of vias = 2861
up-via summary (total 2861):

-----------------------
 FR_MASTERSLICE       0
            li1     386
           met1    2240
           met2     207
           met3      28
           met4       0
-----------------------
                   2861


start 2nd optimization iteration ...
    completing 10% with 1635 violations
    elapsed time = 00:00:02, memory = 416.72 (MB)
    completing 20% with 1635 violations
    elapsed time = 00:00:13, memory = 416.72 (MB)
    completing 30% with 1830 violations
    elapsed time = 00:00:17, memory = 416.72 (MB)
    completing 40% with 1830 violations
    elapsed time = 00:00:29, memory = 416.72 (MB)
    completing 50% with 1685 violations
    elapsed time = 00:00:33, memory = 416.72 (MB)
    completing 60% with 1659 violations
    elapsed time = 00:00:38, memory = 416.72 (MB)
    completing 70% with 1659 violations
    elapsed time = 00:00:47, memory = 416.72 (MB)
    completing 80% with 1768 violations
    elapsed time = 00:00:50, memory = 416.72 (MB)
    completing 90% with 1768 violations
    elapsed time = 00:01:06, memory = 416.72 (MB)
    completing 100% with 1257 violations
    elapsed time = 00:01:10, memory = 416.72 (MB)
  number of violations = 1257
cpu time = 00:02:10, elapsed time = 00:01:11, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433427 um
total wire length on LAYER li1 = 649 um
total wire length on LAYER met1 = 440441 um
total wire length on LAYER met2 = 938485 um
total wire length on LAYER met3 = 38922 um
total wire length on LAYER met4 = 14928 um
total wire length on LAYER met5 = 0 um
total number of vias = 2969
up-via summary (total 2969):

-----------------------
 FR_MASTERSLICE       0
            li1     494
           met1    2248
           met2     199
           met3      28
           met4       0
-----------------------
                   2969


start 3rd optimization iteration ...
    completing 10% with 1257 violations
    elapsed time = 00:00:08, memory = 416.72 (MB)
    completing 20% with 1257 violations
    elapsed time = 00:00:41, memory = 416.72 (MB)
    completing 30% with 1099 violations
    elapsed time = 00:00:49, memory = 416.72 (MB)
    completing 40% with 1099 violations
    elapsed time = 00:01:20, memory = 416.72 (MB)
    completing 50% with 906 violations
    elapsed time = 00:01:34, memory = 416.72 (MB)
    completing 60% with 904 violations
    elapsed time = 00:01:38, memory = 416.72 (MB)
    completing 70% with 904 violations
    elapsed time = 00:02:11, memory = 416.72 (MB)
    completing 80% with 685 violations
    elapsed time = 00:02:20, memory = 416.72 (MB)
    completing 90% with 685 violations
    elapsed time = 00:02:55, memory = 416.72 (MB)
    completing 100% with 454 violations
    elapsed time = 00:03:02, memory = 416.72 (MB)
  number of violations = 454
cpu time = 00:05:28, elapsed time = 00:03:03, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433549 um
total wire length on LAYER li1 = 4431 um
total wire length on LAYER met1 = 441244 um
total wire length on LAYER met2 = 934602 um
total wire length on LAYER met3 = 38135 um
total wire length on LAYER met4 = 15136 um
total wire length on LAYER met5 = 0 um
total number of vias = 4001
up-via summary (total 4001):

-----------------------
 FR_MASTERSLICE       0
            li1     808
           met1    2640
           met2     441
           met3     112
           met4       0
-----------------------
                   4001


start 4th optimization iteration ...
    completing 10% with 454 violations
    elapsed time = 00:00:03, memory = 416.72 (MB)
    completing 20% with 454 violations
    elapsed time = 00:00:25, memory = 416.72 (MB)
    completing 30% with 403 violations
    elapsed time = 00:00:29, memory = 416.72 (MB)
    completing 40% with 403 violations
    elapsed time = 00:00:46, memory = 416.72 (MB)
    completing 50% with 314 violations
    elapsed time = 00:00:51, memory = 416.72 (MB)
    completing 60% with 309 violations
    elapsed time = 00:00:54, memory = 416.72 (MB)
    completing 70% with 309 violations
    elapsed time = 00:01:28, memory = 416.72 (MB)
    completing 80% with 287 violations
    elapsed time = 00:01:33, memory = 416.72 (MB)
    completing 90% with 287 violations
    elapsed time = 00:01:50, memory = 416.72 (MB)
    completing 100% with 194 violations
    elapsed time = 00:01:54, memory = 416.72 (MB)
  number of violations = 194
cpu time = 00:02:50, elapsed time = 00:01:55, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433651 um
total wire length on LAYER li1 = 9391 um
total wire length on LAYER met1 = 441657 um
total wire length on LAYER met2 = 929273 um
total wire length on LAYER met3 = 37848 um
total wire length on LAYER met4 = 15480 um
total wire length on LAYER met5 = 0 um
total number of vias = 4763
up-via summary (total 4763):

-----------------------
 FR_MASTERSLICE       0
            li1    1034
           met1    3026
           met2     569
           met3     134
           met4       0
-----------------------
                   4763


start 5th optimization iteration ...
    completing 10% with 194 violations
    elapsed time = 00:00:02, memory = 416.72 (MB)
    completing 20% with 194 violations
    elapsed time = 00:00:09, memory = 416.72 (MB)
    completing 30% with 157 violations
    elapsed time = 00:00:12, memory = 416.72 (MB)
    completing 40% with 157 violations
    elapsed time = 00:00:16, memory = 416.72 (MB)
    completing 50% with 127 violations
    elapsed time = 00:00:18, memory = 416.72 (MB)
    completing 60% with 127 violations
    elapsed time = 00:00:20, memory = 416.72 (MB)
    completing 70% with 127 violations
    elapsed time = 00:00:29, memory = 416.72 (MB)
    completing 80% with 73 violations
    elapsed time = 00:00:32, memory = 416.72 (MB)
    completing 90% with 73 violations
    elapsed time = 00:00:38, memory = 416.72 (MB)
    completing 100% with 35 violations
    elapsed time = 00:00:40, memory = 416.72 (MB)
  number of violations = 35
cpu time = 00:01:16, elapsed time = 00:00:41, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433685 um
total wire length on LAYER li1 = 10754 um
total wire length on LAYER met1 = 441748 um
total wire length on LAYER met2 = 927776 um
total wire length on LAYER met3 = 37823 um
total wire length on LAYER met4 = 15582 um
total wire length on LAYER met5 = 0 um
total number of vias = 4979
up-via summary (total 4979):

-----------------------
 FR_MASTERSLICE       0
            li1    1092
           met1    3132
           met2     613
           met3     142
           met4       0
-----------------------
                   4979


start 6th optimization iteration ...
    completing 10% with 35 violations
    elapsed time = 00:00:02, memory = 416.72 (MB)
    completing 20% with 35 violations
    elapsed time = 00:00:05, memory = 416.72 (MB)
    completing 30% with 30 violations
    elapsed time = 00:00:08, memory = 416.72 (MB)
    completing 40% with 30 violations
    elapsed time = 00:00:10, memory = 416.72 (MB)
    completing 50% with 30 violations
    elapsed time = 00:00:12, memory = 416.72 (MB)
    completing 60% with 30 violations
    elapsed time = 00:00:16, memory = 416.72 (MB)
    completing 70% with 30 violations
    elapsed time = 00:00:20, memory = 416.72 (MB)
    completing 80% with 17 violations
    elapsed time = 00:00:22, memory = 416.72 (MB)
    completing 90% with 17 violations
    elapsed time = 00:00:25, memory = 416.72 (MB)
    completing 100% with 10 violations
    elapsed time = 00:00:28, memory = 416.72 (MB)
  number of violations = 10
cpu time = 00:00:50, elapsed time = 00:00:29, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433698 um
total wire length on LAYER li1 = 10950 um
total wire length on LAYER met1 = 441755 um
total wire length on LAYER met2 = 927529 um
total wire length on LAYER met3 = 37832 um
total wire length on LAYER met4 = 15630 um
total wire length on LAYER met5 = 0 um
total number of vias = 5023
up-via summary (total 5023):

-----------------------
 FR_MASTERSLICE       0
            li1    1098
           met1    3148
           met2     633
           met3     144
           met4       0
-----------------------
                   5023


start 7th optimization iteration ...
    completing 10% with 10 violations
    elapsed time = 00:00:02, memory = 416.72 (MB)
    completing 20% with 10 violations
    elapsed time = 00:00:06, memory = 416.72 (MB)
    completing 30% with 5 violations
    elapsed time = 00:00:08, memory = 416.72 (MB)
    completing 40% with 5 violations
    elapsed time = 00:00:11, memory = 416.72 (MB)
    completing 50% with 2 violations
    elapsed time = 00:00:13, memory = 416.72 (MB)
    completing 60% with 2 violations
    elapsed time = 00:00:15, memory = 416.72 (MB)
    completing 70% with 2 violations
    elapsed time = 00:00:18, memory = 416.72 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:20, memory = 416.72 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:22, memory = 416.72 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:26, memory = 416.72 (MB)
  number of violations = 0
cpu time = 00:00:46, elapsed time = 00:00:27, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433699 um
total wire length on LAYER li1 = 11001 um
total wire length on LAYER met1 = 441756 um
total wire length on LAYER met2 = 927477 um
total wire length on LAYER met3 = 37832 um
total wire length on LAYER met4 = 15630 um
total wire length on LAYER met5 = 0 um
total number of vias = 5035
up-via summary (total 5035):

-----------------------
 FR_MASTERSLICE       0
            li1    1104
           met1    3156
           met2     631
           met3     144
           met4       0
-----------------------
                   5035


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:02, memory = 416.72 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:04, memory = 416.72 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:07, memory = 416.72 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:09, memory = 416.72 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:11, memory = 416.72 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:14, memory = 416.72 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:16, memory = 416.72 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:18, memory = 416.72 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:21, memory = 416.72 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:24, memory = 416.72 (MB)
  number of violations = 0
cpu time = 00:00:44, elapsed time = 00:00:24, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433699 um
total wire length on LAYER li1 = 11001 um
total wire length on LAYER met1 = 441756 um
total wire length on LAYER met2 = 927477 um
total wire length on LAYER met3 = 37832 um
total wire length on LAYER met4 = 15630 um
total wire length on LAYER met5 = 0 um
total number of vias = 5035
up-via summary (total 5035):

-----------------------
 FR_MASTERSLICE       0
            li1    1104
           met1    3156
           met2     631
           met3     144
           met4       0
-----------------------
                   5035


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:02, memory = 416.72 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:04, memory = 416.72 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:07, memory = 416.72 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:10, memory = 416.72 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:15, memory = 416.72 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:21, memory = 416.72 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:25, memory = 416.72 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:28, memory = 416.72 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:30, memory = 416.72 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:33, memory = 416.72 (MB)
  number of violations = 0
cpu time = 00:00:48, elapsed time = 00:00:33, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433699 um
total wire length on LAYER li1 = 11001 um
total wire length on LAYER met1 = 441756 um
total wire length on LAYER met2 = 927477 um
total wire length on LAYER met3 = 37832 um
total wire length on LAYER met4 = 15630 um
total wire length on LAYER met5 = 0 um
total number of vias = 5035
up-via summary (total 5035):

-----------------------
 FR_MASTERSLICE       0
            li1    1104
           met1    3156
           met2     631
           met3     144
           met4       0
-----------------------
                   5035


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:02, memory = 416.72 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:05, memory = 416.72 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:09, memory = 416.72 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:11, memory = 416.72 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:14, memory = 416.72 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:17, memory = 416.72 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:21, memory = 416.72 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:25, memory = 416.72 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:28, memory = 416.72 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:31, memory = 416.72 (MB)
  number of violations = 0
cpu time = 00:00:55, elapsed time = 00:00:31, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433699 um
total wire length on LAYER li1 = 11001 um
total wire length on LAYER met1 = 441756 um
total wire length on LAYER met2 = 927477 um
total wire length on LAYER met3 = 37832 um
total wire length on LAYER met4 = 15630 um
total wire length on LAYER met5 = 0 um
total number of vias = 5035
up-via summary (total 5035):

-----------------------
 FR_MASTERSLICE       0
            li1    1104
           met1    3156
           met2     631
           met3     144
           met4       0
-----------------------
                   5035


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:02, memory = 416.72 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:05, memory = 416.72 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:08, memory = 416.72 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:11, memory = 416.72 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:15, memory = 416.72 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:18, memory = 416.72 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:20, memory = 416.72 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:24, memory = 416.72 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:27, memory = 416.72 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:30, memory = 416.72 (MB)
  number of violations = 0
cpu time = 00:00:55, elapsed time = 00:00:30, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433699 um
total wire length on LAYER li1 = 11001 um
total wire length on LAYER met1 = 441756 um
total wire length on LAYER met2 = 927477 um
total wire length on LAYER met3 = 37832 um
total wire length on LAYER met4 = 15630 um
total wire length on LAYER met5 = 0 um
total number of vias = 5035
up-via summary (total 5035):

-----------------------
 FR_MASTERSLICE       0
            li1    1104
           met1    3156
           met2     631
           met3     144
           met4       0
-----------------------
                   5035


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:03, memory = 416.72 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:05, memory = 416.72 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:08, memory = 416.72 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:11, memory = 416.72 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:14, memory = 416.72 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:17, memory = 416.72 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:20, memory = 416.72 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:23, memory = 416.72 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:26, memory = 416.72 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:29, memory = 416.72 (MB)
  number of violations = 0
cpu time = 00:00:54, elapsed time = 00:00:29, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433699 um
total wire length on LAYER li1 = 11001 um
total wire length on LAYER met1 = 441756 um
total wire length on LAYER met2 = 927477 um
total wire length on LAYER met3 = 37832 um
total wire length on LAYER met4 = 15630 um
total wire length on LAYER met5 = 0 um
total number of vias = 5035
up-via summary (total 5035):

-----------------------
 FR_MASTERSLICE       0
            li1    1104
           met1    3156
           met2     631
           met3     144
           met4       0
-----------------------
                   5035


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:02, memory = 416.72 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:06, memory = 416.72 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:09, memory = 416.72 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:12, memory = 416.72 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:14, memory = 416.72 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:17, memory = 416.72 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:20, memory = 416.72 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:23, memory = 416.72 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:26, memory = 416.72 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:29, memory = 416.72 (MB)
  number of violations = 0
cpu time = 00:00:54, elapsed time = 00:00:29, memory = 416.72 (MB), peak = 695.67 (MB)
total wire length = 1433699 um
total wire length on LAYER li1 = 11001 um
total wire length on LAYER met1 = 441756 um
total wire length on LAYER met2 = 927477 um
total wire length on LAYER met3 = 37832 um
total wire length on LAYER met4 = 15630 um
total wire length on LAYER met5 = 0 um
total number of vias = 5035
up-via summary (total 5035):

-----------------------
 FR_MASTERSLICE       0
            li1    1104
           met1    3156
           met2     631
           met3     144
           met4       0
-----------------------
                   5035


complete detail routing
total wire length = 1433699 um
total wire length on LAYER li1 = 11001 um
total wire length on LAYER met1 = 441756 um
total wire length on LAYER met2 = 927477 um
total wire length on LAYER met3 = 37832 um
total wire length on LAYER met4 = 15630 um
total wire length on LAYER met5 = 0 um
total number of vias = 5035
up-via summary (total 5035):

-----------------------
 FR_MASTERSLICE       0
            li1    1104
           met1    3156
           met2     631
           met3     144
           met4       0
-----------------------
                   5035

cpu time = 00:30:38, elapsed time = 00:19:05, memory = 416.72 (MB), peak = 695.67 (MB)

post processing ...

Runtime taken (hrt): 1170.31
user_project_wrapper/runs/user_project_wrapper/logs/routing/spef_extraction.log
Start parsing LEF file...
Parsing LEF file done.
Start parsing DEF file...
Parsing DEF file done.

Parameters Used:
Edge Capacitance Factor: 1.0
Wire model: L 

Traceback (most recent call last):
  File "/openLANE_flow/scripts/spef_extractor/main.py", line 562, in 
    inst.extract(lef_file_name, def_file_name, wireModel, edgeCapFactor)
  File "/openLANE_flow/scripts/spef_extractor/main.py", line 520, in extract
    netsDict[net.name] = self.extract_net(net)
  File "/openLANE_flow/scripts/spef_extractor/main.py", line 364, in extract_net
    locationsOfCurrentPin = [((pinLocation[0], pinLocation[1]),
TypeError: 'NoneType' object is not subscriptable