Submodule: user_proj_example

###############################################

[INFO]: ___ ____ ___ ____ _ ____ ____ ___ / \ | \ / _]| \ | | / || \ / _] | || o ) [_ | _ || | | o || _ | / [_ | O || _/ _]| | || |___ | || | || _] | || | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____|

[INFO]: Version: openram_tc_1kb-alpha-1-457-gc86ca2f

[INFO]: Running non-interactively

[INFO]: Using design configuration at /project/openlane/user_proj_example/config.tcl

[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl

[INFO]: PDKs root directory: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A

[INFO]: PDK: sky130A

[INFO]: Standard Cell Library: sky130_fd_sc_hd

[INFO]: Sourcing Configurations from /project/openlane/user_proj_example/config.tcl

[WARNING]: CELL_PAD_EXECLUDE is now deprecated; use CELL_PAD_EXCLUDE instead.

[INFO]: Current run directory is /project/openlane/user_proj_example/runs/user_proj_example

[WARNING]: Removing exisiting run /project/openlane/user_proj_example/runs/user_proj_example

[INFO]: Preparing LEF Files

mergeLef.py : Merging LEFs sky130_fd_sc_hd.lef: SITEs matched found: 0 sky130_fd_sc_hd.lef: MACROs matched found: 437 mergeLef.py : Merging LEFs complete mergeLef.py : Merging LEFs NAND3X1.lef: SITEs matched found: 0 NAND3X1.lef: MACROs matched found: 1 INVX8.lef: SITEs matched found: 0 INVX8.lef: MACROs matched found: 1 OAI21X1.lef: SITEs matched found: 0 OAI21X1.lef: MACROs matched found: 1 INVX4.lef: SITEs matched found: 0 INVX4.lef: MACROs matched found: 1 OAI22X1.lef: SITEs matched found: 0 OAI22X1.lef: MACROs matched found: 1 XOR2X1.lef: SITEs matched found: 0 XOR2X1.lef: MACROs matched found: 1 BUFX4.lef: SITEs matched found: 0 BUFX4.lef: MACROs matched found: 1 NOR2X1.lef: SITEs matched found: 0 NOR2X1.lef: MACROs matched found: 1 HAX1.lef: SITEs matched found: 0 HAX1.lef: MACROs matched found: 1 LATCH.lef: SITEs matched found: 0 LATCH.lef: MACROs matched found: 1 AOI21X1.lef: SITEs matched found: 0 AOI21X1.lef: MACROs matched found: 1 MUX2X1.lef: SITEs matched found: 0 MUX2X1.lef: MACROs matched found: 1 BUFX2.lef: SITEs matched found: 0 BUFX2.lef: MACROs matched found: 1 OR2X1.lef: SITEs matched found: 0 OR2X1.lef: MACROs matched found: 1 NAND2X1.lef: SITEs matched found: 0 NAND2X1.lef: MACROs matched found: 1 INVX2.lef: SITEs matched found: 0 INVX2.lef: MACROs matched found: 1 NOR3X1.lef: SITEs matched found: 0 NOR3X1.lef: MACROs matched found: 1 AND2X2.lef: SITEs matched found: 0 AND2X2.lef: MACROs matched found: 1 OR2X2.lef: SITEs matched found: 0 OR2X2.lef: MACROs matched found: 1 TBUFX2.lef: SITEs matched found: 0 TBUFX2.lef: MACROs matched found: 1 AOI22X1.lef: SITEs matched found: 0 AOI22X1.lef: MACROs matched found: 1 CLKBUF1.lef: SITEs matched found: 0 CLKBUF1.lef: MACROs matched found: 1 XNOR2X1.lef: SITEs matched found: 0 XNOR2X1.lef: MACROs matched found: 1 AND2X1.lef: SITEs matched found: 0 AND2X1.lef: MACROs matched found: 1 TBUFX1.lef: SITEs matched found: 0 TBUFX1.lef: MACROs matched found: 1 INVX1.lef: SITEs matched found: 0 INVX1.lef: MACROs matched found: 1 INV.lef: SITEs matched found: 0 INV.lef: MACROs matched found: 1 mergeLef.py : Merging LEFs complete

[INFO]: Merging the following extra LEFs: /project/openlane/user_proj_example/../../cells/lef/NAND3X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX8.lef /project/openlane/user_proj_example/../../cells/lef/OAI21X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX4.lef /project/openlane/user_proj_example/../../cells/lef/OAI22X1.lef /project/openlane/user_proj_example/../../cells/lef/XOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX4.lef /project/openlane/user_proj_example/../../cells/lef/NOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/HAX1.lef /project/openlane/user_proj_example/../../cells/lef/LATCH.lef /project/openlane/user_proj_example/../../cells/lef/AOI21X1.lef /project/openlane/user_proj_example/../../cells/lef/MUX2X1.lef /project/openlane/user_proj_example/../../cells/lef/BUFX2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X1.lef /project/openlane/user_proj_example/../../cells/lef/NAND2X1.lef /project/openlane/user_proj_example/../../cells/lef/INVX2.lef /project/openlane/user_proj_example/../../cells/lef/NOR3X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X2.lef /project/openlane/user_proj_example/../../cells/lef/OR2X2.lef /project/openlane/user_proj_example/../../cells/lef/TBUFX2.lef /project/openlane/user_proj_example/../../cells/lef/AOI22X1.lef /project/openlane/user_proj_example/../../cells/lef/CLKBUF1.lef /project/openlane/user_proj_example/../../cells/lef/XNOR2X1.lef /project/openlane/user_proj_example/../../cells/lef/AND2X1.lef /project/openlane/user_proj_example/../../cells/lef/TBUFX1.lef /project/openlane/user_proj_example/../../cells/lef/INVX1.lef /project/openlane/user_proj_example/../../cells/lef/INV.lef

[INFO]: Trimming Liberty...

[INFO]: Preparation complete

[INFO]: Running Synthesis...

Reading /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib as a blackbox /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. 1. Executing Liberty frontend. Imported 428 cell types from liberty file. 2. Executing Liberty frontend. Imported 27 cell types from liberty file. 3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v' to AST representation. Replacing existing blackbox module `\AND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:10.1-17.10. Generating RTLIL representation for module `\AND2X1'. Replacing existing blackbox module `\AND2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:19.1-26.10. Generating RTLIL representation for module `\AND2X2'. Replacing existing blackbox module `\AOI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:28.1-36.10. Generating RTLIL representation for module `\AOI21X1'. Replacing existing blackbox module `\AOI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:38.1-47.10. Generating RTLIL representation for module `\AOI22X1'. Replacing existing blackbox module `\BUFX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:49.1-55.10. Generating RTLIL representation for module `\BUFX2'. Replacing existing blackbox module `\BUFX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:57.1-63.10. Generating RTLIL representation for module `\BUFX4'. Replacing existing blackbox module `\CLKBUF1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:65.1-71.10. Generating RTLIL representation for module `\CLKBUF1'. Replacing existing blackbox module `\HAX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:73.1-81.10. Generating RTLIL representation for module `\HAX1'. Replacing existing blackbox module `\INV' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:83.1-89.10. Generating RTLIL representation for module `\INV'. Replacing existing blackbox module `\INVX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:91.1-97.10. Generating RTLIL representation for module `\INVX1'. Replacing existing blackbox module `\INVX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:99.1-105.10. Generating RTLIL representation for module `\INVX2'. Replacing existing blackbox module `\INVX4' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:107.1-113.10. Generating RTLIL representation for module `\INVX4'. Replacing existing blackbox module `\INVX8' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:115.1-121.10. Generating RTLIL representation for module `\INVX8'. Replacing existing blackbox module `\LATCH' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:123.1-130.10. Generating RTLIL representation for module `\LATCH'. Replacing existing blackbox module `\MUX2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:132.1-140.10. Generating RTLIL representation for module `\MUX2X1'. Replacing existing blackbox module `\NAND2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:142.1-149.10. Generating RTLIL representation for module `\NAND2X1'. Replacing existing blackbox module `\NAND3X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:151.1-159.10. Generating RTLIL representation for module `\NAND3X1'. Replacing existing blackbox module `\NOR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:161.1-168.10. Generating RTLIL representation for module `\NOR2X1'. Replacing existing blackbox module `\NOR3X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:170.1-178.10. Generating RTLIL representation for module `\NOR3X1'. Replacing existing blackbox module `\OAI21X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:180.1-188.10. Generating RTLIL representation for module `\OAI21X1'. Replacing existing blackbox module `\OAI22X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:190.1-199.10. Generating RTLIL representation for module `\OAI22X1'. Replacing existing blackbox module `\OR2X1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:201.1-208.10. Generating RTLIL representation for module `\OR2X1'. Replacing existing blackbox module `\OR2X2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:210.1-217.10. Generating RTLIL representation for module `\OR2X2'. Replacing existing blackbox module `\TBUFX1' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:219.1-226.10. Generating RTLIL representation for module `\TBUFX1'. Replacing existing blackbox module `\TBUFX2' at /project/openlane/user_proj_example/../../verilog//rtl/user_proj_cells.v:228.1-235.10. Generating RTLIL representation for module `\TBUFX2'.

Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/defines.v Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/defines.v' to AST representation.

Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation. Generating RTLIL representation for module `\user_proj_example'.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:142: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:143: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:144: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:145: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:150: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:151: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:152: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:157: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:158: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:159: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:160: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:165: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:166: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:167: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:172: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:173: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:174: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:175: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:180: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:181: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:182: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:183: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:188: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:189: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:190: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:191: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:192: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:197: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:198: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:199: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:204: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:205: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:206: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:211: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:212: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:213: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:218: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:219: Warning: Range select out of bounds on signal `\io_in': Setting result bit to undef.

/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:220: Warning: Range select out of bounds on signal `\io_out': Setting result bit to undef.

Successfully finished Verilog frontend.

6. Generating Graphviz representation of design. Writing dot description to `/project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/hierarchy.dot'. Dumping module user_proj_example to page 1. 7. Executing HIERARCHY pass (managing design hierarchy). 7.1. Analyzing design hierarchy.. Top module: \user_proj_example 7.2. Analyzing design hierarchy.. Top module: \user_proj_example Removed 0 unused modules. 8. Executing SYNTH pass. 8.1. Executing HIERARCHY pass (managing design hierarchy). 8.1.1. Analyzing design hierarchy.. Top module: \user_proj_example 8.1.2. Analyzing design hierarchy.. Top module: \user_proj_example Removed 0 unused modules. 8.2. Executing PROC pass (convert processes to netlists). 8.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 8.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 8.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 8.2.4. Executing PROC_INIT pass (extract init attributes). 8.2.5. Executing PROC_ARST pass (detect async resets in processes). 8.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). 8.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). 8.2.8. Executing PROC_DFF pass (convert process syncs to FFs). 8.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 8.3. Executing FLATTEN pass (flatten design). 8.4. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 8.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 8.6. Executing CHECK pass (checking for obvious problems). checking module user_proj_example..

Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [29] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [28] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [27] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [26] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [25] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [24] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [23] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [22] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [21] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [20] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [19] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [18] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [17] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [16] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [15] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [14] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [13] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [12] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [11] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [10] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [9] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [8] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [7] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [6] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [5] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [4] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [3] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [2] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [1] is used but has no driver.

Warning: Wire user_proj_example.\wbs_dat_o [0] is used but has no driver.

Warning: Wire user_proj_example.\wbs_ack_o is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [126] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [125] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [124] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [123] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [122] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [121] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [120] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [119] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [118] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [117] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [116] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [115] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [114] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [113] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [112] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [111] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [110] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [109] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [108] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [107] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [106] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [105] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [104] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [103] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [102] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [101] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [100] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [99] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [98] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [97] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [96] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [95] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [94] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [93] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [92] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [91] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [90] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [89] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [88] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [87] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [86] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [85] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [84] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [83] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [82] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [81] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [80] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [79] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [78] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [77] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [76] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [75] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [74] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [73] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [72] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [71] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [70] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [69] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [68] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [67] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [66] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [65] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [64] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [63] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [62] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [61] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [60] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [59] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [57] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [56] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [55] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [54] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [53] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [52] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [51] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [50] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [49] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [48] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [47] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [46] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [45] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [44] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [43] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [42] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [41] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [40] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [39] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [38] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [37] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [36] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [35] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [34] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [33] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [32] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [31] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [30] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [29] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [28] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [27] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [26] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [25] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [24] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [23] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [22] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [21] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [18] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [17] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [15] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [13] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [10] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [6] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [3] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.

Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.

Warning: Wire user_proj_example.\io_out [36] is used but has no driver.

Warning: Wire user_proj_example.\io_out [35] is used but has no driver.

Warning: Wire user_proj_example.\io_out [33] is used but has no driver.

Warning: Wire user_proj_example.\io_out [31] is used but has no driver.

Warning: Wire user_proj_example.\io_out [29] is used but has no driver.

Warning: Wire user_proj_example.\io_out [27] is used but has no driver.

Warning: Wire user_proj_example.\io_out [25] is used but has no driver.

Warning: Wire user_proj_example.\io_out [22] is used but has no driver.

Warning: Wire user_proj_example.\io_out [21] is used but has no driver.

Warning: Wire user_proj_example.\io_out [19] is used but has no driver.

Warning: Wire user_proj_example.\io_out [17] is used but has no driver.

Warning: Wire user_proj_example.\io_out [15] is used but has no driver.

Warning: Wire user_proj_example.\io_out [13] is used but has no driver.

Warning: Wire user_proj_example.\io_out [12] is used but has no driver.

Warning: Wire user_proj_example.\io_out [11] is used but has no driver.

Warning: Wire user_proj_example.\io_out [10] is used but has no driver.

Warning: Wire user_proj_example.\io_out [8] is used but has no driver.

Warning: Wire user_proj_example.\io_out [7] is used but has no driver.

Warning: Wire user_proj_example.\io_out [6] is used but has no driver.

Warning: Wire user_proj_example.\io_out [4] is used but has no driver.

Warning: Wire user_proj_example.\io_out [3] is used but has no driver.

Warning: Wire user_proj_example.\io_out [1] is used but has no driver.

Warning: Wire user_proj_example.\io_out [0] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [37] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [36] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [35] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [34] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [33] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [32] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [31] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [30] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [29] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [28] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [27] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [26] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [25] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [24] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [23] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [22] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [21] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [20] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [19] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [18] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [17] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [16] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [15] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [14] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [13] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [12] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [11] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [10] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [9] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [8] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [7] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [6] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [5] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [4] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [3] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [2] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [1] is used but has no driver.

Warning: Wire user_proj_example.\io_oeb [0] is used but has no driver.

found and reported 222 problems. 8.7. Executing OPT pass (performing simple optimizations). 8.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 8.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \user_proj_example.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 8.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \user_proj_example. Performed a total of 0 changes. 8.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.7.6. Executing OPT_DFF pass (perform DFF optimizations). 8.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 8.7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example.

8.7.9. Finished OPT passes. (There is nothing left to do.)

8.8. Executing FSM pass (extract and optimize FSM). 8.8.1. Executing FSM_DETECT pass (finding FSMs in design). 8.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). 8.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). 8.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 8.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). 8.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 8.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 8.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 8.9. Executing OPT pass (performing simple optimizations). 8.9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 8.9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \user_proj_example.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 8.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \user_proj_example. Performed a total of 0 changes. 8.9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.9.6. Executing OPT_DFF pass (perform DFF optimizations). 8.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 8.9.8. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example.

8.9.9. Finished OPT passes. (There is nothing left to do.)

8.10. Executing WREDUCE pass (reducing word size of cells). 8.11. Executing PEEPOPT pass (run peephole optimizers). 8.12. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 8.13. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module user_proj_example: created 0 $alu and 0 $macc cells. 8.14. Executing SHARE pass (SAT-based resource sharing). 8.15. Executing OPT pass (performing simple optimizations). 8.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 8.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \user_proj_example.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 8.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \user_proj_example. Performed a total of 0 changes. 8.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.15.6. Executing OPT_DFF pass (perform DFF optimizations). 8.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 8.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example.

8.15.9. Finished OPT passes. (There is nothing left to do.)

8.16. Executing MEMORY pass. 8.16.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 8.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 8.16.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 8.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 8.16.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 8.16.6. Executing MEMORY_COLLECT pass (generating $mem cells). 8.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 8.18. Executing OPT pass (performing simple optimizations). 8.18.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 8.18.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.18.3. Executing OPT_DFF pass (perform DFF optimizations). 8.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example..

8.18.5. Finished fast OPT passes.

8.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 8.20. Executing OPT pass (performing simple optimizations). 8.20.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 8.20.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \user_proj_example.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 8.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \user_proj_example. Performed a total of 0 changes. 8.20.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.20.6. Executing OPT_SHARE pass. 8.20.7. Executing OPT_DFF pass (perform DFF optimizations). 8.20.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 8.20.9. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example.

8.20.10. Finished OPT passes. (There is nothing left to do.)

8.21. Executing TECHMAP pass (map to technology primitives). 8.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'.

Successfully finished Verilog frontend.

8.21.2. Continuing TECHMAP pass. No more expansions possible. 8.22. Executing OPT pass (performing simple optimizations). 8.22.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 8.22.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.22.3. Executing OPT_DFF pass (perform DFF optimizations). 8.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example..

8.22.5. Finished fast OPT passes.

8.23. Executing ABC pass (technology mapping using ABC). 8.23.1. Extracting gate netlist of module `\user_proj_example' to `/input.blif'.. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 8.24. Executing OPT pass (performing simple optimizations). 8.24.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 8.24.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 8.24.3. Executing OPT_DFF pass (perform DFF optimizations). 8.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example..

8.24.5. Finished fast OPT passes.

8.25. Executing HIERARCHY pass (managing design hierarchy). 8.25.1. Analyzing design hierarchy.. Top module: \user_proj_example 8.25.2. Analyzing design hierarchy.. Top module: \user_proj_example Removed 0 unused modules. 8.26. Printing statistics. === user_proj_example === Number of wires: 24 Number of wire bits: 612 Number of public wires: 24 Number of public wire bits: 612 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 25 AND2X1 1 AND2X2 1 AOI21X1 1 AOI22X1 1 BUFX2 1 BUFX4 1 CLKBUF1 1 HAX1 1 INV 1 INVX1 1 INVX2 1 INVX4 1 INVX8 1 LATCH 1 MUX2X1 1 NAND2X1 1 NAND3X1 1 NOR2X1 1 NOR3X1 1 OAI21X1 1 OAI22X1 1 OR2X1 1 OR2X2 1 TBUFX1 1 TBUFX2 1 8.27. Executing CHECK pass (checking for obvious problems). checking module user_proj_example.. found and reported 0 problems. 9. Executing SHARE pass (SAT-based resource sharing). 10. Executing OPT pass (performing simple optimizations). 10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example. 10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \user_proj_example.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \user_proj_example. Performed a total of 0 changes. 10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\user_proj_example'. Removed a total of 0 cells. 10.6. Executing OPT_DFF pass (perform DFF optimizations). 10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module user_proj_example.

10.9. Finished OPT passes. (There is nothing left to do.)

11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. 12. Printing statistics. === user_proj_example === Number of wires: 24 Number of wire bits: 612 Number of public wires: 24 Number of public wire bits: 612 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 25 AND2X1 1 AND2X2 1 AOI21X1 1 AOI22X1 1 BUFX2 1 BUFX4 1 CLKBUF1 1 HAX1 1 INV 1 INVX1 1 INVX2 1 INVX4 1 INVX8 1 LATCH 1 MUX2X1 1 NAND2X1 1 NAND3X1 1 NOR2X1 1 NOR3X1 1 OAI21X1 1 OAI22X1 1 OR2X1 1 OR2X2 1 TBUFX1 1 TBUFX2 1 13. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_. cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_. cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_. cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_. final dff cell mappings: unmapped dff cell: $_DFF_N_ \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q)); unmapped dff cell: $_DFF_NN0_ unmapped dff cell: $_DFF_NN1_ unmapped dff cell: $_DFF_NP0_ unmapped dff cell: $_DFF_NP1_ \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R)); \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R)); unmapped dff cell: $_DFF_PP0_ unmapped dff cell: $_DFF_PP1_ \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); unmapped dff cell: $_DFFSR_NNP_ unmapped dff cell: $_DFFSR_NPN_ unmapped dff cell: $_DFFSR_NPP_ unmapped dff cell: $_DFFSR_PNN_ unmapped dff cell: $_DFFSR_PNP_ unmapped dff cell: $_DFFSR_PPN_ unmapped dff cell: $_DFFSR_PPP_ 13.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Mapping DFF cells in module `\user_proj_example': 14. Printing statistics. [INFO]: ABC: WireLoad : S_2 === user_proj_example === Number of wires: 24 Number of wire bits: 612 Number of public wires: 24 Number of public wire bits: 612 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 25 AND2X1 1 AND2X2 1 AOI21X1 1 AOI22X1 1 BUFX2 1 BUFX4 1 CLKBUF1 1 HAX1 1 INV 1 INVX1 1 INVX2 1 INVX4 1 INVX8 1 LATCH 1 MUX2X1 1 NAND2X1 1 NAND3X1 1 NOR2X1 1 NOR3X1 1 OAI21X1 1 OAI22X1 1 OR2X1 1 OR2X2 1 TBUFX1 1 TBUFX2 1 15. Executing ABC pass (technology mapping using ABC). 15.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-R2knOZ/input.blif'.. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 16. Executing SETUNDEF pass (replace undef values with defined constants). 17. Executing HILOMAP pass (mapping to constant drivers). 18. Executing SPLITNETS pass (splitting up multi-bit signals). 19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \user_proj_example.. Removed 0 unused cells and 222 unused wires. 20. Executing INSBUF pass (insert buffer cells for connected wires). 21. Executing CHECK pass (checking for obvious problems). checking module user_proj_example.. found and reported 0 problems. 22. Printing statistics. === user_proj_example === Number of wires: 63 Number of wire bits: 651 Number of public wires: 24 Number of public wire bits: 612 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 286 AND2X1 1 AND2X2 1 AOI21X1 1 AOI22X1 1 BUFX2 1 BUFX4 1 CLKBUF1 1 HAX1 1 INV 1 INVX1 1 INVX2 1 INVX4 1 INVX8 1 LATCH 1 MUX2X1 1 NAND2X1 1 NAND3X1 1 NOR2X1 1 NOR3X1 1 OAI21X1 1 OAI22X1 1 OR2X1 1 OR2X2 1 TBUFX1 1 TBUFX2 1 sky130_fd_sc_hd__conb_1 261 Area for cell type \AND2X1 is unknown! Area for cell type \AND2X2 is unknown! Area for cell type \AOI21X1 is unknown! Area for cell type \AOI22X1 is unknown! Area for cell type \BUFX2 is unknown! Area for cell type \BUFX4 is unknown! Area for cell type \CLKBUF1 is unknown! Area for cell type \HAX1 is unknown! Area for cell type \INV is unknown! Area for cell type \INVX1 is unknown! Area for cell type \INVX2 is unknown! Area for cell type \INVX4 is unknown! Area for cell type \INVX8 is unknown! Area for cell type \LATCH is unknown! Area for cell type \MUX2X1 is unknown! Area for cell type \NAND2X1 is unknown! Area for cell type \NAND3X1 is unknown! Area for cell type \NOR2X1 is unknown! Area for cell type \NOR3X1 is unknown! Area for cell type \OAI21X1 is unknown! Area for cell type \OAI22X1 is unknown! Area for cell type \OR2X1 is unknown! Area for cell type \OR2X2 is unknown! Area for cell type \TBUFX1 is unknown! Area for cell type \TBUFX2 is unknown! Chip area for module '\user_proj_example': 979.689600 23. Executing Verilog backend. Dumping module `\user_proj_example'.

Warnings: 224 unique messages, 261 total

End of script. Logfile hash: 9d11ab30a3, CPU: user 2.10s system 0.08s, MEM: 44.35 MB peak Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) Time spent: 31% 4x stat (0 sec), 31% 4x read_liberty (0 sec), ...

[INFO]: Changing netlist from 0 to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v

[INFO]: Running Static Timing Analysis...

OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc. License GPLv3: GNU GPL version 3 This is free software, and you are free to change and redistribute it under certain conditions; type `show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 850 module AND2X1 not found. Creating black box for AND2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 857 module AND2X2 not found. Creating black box for AND2X2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 864 module AOI21X1 not found. Creating black box for AOI21X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 872 module AOI22X1 not found. Creating black box for AOI22X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 881 module BUFX2 not found. Creating black box for BUFX2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 887 module BUFX4 not found. Creating black box for BUFX4.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 893 module CLKBUF1 not found. Creating black box for CLKBUF1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 899 module HAX1 not found. Creating black box for HAX1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 907 module INV not found. Creating black box for INV.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 913 module INVX1 not found. Creating black box for INVX1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 919 module INVX2 not found. Creating black box for INVX2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 925 module INVX4 not found. Creating black box for INVX4.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 931 module INVX8 not found. Creating black box for INVX8.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 937 module LATCH not found. Creating black box for LATCH.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 944 module MUX2X1 not found. Creating black box for MUX2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 952 module NAND2X1 not found. Creating black box for NAND2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 959 module NAND3X1 not found. Creating black box for NAND3X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 967 module NOR2X1 not found. Creating black box for NOR2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 974 module NOR3X1 not found. Creating black box for NOR3X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 982 module OAI21X1 not found. Creating black box for OAI21X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 990 module OAI22X1 not found. Creating black box for OAI22X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 999 module OR2X1 not found. Creating black box for OR2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 1006 module OR2X2 not found. Creating black box for OR2X2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 1013 module TBUFX1 not found. Creating black box for TBUFX1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v, line 1020 module TBUFX2 not found. Creating black box for TBUFX2.

create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] puts "\[INFO\]: Setting output delay to: $output_delay_value" [INFO]: Setting output delay to: 0.0 puts "\[INFO\]: Setting input delay to: $input_delay_value" [INFO]: Setting input delay to: 0.0 set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] #set rst_indx [lsearch [all_inputs] [get_port resetn]] set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] set all_inputs_wo_clk_rst $all_inputs_wo_clk # correct resetn set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] # TODO set this as parameter set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "\[INFO\]: Setting load to: $cap_load" [INFO]: Setting load to: 0.01765 set_load $cap_load [all_outputs] tns 0.00 wns 0.00

[INFO]: Synthesis was successful

[INFO]: Running Floorplanning...

[INFO]: Running Initial Floorplanning...

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.

Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 464 library cells

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 pin VPB missing from liberty cell

Warning: LEF macro sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 pin VPB missing from liberty cell

Warning: LEF master AND2X1 has no liberty cell.

Warning: LEF master AND2X2 has no liberty cell.

Warning: LEF master AOI21X1 has no liberty cell.

Warning: LEF master AOI22X1 has no liberty cell.

Warning: LEF master BUFX2 has no liberty cell.

Warning: LEF master BUFX4 has no liberty cell.

Warning: LEF master CLKBUF1 has no liberty cell.

Warning: LEF master HAX1 has no liberty cell.

Warning: LEF master INV has no liberty cell.

Warning: LEF master INVX1 has no liberty cell.

Warning: LEF master INVX2 has no liberty cell.

Warning: LEF master INVX4 has no liberty cell.

Warning: LEF master INVX8 has no liberty cell.

Warning: LEF master LATCH has no liberty cell.

Warning: LEF master MUX2X1 has no liberty cell.

Warning: LEF master NAND2X1 has no liberty cell.

Warning: LEF master NAND3X1 has no liberty cell.

Warning: LEF master NOR2X1 has no liberty cell.

Warning: LEF master NOR3X1 has no liberty cell.

Warning: LEF master OAI21X1 has no liberty cell.

Warning: LEF master OAI22X1 has no liberty cell.

Warning: LEF master OR2X1 has no liberty cell.

Warning: LEF master OR2X2 has no liberty cell.

Warning: LEF master TBUFX1 has no liberty cell.

Warning: LEF master TBUFX2 has no liberty cell.

Info: Added 102 rows of 628 sites.

[INFO]: Core area width: 288.96000000000004

[INFO]: Core area height: 278.24

[INFO]: Changing layout from 0 to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def

Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 464 library cells

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef

Notice 0: Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def Notice 0: Design: user_proj_example Notice 0: Created 612 pins. Notice 0: Created 286 components and 1171 component-terminals. Notice 0: Created 651 nets and 388 connections.

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def

Top-level design name: user_proj_example

Warning: Some pins weren't matched by the config file

Those are: ['vccd1', 'vccd2', 'vdda1', 'vdda2', 'vssa1', 'vssa2', 'vssd1', 'vssd2'] Assigning random sides to the above pins Block boundaries: 0 0 300000 300000 Writing /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def

[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def

[INFO]: Manual Macro Placement...

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef

Notice 0: Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def Notice 0: Design: user_proj_example Notice 0: Created 612 pins. Notice 0: Created 286 components and 1171 component-terminals. Notice 0: Created 651 nets and 388 connections.

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def

Placing the following macros: {'AND2X1': ['40480', '13600', 'N'], 'AND2X2': ['40480', '19040', 'N'], 'AOI21X1': ['40480', '24480', 'N'], 'AOI22X1': ['40480', '29920', 'N'], 'BUFX2': ['40480', '35360', 'N'], 'BUFX4': ['40480', '40800', 'N'], 'CLKBUF1': ['40480', '46240', 'N'], 'HAX1': ['40480', '51680', 'N'], 'INV': ['40480', '57120', 'N'], 'INVX1': ['40480', '62560', 'N'], 'INVX2': ['40480', '68000', 'N'], 'INVX4': ['40480', '73440', 'N'], 'INVX8': ['40480', '78880', 'N'], 'LATCH': ['40480', '84320', 'N'], 'MUX2X1': ['40480', '89760', 'N'], 'NAND2X1': ['40480', '95200', 'N'], 'NAND3X1': ['40480', '100640', 'N'], 'NOR2X1': ['40480', '106080', 'N'], 'NOR3X1': ['40480', '111520', 'N'], 'OAI21X1': ['40480', '116960', 'N'], 'OAI22X1': ['40480', '122400', 'N'], 'OR2X1': ['40480', '127840', 'N'], 'OR2X2': ['40480', '133280', 'N'], 'TBUFX1': ['40480', '138720', 'N'], 'TBUFX2': ['40480', '144160', 'N']} Design name: user_proj_example Placing AND2X1 Placing AND2X2 Placing AOI21X1 Placing AOI22X1 Placing BUFX2 Placing BUFX4 Placing CLKBUF1 Placing HAX1 Placing INV Placing INVX1 Placing INVX2 Placing INVX4 Placing INVX8 Placing LATCH Placing MUX2X1 Placing NAND2X1 Placing NAND3X1 Placing NOR2X1 Placing NOR3X1 Placing OAI21X1 Placing OAI22X1 Placing OR2X1 Placing OR2X2 Placing TBUFX1 Placing TBUFX2

Successfully placed 25 instances

[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def

[INFO]: Running Tap/Decap Insertion...

OpenROAD 0.9.0 d03ebfc244 This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef Notice 0: Created 11 technology layers Notice 0: Created 25 technology vias Notice 0: Created 464 library cells

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef

Notice 0: Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def Notice 0: Design: user_proj_example Notice 0: Created 612 pins. Notice 0: Created 286 components and 1171 component-terminals. Notice 0: Created 651 nets and 388 connections.

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def

Running tapcell... Step 1: Cut rows... [INFO] Macro blocks found: 0 [INFO] #Original rows: 102 [INFO] #Cut rows: 0 Step 2: Insert endcaps... [INFO] #Endcaps inserted: 204 Step 3: Insert tapcells... [INFO] #Tapcells inserted: 1040 Running tapcell... Done!

[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/ioPlacer.def.macro_placement.def to /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def

[INFO]: Running Placement...

[WARNING]: Performing Random Global Placement...

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef

Notice 0: Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def Notice 0: Design: user_proj_example Notice 0: Created 612 pins. Notice 0: Created 1530 components and 3659 component-terminals. Notice 0: Created 651 nets and 388 connections.

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def

Design name: user_proj_example Core Area Boundaries: 5520 10880 294400 288320 Number of instances 1530 Placed 261 instances

[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/floorplan/user_proj_example.floorplan.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def

[INFO]: Running OpenPhySyn Timing Optimization...

[INFO]: Trimming Liberty...

[OpenPhySyn] [2020-12-01 20:12:41.533] [info] Loaded 6 transforms. [OpenPhySyn] [2020-12-01 20:12:43.992] [info] OpenPhySyn: 1.8.1

Warning: /project/openlane/user_proj_example/runs/user_proj_example/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef

Notice 0: Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def Notice 0: Design: user_proj_example Notice 0: Created 612 pins. Notice 0: Created 1530 components and 3659 component-terminals. Notice 0: Created 651 nets and 388 connections.

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def

[INFO]: Setting output delay to: 0.0 [INFO]: Setting input delay to: 0.0 [INFO]: Setting load to: 0.01765 =============== Initial Reports ============= No paths found. Capacitance violations: 0 Transition violations: 0 wns 0.00 tns 0.00 Initial area: 33320 um2 OpenPhySyn timing repair: [OpenPhySyn] [2020-12-01 20:13:47.621] [info] Invoking repair_timing transform [OpenPhySyn] [2020-12-01 20:13:47.638] [info] Buffer library: sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_1 [OpenPhySyn] [2020-12-01 20:13:47.638] [info] Inverter library: None [OpenPhySyn] [2020-12-01 20:13:47.638] [info] Buffering: enabled [OpenPhySyn] [2020-12-01 20:13:47.638] [info] Driver sizing: enabled [OpenPhySyn] [2020-12-01 20:13:47.638] [info] Pin-swapping: enabled [OpenPhySyn] [2020-12-01 20:13:47.638] [info] Mode: Timing-Driven [OpenPhySyn] [2020-12-01 20:13:47.638] [info] Iteration 1 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] No more violations or cannot find more optimal buffer [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Runtime: 0s [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Buffers: 0 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Resize up: 0 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Resize down: 0 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Pin Swap: 0 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Buffered nets: 0 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Fanout violations: 0 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Transition violations: 0 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Capacitance violations: 0 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Slack gain: 0.0 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] Initial area: 3332 [OpenPhySyn] [2020-12-01 20:13:47.804] [info] New area: 3332

[OpenPhySyn] [2020-12-01 20:13:47.804] [info] Finished repair_timing transform (0)

Added/updated 0 cells =============== Final Reports ============= No paths found. Capacitance violations: 0 Transition violations: 0 wns 0.00 tns 0.00 Final area: 33320 um2 Export optimized design

[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/replace.def to /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def

[INFO]: Writing Verilog...

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef

Notice 0: Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def Notice 0: Design: user_proj_example Notice 0: Created 612 pins. Notice 0: Created 1530 components and 3659 component-terminals. Notice 0: Created 651 nets and 388 connections.

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def

[INFO]: Changing netlist from /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis.v to /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v

[INFO]: Running Static Timing Analysis...

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.

Warning: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 50 module AND2X1 not found. Creating black box for AND2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 55 module AND2X2 not found. Creating black box for AND2X2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 60 module AOI21X1 not found. Creating black box for AOI21X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 66 module AOI22X1 not found. Creating black box for AOI22X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 73 module BUFX2 not found. Creating black box for BUFX2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 77 module BUFX4 not found. Creating black box for BUFX4.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 81 module CLKBUF1 not found. Creating black box for CLKBUF1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 85 module HAX1 not found. Creating black box for HAX1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 91 module INV not found. Creating black box for INV.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 95 module INVX1 not found. Creating black box for INVX1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 99 module INVX2 not found. Creating black box for INVX2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 103 module INVX4 not found. Creating black box for INVX4.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 107 module INVX8 not found. Creating black box for INVX8.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 111 module LATCH not found. Creating black box for LATCH.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 116 module MUX2X1 not found. Creating black box for MUX2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 122 module NAND2X1 not found. Creating black box for NAND2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 127 module NAND3X1 not found. Creating black box for NAND3X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 133 module NOR2X1 not found. Creating black box for NOR2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 138 module NOR3X1 not found. Creating black box for NOR3X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 144 module OAI21X1 not found. Creating black box for OAI21X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 150 module OAI22X1 not found. Creating black box for OAI22X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 157 module OR2X1 not found. Creating black box for OR2X1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 162 module OR2X2 not found. Creating black box for OR2X2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 167 module TBUFX1 not found. Creating black box for TBUFX1.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 172 module TBUFX2 not found. Creating black box for TBUFX2.

Warning: /project/openlane/user_proj_example/runs/user_proj_example/results/synthesis/user_proj_example.synthesis_optimized.v, line 642 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for PHY_204.

[INFO]: Running Detailed Placement...

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def

detailed_placement...

Warning: could not find power special net

Design Stats -------------------------------- total instances 1530 multi row instances 0 fixed instances 1269 nets 651 design area 80146.9 u^2 fixed area 2352.3 u^2 movable area 979.7 u^2 utilization 1 % utilization padded 2 % rows 102 row height 2.7 u Placement Analysis -------------------------------- total displacement 445.8 u average displacement 0.3 u max displacement 5.9 u original HPWL 73068.9 u legalized HPWL 72867.7 u delta HPWL -0 % check_placement...

[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/tmp/placement/openphysyn.def to /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def

[INFO]: Changing layout from /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def to /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def

[INFO]: Generating PDN...

Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef

Notice 0: Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def Notice 0: Design: user_proj_example Notice 0: Created 612 pins. Notice 0: Created 1530 components and 3659 component-terminals. Notice 0: Created 651 nets and 388 connections.

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def

[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN [INFO] [PDNG-0016] config: /media/philipp/Daten/skywater/open_pdks/sky130/sky130A/sky130A/libs.tech/openlane/common_pdn.tcl [INFO] [PDNG-0008] Design Name is user_proj_example [INFO] [PDNG-0009] Reading technology data [INFO] [PDNG-0011] ****** INFO ****** Type: stdcell, grid Stdcell Rails Layer: met1 - width: 0.480 pitch: 2.720 offset: 0.000 Straps Layer: met4 - width: 1.600 pitch: 153.600 offset: 16.320 Layer: met5 - width: 1.600 pitch: 153.180 offset: 16.650 Connect: {met1 met4} {met4 met5} Type: macro, macro_1 Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90 Straps Connect: [INFO] [PDNG-0012] **** END INFO **** [INFO] [PDNG-0013] Inserting stdcell grid - grid [INFO] [PDNG-0015] Writing to database

[INFO]: Routing...

[INFO]: Running Global Routing...